CN102376621A - Manufacturing method of shallow trench isolation structure - Google Patents
Manufacturing method of shallow trench isolation structure Download PDFInfo
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- CN102376621A CN102376621A CN2010102537906A CN201010253790A CN102376621A CN 102376621 A CN102376621 A CN 102376621A CN 2010102537906 A CN2010102537906 A CN 2010102537906A CN 201010253790 A CN201010253790 A CN 201010253790A CN 102376621 A CN102376621 A CN 102376621A
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Abstract
The invention discloses a manufacturing method of a shallow trench isolation structure, which comprises the steps that after an isolation oxide pad and a blocking silicon nitride layer are sequentially deposited on a silicon substrate of a semi-conductor device, a shallow trench isolation tank is formed on the silicon substrate of the semi-conductor device through a lithography process and an etching process; a substrate silicon oxide layer is grown on the surface of the shallow trench isolation tank; a silicon nitride layer is deposited on the substrate silicon oxide layer; a silicon dioxide layer is deposited on the surface of the silicon nitride layer, and the shallow trench isolation tank is fully filled; and after the height of the silicon dioxide layer which is etched through a dry process reaches the height of the shallow trench isolation structure and the silicon nitride layer and the substrate silicon oxide layer on the blocking silicon nitride layer are sequentially removed, the surface of the silicon substrate is polished through a chemical mechanical process, the shallow trench isolation structure is obtained and the isolation oxide pad is removed. The shallow trench isolation (STI) structure which is manufactured through the method not only avoids the phenomenon of defects, but also avoids a gap in the STI structure.
Description
Technical field
The present invention relates to technical field of semiconductors, the manufacture method of particularly a kind of shallow-trench isolation (STI) structure.
Background technology
In the manufacture craft of semiconductor device, comprise the making of sti structure.The making of sti structure is exactly the isolated area between the active area of making on the semiconductor device substrates.The manufacture method of sti structure mainly is divided into three steps and carries out: the etching of STI groove, STI material are filled and the sti structure planarization, below existing method of making sti structure are elaborated.
The method flow diagram of the making shallow groove isolation structure that Fig. 1 provides for prior art is made generalized section in conjunction with the shallow groove isolation structure shown in Fig. 2 a～Fig. 2 d and is described, and its concrete steps are:
Before this step, adopted N type alloy and P alloy to carry out two trap doping processs on the substrate 10 of semiconductor device, defined active region, STI groove 20 is etched between the active region, as isolation;
In this step; After on substrate 10, being formed with the source region; Carry out before the etching of STI groove 20, also need and deposit ca nitride layer 102, wherein on substrate 10 surfaces deposit oxide pad 101 successively; Isolation oxidation pad 101 is used for protecting follow-up active area to avoid chemical contamination in the process of removing nitride layer, and ca nitride layer 102 is used at the deposition process protection active area of follow-up STI filler and in the subsequent chemical-mechanical polishing process, serves as the barrier material of polishing;
In this step, the process of STI groove 20 etchings is: (nitride layer surface just) spin coating photoresist layer on substrate 10 surfaces of semiconductor device, develop after adopting the mask plate with STI groove 20 figures that photoresist layer is made public then again; Obtain the photoresist layer of patterning; At last, be mask with the photoresist layer of patterning, the substrate 10 of semiconductor device is carried out etching; Obtain STI groove 20, remove remaining photoresist layer after the etching;
In this step, the degree of depth of STI groove 20 confirms according to the making needs, and along with the characteristic size of semiconductor device reduces, the depth-to-width ratio of STI groove 20 is also increasing;
In this step; The process of hot grow liners silicon oxide layer 30 is: the semiconductor device that will have STI groove 20 is put into high-temperature oxydation equipment; Aerating oxygen in this equipment then, the pad silicon oxide layer 30 of growth one deck 50～300 dusts on the bottom of STI groove 20 and sidewall.This pad silicon oxide layer 30 can stop oxygen molecule in the oxide layer 40 of deposition to the diffusion of the active area of substrate 10 when subsequent deposition oxide layer 40;
In this step; HDPCVD makes plasma under low pressure mix the semiconductor device surface of the direct bombardment of form in reaction chamber of gas with high density; It mainly can fill the STI groove 20 of high-aspect-ratio under 300 degrees centigrade～400 degrees centigrade lower depositing temperatures;
In this step, HDPCVD comprises two or more gases participation chemical reactions, and the frequent and silicon-containing gas of oxygen or ozone mixes such as TEOS or SiH4, and with argon gas (Ar), feeds the reaction chamber that is placed with semiconductor device;
Like this, just on the substrate of semiconductor device, obtained sti structure.
But; In step 104, remove in the process of isolation oxidation pad 101; When having adopted hydrofluoric acid to remove, it also can cause sti structure corner poor damaged phenomenon (Worse Divot) to occur to being that the sti structure of earth silicon material carries out etching near the corner part of isolation oxidation pad 101; As shown in Figure 3, have a strong impact on the sti structure pattern of final formation.In order to overcome this defective; Before step 102, increase the step of the rollback etching carry out ca nitride layer 102 and isolation oxidation pad 101, make ca nitride layer 102 and the width of isolation oxidation pad 101 width in STI groove 20 positions greater than STI groove 20; Like this; In the process of removing isolation oxidation pad 101, because the width of STI groove is greater than the width of final sti structure, so though carried out etching at sti structure near the part of isolation oxidation pad 101; But be not the turning of sti structure, finally can not influence formed sti structure pattern (etch amount having been taken into account) yet.But; Adopt this mode also to have defective: in step 103 deposited oxide layer 40, in the process of the full STI groove 20 of filling, because the rollback etching of ca nitride layer 102 and isolation oxidation pad 101 causes the ca nitride layer 102 and the substrate 10 of isolation oxidation pad 101 and below that step difference is arranged; So the space can in the middle of STI groove 20, occur filling; This makes the final STI that forms the space can occur, has influenced the effect that semiconductor device is isolated, and seriously can cause semiconductor device failure.
Summary of the invention
In view of this, the present invention provides the manufacture method of a kind of STI, and the STI that adopts this method to make had both avoided occurring damaged phenomenon, avoids again the space occurring in the middle of the sti structure.
For achieving the above object, the technical scheme that the present invention implements specifically is achieved in that
A kind of manufacture method of shallow groove isolation structure, this method comprises:
On the silicon substrate of semiconductor device successively the deposit oxide pad and stop silicon nitride layer after, adopt photoetching process and etching technics on the silicon substrate of semiconductor device, to form the shallow-trench isolation groove;
At said shallow-trench isolation rooved face grow liners silicon oxide layer;
At said pad silicon oxide layer deposition one deck silicon nitride layer;
At said silicon nitride layer surface deposition layer of silicon dioxide layer, fill up said shallow-trench isolation groove;
The height that adopts the dry etching silicon dioxide layer is behind the height of shallow groove isolation structure; After removal stops the silicon nitride layer and pad silicon oxide layer on the silicon nitride layer successively; After adopting the chemico-mechanical polishing surface of silicon, obtain shallow groove isolation structure, remove the isolation oxidation pad.
The height of said dry etching silicon dioxide layer guarantees the back surfacing of subsequent gate material deposition.
The thickness of said grow liners silicon oxide layer is 15～25 dusts.
The thickness of said silicon nitride layer is 290 dusts～310 dusts.
The thickness of said silicon dioxide layer is 290 dusts～310 dusts.
Visible by technique scheme; The present invention is in making the STI process; Do not increase the rollback etch step of carrying out ca nitride layer 102 and isolation oxidation pad 101, but after forming the STI groove, adopt oxygen nitrogen oxide structure to fill the STI groove; Adopt dry etching oxygen nitrogen oxide structure silicon dioxide layer at the middle and upper levels to the sti structure height then; And then silicon nitride layer and the silicon dioxide layer of lower floor removed in the oxygen nitrogen oxide structure flush with nitride layer 102, removes ca nitride layer 102 and isolation oxidation pad 101 at last again, obtains sti structure.Because resulting sti structure has adopted oxygen nitrogen oxide structure; So near the STI turning, only have the very thin upper strata silicon dioxide layer of one deck; If smaller damaged phenomenon appears in this upper strata silicon dioxide layer of etching when removing isolation oxidation pad 101, can be filled and led up, and the silicon nitride layer among the STI does not receive the influence of hydrofluoric acid to occur damaged by the follow-up gate oxide that forms above that yet; Thereby the sti structure of making had both avoided occurring damaged phenomenon, avoided occurring the space again.
Description of drawings
The method flow diagram of the making sti structure that Fig. 1 provides for prior art;
Fig. 2 a～Fig. 2 d is that the sti structure of prior art is made generalized section;
The sti structure generalized section of damaged phenomenon appears in Fig. 3 for the turning;
Fig. 4 is the method flow diagram of making sti structure provided by the invention;
Fig. 5 a～Fig. 5 g is that sti structure provided by the invention is made generalized section.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is done further explain.
The present invention has satisfactory pattern for the sti structure that guarantees made, and the just middle space that do not occur is not so adopt the rollback etch step of the ca nitride layer 102 and the isolation oxidation pad 101 of prior art in making sti structure process.For the sti structure that guarantees to make avoids occurring very poor damaged phenomenon; In follow-up gate fabrication process, can't be filled and led up by gate oxide; Change the material of sti structure, that is: after forming the STI groove, adopted oxygen nitrogen oxide structure to fill the STI groove; Adopt dry etching oxygen nitrogen oxide structure silicon dioxide layer at the middle and upper levels to the sti structure height then; And then silicon nitride layer and the silicon dioxide layer of lower floor removed in the oxygen nitrogen oxide structure flush with nitride layer 102, removes ca nitride layer 102 and isolation oxidation pad 101 at last again, obtains sti structure.Because resulting sti structure has adopted oxygen nitrogen oxide structure; So near the STI turning, only have the very thin upper strata silicon dioxide layer of one deck; If smaller damaged phenomenon appears in this upper strata silicon dioxide layer of etching when removing isolation oxidation pad 101; Also can be filled and led up, and the silicon nitride layer among the STI does not receive the influence appearance of hydrofluoric acid damaged, thereby damaged phenomenon appears in the sti structure of making by the follow-up gate oxide that forms above that.
Fig. 4 is the method flow diagram of making sti structure provided by the invention, makes generalized section in conjunction with the sti structure provided by the invention shown in Fig. 5 a～Fig. 5 g.Be elaborated.The concrete steps of method are:
Before this step, adopted N type alloy and P alloy to carry out two trap doping processs on the substrate 10 of semiconductor device, defined active region, STI groove 20 is etched between the active region, as isolation;
In this step; After on substrate 10, being formed with the source region; Carry out before the etching of STI groove 20, also need and deposit ca nitride layer 102, wherein on substrate 10 surfaces deposit oxide pad 101 successively; Isolation oxidation pad 101 is used for protecting follow-up active area to avoid chemical contamination in the process of removing nitride layer, and ca nitride layer 102 is used at the deposition process protection active area of follow-up STI filler and in the subsequent chemical-mechanical polishing process, serves as the barrier material of polishing;
In this step, the process of STI groove 20 etchings is: (nitride layer surface just) spin coating photoresist layer on substrate 10 surfaces of semiconductor device, develop after adopting the mask plate with STI groove 20 figures that photoresist layer is made public then again; Obtain the photoresist layer of patterning; At last, be mask with the photoresist layer of patterning, the substrate 10 of semiconductor device is carried out etching; Obtain STI groove 20, remove remaining photoresist layer after the etching;
In this step, the degree of depth of STI groove 20 confirms according to the making needs, and along with the characteristic size of semiconductor device reduces, the depth-to-width ratio of STI groove 20 is also increasing;
In this step; The process of hot grow liners silicon oxide layer 30 is: the semiconductor device that will have STI groove 20 is put into high-temperature oxydation equipment; Aerating oxygen in this equipment then, the pad silicon oxide layer 30 of growth one deck 50～300 dusts on the bottom of STI groove 20 and sidewall.This pad silicon oxide layer 30 can stop oxygen molecule in the oxide layer 40 of deposition to the diffusion of the active area of substrate 10 when subsequent deposition oxide layer 40;
In this step, the thickness of pad silicon oxide layer 30 is 15～25 dusts;
In this step, the thickness of deposited silicon nitride layer 40 ' is 290 dusts～310 dusts;
In this step, the thickness of the silicon dioxide layer 50 ' of deposition is 290 dusts～310 dusts;
In this step, just silicon dioxide layer 50 ' is etched into the height of sti structure;
In this step; Employing hydrofluoric acid is removed; When removing, also can remove the silicon dioxide layer in the sti structure 50 ', but because the silicon dioxide layer 50 ' of sti structure corner is relatively thinner and silicon nitride layer 40 ' can not removed by hydrofluoric acid; Can not form very poor defective phenomenon even remove some yet; But or slight defective phenomenon is not arranged, fill and lead up during the oxidation grid oxide layer in also can the technology in follow-up manufacturing grid when slight defective phenomenon is arranged, can not influence the device performance that finally obtains.
More than lift preferred embodiment; The object of the invention, technical scheme and advantage have been carried out further explain, and institute it should be understood that the above is merely preferred embodiment of the present invention; Not in order to restriction the present invention; All within spirit of the present invention and principle, any modification of being done, be equal to replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. the manufacture method of a shallow groove isolation structure, this method comprises:
On the silicon substrate of semiconductor device successively the deposit oxide pad and stop silicon nitride layer after, adopt photoetching process and etching technics on the silicon substrate of semiconductor device, to form the shallow-trench isolation groove;
At said shallow-trench isolation rooved face grow liners silicon oxide layer;
At said pad silicon oxide layer deposition one deck silicon nitride layer;
At said silicon nitride layer surface deposition layer of silicon dioxide layer, fill up said shallow-trench isolation groove;
The height that adopts the dry etching silicon dioxide layer is behind the height of shallow groove isolation structure; After removal stops the silicon nitride layer and pad silicon oxide layer on the silicon nitride layer successively; After adopting the chemico-mechanical polishing surface of silicon, obtain shallow groove isolation structure, remove the isolation oxidation pad.
2. the method for claim 1 is characterized in that, the height of said dry etching silicon dioxide layer guarantees the back surfacing of subsequent gate material deposition.
3. the method for claim 1 is characterized in that, the thickness of said grow liners silicon oxide layer is 15～25 dusts.
4. the method for claim 1 is characterized in that, the thickness of said silicon nitride layer is 290 dusts～310 dusts.
5. the method for claim 1 is characterized in that, the thickness of said silicon dioxide layer is 290 dusts～310 dusts.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105719996A (en) * | 2014-12-04 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor structure |
| CN110120364A (en) * | 2018-02-07 | 2019-08-13 | 无锡华润上华科技有限公司 | The preparation method of fleet plough groove isolation structure |
| CN113629374A (en) * | 2021-08-03 | 2021-11-09 | 合肥工业大学 | Preparation method of millimeter wave chip cavity device based on metal-assisted chemical etching |
| CN113654600A (en) * | 2021-07-23 | 2021-11-16 | 无锡莱斯能特科技有限公司 | Manufacturing method of flow sensor |
| CN116978788A (en) * | 2023-09-25 | 2023-10-31 | 粤芯半导体技术股份有限公司 | LDMOS device with multi-layer field plate structure and preparation method thereof |
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| US6200881B1 (en) * | 1999-07-23 | 2001-03-13 | Worldwide Semiconductor Manufacturing Corp. | Method of forming a shallow trench isolation |
| US20020022340A1 (en) * | 1998-08-13 | 2002-02-21 | Tony Lin | Method of forming a shallow trench isolation |
| US20020031890A1 (en) * | 2000-08-28 | 2002-03-14 | Takayuki Watanabe | Semiconductor device of STI structure and method of fabricating MOS transistors having consistent threshold voltages |
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2010
- 2010-08-09 CN CN2010102537906A patent/CN102376621A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020022340A1 (en) * | 1998-08-13 | 2002-02-21 | Tony Lin | Method of forming a shallow trench isolation |
| US6200881B1 (en) * | 1999-07-23 | 2001-03-13 | Worldwide Semiconductor Manufacturing Corp. | Method of forming a shallow trench isolation |
| US20020031890A1 (en) * | 2000-08-28 | 2002-03-14 | Takayuki Watanabe | Semiconductor device of STI structure and method of fabricating MOS transistors having consistent threshold voltages |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105719996A (en) * | 2014-12-04 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor structure |
| CN105719996B (en) * | 2014-12-04 | 2018-12-21 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN110120364A (en) * | 2018-02-07 | 2019-08-13 | 无锡华润上华科技有限公司 | The preparation method of fleet plough groove isolation structure |
| CN110120364B (en) * | 2018-02-07 | 2021-10-15 | 无锡华润上华科技有限公司 | Preparation method of shallow trench isolation structure |
| CN113654600A (en) * | 2021-07-23 | 2021-11-16 | 无锡莱斯能特科技有限公司 | Manufacturing method of flow sensor |
| CN113629374A (en) * | 2021-08-03 | 2021-11-09 | 合肥工业大学 | Preparation method of millimeter wave chip cavity device based on metal-assisted chemical etching |
| CN113629374B (en) * | 2021-08-03 | 2022-03-25 | 合肥工业大学 | Method for preparing millimeter wave chip cavity device based on metal-assisted chemical etching |
| CN116978788A (en) * | 2023-09-25 | 2023-10-31 | 粤芯半导体技术股份有限公司 | LDMOS device with multi-layer field plate structure and preparation method thereof |
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