CN105826236A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN105826236A CN105826236A CN201510009809.5A CN201510009809A CN105826236A CN 105826236 A CN105826236 A CN 105826236A CN 201510009809 A CN201510009809 A CN 201510009809A CN 105826236 A CN105826236 A CN 105826236A
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Abstract
The invention discloses a semiconductor structure and a forming method thereof. The method comprises steps: a semiconductor substrate is provided, and a mask layer with an opening is formed on the surface of the semiconductor substrate; the semiconductor substrate is etched along the opening, and a groove is formed inside the semiconductor substrate; a first initial dielectric layer is formed in the groove, wherein the surface of the first initial dielectric layer is flush with that of the mask layer; the first initial dielectric layer is etched to form a first dielectric layer to enable the surface of the first dielectric layer to be lower than that of the semiconductor substrate; a second initial dielectric layer is formed on the surface of the first dielectric layer after being etched, wherein the surface of the second initial dielectric layer is flush with that of the mask layer, and the wet etching rate of the second initial dielectric layer is smaller than that of the first dielectric layer; the second initial dielectric layer is etched to form a second dielectric layer to enable the surface of the second dielectric layer to be flush with that of the semiconductor substrate; and the mask layer is removed. The method of the invention can improve the corrosion resistance of the formed shallow trench isolation structure.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to a kind of semiconductor structure and forming method thereof.
Background technology
Along with semiconductor technology enters deep sub-micron era, the element (between the active area of such as CMOS integrated circuit) of less than 0.18 micron mostly uses fleet plough groove isolation structure (STI) to carry out lateral isolation and makes.Integrated circuit includes many transistors formed on a semiconductor substrate, and in general, transistor is to be spaced apart from each other by insulation or isolation structure.The technique being commonly used to form isolation structure is shallow trench isolation (shallowtrenchisolation is called for short STI) technique.
Shallow ditch groove separation process is typically to be formed on a semiconductor substrate groove, then fill insulant in groove, forms fleet plough groove isolation structure.Described fleet plough groove isolation structure surrounds each active area in Semiconductor substrate, isolated between transistor active area and surfaces of active regions are formed.Described insulant is typically silicon oxide.
Generally fleet plough groove isolation structure is to form formation before semiconductor device on the active area; and during forming semiconductor device; wet etching and cleaning would generally be used for multiple times; and during wet etching and cleaning; using most is hydrofluoric acid solution; and hydrofluoric acid solution has higher Etch selectivity for silicon oxide, it will usually the insulant in fleet plough groove isolation structure is caused corrosion.And when described surface of shallow trench isolation structure is formed with grid structure, insulant in described fleet plough groove isolation structure easily exposes grid after being corroded and connects the gate dielectric layer of structural base, grid, described grid structure is damaged in subsequent technique, affects device performance and productivity.
Refer to Fig. 1, for a kind of semiconductor structure, including some active areas 10 arranged in parallel, isolated by fleet plough groove isolation structure (white space between adjacent active regions) between adjacent active regions 10, also include some grid structures 20, grid structure 20, grid structure 20 part is positioned at surface of shallow trench isolation structure.
Refer to Fig. 2, in Fig. 1 along the generalized section in secant AA ' direction.
Described grid structure 20 (refer to Fig. 1) includes gate dielectric layer 21, is positioned at the grid 22 on gate dielectric layer 21 surface, and the mask layer 24 on grid 22 surface is positioned at grid 22 and the side wall 23 of gate dielectric layer 21 sidewall surfaces.Grid structure 20 in Fig. 2 is positioned at fleet plough groove isolation structure 30 surface.
Refer to Fig. 3, when described semiconductor structure is after the etching of hydrofluoric acid solution or cleaning, the uncovered part of surface of shallow trench isolation structure can be corroded generation depression, when described etching or cleaning process are shorter, the degree that groove isolation construction surface is corroded is little, can not expose gate dielectric layer 21 and the grid 22 of grid structure 20.
Refer to Fig. 4, when described etching or time cleaning process is longer or number of times is more, owing to described Fluohydric acid. has isotropic etching character, so, horizontal and vertical synchronization etching can be carried out along recess, cause the bottom exposing gate dielectric layer 21, owing to the material of described gate dielectric layer 21 is usually silicon oxide, so, described gate dielectric layer 21 can be also carried out etching, expose the bottom of grid 22.Described grid structure is damaged in subsequent technique, such as meeting growth material thin film below acid solution the meeting etching grid 22, and grid 22 in subsequent technique, cause component failure.
The corrosion resistance of existing fleet plough groove isolation structure needs further to be improved.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor structure and forming method thereof, improves fleet plough groove isolation structure corrosion resistance in cleaning.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, including: providing Semiconductor substrate, described semiconductor substrate surface is formed with the mask layer with opening；Etch described Semiconductor substrate along described opening, in described Semiconductor substrate, form groove；Forming the first initial medium layer in described groove, described first initial medium layer surface flushes with mask layer surface；Etch described first initial medium layer, form first medium layer, make described first medium layer surface less than semiconductor substrate surface；First medium layer surface after described etching forms the second initial medium layer, and described second initial medium layer surface flushes with mask layer surface, and the wet-etch rate of described second initial medium layer is less than the wet-etch rate of first medium layer；Etch described second initial medium layer, form second dielectric layer, make described second dielectric layer surface flush with semiconductor substrate surface；Remove described mask layer.
Optionally, the material of described second dielectric layer is SiCO, SiON, SiCON or SiC.
Optionally, the thickness of described second dielectric layer is 2nm～20nm.
Optionally, the method forming described second initial medium layer includes: form second medium material layer on described first medium layer surface and mask layer surface, and described second medium material layer fills full described groove and opening；With described mask layer as stop-layer, described second medium material layer is planarized, forms the second initial medium layer, make the surface of described second initial medium layer flush with mask layer surface.
Optionally, boiler tube deposition or chemical vapor deposition method is used to form described second medium material layer.
Optionally, the distance between described first medium layer and semiconductor substrate surface is less than 20nm.
Optionally, the material of described first medium layer is silicon oxide.
Optionally, the method forming described first initial medium layer includes: deposit first medium material layer with mask layer surface in described groove, and described first medium material layer fills full described groove and mask layer opening；With described mask layer as stop-layer, described first medium material layer is planarized, forms the first initial medium layer, make the surface of described first initial medium layer flush with mask layer surface.
Optionally, chemical vapor deposition method, high-density plasma deposition process or high-aspect-ratio depositing operation is used to form described first medium material layer.
Optionally, use wet method or dry etch process to etch described second initial medium layer, form second dielectric layer.
Optionally, the etching gas that described dry etch process uses includes NF3And NH3, NF3With NH3Flow-rate ratio be 1:20～5:1, etching temperature is 40 degrees Celsius～80 degrees Celsius, and pressure is 0.5 torr～50 torr, power be less than 100 watts, frequency be less than 100 KHz.
Optionally, the material of described mask layer is silicon nitride.
Optionally, using wet-etching technology to remove described mask layer, the etching solution that described wet-etching technology uses is phosphoric acid solution.
Optionally, between described mask layer and Semiconductor substrate, there is silicon oxide layer.
Optionally, also include, form grid structure on described second dielectric layer surface.
Technical scheme also provides for a kind of semiconductor structure using said method to be formed, including: Semiconductor substrate；It is positioned at the groove of described Semiconductor substrate；Being positioned at the first medium layer of described groove, the surface of described first medium layer is less than semiconductor substrate surface；Being positioned at the second dielectric layer on described first medium layer surface, the surface of described second dielectric layer flushes with semiconductor substrate surface, and the wet-etch rate of described second dielectric layer is less than the wet-etch rate of first medium layer.
Optionally, the material of described second dielectric layer is SiCO, SiON, SiCON or SiC.
Optionally, the thickness of described second dielectric layer is 2nm～20nm.
Optionally, the material of described first medium layer is silicon oxide.
Optionally, also include: be positioned at the grid structure on second dielectric layer surface.
Compared with prior art, technical scheme has the advantage that
In technical scheme, after forming groove in Semiconductor substrate, in described groove, form first medium layer, then etch described first medium layer, make the surface of described first medium layer less than semiconductor substrate surface；Then form second dielectric layer on described first medium layer surface, make described second dielectric layer surface flush with semiconductor substrate surface.The wet-etch rate of described second dielectric layer is less than the wet-etch rate of first medium layer.So that described semiconductor structure is in follow-up wet etching and cleaning process, compared with prior art, corrosion resistance is improved.
Further, the thickness of described second dielectric layer is 2nm～20nm, and described thickness can keep out the corrosion of hydrofluoric acid solution in follow-up wet etching or cleaning, the first medium layer below protection.
Further, forming grid structure on described second dielectric layer surface, the second dielectric layer of described Semiconductor substrate and second dielectric layer are as the fleet plough groove isolation structure in Semiconductor substrate.Wet-etch rate due to second dielectric layer is less than the wet-etch rate of first medium layer, so that described semiconductor structure is in follow-up wet etching and cleaning process, described second dielectric layer subject to corrosion is less, the bottom of the grid structure formed on second dielectric layer surface will not be exposed, such that it is able to avoid device to lose efficacy.
In the semiconductor structure that technical scheme proposes, second dielectric layer and second dielectric layer are as the fleet plough groove isolation structure in Semiconductor substrate.Wet-etch rate due to second dielectric layer is less than the wet-etch rate of first medium layer, so that described semiconductor structure is in follow-up wet etching and cleaning process, described second dielectric layer subject to corrosion is less, compared with prior art, the corrosion resistance of described fleet plough groove isolation structure improves.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the schematic diagram after fleet plough groove isolation structure is corroded in the semiconductor structure of the prior art of the present invention and described semiconductor structure；
Fig. 5 to Figure 15 is the schematic diagram of the semiconductor structure of embodiments of the invention.
Detailed description of the invention
As described in the background art, owing to the fleet plough groove isolation structure of existing formation is in follow-up wet etching and cleaning process, easily it is corroded, causes the bottom exposing the device formed at described surface of shallow trench isolation structure, the performance of the semiconductor structure that impact is formed and productivity.
In embodiments of the invention, after forming groove in Semiconductor substrate, in described groove, form first medium layer, then etch described first medium layer, make the surface of described first medium layer less than semiconductor substrate surface；Then form second dielectric layer on described first medium layer surface, make described second dielectric layer surface flush with semiconductor substrate surface.The internal corrosion performance of described second dielectric layer is more than the decay resistance of first medium layer, thus should not be corroded.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with the accompanying drawings the specific embodiment of the present invention is described in detail.
Refer to Fig. 5, it is provided that Semiconductor substrate 100, form mask layer 200 on described Semiconductor substrate 100 surface.
The material of described Semiconductor substrate 100 includes the semi-conducting materials such as silicon, germanium, SiGe, GaAs, described Semiconductor substrate 100 can be body material can also be composite construction such as silicon-on-insulator.Those skilled in the art can select the type of described Semiconductor substrate 100 according to the semiconductor device formed in Semiconductor substrate 100, and the type of the most described Semiconductor substrate should not limit the scope of the invention.In the present embodiment, the material of described Semiconductor substrate 100 is silicon.
The material of described mask layer 200 is silicon nitride, in the present embodiment, chemical vapor deposition method can be used to form described mask layer 200.Described mask layer 200 is also used as the stop-layer of subsequent chemical mechanical grinding technics, and the thickness of described mask layer 200 is
In the present embodiment, before forming described mask layer 200, forming silicon oxide layer 201 on described Semiconductor substrate 100 surface, described silicon oxide layer 201 provides cushion for the mask layer 200 being subsequently formed.If mask layer 200 is formed directly in described Semiconductor substrate, owing to stress relatively conference causes dislocation on Semiconductor substrate 100 surface, and silicon oxide layer 201 is formed between Semiconductor substrate 100 and mask layer 200, avoid formation mask layer 200 the most on a semiconductor substrate 100 and can produce the shortcoming of dislocation, and silicon oxide layer 201 is also used as the etching stop layer in subsequent etching mask layer 200 step.
Refer to Fig. 6, etch described mask layer 200 and silicon oxide layer 201, form opening 202.
The method forming described opening 202 includes: form graphical photoresist layer on described mask layer 200 surface, and described graphical photoresist layer defines the size of follow-up fleet plough groove isolation structure to be formed and is positioned at, and exposes the surface of part mask layer 200；With described graphical photoresist layer as mask, using dry etch process to etch described mask layer 202 and silicon oxide layer 201, until exposing the surface of Semiconductor substrate 100, forming opening 202.Use cineration technics or chemical reagent to remove technique after forming described opening 202 and remove photoetching offset plate figure.In the present embodiment, described dry etch process is plasma etch process.
The width of described opening 202 can be 5nm～100nm, and the position of described opening 202 defines the position of the fleet plough groove isolation structure being subsequently formed.Distance between adjacent apertures 202 and the width of opening 202, can adjust according to the Density Distribution of the integrated level of side circuit and circuit.
Refer to Fig. 7, etch described Semiconductor substrate 100 along described opening 202, in described Semiconductor substrate 100, form groove 300.
Use dry etch process, etch described Semiconductor substrate 100 along described opening 202, form groove 300.
In the present embodiment, using plasma etching technics etches described Semiconductor substrate 100.The degree of depth of described groove 300 can be 10nm～200nm, follow-up filled media material in described groove 300, forms fleet plough groove isolation structure.
In the present embodiment, owing to the etching gas exchange rate at groove 300 top is very fast, etch rate is relatively big, forms the groove 300 of sidewall slope；In other embodiments of the invention, the groove that sidewall is vertical can be formed by adjusting the parameter of etching technics, or there is the groove of Σ shape sidewall.
Refer to Fig. 8, form the first initial medium layer 301 in described groove 300 (refer to Fig. 7), described first initial medium layer 301 surface flushes with mask layer 200 surface.
The method forming described first initial medium layer 301 includes: deposit first medium material layer with mask layer 200 surface in described groove 300, and described first medium material layer fills full described groove 300 and mask layer 300 opening；With described mask layer 300 as stop-layer, described first medium material layer is planarized, forms the first initial medium layer 301, make the surface of described first initial medium layer 301 flush with mask layer 200 surface.Can use chemical mechanical milling tech that described first medium material layer is planarized.
In the present embodiment, the material of described first initial medium layer 301 is silicon oxide.Chemical vapor deposition method, high-density plasma deposition process or high-aspect-ratio depositing operation can be used to form described first medium material layer.
In other embodiments of the invention, before forming described first medium material layer, protection oxide layer can be formed in the inner wall surface of described groove 300.During owing to directly filling first medium material in described groove 300, first medium material is poor with the sidewall silicon adhesion of groove 300, cavity easily occurs, and described protection oxide layer is higher with the adhesiveness of first medium material, can avoid producing cavity.And; described protection oxide layer can also avoid first medium material layer not mate the bigger stress of formation with the silicon of groove 300 sidewall; and damage recess sidewall surface caused when etching described Semiconductor substrate and forming groove can be repaired, improve the isolation effect of the fleet plough groove isolation structure being subsequently formed.The formation process of described protection oxide layer can be chemical vapor deposition method.
Refer to Fig. 9, etch described first initial medium layer 301, form first medium layer 302, make described first medium layer 302 surface less than Semiconductor substrate 100 surface.
Wet method or dry etch process is used to etch described first initial medium layer 301 (refer to Fig. 8), the height making described first initial medium layer 301 declines, make the surface of the first medium layer 302 after finally etching less than Semiconductor substrate 100 surface, it is simple to follow-up described groove 300 (refer to Fig. 7) in formation be positioned at the second dielectric layer on first medium layer 302 surface.
In the present embodiment, using dry etch process to etch described first initial medium layer 301, the etching gas that described dry etch process uses includes CF4、C2F6Or CHF3Deng, described etching gas flow is 20sccm～200sccm.
Distance between surface and Semiconductor substrate 100 surface of the first medium layer 302 after described etching is less than 20nm, the consistency of thickness of the distance between surface and Semiconductor substrate 100 surface of described first medium layer 302 and the second dielectric layer ultimately formed.
Refer to Figure 10, first medium layer 302 surface after described etching forms the second initial medium layer 303, described second initial medium layer 303 surface flushes with mask layer 200 surface, and the wet-etch rate of described second initial medium layer 303 is less than the wet-etch rate of first medium layer 302.
The material of described second initial medium layer 303 can be SiCO, SiON, SiCON or SiC.
The method forming described second initial medium layer 303 includes: first medium layer 302 surface and mask layer 200 surface after described etching form second medium material layer, and described second medium material layer fills full described groove and opening；With described mask layer 200 as stop-layer, described second medium material layer is planarized, forms the second initial medium layer 303, make the surface of described second initial medium layer 303 flush with mask layer 200 surface.Can use chemical mechanical milling tech that described second medium material layer is planarized.
Boiler tube deposition or chemical vapor deposition method can be used to form described second medium material layer.Concrete, the material of the layer of second medium material described in the present embodiment is SiCO, using plasma strengthens chemical vapor deposition method and forms described second medium material layer, and the reacting gas of employing includes that silicon-containing gas, described silicon-containing gas include: silane (SiH4), one or more in orthosilicic acid tetrem fat (TEOS) or trimethylsilane, and oxygen-containing gas, described oxygen-containing gas includes oxygen, nitrous oxide, nitrogen monoxide, carbon monoxide, carbon dioxide etc..Wherein the flow of silicon-containing gas is 20sccm～200sccm, and the flow of oxygen-containing gas is 20sccm～300sccm, and pressure is 500mTorr～10Torr, and temperature is 300 DEG C～500 DEG C, and power is 50W～1000W.
The wet-etch rate of described second initial medium layer 303 is less than the wet-etch rate of first medium layer 302, thus in follow-up wet etching or cleaning process, the etch rate of described second initial medium layer 303 is slower.
Refer to Figure 11, etch described second initial medium layer 303 (refer to Figure 10), form second dielectric layer 304, make described second dielectric layer 304 surface flush with Semiconductor substrate 100 surface.
Wet method or dry etch process can be used to etch described second initial medium layer 303, form second dielectric layer 304.
In the present embodiment, dry etch process is used to etch described second initial medium layer 303.
The etching gas that described dry etch process uses is NF3And NH3, NF3With NH3Flow-rate ratio be 1:20～5:1, etching temperature is 40 degrees Celsius～80 degrees Celsius, and pressure is 0.5 torr～50 torr, power be less than 100 watts, frequency be less than 100 KHz.The energy of plasma of described etching technics is relatively low, and the etching injury causing the second initial medium layer 303 is less, it is possible to form the second dielectric layer 304 that surface is smooth so that the thickness of second dielectric layer 304 is evenly.
In other embodiments of the invention, it would however also be possible to employ wet-etching technology etches described second initial medium layer 303.
After etching described second initial medium layer 303; the surface of the second dielectric layer 304 formed flushes with Semiconductor substrate 100 surface; the thickness of described second dielectric layer 304 is 2nm～20nm; described thickness can keep out the corrosion of hydrofluoric acid solution in follow-up wet etching or cleaning, the first medium layer 302 below protection.
Owing to the material of second dielectric layer 304 etch rate in wet etching or cleaning is more than the etch rate of first medium layer 302, so compared with prior art, in same amount of solution, the etch amount that second dielectric layer 304 is subject to is less, more resistant to corrosion.
Refer to Figure 12, remove described mask layer 200 (refer to Figure 11).
Wet-etching technology is used to remove described mask layer 200, owing to, in the present embodiment, the material of described mask layer 200 is silicon nitride, so the etching solution that described wet-etching technology uses is phosphoric acid solution.
In other embodiments of the invention, it would however also be possible to employ dry etch process removes described mask layer 200.
In the present embodiment; retain described silicon oxide layer 201; described silicon oxide layer 201 can as follow-up on a semiconductor substrate formed semiconductor device time; the protective layer carrying out ion implanting avoids ion implanting to there being semiconductor substrate surface to cause damage; after performing the ion implant, then remove described silicon oxide layer 201.In other embodiments of the invention, it is also possible to after removing described mask layer 200, continue to use wet-etching technology to remove described silicon oxide layer 201.
Refer to Figure 13, for the generalized section of secant BB ' along Figure 12.
In described fleet plough groove isolation structure, first medium layer 302 is positioned at Semiconductor substrate 100 surface of bottom portion of groove, described second dielectric layer 304 is positioned at first medium layer 302 surface.
Refer to Figure 14, in described Figure 13 based on schematic diagram, form grid structure on described second dielectric layer 304 surface.
In embodiments of the invention, to form two grid structures on described second dielectric layer 304 surface as example.In other embodiments of the invention, one or more grid structure can be formed on described second dielectric layer 304 surface.
Described grid structure includes gate dielectric layer 401, is positioned at the grid 402 on described gate dielectric layer 401 surface.In the present embodiment, the sidewall surfaces of described gate dielectric layer 401 and grid 402 is formed with side wall 403.Described grid 402 top is coated with Patterned masking layer 400.
Described grid structure can also partly be positioned at Semiconductor substrate 100 surface of described second dielectric layer 304 both sides.
Concrete, the method forming described grid structure includes: after the gate material layers that described second dielectric layer 304 surface sequentially forms gate dielectric material layer and is positioned at described gate dielectric material layer surface, Patterned masking layer, described Patterned masking layer covering part gate material layers is formed on described gate material layers surface；With described Patterned masking layer as mask, etch described gate material layers and gate dielectric material layer to second dielectric layer 304 surface, form described gate dielectric layer 401, grid 402；Then side wall 403 is formed at described grid 402 and gate dielectric layer 401 sidewall surfaces.
In other embodiments of the invention, described gate dielectric material layer and gate material layers also cover Semiconductor substrate 100 surface, etch told gate dielectric material layer and gate material layers, form grid structure in described second dielectric layer 304 and Semiconductor substrate 100 surface simultaneously.
Refer to Figure 15, Figure 15 be said method formed semiconductor structure in the generalized section after follow-up wet etching or cleaning.
Hydrofluoric acid solution is mostly used owing to described wet etching or cleaning use, and described hydrofluoric acid solution is the lowest for the etch rate of second dielectric layer 304, so, can reduce in subsequent process, being cleaned multiple times or etching through hydrofluoric acid solution, exposes the risk of grid 402.During the hydrofluoric acid clean of amount same as the prior art, owing to described second dielectric layer 304 is compared with the silicon oxide that prior art uses, etch rate reduces, although there will be portion concave, but will not expose gate dielectric layer 401 and grid 402.
In embodiments of the invention, after forming groove in Semiconductor substrate, in described groove, form first medium layer, then etch described first medium layer, make the surface of described first medium layer less than semiconductor substrate surface；Then form second dielectric layer on described first medium layer surface, make described second dielectric layer surface flush with semiconductor substrate surface.The wet-etch rate of described second dielectric layer is less than the wet-etch rate of first medium layer.So that described semiconductor structure is in follow-up wet etching and cleaning process, described second dielectric layer subject to corrosion is less, will not expose the bottom of the grid structure formed on second dielectric layer surface.
Embodiments of the invention also provide for a kind of semiconductor structure.
Refer to Figure 12, described semiconductor structure includes: Semiconductor substrate 100, is positioned at the groove of described Semiconductor substrate 100；Being positioned at the first medium layer 302 of described groove, the surface of described first medium layer 302 is less than Semiconductor substrate 100 surface；Being positioned at the second dielectric layer 304 on described first medium layer 302 surface, the surface of described second dielectric layer 304 flushes with Semiconductor substrate 100 surface, and the wet-etch rate of described second dielectric layer 304 is less than the wet-etch rate of first medium layer 302.
The material of described second dielectric layer 304 is SiCO, SiON, SiCON or SiC, and the thickness of described second dielectric layer 304 is 2nm～20nm.In the present embodiment, the material of described second dielectric layer 304 is SiC.
The material of described first medium layer 302 is silicon oxide.
Refer to Figure 14, described semiconductor structure also includes: be positioned at the grid structure on second dielectric layer 304 surface, and described grid structure includes gate dielectric layer 401, is positioned at the grid 402 on described gate dielectric layer 401 surface.In the present embodiment, the sidewall surfaces of described gate dielectric layer 401 and grid 402 is formed with side wall 403.Described grid 402 top is coated with Patterned masking layer 400.
Described first medium layer 302 and second dielectric layer 304 are as the fleet plough groove isolation structure in Semiconductor substrate 100.Wet-etch rate due to second dielectric layer 304 is less than the wet-etch rate of first medium layer 302, so that described semiconductor structure is in follow-up wet etching and cleaning process, described second dielectric layer 304 subject to corrosion is less, will not expose the bottom of the grid structure formed on second dielectric layer 304 surface.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. the forming method of a semiconductor structure, it is characterised in that including:
Thering is provided Semiconductor substrate, described semiconductor substrate surface is formed with the mask layer with opening；
Etch described Semiconductor substrate along described opening, in described Semiconductor substrate, form groove；
Forming the first initial medium layer in described groove, described first initial medium layer surface flushes with mask layer surface；
Etch described first initial medium layer, form first medium layer, make described first medium layer surface less than semiconductor substrate surface；
First medium layer surface after described etching forms the second initial medium layer, and described second initial medium layer surface flushes with mask layer surface, and the wet-etch rate of described second initial medium layer is less than the wet-etch rate of first medium layer；
Etch described second initial medium layer, form second dielectric layer, make described second dielectric layer surface flush with semiconductor substrate surface；
Remove described mask layer.
The forming method of semiconductor structure the most according to claim 1, it is characterised in that the material of described second dielectric layer is SiCO, SiON, SiCON or SiC.
The forming method of semiconductor structure the most according to claim 1, it is characterised in that the thickness of described second dielectric layer is 2nm～20nm.
The forming method of semiconductor structure the most according to claim 1, it is characterized in that, the method forming described second initial medium layer includes: form second medium material layer on described first medium layer surface and mask layer surface, and described second medium material layer fills full described groove and opening；With described mask layer as stop-layer, described second medium material layer is planarized, forms the second initial medium layer, make the surface of described second initial medium layer flush with mask layer surface.
The forming method of semiconductor structure the most according to claim 4, it is characterised in that use boiler tube deposition or chemical vapor deposition method to form described second medium material layer.
The forming method of semiconductor structure the most according to claim 1, it is characterised in that the distance between described first medium layer and semiconductor substrate surface is less than 20nm.
The forming method of semiconductor structure the most according to claim 1, it is characterised in that the material of described first medium layer is silicon oxide.
The forming method of semiconductor structure the most according to claim 1, it is characterized in that, the method forming described first initial medium layer includes: deposit first medium material layer with mask layer surface in described groove, and described first medium material layer fills full described groove and mask layer opening；With described mask layer as stop-layer, described first medium material layer is planarized, forms the first initial medium layer, make the surface of described first initial medium layer flush with mask layer surface.
The forming method of semiconductor structure the most according to claim 8, it is characterised in that use chemical vapor deposition method, high-density plasma deposition process or high-aspect-ratio depositing operation to form described first medium material layer.
The forming method of semiconductor structure the most according to claim 1, it is characterised in that use wet method or dry etch process to etch described second initial medium layer, form second dielectric layer.
The forming method of 11. semiconductor structures according to claim 10, it is characterised in that the etching gas that described dry etch process uses includes NF3And NH3, NF3With NH3Flow-rate ratio be 1:20～5:1, etching temperature is 40 degrees Celsius～80 degrees Celsius, and pressure is 0.5 torr～50 torr, power be less than 100 watts, frequency be less than 100 KHz.
The forming method of 12. semiconductor structures according to claim 1, it is characterised in that the material of described mask layer is silicon nitride.
The forming method of 13. semiconductor structures according to claim 12, it is characterised in that using wet-etching technology to remove described mask layer, the etching solution that described wet-etching technology uses is phosphoric acid solution.
The forming method of 14. semiconductor structures according to claim 1, it is characterised in that between described mask layer and Semiconductor substrate, there is silicon oxide layer.
The forming method of 15. semiconductor structures according to claim 1, it is characterised in that also include, forms grid structure on described second dielectric layer surface.
16. 1 kinds of semiconductor structures, it is characterised in that including:
Semiconductor substrate；
It is positioned at the groove of described Semiconductor substrate；
Being positioned at the first medium layer of described groove, the surface of described first medium layer is less than semiconductor substrate surface；
Being positioned at the second dielectric layer on described first medium layer surface, the surface of described second dielectric layer flushes with semiconductor substrate surface, and the wet-etch rate of described second dielectric layer is less than the wet-etch rate of first medium layer.
17. semiconductor structures according to claim 16, it is characterised in that the material of described second dielectric layer is SiCO, SiON, SiCON or SiC.
18. semiconductor structures according to claim 16, it is characterised in that the thickness of described second dielectric layer is 2nm～20nm.
19. semiconductor structures according to claim 16, it is characterised in that the material of described first medium layer is silicon oxide.
20. semiconductor structures according to claim 16, it is characterised in that also include: be positioned at the grid structure on second dielectric layer surface.
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| CN113488430A (en) * | 2018-04-03 | 2021-10-08 | 长鑫存储技术有限公司 | Method for forming self-aligned trench |
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| US20030199151A1 (en) * | 2002-04-18 | 2003-10-23 | Nanya Technology Corporation | Method of fabricating a shallow trench isolation structure |
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| KR100868656B1 (en) * | 2007-06-26 | 2008-11-12 | 주식회사 동부하이텍 | Method for fabricating semiconductor device |
| CN101930941A (en) * | 2010-07-30 | 2010-12-29 | 上海宏力半导体制造有限公司 | Manufacturing method of shallow trench isolation structure |
| CN104103516A (en) * | 2013-04-02 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove isolation structure and formation method thereof |
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| US20030199151A1 (en) * | 2002-04-18 | 2003-10-23 | Nanya Technology Corporation | Method of fabricating a shallow trench isolation structure |
| US20050167778A1 (en) * | 2004-02-03 | 2005-08-04 | Shin-Hye Kim | Shallow trench isolation structure with converted liner layer |
| KR100868656B1 (en) * | 2007-06-26 | 2008-11-12 | 주식회사 동부하이텍 | Method for fabricating semiconductor device |
| CN101930941A (en) * | 2010-07-30 | 2010-12-29 | 上海宏力半导体制造有限公司 | Manufacturing method of shallow trench isolation structure |
| CN104103516A (en) * | 2013-04-02 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove isolation structure and formation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113488430A (en) * | 2018-04-03 | 2021-10-08 | 长鑫存储技术有限公司 | Method for forming self-aligned trench |
| CN113488430B (en) * | 2018-04-03 | 2023-04-25 | 长鑫存储技术有限公司 | Forming method of self-aligned groove |
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