CN109872953B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN109872953B CN109872953B CN201711262127.0A CN201711262127A CN109872953B CN 109872953 B CN109872953 B CN 109872953B CN 201711262127 A CN201711262127 A CN 201711262127A CN 109872953 B CN109872953 B CN 109872953B
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Abstract
A semiconductor device and a method of forming the same, the method comprising: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a fin part and a pseudo gate structure crossing the fin part; forming a side wall material layer on the fin part and the pseudo gate structure, wherein the side wall material layer covers the side wall and the top surface of the pseudo gate structure and the side wall and the top surface of the fin part; after the side wall material layer is formed, forming a dielectric layer on the surface of the side wall material layer, wherein the top surface of the dielectric layer is lower than or flush with the top surface of the fin part, and the top surface of the fin part is exposed; after the dielectric layer is formed, forming grooves in the fin parts on two sides of the pseudo gate structure, wherein the grooves expose partial side walls of the side wall material layer; carrying out surface cleaning treatment on the bottom of the groove; and after the surface of the bottom of the groove is cleaned, forming a source-drain doped layer in the groove. The method improves the performance of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. The device is widely used as the most basic semiconductor device at present, and the traditional planar device has weak control capability on channel current, short channel effect is generated to cause leakage current, and finally the electrical performance of the semiconductor device is influenced.
In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the semiconductor device comprises a fin part and an isolation layer, wherein the fin part and the isolation layer are positioned on the surface of a semiconductor substrate, the isolation layer covers part of the side wall of the fin part, and the surface of the isolation layer is lower than the top of the fin part; the grid electrode structures are positioned on the surface of the isolation layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, the performance of the semiconductor device formed by the existing method for forming the semiconductor device is poor.
Disclosure of Invention
The invention aims to provide a semiconductor device and a forming method thereof, which can optimize the performance of the semiconductor device.
In order to solve the above technical problem, the present invention provides a method for forming a semiconductor device, including: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a fin part and a pseudo gate structure crossing the fin part; forming a side wall material layer on the fin part and the pseudo gate structure, wherein the side wall material layer covers the side wall and the top surface of the pseudo gate structure and the side wall and the top surface of the fin part; after the side wall material layer is formed, forming a dielectric layer on the surface of the side wall material layer, wherein the top surface of the dielectric layer is lower than or flush with the top surface of the fin part, and the top surface of the fin part is exposed; after the dielectric layer is formed, forming grooves in the fin parts on two sides of the pseudo gate structure, wherein the grooves expose partial side walls of the side wall material layer; carrying out surface cleaning treatment on the bottom of the groove; and after the surface of the bottom of the groove is cleaned, forming a source-drain doped layer in the groove.
Optionally, the step of forming the groove in the fin portions on the two sides of the dummy gate structure includes: after the dielectric layer is formed, removing the side wall material layers on the tops of the fin parts on two sides of the pseudo gate structure; and after removing the side wall material layers on the tops of the fin parts at two sides of the pseudo gate structure, forming grooves in the fin parts at two sides of the pseudo gate structure.
Optionally, the surface cleaning process includes a wet etching process or a dry etching process.
Optionally, the wet etching process parameters include: a hydrofluoric acid solution with a volume ratio of the HF to the H2O of 1/3000-1/100.
Optionally, the dry etching parameters of the surface cleaning process include: the gas includes NH3 gas and NF3Gas and He, NH3The flow rate of the gas is 200 sccm-500 sccm, NF3The flow rate of the gas is 20 sccm-200 sccm, the flow rate of He is 600 sccm-2000 sccm, the pressure is 2-10 torr, and the time is 20-100 seconds.
Optionally, the material of the side wall material layer includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
Optionally, the thickness of the side wall material layer is 25 angstroms to 200 angstroms.
Optionally, the forming step of the dielectric layer includes: after the side wall material layer is formed, an initial dielectric layer is formed on the surface of the side wall material layer; and etching the initial dielectric layer back until the top surface of the fin part is exposed to form the dielectric layer.
Optionally, the surface of the dielectric layer is flush with the top surface of the fin portion.
Optionally, a distance between the surface of the dielectric layer and the surface of the top of the fin portion is a first distance, a distance between the top of the fin portion and the surface of the isolation layer is a second distance, and a height of the first distance is less than a quarter of the second distance.
Optionally, the surface of the dielectric layer is lower than the top surface of the fin portion, and the distance between the surface of the dielectric layer and the top surface of the fin portion is 2 nm-20 nm.
Optionally, the dummy gate structure includes: the dummy gate structure comprises a dummy gate dielectric layer, a dummy gate layer positioned on the dummy gate dielectric layer and a first side wall, wherein the first side wall covers the side wall of the dummy gate layer.
Optionally, the process for forming the source-drain doping layer includes an epitaxial growth process.
Optionally, in the process of forming the source-drain doping layer by epitaxial growth, in-situ doping is performed on the source-drain doping layer, and first ions are doped in the source-drain doping layer.
Optionally, when the gate structure is used to form a P-type device, the source-drain doping layer is made of a material including silicon germanium doped with first ions, and the conductivity type of the first ions is P-type; when the grid structure is used for forming an N-type device, the material of the source-drain doping layer comprises silicon doped with first ions, and the conductivity type of the first ions is N type.
Optionally, the method further includes: after the source-drain doped layer is formed, removing the dielectric layer and the side wall material layer to expose the surface of the original doped layer; after the dielectric layer and the side wall material layer are removed, forming a second dielectric layer on the fin portion, the pseudo gate structure and the source drain doping layer, wherein the second dielectric layer exposes the top surface of the pseudo gate structure; after the second dielectric layer is formed, removing the pseudo gate structure, and forming a gate opening in the second dielectric layer; forming a gate structure in the gate opening after forming the gate opening; after the grid structure is formed, forming openings in the second dielectric layers on two sides of the grid structure, wherein the openings expose the top surface and the side wall surface of the source drain doping layer; and after the opening is formed, forming a plug in the opening, wherein the plug covers the top surface and the side wall surface of the source drain doping layer.
Correspondingly, the invention also provides a semiconductor device formed by adopting any one of the methods.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the forming method of the semiconductor device provided by the technical scheme of the invention, after the side wall material layer is formed, a dielectric layer is formed on the surface of the side wall material layer, and the dielectric layer covers the side wall of the fin part; performing intermediate treatment on the bottom of the groove to remove the oxide on the surface of the fin part, wherein part of the isolation layer below the side wall material layer on the side wall of the groove can be consumed in the intermediate treatment process; the side wall material layer and the dielectric layer positioned on the surface of the side wall material layer support the side wall material layer on the side wall of the groove together, collapse of the side wall material layer on the side wall of the groove is prevented, the formed groove is complete in appearance, and the source drain doped layer formed in the groove is complete in appearance. Due to the limitation of the side wall material side layer, the shape of the formed source-drain doping layer is regular, the contact area between the subsequently formed full-contact plug and the source-drain doping layer is increased, the contact resistance is reduced, the current which can be borne by the semiconductor device is increased, and the performance of the semiconductor device is improved.
Drawings
Fig. 1 to 5 are schematic structural views of a semiconductor device;
fig. 6 to 15 are schematic structural views illustrating a method of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of semiconductor devices formed by the prior art is poor.
Fig. 1 to 5 are schematic structural views of a semiconductor device.
Referring to fig. 1 and 2, fig. 2 is a cross-sectional view taken along a cutting line N-N1 in fig. 1, providing a semiconductor substrate 100 having a fin 110 and an isolation structure 101 thereon, wherein the isolation structure 101 covers a portion of a sidewall of the fin 110; and forming a dummy gate structure crossing the fin portion on the fin portion, wherein the dummy gate structure comprises a dummy gate dielectric layer 102 positioned on the surface of the semiconductor substrate, a dummy gate layer 120 positioned on the dummy gate dielectric layer 102, a protection layer 103 positioned on the surface of the dummy gate layer 120, and a first side wall 130 positioned on the side wall of the dummy gate layer, and the first side wall 130 is positioned on the dummy gate dielectric layer 102. A second layer of sidewall material 140 is formed over the dummy gate structure, fin 110, and isolation structure 101.
Referring to fig. 3, the cross-sectional directions of fig. 3 and fig. 2 are the same, after the second sidewall material layer 140 is formed, the second sidewall material layer 140 is etched back, a second sidewall 141 is formed on the sidewall of the first sidewall 130, and the second sidewall 141 is also located on the sidewall of the fin 110; after the second sidewalls 141 are formed, first recesses 104 are formed in the fin portions at two sides of the dummy gate structure.
Referring to fig. 4, after the first groove 104 is formed, a surface cleaning process is performed on the bottom surface of the first groove 104 to form a second groove 105, and a portion of the bottom surface of the second groove 105 is located at the bottom of the second sidewall 141.
Referring to fig. 5, after forming the second recess 105, a source-drain doping layer 150 is formed in the second recess 105.
However, the performance of the semiconductor device formed by the above method is poor, and with the development of semiconductor technology, the critical dimension of the semiconductor device is smaller and smaller, and the thickness of the corresponding sidewall is correspondingly reduced. Generally, the cleaning process is a wet etching process, since the intermediate processing process for the bottom of the first groove 104 is wet etching, the wet etching is isotropic, the oxide on the surface of the fin part is cleaned, simultaneously, the isolation structure is etched along the direction vertical to the extension direction of the fin part and parallel to the plane direction of the semiconductor substrate, such that the distance between the bottom of the second recess 105 and the first recess 104 increases along the direction perpendicular to the extending direction of the fin and parallel to the plane of the semiconductor substrate, that is, the isolation structure 101 at the bottom of the second sidewall 141 is removed, the second sidewall 141 itself has a smaller thickness, and after the isolation structure 101 for supporting at the bottom is removed, the bottom of the second sidewall 141 is prone to collapse due to loss of support, and the collapse of the second sidewall 141 may cause that a regular source-drain doping layer cannot be formed, which affects the performance of a subsequently formed semiconductor device.
In order to solve the technical problems, according to the technical scheme, the dielectric layer is formed on the surface of the side wall material layer, and the dielectric layer and the side wall material layer are supported together, so that collapse of the side wall material layer on the side wall of the groove is prevented, the formed groove is complete in appearance, the source drain doping layer formed in the groove is complete in appearance, and performance of a device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 6 to 15 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 6, a semiconductor substrate 200 is provided, wherein the semiconductor substrate 200 has a fin portion 210 thereon.
In this embodiment, the material of the semiconductor substrate 200 is monocrystalline silicon. The semiconductor substrate 200 may also be polysilicon or amorphous silicon. The material of the semiconductor substrate 200 may also be germanium, silicon germanium, gallium arsenide, or other semiconductor materials.
In this embodiment, the fin 210 is formed by patterning the semiconductor substrate 200. In other embodiments, it may be: a fin material layer is formed on the semiconductor substrate and then patterned to form a fin 210.
In this embodiment, the material of the fin 210 is monocrystalline silicon. In other embodiments, the material of the fin is single crystal silicon germanium or other semiconductor materials. The number of the fins 210 is one or more.
In this embodiment, the method further includes: an isolation structure 201 is formed on the semiconductor substrate 200, and the isolation structure 201 covers part of the sidewall surface of the fin 210. The material of the isolation structure 210 includes silicon oxide.
And forming a pseudo gate structure crossing the fin structure, wherein the pseudo gate structure covers part of the top surface and part of the side wall surface of the fin structure. The pseudo gate structure comprises a pseudo gate structure body and a first side wall covering the side wall of the pseudo gate structure body, and the pseudo gate structure body comprises: the first side wall covers the side wall of the dummy gate layer. Please refer to fig. 7 and 8.
Referring to fig. 7, a dummy gate structure body crossing the fin 210 is formed on the semiconductor substrate 200, and the dummy gate structure body covers a portion of the top surface and a portion of the sidewall surface of the fin 210.
The dummy gate structure body comprises a dummy gate dielectric layer 202 crossing the fin portion 210, a dummy gate electrode layer 220 located on the dummy gate dielectric layer 202, and a protection layer 203 located on the top of the dummy gate electrode layer 220.
In this embodiment, the dummy gate dielectric layer 202 is made of silicon oxide. The dummy gate electrode layer 220 is made of polysilicon. The dummy gate dielectric layer 202 is located on a portion of the surface of the isolation structure 201, and covers a portion of the top surface and a portion of the sidewall surface of the fin 210.
The material of the protective layer 203 includes SiN, SiCN, SiBN, or SiON. In this embodiment, the material of the protection layer 203 is SiN.
Referring to fig. 8, after forming the dummy gate structure body, first sidewalls 231 are formed on sidewalls of the dummy gate electrode layer 220.
The step of forming the first sidewall 231 includes: forming a first sidewall material layer (not shown) on the isolation structure 201, the fin portion 210 and the dummy gate structure body; the first sidewall material layer is etched back until the passivation layer 203 and the dummy gate dielectric layer 202 are exposed, and a first sidewall 231 is formed on the sidewall of the dummy gate electrode layer 220.
The process for forming the first sidewall material layer is a deposition process, such as a plasma chemical vapor deposition process, an atomic layer deposition process, or a low pressure chemical vapor deposition process.
In this embodiment, a forming process of the first sidewall material layer is an atomic layer deposition process, and parameters of the atomic layer deposition process include: the gas used is SiH2Cl2And NH3The flow rate of the mixed gas is 1500 sccm-4000 sccm, the pressure is 1 mtorr-10 mtorr, the temperature is 200 ℃ -600 ℃, and the deposition times are 30-100 times.
In this embodiment, the step of forming the semiconductor device further includes: and after the first side wall is formed, carrying out ion implantation on the fin part to form a lightly doped region.
Referring to fig. 9 and 10, fig. 10 is a cross-sectional view taken along the direction N-N1 in fig. 9, after forming lightly doped regions, an initial second sidewall material layer 240 is formed on the fin 210 and the dummy gate structure.
The initial second sidewall material layer 240 is used to provide material for forming the second sidewall material layer.
The material of the initial second sidewall material layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride. In this embodiment, the material of the initial second sidewall material layer is silicon nitride.
The forming process of the initial second sidewall material layer comprises a deposition process, such as a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the forming process of the second sidewall material layer is an atomic layer deposition process, and the atomic layer deposition process parameters include: the gas used is SiH2Cl2And NH3The flow rate of the mixed gas is 1500 sccm-4000 sccm, the pressure is 1 mtorr-10 mtorr, the temperature is 200 ℃ -600 ℃, and the deposition times are 30-100 times.
The thickness of the initial second sidewall material layer is 25-200 angstroms.
In this embodiment, a dielectric layer is formed on the surface of the second sidewall material layer. The forming step of the dielectric layer comprises the following steps: after the side wall material layer is formed, an initial dielectric layer is formed on the surface of the side wall material layer; and etching the initial dielectric layer back to form a dielectric layer, wherein the dielectric layer is exposed out of the top surface of the fin part. Please refer to fig. 11 to fig. 12.
Referring to fig. 11, an initial dielectric layer 204 is formed on the initial second sidewall material layer 240; the initial dielectric layer 204 covers the surface of the initial second sidewall material layer 240, and the surface of the initial dielectric layer 204 is higher than the surface of the fin 210.
The initial dielectric layer 204 provides a material layer for subsequent formation of dielectric layers.
The forming process of the initial dielectric layer 204 comprises the following steps: one or more combinations of chemical vapor deposition processes, physical vapor deposition processes, and atomic layer deposition processes.
In one embodiment, the initial dielectric layer 204 is formed by a fluid chemical vapor deposition process on the second sidewall material layer 240 to form the initial dielectric layer 204. The initial dielectric layer 204 filled by the fluid chemical vapor deposition in the forming process has fluidity initially, can be fully filled between the fin portions 210, and is not easy to generate defects such as gaps, so that the electrical performance of the semiconductor structure is ensured.
Referring to fig. 12, after forming the initial dielectric layer 204, the initial dielectric layer 204 is etched back to form a dielectric layer 205, and the dielectric layer 205 is located on the surface of the initial second sidewall material layer 240 and exposes the top surface of the fin portion.
The dielectric layer 205 is formed on the surface of the initial second sidewall material layer 240, the dielectric layer 205, the fin portion 210 and the initial second sidewall material layer form an integral film layer with thickness, a groove is formed in the integral film layer subsequently, the side wall of the groove exposes the second sidewall material layer, the groove exposes part of the bottom surface of the second sidewall material layer, and due to cohesion between the integral film layers, even if the bottom of the second sidewall material layer in the height direction of the fin portion loses support, the original appearance of the second sidewall material layer is maintained due to the characteristics of the integral film layer, so that the appearance of the groove is complete, the source-drain doping layer formed subsequently is also regular in shape, and the contact resistance with the source-drain doping layer is smaller when a full contact plug is formed subsequently, and the performance of the device is improved.
The material of the dielectric layer 205 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the dielectric layer 205 is made of silicon oxide.
The process for etching back the initial dielectric layer 204 is a dry etching process, and the dry etching process parameters include: the gas used comprises CH4Gas, CHF3Gas, CH4The flow rate of the gas is 8sccm to 500sccm, CHF3The flow rate of the gas is 30 sccm-200 sccm, the pressure of the chamber is 10 mtorr-2000 mtorr, the radio frequency power is 100W-1300W, the direct current is 80V-500V, and the time is 4 seconds-50 seconds.
In this embodiment, the surface of the dielectric layer 205 is flush with the top surface of the fin portion 210, and at this time, the sidewall of the second sidewall material layer 241 is the highest, so that it can be ensured that the volume of the subsequently formed source-drain doped layer 250 limited by the second sidewall material layer 241 is larger, thereby reducing the contact resistance and further improving the performance of the device.
In other embodiments, the surface of the dielectric layer 205 is lower than the top surface of the fin 210, the distance between the surface of the dielectric layer 205 and the top surface of the fin 210 is a first distance, and the first distance is 2nm to 20 nm.
When the first distance is greater than 20nm, the thickness of the dielectric layer is too thin, which has a limited supporting effect on the second sidewall material layer 241, and it cannot be ensured that the second sidewall material layer 241 of the subsequently formed groove sidewall does not collapse.
Referring to fig. 13, after forming the dielectric layer 205, a first groove 206 is formed in the fin 210 at two sides of the dummy gate structure, and the first groove 206 exposes the sidewall of the second sidewall material layer 241.
The step of forming the first recess 206 in the fin 210 on both sides of the dummy gate structure includes: after the dielectric layer is formed 205, removing the initial second sidewall material layer 240 on the top of the fin portion 210 on both sides of the dummy gate structure to form a second sidewall material layer 241; after the second sidewall material layer 241 is formed, the fin portions 210 at two sides of the dummy gate structure are removed, and a first groove 206 is formed.
The process of removing the initial second sidewall material layer 240 on the tops of the fin portions 210 on both sides of the dummy gate structure is a dry etching process, and the dry etching process parameters include: the gas used comprises CF4Gas, CH3F gas and O2，CF4The flow rate of the gas is 5 sccm-100 sccm, CH3The flow rate of the F gas is 8sccm to 50sccm, and O2The flow rate of the gas source is 10-100 sccm, the pressure of the chamber is 10-2000 mtorr, the radio frequency power is 50-300W, the direct current is 30-100V, and the time is 4-50 seconds.
The process parameters for removing the fin portions 210 on the two sides of the dummy gate structure include: the first stage using CF4And H2Mixed gas of gases, CF4The flow rate is 10sccm to 30sccm, H2The flow rate is 10 sccm-130 sccm, the time is 7s, and the temperature is 70 ℃; second stage using a channel comprising CH3F gas, O2Mixed gas of He and CH3F flow rate is 60 sccm-200 sccm, O2The flow rate is 50 sccm-115 sccm, the He flow rate is 50 sccm-120 sccm, the time is 5 seconds-15 seconds, and the temperature is 35 ℃ -75 ℃.
Referring to fig. 14, after forming the first groove 206, an intermediate process is performed on the bottom of the first groove 206 to form a second groove 207.
The first groove 206 is subsequently used for forming a source-drain doping layer, the source-drain doping layer is formed by an epitaxial growth process, and the surface of an epitaxial substrate needs to be clean and free of impurities, so that the surface of the fin portion 210 at the bottom of the first groove 206 needs to be subjected to intermediate processing, and the surface of the fin portion 210 is clean. The impurities on the surface of the fin 210 are mainly oxides, so the surface oxides need to be removed.
In this embodiment, the intermediate treatment process is a SiCoNi process, and the process parameters include: the gas used comprises NH3Gas, NF3Gas and He, NH3The flow rate of the gas is 200 sccm-500 sccm, NF3The flow rate of the gas is 20sccm to 200sccm, and the flow rate of the He is 600sccm to 2000sccmm, the pressure is 2to 10torr, and the time is 20 to 100 seconds.
In an embodiment, the intermediate processing process includes a wet etching process, and the parameters of the wet etching process include: HF and H2A hydrofluoric acid solution with the volume ratio of O being 1/3000-1/100.
Performing intermediate treatment on the bottom of the first recess 206 to remove the oxide on the surface of the fin 210, wherein in the intermediate treatment process, a part of the isolation layer below the sidewall material layer on the sidewall of the first recess 206 is consumed to form a second recess 207; the second sidewall material layer 241 and the dielectric layer 205 on the surface of the second sidewall material layer 241 jointly support the second sidewall material layer 241 on the sidewall of the second groove 207, so that the collapse of the second sidewall material layer 241 on the sidewall of the second groove 207 is prevented, the formed second groove 207 has a complete shape, the shape rule of the subsequently formed source-drain doping layer 250 is ensured, the contact area between the subsequently formed full contact plug and the source-drain doping layer 250 is increased, the contact resistance is reduced, the current bearable by the semiconductor device is increased, and the performance of the semiconductor device is improved.
Referring to fig. 15, a source-drain doped layer 250 is formed in the second recess 207.
The process for forming the source-drain doping layer 250 includes an epitaxial growth process, and in the process of forming the source-drain doping layer 250 through epitaxial growth, the process further includes in-situ doping the source-drain doping layer 250, and doping first ions in the source-drain doping layer 250.
When the gate structure is used for forming a P-type device, the material of the source-drain doping layer 250 includes silicon germanium doped with first ions, and the conductivity type of the first ions is P-type; when the gate structure is used to form an N-type device, the source-drain doping layer 250 is made of silicon doped with first ions, and the conductivity type of the first ions is N-type.
After the source-drain doping layer 250 is formed, removing the dielectric layer 205 and the second side wall material layer 241 to expose the surface of the source-drain doping layer 250; after the dielectric layer 205 and the second side wall material layer 241 are removed, a second dielectric layer is formed on the fin portion 210, the dummy gate structure and the source drain doping layer 250, covers the surface of the side wall of the dummy gate structure, and exposes the surface of the top of the dummy gate structure; after the second dielectric layer is formed, removing the pseudo grid structure body to form a grid opening; forming a gate structure in the gate opening after forming the gate opening; after the gate structure is formed, forming openings in the second dielectric layers on two sides of the gate structure, wherein the openings expose the top surface and the side wall surface of the source-drain doping layer 250; after the opening is formed, a plug is formed in the opening, and the plug covers the top surface and the side wall surface of the source drain doping layer 250.
Performing intermediate treatment on the bottom of the first recess 206 to remove the oxide on the surface of the fin 210, wherein in the intermediate treatment process, a part of the isolation layer below the sidewall material layer on the sidewall of the first recess 206 is consumed to form a second recess 207; the second sidewall material layer 241 and the dielectric layer 205 jointly support the second sidewall material layer 241 of the sidewall of the second groove 207, so that collapse of the second sidewall material layer 241 of the sidewall of the second groove is prevented, the formed second groove 207 is complete in appearance, the appearance rule of the subsequently formed source-drain doping layer 250 is guaranteed, the contact area between the formed full-contact plug and the source-drain doping layer 250 is increased, the contact resistance is reduced, the current bearable by a semiconductor device is increased, and the performance of the semiconductor device is improved.
Accordingly, the present embodiment also provides a semiconductor device formed by the above method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a fin part and a pseudo gate structure crossing the fin part;
forming a side wall material layer on the fin part and the pseudo gate structure, wherein the side wall material layer covers the side wall and the top surface of the pseudo gate structure and the side wall and the top surface of the fin part;
after the side wall material layer is formed, a dielectric layer is formed on the surface of the side wall material layer, the dielectric layer is filled between adjacent fin parts, the top surface of the dielectric layer is lower than or level with the top surface of the fin part, and the top surface of the fin part is exposed;
after the dielectric layer is formed, forming grooves in fin parts on two sides of the pseudo gate structure, wherein the bottoms of the grooves are lower than the bottoms of the side wall material layers, and the side walls parallel to the extending direction of the fin parts are exposed out of the side wall material layers;
carrying out surface cleaning treatment on the bottom of the groove;
and after the surface of the bottom of the groove is cleaned, forming a source-drain doped layer in the groove.
2. The method of claim 1, wherein the step of forming the recess in the fin on both sides of the dummy gate structure comprises: after the dielectric layer is formed, removing the side wall material layers on the tops of the fin parts on two sides of the pseudo gate structure; and after removing the side wall material layers on the tops of the fin parts at two sides of the pseudo gate structure, forming grooves in the fin parts at two sides of the pseudo gate structure.
3. The method for forming a semiconductor device according to claim 1, wherein the process of the surface cleaning treatment includes a wet etching process or a dry etching process.
4. The method for forming a semiconductor device according to claim 3, wherein the process parameters of the wet etching include: HF and H2A hydrofluoric acid solution with the volume ratio of O being 1/3000-1/100.
5. The method for forming a semiconductor device according to claim 3, wherein the dry etching parameters of the surface cleaning process include: the gas used comprises NH3Gas, NF3Gas and He, NH3The flow rate of the gas is 200 sccm-500 sccm, NF3The flow rate of the gas is 20sccm to 200sccm, the flow rate of the He is 600sccm to 2000sccm, and the pressure is2to 10torr, and the time is 20 to 100 seconds.
6. The method for forming the semiconductor device according to claim 1, wherein the material of the side wall material layer comprises: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
7. The method for forming the semiconductor device according to claim 1, wherein the thickness of the side wall material layer is 25-200 angstroms.
8. The method of forming a semiconductor device of claim 1, wherein the step of forming the dielectric layer comprises: after the side wall material layer is formed, an initial dielectric layer is formed on the surface of the side wall material layer; and etching the initial dielectric layer back until the top surface of the fin part is exposed to form the dielectric layer.
9. The method of claim 8, wherein the dielectric layer surface is flush with a fin top surface.
10. The method of claim 8, wherein a distance between the surface of the dielectric layer and the top surface of the fin is a first distance, a distance between the top of the fin and the surface of the isolation layer is a second distance, and the first distance is less than one quarter of the second distance.
11. The method of claim 10, wherein the dielectric layer surface is lower than the fin top surface, and a distance between the dielectric layer surface and the fin top surface is 2nm to 20 nm.
12. The method of forming a semiconductor device of claim 1, wherein the dummy gate structure comprises: the dummy gate structure comprises a dummy gate dielectric layer, a dummy gate layer positioned on the dummy gate dielectric layer and a first side wall, wherein the first side wall covers the side wall of the dummy gate layer.
13. The method for forming the semiconductor device according to claim 1, wherein the process for forming the source-drain doping layer comprises an epitaxial growth process.
14. The method for forming the semiconductor device according to claim 13, wherein in a process of forming the source and drain doping layer by epitaxial growth, in-situ doping is performed on the source and drain doping layer, and first ions are doped in the source and drain doping layer.
15. The method of claim 14, wherein when the gate structure is used to form a P-type device, the source and drain dopant layer comprises silicon germanium doped with first ions having a conductivity type of P-type; when the grid structure is used for forming an N-type device, the material of the source-drain doping layer comprises silicon doped with first ions, and the conductivity type of the first ions is N type.
16. The method for forming a semiconductor device according to claim 1, further comprising: after the source drain doping layer is formed, removing the dielectric layer and the side wall material layer, and exposing the surface of the source drain doping layer; after the dielectric layer and the side wall material layer are removed, forming a second dielectric layer on the fin portion, the pseudo gate structure and the source drain doping layer, wherein the second dielectric layer exposes the top surface of the pseudo gate structure; after the second dielectric layer is formed, removing the pseudo gate structure, and forming a gate opening in the second dielectric layer; forming a gate structure in the gate opening after forming the gate opening; after the grid structure is formed, forming openings in the second dielectric layers on two sides of the grid structure, wherein the openings expose the top surface and the side wall surface of the source drain doping layer; and after the opening is formed, forming a plug in the opening, wherein the plug covers the top surface and the side wall surface of the source drain doping layer.
17. A semiconductor device formed by the method of any of claims 1 through 16.
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