CN110858544B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

Info

Publication number
CN110858544B
CN110858544B CN201810959497.8A CN201810959497A CN110858544B CN 110858544 B CN110858544 B CN 110858544B CN 201810959497 A CN201810959497 A CN 201810959497A CN 110858544 B CN110858544 B CN 110858544B
Authority
CN
China
Prior art keywords
side wall
forming
gate structure
fin
barrier layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810959497.8A
Other languages
Chinese (zh)
Other versions
CN110858544A (en
Inventor
周飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201810959497.8A priority Critical patent/CN110858544B/en
Publication of CN110858544A publication Critical patent/CN110858544A/en
Application granted granted Critical
Publication of CN110858544B publication Critical patent/CN110858544B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C23C16/402—Silicon dioxide
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Organic Chemistry (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Inorganic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device and method of forming the same, wherein the method of forming comprises: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a fin part, an isolation structure covering part of the side wall of the fin part and a pseudo gate structure crossing the fin part and covering part of the isolation structure; forming a first side wall on the surface of the side wall of the fin part; forming a barrier layer on the surface of the side wall of the first side wall; after the barrier layer is formed, grooves are formed in fin parts on two sides of the pseudo gate structure, and the grooves expose the first side wall; and forming a source-drain doping layer in the groove. The barrier layer can be stably positioned on the surface of the isolation structure and plays a good supporting role on the first side wall covered by the barrier layer, so that the first side wall is prevented from being separated from the isolation structure, and the formed semiconductor device is good in performance.

Description

Semiconductor device and method of forming the same
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor device and a method of forming the same.
Background
As the fabrication of integrated circuits progresses toward very large scale integrated circuits, the density of circuits therein increases, and as the number of devices contained in a chip increases, the space available for surface wiring is reduced. One solution to this problem is to use a multi-layer metal wire design, with multiple layers of insulating and conductive layers stacked on top of each other, which requires the fabrication of a large number of conductive plugs.
As device sizes shrink further, conventional planar MOS transistors have a reduced capability to control channel current, and short channel effects (short channel effect, SCE) are becoming more severe. In order to overcome the short channel effect of the device, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device. In the prior art, a conductive plug is formed on a source-drain doped region of a limited region, so that contact between adjacent source-drain doped regions is avoided, and the performance of a semiconductor device is improved.
However, when the source-drain doped region is formed by adopting the prior art, the side wall for limiting the range of forming the source-drain doped region is easily separated from the isolation structure in the pre-cleaning process, so that the performance of the formed semiconductor device is poor.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which aims to improve the performance of the semiconductor device.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a fin part, an isolation structure covering part of the side wall of the fin part and a pseudo gate structure crossing the fin part and covering part of the isolation structure; forming a first side wall on the surface of the side wall of the fin part; forming a barrier layer on the surface of the side wall of the first side wall; after the barrier layer is formed, grooves are formed in fin parts on two sides of the pseudo gate structure, and the grooves expose the first side wall; and forming a source-drain doping layer in the groove.
Optionally, the first side wall also covers the side wall surface of the pseudo gate structure.
Optionally, the method for forming the first side wall includes: forming a first side wall material layer on the isolation structure, the fin part and the pseudo gate structure; and etching back the first side wall material layer until the top surface of the fin part and the top surface of the pseudo gate structure are exposed, so as to form a first side wall covering the side wall surface of the fin part and the side wall surface of the pseudo gate structure.
Optionally, the material of the first side wall includes: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or silicon oxycarbonitride; the thickness of the first side wall is as follows: 5-15 nm.
Optionally, the blocking layer also covers the first side wall of the side wall surface of the pseudo gate structure.
Optionally, the method for forming the barrier layer includes: forming a barrier material layer on the isolation structure, the fin portion, the dummy gate structure and the first side wall; and etching the blocking material layer until the top surface of the fin part and the top surface of the pseudo gate structure are exposed, and forming a blocking layer covering the surface of the first side wall.
Optionally, the process of forming the barrier material layer includes an atomic layer deposition process; the parameters of the atomic layer deposition process include: the gas used comprises SiH 2 Cl 2 And NH 3 ，SiH 2 Cl 2 And NH 3 The flow rate of the catalyst is 1500-4000 standard milliliters/minute, the temperature is 200-600 ℃, the pressure is 1-10 mTorr, and the cycle time is 5-100 times.
Optionally, the material of the barrier layer includes: silicon oxide; the thickness of the barrier layer is as follows: 3-10 nm.
Optionally, after forming the barrier layer, before forming the groove, the method further includes: doping first ions in a part of barrier layer positioned on the side wall of the fin part by adopting a first ion implantation process; and after the first ion implantation, etching to remove the barrier layer on the side wall surface of the pseudo gate structure, wherein in the process of etching to remove the barrier layer on the side wall surface of the pseudo gate structure, the etching rate of the barrier layer on the side wall of the fin part is smaller than that of the barrier layer on the side wall of the pseudo gate structure.
Optionally, the first ion includes: silicon ions, carbon ions or germanium ions; the process parameters of the first ion implantation include: the implanted ions are silicon ions, carbon ions or germanium ions, the energy range is 1KeV to 20KeV, and the dosage range is 1.0e14atm/cm 2 ～2.0e16atm/cm 2 The inclination angle is 15-30 degrees; the direction of the first ion implantation is perpendicular to the extending direction of the fin portion.
Optionally, before forming the first side wall, the method further includes: forming a second side wall on the surface of the side wall of the fin part and the pseudo gate structure; and after the second side wall is formed, forming a lightly doped region in the fin parts at two sides of the pseudo gate structure and the second side wall.
Optionally, before forming the source-drain doped layer, the method further includes: carrying out a pre-cleaning process on the groove; the pre-cleaning process parameters comprise: the etching solution is dilute hydrofluoric acid, and the dilution ratio is 100:1-1000:1.
Optionally, the method for forming the groove includes: and etching the exposed fin parts at two sides of the pseudo gate structure by taking the pseudo gate structure and the first side wall as masks, and forming grooves in the fin parts.
Optionally, the process of etching to remove the barrier layer on the surface of the side wall of the pseudo gate structure is as follows; the parameters of the etching process include: the parameters of the etching process include: the gas adopted comprises He, NH 3 And NF (NF) 3 Wherein, the flow rate of He is 600 to 2000 standard milliliters per minute, NH 3 The flow rate of the water is 200-500 standard milliliters/minute, NF 3 The pressure is 2 to 10 Torr, and the time is 20 to 100 seconds.
Optionally, the distance from the bottom of the groove to the surface of the fin portion is: 30 nm-60 nm.
Correspondingly, the invention also provides a semiconductor device, which comprises: the semiconductor substrate is provided with a fin part, an isolation structure covering part of the side wall of the fin part and a pseudo gate structure crossing the fin part and covering part of the isolation structure; the first side wall is positioned on the surface of the side wall of the fin part; a barrier layer on a surface of the first sidewall; and grooves in the fin parts at two sides of the pseudo gate structure. And the source-drain doping layer is positioned in the groove.
Optionally, the first side wall also covers the side wall surface of the pseudo gate structure; the first side wall comprises the following materials: silicon oxide, silicon nitride or silicon oxynitride, silicon carbonitride or silicon oxycarbonitride; the thickness of the first side wall is as follows: 5-15 nm.
Optionally, the material of the barrier layer includes: silicon oxide; the thickness of the barrier layer is as follows: 3-10 nm.
Optionally, the semiconductor device further includes a second sidewall located on the surface of the sidewall of the fin portion and the dummy gate structure; and the lightly doped region is positioned in the fin parts at two sides of the pseudo gate structure and the second side wall.
Optionally, the distance from the bottom of the groove to the surface of the fin portion is: 30 nm-60 nm.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor device, a first side wall is formed on the surface of the side wall of the fin part; forming a barrier layer on the surface of the side wall of the first side wall; and after the barrier layer is formed, forming grooves in the fin parts at two sides of the pseudo gate structure. When the pre-cleaning process is performed later, a part of the isolation structure below the first side wall is etched to a certain extent. Because the barrier layer has a certain thickness, the contact area between the bottom of the barrier layer and the isolation structure is larger, and the barrier layer can still be stably positioned on the surface of the isolation structure. The blocking layer covers the side wall of the first side wall of the fin part and plays a good supporting role on the first side wall of the fin part, so that the blocking layer and the first side wall of the fin part covered by the blocking layer can still be stably positioned on the surface of the isolation structure, further, the process of forming the source-drain doped layer in the groove can be limited, and the performance of the formed semiconductor device is good.
And further, performing first ion implantation on the barrier layer of the side wall of the fin part, so that the barrier layer of the side wall of the fin part is doped with first ions. And when the etching process is carried out subsequently, the etching process has different etching rate ratios on the barrier layer of the side wall of the fin part and the barrier layer of the side wall of the pseudo gate structure, and the etching rate for removing the barrier layer of the side wall surface of the pseudo gate structure is far greater than the etching rate of the barrier layer of the side wall surface of the fin part, so that the barrier layer of the first side wall surface of the fin part can be removed while the barrier layer of the first side wall surface of the pseudo gate structure is reserved. And forming a source-drain doped layer by taking the pseudo gate structure and the first side wall as masks, so that the distance between the source-drain doped layer and a channel can be prevented from being too large, and the formation of a semiconductor device with better performance is facilitated.
Drawings
Fig. 1 to 6 are schematic structural views of steps in a semiconductor device forming process;
fig. 7 to 19 are schematic structural views illustrating steps of a method for forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background, the prior art forms semiconductor devices with poor performance.
Fig. 1 to 6 are schematic structural views of steps in a semiconductor device forming process.
Referring to fig. 1, a semiconductor substrate 100 is provided, which has a fin 101, an isolation structure 102 covering a portion of the sidewalls of the fin 101, and a dummy gate structure 110 crossing the fin 101 and covering a portion of the isolation structure 102.
Referring to fig. 2 and 3, fig. 3 is a cross-sectional view taken along a line X-X1 in fig. 2, and a sidewall 120 is formed on the fin 101 and the surface of the sidewall of the dummy gate structure 110;
referring to fig. 4, with the dummy gate structure 110 and the sidewall 120 as masks, portions of the fin portion 101 at two sides of the dummy gate structure 110 are etched away, and a recess 130 is formed in the fin portion 101.
Referring to fig. 5, after forming the recess 130, a pre-cleaning process is performed.
Referring to fig. 6, after the pre-cleaning process, a source-drain doped layer 140 is epitaxially grown in the recess 130.
The pre-cleaning process is used for removing byproducts, a natural oxide layer and other impurities on the side wall and the bottom of the groove 130 and the surface of the fin portion 101, so as to reduce impurities and defects on the side wall and the bottom of the groove 130 and the surface of the fin portion 101, thereby facilitating the subsequent epitaxial growth in the groove 130 by taking the surface of the fin portion 101 as a seed layer to form the source-drain doped layer 140.
However, the pre-cleaning process may etch the isolation structure 102 under the fin 101 sidewall to some extent while removing byproducts, native oxide layers and other impurities. Because the thickness of the fin 101 side wall 120 is smaller, the contact area between the bottom of the fin 101 side wall 120 and the isolation structure 102 is smaller, and the isolation structure 102 is easier to etch away at the portion contacting the fin 101 side wall 120, so that the fin 101 side wall 120 is easy to separate from the isolation structure 102 due to loss of support, and the morphology of the source-drain doped layer 140 cannot be limited by the fin 101 side wall 120 in the following steps, and the performance of the formed semiconductor device is poorer.
In order to solve the technical problem, the invention provides a method for forming a semiconductor device, which comprises the following steps: forming a first side wall on the surface of the side wall of the fin part; forming a barrier layer on the surface of the side wall of the first side wall; after the barrier layer is formed, grooves are formed in fin parts on two sides of the pseudo gate structure, and the grooves expose the first side wall; and forming a source-drain doping layer in the groove. The semiconductor device formed by the method has better performance.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 7 to 19 are schematic structural views illustrating steps of a method for forming a semiconductor device according to an embodiment of the present invention.
Referring to fig. 7, a semiconductor substrate 200 is provided, and the semiconductor substrate 200 has a fin 201 and an isolation structure 202 covering a portion of a sidewall of the fin 201.
The semiconductor substrate 200 may be monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the semiconductor substrate 200 may be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like; in this embodiment, the material of the semiconductor substrate 200 is silicon.
The method for forming the semiconductor substrate 200 and the fin 201 includes: providing an initial substrate (not shown), and forming a patterned first mask layer (not shown) on the initial substrate; and etching the initial substrate by taking the first mask layer as a mask to form the semiconductor substrate 200 and the fin 201 on the semiconductor substrate 200.
The isolation structures 202 are used to achieve electrical isolation between adjacent devices.
In this embodiment, the material of the isolation structure 202 is silicon oxide. In other embodiments, the isolation structure may also be made of germanium oxide or silicon oxynitride.
Referring to fig. 8, a dummy gate structure 210 is formed on a semiconductor substrate 200, the dummy gate structure 210 crossing the fin 201 and covering a portion of the isolation structure 202.
In this embodiment, the dummy gate structure 210 includes: the dummy gate dielectric layer is positioned on the substrate; the dummy gate layer is positioned on the dummy gate dielectric layer; and a second mask layer positioned on the dummy gate layer.
The method for forming the dummy gate structure 210 includes: forming a dummy gate dielectric film (not shown) and a dummy gate electrode film (not shown) on the surface of the dummy gate dielectric film on the semiconductor substrate 200, wherein the dummy gate electrode film is provided with a second mask layer (not shown) which exposes a part of the dummy gate electrode film; and etching the dummy gate electrode film and the dummy gate dielectric film by taking the second mask layer as a mask to form a dummy gate dielectric layer and a dummy gate electrode layer positioned on the surface of the dummy gate dielectric layer.
The material of the pseudo gate dielectric layer comprises silicon oxide; the material of the dummy gate electrode layer includes: silicon, amorphous silicon, polysilicon or doped polysilicon.
In this embodiment, the dummy gate structure 210 is a gate structure. In other embodiments, the dummy gate structure 210 is used to define the location and size of the subsequently formed gate structure.
Referring to fig. 9, a second sidewall 220 is formed on the dummy gate structure 210 and the surface of the fin 201; after the second sidewall 220 is formed, lightly doped regions (not shown in the figure) are formed in the fin portions on both sides of the dummy gate structure 210 and the second sidewall 220.
The method for forming the second side wall 220 includes: forming a second sidewall material layer (not shown) on the isolation structure 202, the fin 201 and the dummy gate structure 210; and etching the second sidewall material layer until the top surface of the fin 201 and the top surface of the dummy gate structure 210 are exposed, thereby forming a second sidewall 220 covering the sidewall surfaces of the fin 201 and the dummy gate structure 210.
The materials of the second side wall 220 include: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or silicon carbonitride oxide. In this embodiment, the material of the second sidewall 220 is silicon nitride.
The thickness of the second sidewall 220 is: 3-8 nm.
The second sidewall 220 is used to define the location of the lightly doped region.
The forming step of the lightly doped region comprises the following steps: with the dummy gate structure 210 and the second sidewall 220 as masks, an ion implantation process is performed in the fin 201 at two sides of the dummy gate structure 210.
The lightly doped region has lightly doped ions therein, and the conductivity type of the lightly doped ions is related to the type of the transistor. In this embodiment, the device is used to form a PMOS transistor, so the lightly doped ions in the lightly doped region are P-type ions, such as: boron ions, BF 2- Or indium ions. In other embodiments, the device is used to form an NMOS transistor, and therefore, the lightly doped ions of the lightly doped region are N-type ions, such as: phosphorus ions or arsenic ions.
Referring to fig. 10, a first sidewall 230 is formed on the dummy gate structure 210 and the surface of the second sidewall 220 of the fin 201.
The method for forming the first side wall 230 includes: forming a first sidewall material layer (not shown) on the isolation structure 202, the fin 201 and the dummy gate structure 210; and etching back the first sidewall material layer until the top surface of the fin 201 and the top surface of the dummy gate structure 210 are exposed, thereby forming a first sidewall 230 covering the sidewall surface of the second sidewall 220 of the fin 201 and the sidewall surface of the second sidewall 220 of the dummy gate structure 210.
The materials of the first sidewall 230 include: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or silicon carbonitride oxide. In this embodiment, the material of the first sidewall 230 is silicon nitride.
The first sidewall 230 is used to define a position where the source-drain doped layer is formed later.
The thickness of the first sidewall 230 is: 5-15 nm.
The significance of selecting the thickness range of the first sidewall 230 is that: if the thickness of the first sidewall 230 is too small, the distance between the source-drain doped layer formed later and the channel is too short, the short channel effect is poor, and the performance of the formed semiconductor device is poor; if the thickness of the first sidewall 230 is too large, the distance between the source-drain doped layer and the channel formed later is too large, the stress provided is small, and the performance of the semiconductor device formed is poor.
Referring to fig. 11 and 12, fig. 12 is a cross-sectional view along a cutting line A-A1 in fig. 11, fig. 11 is a cross-sectional view along B-B1 in fig. 12, a barrier layer 240 is formed on a sidewall surface of the first sidewall 230, and the barrier layer 240 covers the first sidewall 230 of the fin 201 and the first sidewall 230 of the dummy gate structure 210.
The method for forming the barrier layer 240 includes: forming a barrier material layer on the isolation structure 202, the fin 201, the dummy gate structure 210, and the first sidewall 230; the barrier material layer is etched back until the top surface of the fin 201 and the top surface of the dummy gate structure 210 are exposed, forming a barrier layer 240 covering the sidewall surfaces of the first sidewall 230.
The process of forming the barrier material layer includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the process of forming the barrier material layer is an atomic layer deposition process; the parameters of the atomic layer deposition process include: the gas used comprises SiH 2 Cl 2 And NH 3 ，SiH 2 Cl 2 And NH 3 The flow rate of the catalyst is 1500-4000 standard milliliters/minute, the temperature is 200-600 ℃, the pressure is 1-10 mTorr, and the cycle time is 5-100 times.
The barrier material layer formed by the atomic layer deposition process has good uniformity, and correspondingly, the formed barrier layer has good uniformity, so that the formed semiconductor device has good performance.
The material of the barrier layer comprises silicon oxide. The barrier layer 240 is located on the surface of the isolation structure 202, covers the first side wall 230, and can support the first side wall 230 covered by the barrier layer.
The thickness of the barrier layer 240 is: 3-10 nm.
The significance of selecting the thickness range of the barrier layer 240 is that: if the thickness of the barrier layer 240 is too thick, the process time is correspondingly increased, thereby increasing the manufacturing cost; if the thickness of the barrier layer 240 is too thin, the contact area between the barrier layer 240 and the isolation structure 202 is small, the isolation structure 202 with a small area under the barrier layer 240 is etched and removed, and the barrier layer 240 is easily separated from the isolation structure, so that the barrier layer 240 cannot support the first sidewall 230 covered by the barrier layer, and the performance of the formed semiconductor device is poor.
Referring to fig. 13, the cross-sectional direction of fig. 13 is identical to that of fig. 12, and after the barrier layer 240 is formed, a first ion implantation process is used to dope first ions into a portion of the barrier layer 240 located on the sidewall of the fin 201.
The first ion includes: silicon ions, carbon ions or germanium ions.
The process parameters of the first ion implantation include: the implanted ions are silicon ions, carbon ions or germanium ions, the energy range is 1KeV to 20KeV, and the dosage range is 1.0e14atm/cm 2 ～2.0e16atm/cm 2 The inclination angle is 15-30 degrees, and is an included angle between the implantation direction and the normal line of the plane of the semiconductor substrate 200; the direction of the first ion implantation is perpendicular to the extending direction of the fin 201.
In this embodiment, the implanted ions are silicon ions, and the material of the barrier layer 240 is silicon oxide. After implanting silicon ions into the silicon oxide, the implanted silicon ions are able to form silicon-silicon bonds with silicon atoms in the barrier layer 240. By the first ion implantation process, silicon ions are doped in the partial barrier layer 240 on the side wall of the fin 201, so that the compactness of the partial barrier layer 240 on the side wall of the fin 201 is improved, and the etching efficiency of the partial barrier layer 240 on the side wall of the fin 201 is reduced in the subsequent etching process of the barrier layer 240.
Referring to fig. 14, the cross-sectional direction of fig. 14 is the same as that of fig. 11, after the first ion implantation, the barrier layer 240 on the sidewall surface of the dummy gate structure 210 is etched and removed, and in the process of etching and removing the barrier layer 240 on the sidewall surface of the dummy gate structure 210, the etching rate of the barrier layer 240 on the sidewall of the fin 201 is smaller than that of the barrier layer 240 on the sidewall of the dummy gate structure 210.
The process of etching to remove the barrier layer 240 includes one or a combination of a dry etching process and a wet etching process.
In this embodiment, the process of etching to remove the barrier layer 240 includes: the gas adopted comprises He, NH 3 And NF (NF) 3 Wherein, the flow rate of He is 600 to 2000 standard milliliters per minute, NH 3 The flow rate of the water is 200-500 standard milliliters/minute, NF 3 The pressure is 2 to 10 Torr, and the time is 20 to 100 seconds.
Because the silicon ions are doped in the partial barrier layer 240 of the side wall of the fin 201, the compactness of the partial barrier layer 240 of the side wall of the fin 201 is improved, the etching process has different etching rates to the barrier layer 240 of the side wall of the fin 201 and the barrier layer 240 of the side wall of the dummy gate structure 210, and the etching rate of removing the barrier layer 240 of the side wall surface of the dummy gate structure 210 is far greater than the etching rate of the barrier layer 240 of the side wall surface of the fin 201, so that the barrier layer 240 of the first side wall 230 of the fin 201 can be removed while the barrier layer 240 of the first side wall 230 of the fin 201 is maintained. When the grooves are formed later and the source-drain doped layers are formed in the grooves, the barrier layer 240 on the surface of the first side wall 230 of the dummy gate structure 210 is removed, and the dummy gate structure 210 and the first side wall 230 are used as masks, so that the distance between the formed source-drain doped layers and the channel is not too large, short channel effect is avoided, and the semiconductor device with better performance is formed.
Referring to fig. 15 and 16, the cross-sectional directions of fig. 15 and 11 are the same, and the cross-sectional directions of fig. 16 and 12 are the same, and grooves 250 are formed in the fin portions at both sides of the dummy gate structure 210, wherein the grooves 250 expose the second sidewalls 220.
The method for forming the groove 250 includes: with the dummy gate structure 210, the second side wall 220 and the first side wall 230 as masks, the fin 201 exposed at two sides of the dummy gate structure 210 is etched, and a groove 250 is formed in the fin 201.
The distance from the bottom of the groove 250 to the surface of the fin 201 is: 30 nm-60 nm.
The significance of selecting the distance range is: if the distance is too shallow, the source-drain doped layer formed in the groove 250 later provides less stress to the channel, which is not beneficial to the performance of the formed semiconductor device; if the distance is too deep, short channel effects are poor, resulting in poor performance of the formed semiconductor device.
The process of etching the recess 250 includes one or a combination of a dry etching process and a wet etching process.
Since the barrier layer 240 on the sidewall surface of the dummy gate structure 210 is etched and removed, the sidewall of the dummy gate structure 210 has the second sidewall 220 and the first sidewall 230 located on the surface of the second sidewall 220, and the first sidewall 230 and the second sidewall 220 define the distance between the dummy gate structure 210 and the source-drain doped layer formed in the recess 250, so that the distance between the dummy gate structure 210 and the source-drain doped layer formed in the recess 250 is not too large, which is beneficial to forming a semiconductor device with better performance.
Referring to fig. 17, after the recess 250 is formed, a pre-cleaning process is performed on the recess 250.
The parameters of the pre-cleaning process include: the etching solution is dilute hydrofluoric acid, and the dilution ratio is 100:1-1000:1.
The pre-cleaning process is used for removing byproducts, a natural oxide layer and other impurities on the side wall and the bottom of the groove 250 and the surface of the fin 201, so as to reduce impurities and defects on the side wall and the bottom of the groove 250 and the surface of the fin 201, and thereby facilitate the subsequent epitaxial growth in the groove 250 by taking the surface of the fin 201 as a seed layer to form a source-drain doped layer.
Although the pre-cleaning process is performed, the portion of the isolation structure 202 under the first sidewall 230 is etched to a certain extent, the contact area between the bottom of the barrier layer 240 and the isolation structure 202 is large due to the wide thickness of the barrier layer 240, so that the barrier layer 240 can still be stably located on the surface of the isolation structure 240. The blocking layer 240 covers the side wall of the first sidewall 230 of the fin 201, and the blocking layer 240 has a better supporting effect on the first sidewall 230 of the fin 201, so that the first sidewall 230 of the fin 201 covered by the blocking layer 240 can still be stably located on the surface of the isolation structure 240. The barrier layer 240, the first side wall 230 and the second side wall 220 can limit the subsequent process of forming the source-drain doped layer in the groove 250, and avoid contact between adjacent source-drain doped layers, so that the performance of the formed semiconductor device is better.
Referring to fig. 18 and 19, the cross-sectional direction of fig. 18 is identical to that of fig. 11, and the cross-sectional direction of fig. 19 is identical to that of fig. 12, and a source/drain doped layer 260 is formed in the recess 250.
The source-drain doped layer 260 is formed by an epitaxial growth process.
The source-drain doped layer 260 has source-drain ions.
The process of forming the source drain doped layer 260 includes an epitaxial growth process; the process of doping drain source ions in the source drain doped layer 260 is an in-situ doping process.
In this embodiment, the device is used to form a PMOS transistor, and thus, the materials of the source-drain doped layer 260 include: silicon, germanium or silicon germanium; the source and drain ions are P-type ions, such as: boron ions, BF 2- Or indium ions. In other embodiments, the device is used to form an NMOS transistor, and thus, the materials of the source-drain doped layer 260 include: silicon, gallium arsenide or indium gallium arsenide; the source and drain ions are N-type ions, such as: phosphorus ions or arsenic ions.
In other embodiments, the process of doping the source and drain ions in the source and drain doped layer 260 is an ion implantation process.
Because the source-drain doped layer 260 is formed in the first sidewall 230 and the second sidewall 220 and is limited in a certain range, contact between adjacent source-drain doped layers 260 can be avoided, and thus the performance of the formed semiconductor device is better.
Accordingly, an embodiment of the present invention further provides a semiconductor device, please continue to refer to fig. 19, including:
a semiconductor substrate 200, wherein the semiconductor substrate 200 is provided with a fin 201, an isolation structure 202 covering part of the side wall of the fin 201, and a dummy gate structure 210 crossing the fin 201 and covering part of the isolation structure 202;
a first sidewall 230 located on a sidewall surface of the fin 201;
a barrier layer 240 located on a sidewall surface of the first sidewall 230;
recesses 250 (shown in fig. 16) in the fins on both sides of the dummy gate structure 210.
And a source-drain doped layer 260 positioned in the groove 250.
The first sidewall 230 also covers the sidewall surface of the dummy gate structure 210; the materials of the first sidewall 230 include: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or silicon oxycarbonitride; the thickness of the first sidewall 230 is: 5-15 nm.
The materials of the barrier layer 240 include: silicon oxide; the thickness of the barrier layer 240 is: 3-10 nm.
The semiconductor device further includes: the second side wall 220 is positioned on the side wall surfaces of the pseudo gate structure 210 and the fin 201; lightly doped regions in fin 201 on both sides of dummy gate structure 210 and second sidewall 220;
the distance from the bottom of the groove 250 to the surface of the fin 201 is: 30 nm-60 nm.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (17)

1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a fin part, an isolation structure covering part of the side wall of the fin part and a pseudo gate structure crossing the fin part and covering part of the isolation structure;
forming a first side wall on the surface of the side wall of the fin part, wherein the first side wall also covers the surface of the side wall of the pseudo gate structure;
forming a barrier layer on the surface of the side wall of the first side wall, wherein the barrier layer also covers the first side wall of the side wall surface of the pseudo gate structure;
after the barrier layer is formed, doping first ions in a part of the barrier layer on the side wall of the fin part by adopting a first ion implantation process; after the first ion implantation, etching to remove the barrier layer on the side wall surface of the pseudo gate structure, wherein in the process of etching to remove the barrier layer on the side wall surface of the pseudo gate structure, the etching rate of the barrier layer on the side wall of the fin part is smaller than that of the barrier layer on the side wall of the pseudo gate structure;
after removing the barrier layer on the side wall surface of the pseudo gate structure, forming grooves in fin parts on two sides of the pseudo gate structure, wherein the grooves expose the first side wall;
and forming a source-drain doping layer in the groove.
2. The method for forming a semiconductor device according to claim 1, wherein the method for forming a first sidewall comprises: forming a first side wall material layer on the isolation structure, the fin part and the pseudo gate structure; and etching back the first side wall material layer until the top surface of the fin part and the top surface of the pseudo gate structure are exposed, so as to form a first side wall covering the side wall surface of the fin part and the side wall surface of the pseudo gate structure.
3. The method for forming a semiconductor device according to claim 1, wherein the material of the first sidewall comprises: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or silicon oxycarbonitride; the thickness of the first side wall is as follows: 5-15 nm.
4. The method of forming a semiconductor device according to claim 1, wherein the method of forming a barrier layer comprises: forming a barrier material layer on the isolation structure, the fin portion, the dummy gate structure and the first side wall; and etching the blocking material layer until the top surface of the fin part and the top surface of the pseudo gate structure are exposed, and forming a blocking layer covering the surface of the first side wall.
5. The method of forming a semiconductor device of claim 4, wherein the process of forming the barrier material layer comprises an atomic layer deposition process; the parameters of the atomic layer deposition process include: the gas used comprises SiH 2 Cl 2 And NH 3 ，SiH 2 Cl 2 And NH 3 The flow rate of the catalyst is 1500-4000 standard milliliters/minute, the temperature is 200-600 ℃, the pressure is 1-10 mTorr, and the cycle time is 5-100 times.
6. The method of forming a semiconductor device of claim 1, wherein the material of the barrier layer comprises: silicon oxide; the thickness of the barrier layer is as follows: 3-10 nm.
7. The method of forming a semiconductor device according to claim 2, wherein the first ions comprise: silicon ions, carbon ions or germanium ions; the process parameters of the first ion implantation include: the implanted ions are silicon ions, carbon ions or germanium ions, the energy range is 1KeV to 20KeV, and the dosage range is 1.0e14atm/cm 2 ～2.0e16atm/cm 2 The inclination angle is 15-30 degrees; the direction of the first ion implantation is perpendicular to the extending direction of the fin portion.
8. The method of forming a semiconductor device of claim 1, further comprising, prior to forming the first sidewall: forming a second side wall on the surface of the side wall of the fin part and the pseudo gate structure; and after the second side wall is formed, forming a lightly doped region in the fin parts at two sides of the pseudo gate structure and the second side wall.
9. The method of forming a semiconductor device of claim 1, further comprising, prior to forming the source drain doped layer: carrying out a pre-cleaning process on the groove; the pre-cleaning process parameters comprise: the etching solution is dilute hydrofluoric acid, and the dilution ratio is 100:1-1000:1.
10. The method of forming a semiconductor device according to claim 1, wherein the method of forming the recess comprises: and etching the exposed fin parts at two sides of the pseudo gate structure by taking the pseudo gate structure and the first side wall as masks, and forming grooves in the fin parts.
11. The method of forming a semiconductor device of claim 1, wherein the process of etching away the barrier layer on the sidewall surface of the dummy gate structure is a dry etching process; the parameters of the etching process include: the gas adopted comprises He, NH 3 And NF (NF) 3 Wherein, the flow rate of He is 600 to 2000 standard milliliters per minute, NH 3 The flow rate of the water is 200-500 standard milliliters/minute, NF 3 The pressure is 2 to 10 Torr, and the time is 20 to 100 seconds.
12. The method of forming a semiconductor device of claim 1, wherein a distance from a bottom of the recess to a surface of the fin is: 30 nm-60 nm.
13. A semiconductor device, comprising:
the semiconductor substrate is provided with a fin part, an isolation structure covering part of the side wall of the fin part and a pseudo gate structure crossing the fin part and covering part of the isolation structure;
the first side wall is positioned on the surface of the side wall of the fin part and also covers the surface of the side wall of the pseudo gate structure;
a barrier layer on a surface of the first sidewall; the barrier layer covers only the first side wall surface except the side wall surface of the pseudo gate structure;
grooves in the fin parts at two sides of the pseudo gate structure;
and the source-drain doping layer is positioned in the groove.
14. The semiconductor device of claim 13, wherein the material of the first sidewall comprises: silicon oxide, silicon nitride or silicon oxynitride, silicon carbonitride or silicon oxycarbonitride; the thickness of the first side wall is as follows: 5-15 nm.
15. The semiconductor device of claim 13, wherein the material of the barrier layer comprises: silicon oxide; the thickness of the barrier layer is as follows: 3-10 nm.
16. The semiconductor device of claim 13, further comprising a second sidewall located on a surface of the fin sidewall and the dummy gate structure; and the lightly doped region is positioned in the fin parts at two sides of the pseudo gate structure and the second side wall.
17. The method of forming a semiconductor device of claim 13, wherein a distance from a bottom of the recess to a surface of the fin is: 30 nm-60 nm.
CN201810959497.8A 2018-08-22 2018-08-22 Semiconductor device and method of forming the same Active CN110858544B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810959497.8A CN110858544B (en) 2018-08-22 2018-08-22 Semiconductor device and method of forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810959497.8A CN110858544B (en) 2018-08-22 2018-08-22 Semiconductor device and method of forming the same

Publications (2)

Publication Number Publication Date
CN110858544A CN110858544A (en) 2020-03-03
CN110858544B true CN110858544B (en) 2023-11-21

Family

ID=69635265

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810959497.8A Active CN110858544B (en) 2018-08-22 2018-08-22 Semiconductor device and method of forming the same

Country Status (1)

Country Link
CN (1) CN110858544B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113451132B (en) * 2020-03-26 2024-04-19 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105448726A (en) * 2014-08-28 2016-03-30 中芯国际集成电路制造(上海)有限公司 Method for forming fin field effect transistor
CN107591436A (en) * 2016-07-07 2018-01-16 中芯国际集成电路制造(上海)有限公司 Fin field effect pipe and forming method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105470132B (en) * 2014-09-03 2018-08-10 中芯国际集成电路制造(上海)有限公司 The forming method of fin field effect pipe

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105448726A (en) * 2014-08-28 2016-03-30 中芯国际集成电路制造(上海)有限公司 Method for forming fin field effect transistor
CN107591436A (en) * 2016-07-07 2018-01-16 中芯国际集成电路制造(上海)有限公司 Fin field effect pipe and forming method thereof

Also Published As

Publication number Publication date
CN110858544A (en) 2020-03-03

Similar Documents

Publication Publication Date Title
US11854898B2 (en) Wrap-around contact on FinFET
US9905646B2 (en) V-shaped epitaxially formed semiconductor layer
US9543419B1 (en) FinFET structures and methods of forming the same
US11854901B2 (en) Semiconductor method and device
US20220302116A1 (en) Semiconductor Device and Method
CN106158747B (en) Semiconductor structure and forming method thereof
US20150364574A1 (en) Semiconductor devices and methods of manufacturing the same
US11854814B2 (en) Semiconductor device and method
US11728173B2 (en) Masking layer with post treatment
CN109872953B (en) Semiconductor device and method of forming the same
CN110858544B (en) Semiconductor device and method of forming the same
US11616133B2 (en) Fin field-effect transistor device and method
TWI827115B (en) Semiconductor device and method of forming the same
US12009406B2 (en) FinFET device and method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant