CN105448726A - Method for forming fin field effect transistor - Google Patents
Method for forming fin field effect transistor Download PDFInfo
- Publication number
- CN105448726A CN105448726A CN201410432180.0A CN201410432180A CN105448726A CN 105448726 A CN105448726 A CN 105448726A CN 201410432180 A CN201410432180 A CN 201410432180A CN 105448726 A CN105448726 A CN 105448726A
- Authority
- CN
- China
- Prior art keywords
- fin
- field effect
- formula field
- etching
- formation method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method for forming a fin field effect transistor comprises the following steps: providing a semiconductor substrate, wherein fins are formed on the semiconductor substrate; forming gate structures which are across and cover part of the surfaces of the side walls and tops of the fins respectively; forming etch stop layers covering the fins and the gate structures respectively; forming a mask layer on each etch stop layer, wherein the mask layer is provided with a first opening which exposes the surface of the corresponding etch stop layer on the surface of the corresponding fin at the two sides of the corresponding gate structure; etching each etch stop layer along the first opening, and forming a second opening in each etch stop layer, wherein impurity elements entering in the etching process is left in the fins exposed by the bottoms of the second openings; performing first impurity element removal on the fins exposed by the bottoms of the second openings to remove the impurity elements left in the fins exposed by the second openings; performing back-etching along the second openings to remove part of the fins, and forming a groove in each fin; and forming stress source/drain regions filling the grooves. By using the method, the performance of the formed stress source/drain regions is improved.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of formation method of fin formula field effect transistor transistor.
Background technology
MOS transistor, by applying voltage at grid, regulates and produces switching signal by the electric current of channel region.But when semiconductor technology enters 45 nanometers with lower node, the traditional control ability of plane formula MOS transistor to channel current dies down, and causes serious leakage current.Fin formula field effect transistor (FinFET) is a kind of emerging multi-gate device, it generally comprise there is high-aspect-ratio semiconductor fin, the top of fin described in cover part and the grid structure of sidewall, the source region being positioned at the fin of described grid structure both sides and drain region, the grid structure of fin formula field effect transistor can control from top and both sides fin, there are the grid more much better than than planar MOS transistors to the control ability of raceway groove, can be good at suppressing short-channel effect.
In addition, because stress can change energy gap and the carrier mobility of silicon materials, the performance therefore improving semiconductor device by stress becomes more and more conventional means.Particularly, by suitable proof stress, charge carrier (electronics in nmos device, the hole in PMOS device) mobility can be improved, and then improve drive current, greatly improve the performance of semiconductor device with this.In order to make fin formula field effect transistor have better performance, stress technique is also applied in fin formula field effect transistor.
There is in prior art the fin formula field effect transistor of stress source/drain region, comprising: Semiconductor substrate; Be positioned at the fin of the projection in described Semiconductor substrate; The sidewall of fin described in cover part and the grid structure of top surface; Be positioned at the groove of the fin of grid structure both sides; Fill the stress source/drain region of full groove.The channel region that described stress source/drain region is often used in described fin formula field effect transistor introduces stress, improves carrier mobility.
The material of described stress source/drain region is carborundum or SiGe, and described stress source/drain region adopts selective epitaxial process to be formed.
But the performance of the stress source/drain region of prior art still has much room for improvement.
Summary of the invention
The problem that the present invention solves is the performance of the stress source/drain region of how to improve formation.
For solving the problem, the invention provides a kind of formation method of fin formula field effect transistor, comprising: Semiconductor substrate is provided, described Semiconductor substrate is formed with fin; Formed across the covering sidewall of described fin and the grid structure on top section surface; Formed and cover the sidewall of described fin and the etching stop layer of top surface and gate structure sidewall and top surface; Described etching stop layer forms mask layer, has the first opening in described mask layer, described first opening exposes the etching stop layer of the fin portion surface of grid structure both sides; Etch described etching stop layer along the first opening, in described etching stop layer, form the second opening exposing fin top surface, in the fin that described second open bottom exposes, remain the impurity element entered in etching process; First decontamination element process is carried out to the fin that the second open bottom exposes, removes impurity element residual in the fin of the second opening exposure; Return etching along the second opening and remove part fin, form groove in the fin; Form the stress source/drain region of filling in full groove.
Optionally, described etching stop layer using plasma etching technics is etched.
Optionally, the etching gas that described plasma etching adopts is CH
3f, O
2and Ar.
Optionally, described plasma etching adopts pulsed plasma etching, CH
3the flow of F is 10 ~ 200sccm, O
2flow 10 ~ 500sccm, the flow of Ar is 10 ~ 200sccm, and bias power source is output offset power in a pulsed fashion, and radio frequency power source exports radio-frequency power in a pulsed fashion, the frequency of bias power source and radio frequency power source is 10Hz ~ 50KHz, and duty ratio is 10% ~ 80%.
Optionally, described impurity element is carbon and fluorine element.
Optionally, described first decontamination element is treated to plasma treatment.
Optionally, the gas that described plasma treatment adopts is H
2and N
2, H
2flow is 10 ~ 200sccm, N
2flow is 50 ~ 1000sccm, and treatment temperature is 0 ~ 100 DEG C, and source power is 100 ~ 1000W, and bias power is 0 ~ 300W, and the time is 10 ~ 600S plasma treatment.
Optionally, return the described fin of etching and adopt plasma etching industrial, the etching gas that plasma etching industrial adopts is HBr, O
2and NF
3.
Optionally, returning etching removal part fin, after forming groove in the fin, also comprising, the second decontamination process is carried out to the fin that groove exposes.
Optionally, described second decontamination element is treated to plasma treatment.
Optionally, the gas that described plasma treatment adopts is H
2and N
2, H
2flow is 10 ~ 200sccm, N
2flow is 50 ~ 1000sccm, and treatment temperature is 0 ~ 100 DEG C, and source power is 100 ~ 1000W, and bias power is 0 ~ 300W, and the time is 10 ~ 600S plasma treatment.
Optionally, the material of described etching stop layer is silicon nitride or silicon oxynitride.
Optionally, after formation grid structure, form the first side wall in the both sides sidewall surfaces of described grid structure, form the second side wall in the both sides sidewall surfaces of described fin.
Optionally, with described first side wall and grid structure for mask, in the fin of grid structure and the first side wall both sides, form shallow doped region.
Optionally, described mask layer comprises: packed layer, the dielectric antireflective coatings be positioned on packed layer, the organic antireflecting layer be positioned in dielectric antireflective coatings, the photoresist layer be positioned on organic antireflective coating.
Optionally, dielectric antireflective coatings material is for containing nitrogen compound.
Optionally, the material of described stress source/drain region is SiGe or carborundum.
Optionally, the formation process of described stress source/drain region is in-situ doped selective epitaxial process.
Optionally, described fin formula field effect transistor is the fin formula field effect transistor of N-type or the fin formula field effect transistor of P type.
Optionally, described grid structure comprises gate dielectric layer and is positioned at the gate electrode on gate dielectric layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
The formation method of fin formula field effect transistor of the present invention, etches described etching stop layer along the first opening, is formed after exposing the second opening of fin portion surface in described etching stop layer, first decontamination element process is carried out to the fin that the second open bottom exposes, remove impurity element residual in the fin of the second opening exposure, thus during etching fin formation groove, prevent the factors such as impurity element (such as carbon and fluorine element) density unevenness residual in fin on the impact of etch rate, thus make the evenness of the recess sidewall of formation and lower surface higher, can prevent residual carbon ion and fluorine ion in the fin of the bottom portion of groove formed from introducing defect in addition, ensure that the growing environment of stressor layers, reduce in the stress source/drain region formed and produce defect.
Further, the plasma etch process etching described etching stop layer is pulsed plasma etching, and the etching gas that pulsed plasma etching adopts is CH
3f, O
2and Ar, CH
3the flow of F is 10 ~ 200sccm, O
2flow 10 ~ 500sccm, the flow of Ar is 10 ~ 200sccm, bias power source is output offset power in a pulsed fashion, radio frequency power source exports radio-frequency power in a pulsed fashion, the frequency of bias power source and radio frequency power source is 10Hz ~ 50KHz, and duty ratio is 10% ~ 80%, the isoionic density adopting pulsed plasma etching can well control to be formed and energy, when completing the etching to etching stop layer, reduce impurity element residual in fin as early as possible.
Further, described first decontamination element is treated to plasma treatment, and the gas that described plasma treatment adopts is H
2and N
2, during plasma treatment, hydrogeneous and the nitrogenous plasma active formed strengthens, be more conducive to remove the impurity element in fin, containing hydrogen plasma, there is stronger reproducibility, fluorine element residual in fin then has oxidizability, hydrogen ion enters into fin, fluorine element residual in fin is combined, form fluorocarbon and discharge fin, then easily be combined with carbon containing nitrogen plasma, form carboritride arrangement fin, thus when subsequent etching fin forms groove, prevent the factors such as carbon residual in fin and fluorine element density unevenness on the impact of etch rate, thus make the evenness of recess sidewall and the lower surface formed higher, prevent residual carbon ion and fluorine ion in the fin of the bottom portion of groove formed from introducing defect in addition, ensure that the growing environment of stressor layers, reduce in the stress source/drain region formed and produce defect.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of an embodiment fin formula field effect transistor formation method;
Fig. 2 ~ Figure 11 is the cross-sectional view of embodiment of the present invention fin formula field effect transistor forming process.
Embodiment
As background technology sayed, the performance forming stress source/drain region in the fin of prior art fin formula field effect transistor still has much room for improvement, and the stress source/drain region such as formed exists the problem such as lattice defect, lack of homogeneity.
The forming process of fin formula field effect transistor is studied, with reference to figure 1, comprises step: step S101, Semiconductor substrate is provided, described Semiconductor substrate is formed with fin; Step S102, is formed across the covering sidewall of described fin and the grid structure on top section surface; Step S103, is formed and covers the sidewall of described fin and the etching stop layer of top surface and gate structure sidewall and top surface; Step S104, described etching stop layer forms mask layer, has the first opening in described mask layer, and described first opening exposes the etching stop layer of the fin portion surface of grid structure both sides; Step S105, etches described etching stop layer along the first opening, forms the second opening exposing fin portion surface in described etching stop layer; Step S106, returns etching along the second opening and removes part fin, form groove in the fin; Step S107, forms the stress source/drain region of filling in full groove.The stress source/drain region formed is positioned at the fin of grid structure both sides, therefore before formation stress source/drain region, the position being defined stress riser drain region to be formed by mask layer and etching stop layer is needed, for the special construction that fin formula field effect transistor is such, in order to make the mask layer of formation, there is good surface thickness uniformity, the thickness of the mask layer of general formation can be very thick, be difficult to etching stopping position when controlling formation the first opening, and formed when etching stop layer can form the first opening in mask layer and obtain preferably stop position.
Further research finds, the material of etching stop layer is generally nitrogen silicon compound, such as silicon nitride, silicon oxynitride etc., and etching described etching stop layer is adopt plasma etching industrial, the etching gas that plasma etching industrial adopts is the gas of carbon elements and fluorine element, such as CHF
3, CH
2f
2deng, carbon containing and fluorine-containing plasma are mainly etched etching stop layer by chemical reaction, when etching etching stop layer, part carbon ion and fluorine ion easily enter into the fin bottom etching stop layer and react with fin material, thus part carbon and fluorine element remain in the fin bottom etching stop layer.
In fin, carbon and fluorine element can affect the etch rate to fin, due to the skewness of carbon and fluorine element concentration in the fin of the second open bottom, make the etch rate of different local fin not identical, when returning etching and removing part fin formation groove, the bottom of groove formed and the evenness poor (surface irregularity) of sidewall surfaces, follow-up in a groove by epitaxy technique formed stress source/drain region time, the stress source/drain region formed and the interface of groove easily produce lattice defect, and rough bottom and sidewall surfaces make the growth rate of different directions stressor layers not identical, the stress source/drain region surface uniformity formed is also poor, in addition, carbon residual in the sidewall of groove and the bottom of bottom and fluorine element can introduce defect, change the growing environment of stressor layers, can affect the growth of stressor layers, easily in formation stress riser drain region, produce defect.
For this reason, the invention provides a kind of fin formula field effect transistor and forming method thereof, etch described etching stop layer along the first opening, formed after exposing the second opening of fin portion surface in described etching stop layer; First decontamination element process is carried out to the fin that the second open bottom exposes, remove impurity element residual in the fin of the second opening exposure, thus prevent impurity element residual in fin on the impact of returning when etching fin formation groove, the sidewall of the groove of formation and surface is made to have good surface smoothness, lattice defect in formation stress source/drain region is reduced, and there is good uniformity.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 2 ~ Figure 11 is the cross-sectional view of embodiment of the present invention fin formula field effect transistor forming process.
Please refer to Fig. 2, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 is formed with fin 201; Formed across the covering sidewall of described fin 201 and the grid structure 203 on top section surface.
Described Semiconductor substrate 200 can be silicon or silicon-on-insulator (SOI), and described Semiconductor substrate 200 also can be germanium, germanium silicon, GaAs or germanium on insulator, and the material of Semiconductor substrate 200 described in this enforcement is silicon.
Described Semiconductor substrate 200 surface is formed with the fin 201 of some projections, and in the present embodiment, described fin 201 is formed by etch semiconductor substrates 200, and in other embodiments of the invention, described fin 201 is formed by epitaxy technique.Can be different from dissimilar foreign ion according to the type of the fin formula field effect transistor formed in described fin 201, in one embodiment, when fin formula field effect transistor to be formed is P type fin formula field effect transistor, can doped N-type foreign ion in fin 201; In another embodiment, when fin formula field effect transistor to be formed is N-type fin formula field effect transistor, can doped p-type foreign ion in fin 201.Described N-type impurity ion is one or more in phosphonium ion, arsenic ion, antimony ion, and described p type impurity ion is one or more in boron ion, gallium ion, indium ion.
In the present embodiment, described Semiconductor substrate 200 is also formed with separator 205, the surface of described separator 205 is lower than the top surface of fin 201, described separator 205 is for the adjacent fin 201 of electric isolation and adjacent grid structure, the material of described separator 205 is silica, silicon nitride or silicon oxynitride, and the material of separator 205 described in the present embodiment is silica.The detailed process that separator 205 is formed is: first form the spacer material layer covering described Semiconductor substrate 200 and fin 201; Then spacer material layer described in chemical mechanical milling tech planarization is adopted, with the top surface of fin 201 for stop-layer; Then return etching and remove part described spacer material layer, form separator 205, the surface of described separator 205 is lower than the top surface of fin 201.
The sidewall of described fin 201 and top surface are also formed with grid structure 203, please refer to Fig. 3, Fig. 3 is the cross-sectional view of Fig. 2 along line of cut CD direction, and described grid structure 203 comprises: the gate electrode 22 covering the partial sidewall of described fin 201 and the gate dielectric layer 21 of top surface and be positioned on gate dielectric layer 21.
The forming process of described grid structure 203 is: form the gate dielectric material layer covering described fin 201 sidewall and bottom; Described gate dielectric material layer forms layer of gate electrode material; Etch described layer of gate electrode material and gate dielectric material layer, the gate electrode 22 forming gate dielectric layer 21 and be positioned on gate dielectric layer 21.
The material of described gate dielectric layer 21 is silica, and the material of described gate electrode 22 is polysilicon.In other embodiments of the invention, the material of described gate dielectric layer can be high-k dielectric material, such as hafnium oxide etc., and the material of described gate electrode is can be metal, such as tungsten etc.
Please continue to refer to Fig. 2, the both sides sidewall of described grid structure 203 forms the first side wall 204; With described grid structure 203 and the first side wall 204 for mask, shallow Doped ions injection is carried out to the fin 201 of grid structure 203 and the first side wall 204 both sides, in the fin 201 of described grid structure 203 and the first side wall 204 both sides, forms shallow doped region (not shown).
The foreign ion that described shallow Doped ions injects is the foreign ion of N-type or the foreign ion of P type, and the dosage range injecting ion is 1E13atom/cm
2~ 2E15atom/cm
2, the energy range of injection is 0.5KeV ~ 10KeV.When fin formula field effect transistor to be formed is P type fin formula field effect transistor, shallow Doped ions injects implanting p-type foreign ion; When fin formula field effect transistor to be formed is N-type fin formula field effect transistor, shallow Doped ions injects N-type impurity ion.
In conjunction with reference to figure 2 and Fig. 4, described Fig. 4 is the cross-sectional view of Fig. 2 along line of cut AB direction, the both sides sidewall of described fin 201 is also formed with the second side wall 202, described second side wall 202 forms the position of groove and stress source/drain region for limiting the follow-up fin 201 in grid structure 203 both sides.
Described second side wall 202 can be single or multiple lift stacked structure, and the material of the second side wall 202 can be silica, silicon nitride etc.
In one embodiment, described second side wall 202 is the silicon nitride of individual layer, second side wall 202 and the first side wall 204 are formed by same processing step, and detailed process is: formed and cover the sidewall of described fin 201 and the spacer material layer of top surface and grid structure 203 sidewall and top surface; Without spacer material layer described in mask etching, the both sides sidewall of described grid structure 203 forms the first side wall 204, the both sides sidewall of described fin 201 is formed the second side wall 202.
With reference to figure 5, formed and cover the sidewall of described fin 201 and the etching stop layer 206 of top surface and gate structure sidewall and top surface.It should be noted that, in the embodiment of the present invention, Fig. 5 and subsequent drawings are all cross-sectional view that the forming process of carrying out fin formula field effect transistor on the basis of Fig. 4 obtains.
Described etching stop layer 206 as follow-up in mask layer, form the first opening time stop-layer.
Described etching stop layer 206 material is nitrogen silicon compound, such as silicon nitride or silicon oxynitride etc., and the thickness of etching stop layer 206 is 100 ~ 1000 dusts.Described etching stop layer 206 is formed by chemical vapor deposition method.
With reference to figure 6, described etching stop layer 206 forms mask layer.
Described mask layer is as mask when etching stop layer described in subsequent etching 206 and part fin 201.
In the present embodiment, described mask layer comprises: packed layer 207, the dielectric antireflective coatings 208 be positioned on packed layer 207, the organic antireflective coating 209 be positioned in dielectric antireflective coatings 208, the photoresist layer 210 be positioned on organic antireflective coating 209.
Described packed layer 207 has good filling capacity, and has good surface smoothness, has good thickness evenness to make formation photoresist layer 210.The material of described packed layer 207 is silica, and mobility chemical vapor deposition method can be adopted to form packed layer 207.
Described dielectric antireflective coatings (DielectricAnti-ReflectionCoating) 208 and organic antireflective coating (OrganicAnti-ReflectiveCoating) 209 are for reducing the reflection of bottom light when exposing photoresist layer 210, make the size of opening that formed in photoresist layer 210 and positional precision higher, and there is good sidewall profile, thus improve make the first opening of follow-up formation, the second opening and the position of groove and the precision of size higher.
Dielectric antireflective coatings 208 material is for containing nitrogen compound, such as titanium nitride or silicon nitride etc., described dielectric antireflective coatings 208 is by plasma reinforced chemical vapour deposition (PECVD, PlasmaEnhancedChemicalVapourDeposition) formed, the material of described organic antireflective coating 209 is organic substance, is formed by spin coating proceeding.
In other embodiments of the invention, described mask layer can be other structure or material.
With reference to figure 7, form the first opening 211 in described mask layer, described first opening 211 exposes the etching stop layer 206 on fin 201 surface of grid structure both sides.
In photoresist layer 210, the first sub-opening is formed by exposure imaging technique, then plasma etching industrial is adopted to etch described organic antireflective coating 209, dielectric antireflective coatings 208 and packed layer 207 along the first sub-opening, in described organic antireflective coating 209, dielectric antireflective coatings 208 and packed layer 207, form the second sub-opening, described first sub-opening and the second sub-opening form the first opening 211.
Etch described organic antireflective coating 209, dielectric antireflective coatings 208 adopt etching gas be CHF
3and O
2, the etching gas etching the employing of described packed layer 207 is CF
4, CHF
3and Ar.
With reference to figure 8, described etching stop layer 206 is etched along the first opening 211, in described etching stop layer 206, form the second opening 212 exposing fin 201 top surface, in the fin 201 of described second opening 212 bottom-exposed, remain the impurity element produced in etching process.
Etch described etching stop layer 206 using plasma etching technics.The etching gas that described plasma etching adopts is CH
3f, O
2and Ar, CH
3the flow of F is 50 ~ 500sccm, O
2flow be the flow of 5 ~ 200sccm, Ar be 5 ~ 200sccm, source power is 500 ~ 2500W, and bias power is 0 ~ 300W.
After etching completes, impurity element can be remained in fin 201 bottom second opening 212, comprise: carbon and fluorine element (existing with the state of ion), the reason that carbon and fluorine element remain is: on the one hand, because the activity of carbon and fluorine element is stronger, and atomic radius is less, easily diffuse in the fin 201 bottom etching stop layer 206 in the etching process to etching stop layer 206, on the other hand, in plasma etching process, source power and bias power can produce acceleration to the plasma formed, carbon and fluorine element also can be injected in the fin 201 of the second open bottom exposure.
Carbon residual in fin 201 and fluorine element not only can affect the surface uniformity of the groove of follow-up formation, also can have an impact to the performance of stress source/drain region epitaxially grown in groove.
In other embodiments of the invention, described plasma etching adopts pulsed plasma etching, and the etching gas that pulsed plasma etching adopts is CH
3f, O
2and Ar, CH
3the flow of F is 10 ~ 200sccm, O
2flow 10 ~ 500sccm, the flow of Ar is 10 ~ 200sccm, bias power source is output offset power in a pulsed fashion, radio frequency power source exports radio-frequency power in a pulsed fashion, the frequency of bias power source and radio frequency power source is 10Hz ~ 50KHz, and duty ratio is 10% ~ 80%, the isoionic density adopting pulsed plasma etching can well control to be formed and energy, when completing the etching to etching stop layer 206, reduce impurity element residual in fin 201 as early as possible.
With reference to figure 9, the first decontamination element process 23 is carried out to the fin 201 of the second opening 212 bottom-exposed, remove impurity element residual in fin 201.
Described first decontamination element process 23 is plasma treatment.
The gas that described plasma treatment adopts is H
2and N
2, H
2flow is 10 ~ 200sccm, N
2flow is 50 ~ 1000sccm (standard milliliters/point), treatment temperature is 0 ~ 100 DEG C, source power is 100 ~ 1000W, bias power is 0 ~ 300W (watt), time is 10 ~ 600S (second), in more effective removal fin while impurity element, prevent the damage to fin 201.During plasma treatment, hydrogeneous and the nitrogenous plasma active formed strengthens, be more conducive to remove the impurity element in fin 201, containing hydrogen plasma, there is stronger reproducibility, fluorine element residual in fin 201 then has oxidizability, hydrogen ion enters into fin 201, fluorine element residual in fin 201 is combined, form fluorocarbon and discharge fin 201, then easily be combined with carbon containing nitrogen plasma, form carboritride arrangement fin 201, thus when subsequent etching fin 201 forms groove, prevent the factors such as carbon residual in fin 201 and fluorine element density unevenness on the impact of etch rate, thus make the evenness of recess sidewall and the lower surface formed higher, prevent residual carbon ion and fluorine ion in the fin of the bottom portion of groove formed from introducing defect in addition, ensure that the growing environment of stressor layers, reduce in the stress source/drain region formed and produce defect.
With reference to Figure 10, remove part fin 201 along the second opening 212 times etchings, in fin 201, form groove 214.
Return the described fin 201 of etching and adopt plasma etching industrial, the etching gas that plasma etching industrial adopts is HBr, O
2and NF
3.
Form groove 214 in fin 201 after, also comprise, the second decontamination process is carried out to the fin 201 that groove 214 exposes.The object of carrying out the second impurity treatment is: that fails when being on the one hand and removing the first decontamination process further to remove completely remains in carbon and fluorine element in fin 201; Be back etched portions fin 201 on the other hand, when forming groove 214, the new impurity element of introducing, such as fluorine element.
Described second decontamination is treated to plasma treatment.
The gas that described plasma treatment adopts is H
2and N
2, H
2flow is 10 ~ 200sccm, N
2flow is 50 ~ 1000sccm, and treatment temperature is 0 ~ 100 DEG C, and source power is 100 ~ 1000W, and bias power is 0 ~ 300W, and the time is 10 ~ 600S.
In other embodiments of the invention, if the quantity of impurity element residual in fin 201 is more, position is darker, be difficult to remove by a decontamination process, in order to impurity element residual in more effective removal fin 201, at the described etching stop layer 206 of etching, form the second opening 212 in etching stop layer 206 after, what replace carries out decontamination step and etch step, until form groove 214 in the fin 201 of grid structure both sides, concrete step is: carry out first step decontamination step, remove part of impurity elements (impurity element comprises carbon and fluorine element) in the fin of the second open bottom exposure, carry out first step etch step, remove the fin of segment thickness along the second opening etching, form the first sub-groove, carry out second step decontamination step, remove the impurity element in the fin of the first sub-bottom portion of groove, carry out second step etch step, remove the fin of segment thickness along the first sub-recess etch, form the second sub-groove, carry out N (N >=3) step decontamination step, remove the impurity element in the fin of N-1 (N >=3) sub-bottom portion of groove, carry out N (N >=3) step etch step, remove the fin of segment thickness along the second sub-recess etch, form groove 214.
Carry out decontamination step and etch step by what replace, thus in whole etching process, make each step etch step all can not be subject to the impact of impurity element, thus make the evenness of the sidewall of the groove formed and lower surface better.
Better going deimpurity effect to reach, improving the sidewall of groove and the evenness of lower surface that are formed, first step decontamination step, second step decontamination step ... the gas that N (N>=3) step decontamination step adopts is H
2and N
2, H
2flow is 10 ~ 200sccm, N
2flow is 50 ~ 1000sccm, and treatment temperature is 0 ~ 100 DEG C, and source power is 100 ~ 1000W, and bias power is 0 ~ 300W, and each step time is 5 ~ 500S; First step etch step, second step etch step ... the gas that N (N>=3) step etch step adopts is HBr, O
2and NF
3, the flow of HBr is 50-500sccm, O
2flow be 10-500sccm, NF
3flow be 10-500sccm, source power is 100 ~ 1000W, and bias power is 0 ~ 300W, and each step time is 5 ~ 500S.
With reference to Figure 11, form the stress source/drain region 213 of filling in full groove 214 (with reference to Figure 10).
The material of described stress source/drain region 213 is SiGe or carborundum.In the particular embodiment, when fin formula field effect transistor to be formed is the fin formula field effect transistor of N-type, the material of described stress source/drain region 213 is carborundum, when fin formula field effect transistor to be formed is the fin formula field effect transistor of P type, the material of described stress source/drain region 213 is SiGe.
Form the process selectivity epitaxy technique of described stress source/drain region 213.
Doped with foreign ion in described stress source/drain region 213, can be formed by in-situ doped technique during selective epitaxy technique, or be formed by ion implantation technology.
Described foreign ion comprises N-type impurity ion and p type impurity ion, and described N-type impurity ion is phosphonium ion, one or more in arsenic ion, antimony ion, and described p type impurity ion is one or more in boron ion, gallium ion, indium ion.In the particular embodiment, when fin formula field effect transistor to be formed is the fin formula field effect transistor of N-type, in stress source/drain region 213, the foreign ion of doping is N-type impurity ion, when fin formula field effect transistor to be formed is the fin formula field effect transistor of P type, in stress source/drain region 213, the foreign ion of doping is p type impurity ion.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for fin formula field effect transistor, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate is formed with fin;
Formed across the covering sidewall of described fin and the grid structure on top section surface;
Formed and cover the sidewall of described fin and the etching stop layer of top surface and gate structure sidewall and top surface;
Described etching stop layer forms mask layer, has the first opening in described mask layer, described first opening exposes the etching stop layer of the fin portion surface of grid structure both sides;
Etch described etching stop layer along the first opening, in described etching stop layer, form the second opening exposing fin top surface, in the fin that described second open bottom exposes, remain the impurity element entered in etching process;
First decontamination element process is carried out to the fin that the second open bottom exposes, removes impurity element residual in the fin of the second opening exposure;
Return etching along the second opening and remove part fin, form groove in the fin;
Form the stress source/drain region of filling in full groove.
2. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, etch described etching stop layer using plasma etching technics.
3. the formation method of fin formula field effect transistor as claimed in claim 2, is characterized in that, the etching gas that described plasma etching adopts is CH
3f, O
2and Ar.
4. the formation method of fin formula field effect transistor as claimed in claim 3, is characterized in that, described plasma etching adopts pulsed plasma etching, CH
3the flow of F is 10 ~ 200sccm, O
2flow 10 ~ 500sccm, the flow of Ar is 10 ~ 200sccm, and bias power source is output offset power in a pulsed fashion, and radio frequency power source exports radio-frequency power in a pulsed fashion, the frequency of bias power source and radio frequency power source is 10Hz ~ 50KHz, and duty ratio is 10% ~ 80%.
5. the formation method of fin formula field effect transistor as claimed in claim 3, it is characterized in that, described impurity element is carbon and fluorine element.
6. the formation method of fin formula field effect transistor as claimed in claim 5, it is characterized in that, described first decontamination element is treated to plasma treatment.
7. the formation method of fin formula field effect transistor as claimed in claim 5, is characterized in that, the gas that described plasma treatment adopts is H
2and N
2, H
2flow is 10 ~ 200sccm, N
2flow is 50 ~ 1000sccm, and treatment temperature is 0 ~ 100 DEG C, and source power is 100 ~ 1000W, and bias power is 0 ~ 300W, and the time is 10 ~ 600S.
8. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, return the described fin of etching and adopt plasma etching industrial, the etching gas that plasma etching industrial adopts is HBr, O
2and NF
3.
9. the formation method of fin formula field effect transistor as claimed in claim 8, is characterized in that, returning etching removal part fin, after forming groove in the fin, also comprising, carrying out the second decontamination process to the fin that groove exposes.
10. the formation method of fin formula field effect transistor as claimed in claim 9, it is characterized in that, described second decontamination element is treated to plasma treatment.
The formation method of 11. fin formula field effect transistors as claimed in claim 10, is characterized in that, the gas that described plasma treatment adopts is H
2and N
2, H
2flow is 10 ~ 200sccm, N
2flow is 50 ~ 1000sccm, and treatment temperature is 0 ~ 100 DEG C, and source power is 100 ~ 1000W, and bias power is 0 ~ 300W, and the time is 10 ~ 600S.
The formation method of 12. fin formula field effect transistors as claimed in claim 1, is characterized in that, the material of described etching stop layer is silicon nitride or silicon oxynitride.
The formation method of 13. fin formula field effect transistors as claimed in claim 1, is characterized in that, after formation grid structure, forms the first side wall, form the second side wall in the both sides sidewall surfaces of described fin in the both sides sidewall surfaces of described grid structure.
The formation method of 14. fin formula field effect transistors as claimed in claim 13, is characterized in that, with described first side wall and grid structure for mask, in the fin of grid structure and the first side wall both sides, forms shallow doped region.
The formation method of 15. fin formula field effect transistors as claimed in claim 1, it is characterized in that, described mask layer comprises: packed layer, the dielectric antireflective coatings be positioned on packed layer, the organic antireflecting layer be positioned in dielectric antireflective coatings, the photoresist layer be positioned on organic antireflective coating.
The formation method of 16. fin formula field effect transistors as claimed in claim 15, is characterized in that, dielectric antireflective coatings material is for containing nitrogen compound.
The formation method of 17. fin formula field effect transistors as claimed in claim 1, is characterized in that, the material of described stress source/drain region is SiGe or carborundum.
The formation method of 18. fin formula field effect transistors as claimed in claim 17, is characterized in that, the formation process of described stress source/drain region is in-situ doped selective epitaxial process.
The formation method of 19. fin formula field effect transistors as claimed in claim 1, is characterized in that, described fin formula field effect transistor is the fin formula field effect transistor of N-type or the fin formula field effect transistor of P type.
The formation method of 20. fin formula field effect transistors as claimed in claim 1, is characterized in that, described grid structure comprises gate dielectric layer and is positioned at the gate electrode on gate dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410432180.0A CN105448726B (en) | 2014-08-28 | 2014-08-28 | The forming method of fin formula field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410432180.0A CN105448726B (en) | 2014-08-28 | 2014-08-28 | The forming method of fin formula field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105448726A true CN105448726A (en) | 2016-03-30 |
| CN105448726B CN105448726B (en) | 2019-01-22 |
Family
ID=55558780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410432180.0A Active CN105448726B (en) | 2014-08-28 | 2014-08-28 | The forming method of fin formula field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105448726B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107275215A (en) * | 2016-04-08 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin formula field effect transistor |
| CN109801914A (en) * | 2017-11-17 | 2019-05-24 | 台湾积体电路制造股份有限公司 | Etching stopping layer between substrate and isolation structure |
| CN109872953A (en) * | 2017-12-04 | 2019-06-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN110349913A (en) * | 2018-04-08 | 2019-10-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110752152A (en) * | 2019-10-17 | 2020-02-04 | 上海华力集成电路制造有限公司 | Process method for cutting off polysilicon gate of fin transistor |
| CN110858544A (en) * | 2018-08-22 | 2020-03-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN111509048A (en) * | 2020-04-28 | 2020-08-07 | 上海华力集成电路制造有限公司 | N-type fin transistor and manufacturing method thereof |
| CN112447510A (en) * | 2019-08-30 | 2021-03-05 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure and transistor |
| WO2023239400A1 (en) * | 2022-06-10 | 2023-12-14 | Applied Materials, Inc. | Method and apparatus for etching a semiconductor substrate in a plasma etch chamber |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050239290A1 (en) * | 2004-04-26 | 2005-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Trench photolithography rework for removal of photoresist residue |
| CN101393842A (en) * | 2007-09-20 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Slot forming method |
| CN102983079A (en) * | 2011-09-06 | 2013-03-20 | 联华电子股份有限公司 | Semiconductor technology |
| US20130099231A1 (en) * | 2011-10-24 | 2013-04-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
-
2014
- 2014-08-28 CN CN201410432180.0A patent/CN105448726B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050239290A1 (en) * | 2004-04-26 | 2005-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Trench photolithography rework for removal of photoresist residue |
| CN101393842A (en) * | 2007-09-20 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Slot forming method |
| CN102983079A (en) * | 2011-09-06 | 2013-03-20 | 联华电子股份有限公司 | Semiconductor technology |
| US20130099231A1 (en) * | 2011-10-24 | 2013-04-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107275215A (en) * | 2016-04-08 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin formula field effect transistor |
| CN109801914A (en) * | 2017-11-17 | 2019-05-24 | 台湾积体电路制造股份有限公司 | Etching stopping layer between substrate and isolation structure |
| CN109872953A (en) * | 2017-12-04 | 2019-06-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN110349913A (en) * | 2018-04-08 | 2019-10-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110349913B (en) * | 2018-04-08 | 2021-05-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110858544A (en) * | 2018-08-22 | 2020-03-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN110858544B (en) * | 2018-08-22 | 2023-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN112447510A (en) * | 2019-08-30 | 2021-03-05 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure and transistor |
| CN110752152A (en) * | 2019-10-17 | 2020-02-04 | 上海华力集成电路制造有限公司 | Process method for cutting off polysilicon gate of fin transistor |
| CN110752152B (en) * | 2019-10-17 | 2021-10-15 | 上海华力集成电路制造有限公司 | Process method for cutting off polysilicon gate of fin transistor |
| CN111509048A (en) * | 2020-04-28 | 2020-08-07 | 上海华力集成电路制造有限公司 | N-type fin transistor and manufacturing method thereof |
| WO2023239400A1 (en) * | 2022-06-10 | 2023-12-14 | Applied Materials, Inc. | Method and apparatus for etching a semiconductor substrate in a plasma etch chamber |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105448726B (en) | 2019-01-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11515418B2 (en) | Vertical tunneling FinFET | |
| KR101795875B1 (en) | Semiconductor structure and manufacturing method thereof | |
| CN105448726A (en) | Method for forming fin field effect transistor | |
| US8748247B2 (en) | Fin field-effect-transistor (FET) structure and manufacturing method | |
| US20160133696A1 (en) | Fin-fet structure and method of manufacturing same | |
| CN104752214B (en) | The forming method of fin field effect pipe | |
| CN107731918B (en) | Semiconductor structure and manufacturing method thereof | |
| US9679962B2 (en) | FinFET and method of manufacturing the same | |
| US9640660B2 (en) | Asymmetrical FinFET structure and method of manufacturing same | |
| CN107437506B (en) | Method for forming semiconductor structure | |
| CN107919324B (en) | Method for forming semiconductor device | |
| CN104752211A (en) | Fin type field-effect transistor and forming method thereof | |
| US20140120677A1 (en) | Methods of forming enhanced mobility channel regions on 3d semiconductor devices, and devices comprising same | |
| US10714469B2 (en) | Electrostatic discharge protection structure | |
| US10269972B2 (en) | Fin-FET devices and fabrication methods thereof | |
| CN109285778B (en) | Semiconductor device and method of forming the same | |
| US11563085B2 (en) | Transistors with separately-formed source and drain | |
| US11205593B2 (en) | Asymmetric fin trimming for fins of FinFET device | |
| KR102082630B1 (en) | Fin-fet and method for fabricating the same | |
| CN111863725B (en) | Semiconductor structure and forming method thereof | |
| CN108231682B (en) | Semiconductor device and method of forming the same | |
| CN107045982B (en) | Method for forming semiconductor structure | |
| CN106328528B (en) | Method for forming semiconductor structure | |
| CN104347413A (en) | Method for manufacturing FinFET semiconductor device | |
| US11217483B2 (en) | Semiconductor structure and fabrication method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |