CN105448726B - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
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- CN105448726B CN105448726B CN201410432180.0A CN201410432180A CN105448726B CN 105448726 B CN105448726 B CN 105448726B CN 201410432180 A CN201410432180 A CN 201410432180A CN 105448726 B CN105448726 B CN 105448726B
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Abstract
A kind of forming method of fin formula field effect transistor, comprising: semiconductor substrate is provided, is formed with fin in the semiconductor substrate；It is developed across the gate structure of the side wall and top section surface that cover the fin；Form the etching stop layer of covering fin and gate structure；Mask layer is formed on the etching stop layer, and there is the first opening of the etching stopping layer surface for the fin portion surface for exposing gate structure two sides in mask layer；The etching stop layer is etched along the first opening, the second opening is formed in etching stop layer, remains the impurity element entered in etching process in the fin of the second open bottom exposure；The processing of first impurity elimination prime element, remaining impurity element in the fin of removal the second opening exposure are carried out to the fin of the second open bottom exposure；It is etched back to removal part fin along the second opening, forms groove in the fin；Form the stress source/drain region filled in full groove.The method of the present invention improves the performance for the stress source/drain region to be formed.
Description
Technical field
The present invention relates to field of semiconductor fabrication, in particular to a kind of formation side of fin formula field effect transistor transistor
Method.
Background technique
MOS transistor adjusts by applying voltage in grid and generates switching signal by the electric current of channel region.But work as
When semiconductor technology enters 45 nanometers with lower node, traditional plane formula MOS transistor dies down to the control ability of channel current,
Cause serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, it, which is generally comprised, has
The gate structure of the top of fin described in the semiconductor fin of high-aspect-ratio, covering part and side wall is located at the gate structure
The gate structure of source region and drain region in the fin of two sides, fin formula field effect transistor can carry out fin from top and two sides
Control can be good at inhibiting short-channel effect with the grid more much better than than planar MOS transistors to the control ability of channel.
In addition, improving half by stress since stress can change the energy gap and carrier mobility of silicon materials
The performance of conductor device becomes more and more common means.Specifically, by suitable control stress, carrier can be improved
(electronics in NMOS device, the hole in PMOS device) mobility, and then driving current is improved, it is greatlyd improve with this and is partly led
The performance of body device.In order to enable fin formula field effect transistor has better performance, stress technique is also applied to fin field effect
It answers in transistor.
In the prior art with the fin formula field effect transistor of stress source/drain region, comprising: semiconductor substrate；Positioned at described
The fin of protrusion in semiconductor substrate；The side wall of fin described in covering part and the gate structure of top surface；Positioned at grid
Groove in the fin of structure two sides；Fill the stress source/drain region of full groove.The stress source/drain region is commonly used in described
The channel region of fin formula field effect transistor introduces stress, improves carrier mobility.
The material of the stress source/drain region is silicon carbide or SiGe, and the stress source/drain region uses selective epitaxial work
Skill is formed.
But the performance of the stress source/drain region of the prior art is still to be improved.
Summary of the invention
Problems solved by the invention is how to improve the performance of the stress source/drain region of formation.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, comprising: offer is partly led
Body substrate is formed with fin in the semiconductor substrate；It is developed across the side wall and top section surface for covering the fin
Gate structure；Form the etching stopping of the side wall and top surface and gate structure sidewall and top surface that cover the fin
Layer；Mask layer is formed on the etching stop layer, there is the first opening in the mask layer, and first opening exposes grid
The etching stop layer of the fin portion surface of pole structure two sides；The etching stop layer is etched along the first opening, in the etching stopping
The second opening for exposing fin top surface is formed in layer, is remained in the fin of the second open bottom exposure etched
The impurity element entered in journey；The processing of first impurity elimination prime element is carried out to the fin of the second open bottom exposure, removal second is opened
Remaining impurity element in the fin of mouth exposure；It is etched back to removal part fin along the second opening, forms groove in the fin；Shape
At the stress source/drain region filled in full groove.
Optionally, the etching stop layer using plasma etching technics is etched.
Optionally, the etching gas that the plasma etching uses is CH3F、O2And Ar.
Optionally, the plasma etching uses pulsed plasma etching, CH3The flow of F is 10~200sccm, O2's
The flow of flow 10~500sccm, Ar are 10~200sccm, and bias power source exports bias power, radio frequency in a pulsed fashion
Power source exports radio-frequency power in a pulsed fashion, and the frequency of bias power source and radio frequency power source is 10Hz~50KHz, duty
Than being 10%~80%.
Optionally, the impurity element is carbon and fluorine element.
Optionally, the first impurity elimination prime element processing is corona treatment.
Optionally, the gas that the corona treatment uses is H2And N2, H2Flow is 10~200sccm, N2Flow is
50~1000sccm, treatment temperature are 0~100 DEG C, and source power is 100~1000W, and bias power is 0~300W, time 10
~600S corona treatment.
Optionally, it is etched back to the etching gas that the fin is used using plasma etching industrial, plasma etching industrial
For HBr, O2And NF3。
It optionally, further include the fin exposed to groove after forming groove in the fin being etched back to removal part fin
Portion carries out the second decontamination processing.
Optionally, the second impurity elimination prime element processing is corona treatment.
Optionally, the gas that the corona treatment uses is H2And N2, H2Flow is 10~200sccm, N2Flow is
50~1000sccm, treatment temperature are 0~100 DEG C, and source power is 100~1000W, and bias power is 0~300W, time 10
~600S corona treatment.
Optionally, the material of the etching stop layer is silicon nitride or silicon oxynitride.
Optionally, after forming gate structure, the first side wall is formed in the two sides sidewall surfaces of the gate structure, in institute
The two sides sidewall surfaces for stating fin form the second side wall.
Optionally, using first side wall and gate structure as exposure mask, in the fin of gate structure and the first side wall two sides
It is interior to form shallow doped region.
Optionally, the mask layer include: filled layer, it is the dielectric antireflective coatings on filled layer, anti-positioned at dielectric
Organic antireflecting figure layer on reflectance coating, the photoresist layer on organic antireflective coating.
Optionally, dielectric antireflective coatings material is containing nitrogen compound.
Optionally, the material of the stress source/drain region is SiGe or silicon carbide.
Optionally, the formation process of the stress source/drain region is doping selective epitaxial process in situ.
Optionally, the fin formula field effect transistor is the fin formula field effect transistor of N-type or the fin field effect crystalline substance of p-type
Body pipe.
Optionally, the gate structure includes gate dielectric layer and the gate electrode on gate dielectric layer.
Compared with prior art, technical solution of the present invention has the advantage that
The forming method of fin formula field effect transistor of the invention etches the etching stop layer along the first opening, in institute
It states and is formed in etching stop layer after the second opening for exposing fin portion surface；The is carried out to the fin of the second open bottom exposure
The processing of one impurity elimination prime element removes remaining impurity element in the fin of the second opening exposure, so that etching fin forms groove
When, prevent in fin the factors such as remaining impurity element (such as carbon and fluorine element) density unevenness to the shadow of etch rate
It rings, to keep the flatness of the recess sidewall to be formed and bottom surface higher, in addition can prevent the fin for the bottom portion of groove to be formed
Remaining carbon ion and fluorine ion introduce defect in portion, ensure that the growing environment of stressor layers, reduce the stress source/drain region of formation
Middle generation defect.
Further, the plasma etch process for etching the etching stop layer is pulsed plasma etching, pulsed
The etching gas that plasma etching uses is CH3F、O2And Ar, CH3The flow of F is 10~200sccm, O2Flow 10~
The flow of 500sccm, Ar are 10~200sccm, and bias power source exports bias power in a pulsed fashion, radio frequency power source with
The mode of pulse exports radio-frequency power, and the frequency of bias power source and radio frequency power source is 10Hz~50KHz, duty ratio 10%
~80%, it can be very good the density and energy of the plasma that control is formed using pulsed plasma etching, complete to quarter
When losing the etching of stop-layer, remaining impurity element in fin is reduced as early as possible.
Further, the first impurity elimination prime element processing is corona treatment, the gas that the corona treatment uses
Body is H2And N2, when corona treatment, the hydrogeneous and nitrogenous plasma active enhancing of formation, more conducively in removal fin
Impurity element, there is stronger reproducibility containing hydrogen plasma, and remaining fluorine element then has an oxidisability in fin, hydrogen from
Son enters in fin, in conjunction with fluorine element remaining in fin, forms fluorocarbon and fin is discharged, and contains nitrogen plasma
It is then easy in conjunction with carbon, forms carboritride arrangement fin, to prevent fin when subsequent etching fin forms groove
Influence of the factors such as remaining carbon and fluorine element density unevenness to etch rate in portion, so that the recess sidewall formed
It is higher with the flatness of bottom surface, in addition prevent remaining carbon ion and fluorine ion in the fin for the bottom portion of groove to be formed from introducing
Defect ensure that the growing environment of stressor layers, reduces in the stress source/drain region of formation and generates defect.
Detailed description of the invention
Fig. 1 is the flow diagram of an embodiment fin formula field effect transistor forming method；
Fig. 2~Figure 11 is the schematic diagram of the section structure of fin formula field effect transistor of embodiment of the present invention forming process.
Specific embodiment
As described in the background art, the performance of stress source/drain region is formed in the fin of prior art fin formula field effect transistor
It is still to be improved, for example, the stress source/drain region that is formed there are lattice defect, uniformity is poor the problems such as.
The forming process of fin formula field effect transistor is studied, with reference to Fig. 1, comprising steps of step S101, provides half
Conductor substrate is formed with fin in the semiconductor substrate；Step S102 is developed across the side wall for covering the fin and top
The gate structure of part of the surface；Step S103 forms the side wall for covering the fin and top surface and gate structure sidewall
With the etching stop layer of top surface；Step S104 forms mask layer on the etching stop layer, has in the mask layer
First opening, first opening expose the etching stop layer of the fin portion surface of gate structure two sides；Step S105, along first
Opening etches the etching stop layer, and the second opening for exposing fin portion surface is formed in the etching stop layer；Step
S106 is etched back to removal part fin along the second opening, forms groove in the fin；Step S107 is formed and is filled in full groove
Stress source/drain region.The stress source/drain region of formation is located in the fin of gate structure two sides, therefore is forming stress source/drain region
The position for needing to define stress source-drain area to be formed before by mask layer and etching stop layer, for fin field effect crystalline substance
Special construction as body pipe, in order to make the mask layer to be formed that there is preferable surface thickness uniformity, the exposure mask generally formed
The thickness of layer can be very thick, is difficult etching stopping position when control forms the first opening, and forming etching stop layer can cover
Preferable stop position is obtained when forming the first opening in film layer.
Further study show that the material of etching stop layer is generally nitrogen silicon compound, such as silicon nitride, silicon oxynitride
Deng etching the etching stop layer is using plasma etching industrial, and the etching gas that plasma etching industrial uses is carbon containing
The gas of element and fluorine element, such as CHF3、CH2F2Mainly pass through chemical reaction to etching Deng, carbon containing and fluorine-containing plasma
Stop-layer performs etching, and when performing etching to etching stop layer, part carbon ion and fluorine ion are easily accessible etching stopping
It is reacted in the fin of layer bottom and with fin material, so that part carbon and fluorine element remain in the fin of etching stop layer bottom
In portion.
Carbon and fluorine element will affect the etch rate to fin in fin, due to carbon in the fin of the second open bottom
Being unevenly distributed for element and fluorine element concentration, so that the etch rate of the fin of different places is not identical, is being etched back to remove
When part fin forms groove, the flatness on the bottom and side wall surface of the groove of formation is poor (surface irregularity), subsequent
When forming stress source/drain region by epitaxy technique in a groove, the stress source/drain region of formation and the interface of groove are easy to produce
Lattice defect, and rough bottom and side wall surface makes the growth rate of different directions stressor layers not identical, is formed
Stress source/drain region surface uniformity it is also poor；In addition, remaining carbon and fluorine member in the side wall of groove and the bottom of bottom
Element can introduce defect, change the growing environment of stressor layers, will affect the growth of stressor layers, be easy in forming stress source-drain area
Generate defect.
For this purpose, the present invention provides a kind of fin formula field effect transistor and forming method thereof, described in the first opening etching
Etching stop layer is formed in the etching stop layer after the second opening for exposing fin portion surface；To the second open bottom
Exposed fin carries out the processing of the first impurity elimination prime element, removes remaining impurity element in the fin of the second opening exposure, thus
Influence of the remaining impurity element to being etched back to when fin forms groove in fin is prevented, side wall and the surface of the groove to be formed are made
With preferable surface smoothness, makes to be formed lattice defect in stress source/drain region and reduce, and there is preferable uniformity.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.In addition, in reality
It should include the three-dimensional space of length, width and depth in production.
Fig. 2~Figure 11 is the schematic diagram of the section structure of fin formula field effect transistor of embodiment of the present invention forming process.
Referring to FIG. 2, providing semiconductor substrate 200, fin 201 is formed in the semiconductor substrate 200；It is developed across
Cover the side wall of the fin 201 and the gate structure 203 on top section surface.
The semiconductor substrate 200 can be silicon or silicon-on-insulator (SOI), and the semiconductor substrate 200 can also be with
It is germanium, germanium silicon, GaAs or germanium on insulator, the material of semiconductor substrate 200 described in this implementation is silicon.
200 surface of semiconductor substrate is formed with the fin 201 of several protrusions, and in the present embodiment, the fin 201 is logical
The formation of over etching semiconductor substrate 200, in other embodiments of the invention, the fin 201 is formed by epitaxy technique.Institute
State in fin 201 can according to the type difference of the fin formula field effect transistor of formation doped with different types of foreign ion,
It in one embodiment, can be with when fin formula field effect transistor to be formed is p-type fin formula field effect transistor, in fin 201
Doped N-type foreign ion；In another embodiment, when fin formula field effect transistor to be formed is N-type fin field effect crystal
Guan Shi, can be with doped p-type foreign ion in fin 201.The N-type impurity ion is phosphonium ion, arsenic ion, one in antimony ion
Kind is several, and the p type impurity ion is one or more of boron ion, gallium ion, indium ion.
In the present embodiment, separation layer 205 is also formed in the semiconductor substrate 200, the surface of the separation layer 205 is low
In the top surface of fin 201, the separation layer 205 is used for the adjacent fin 201 of electric isolation and adjacent gate structure, institute
The material for stating separation layer 205 is silica, silicon nitride or silicon oxynitride, and the material of separation layer 205 described in the present embodiment is oxygen
SiClx.The detailed process that separation layer 205 is formed are as follows: be initially formed the isolation material for covering the semiconductor substrate 200 and fin 201
The bed of material；Then the spacer material layer is planarized using chemical mechanical milling tech, is to stop with the top surface of fin 201
Layer；Then it is etched back to the removal part spacer material layer, forms separation layer 205, the surface of the separation layer 205 is lower than fin
201 top surface.
It is also formed with gate structure 203 on the side wall and top surface of the fin 201, referring to FIG. 3, Fig. 3 is the edge Fig. 2
The schematic diagram of the section structure in the direction cutting line CD, the gate structure 203 include: cover the fin 201 partial sidewall and
The gate dielectric layer 21 of top surface and the gate electrode 22 on gate dielectric layer 21.
The forming process of the gate structure 203 are as follows: form the gate dielectric material for covering fin 201 side wall and bottom
Layer；Layer of gate electrode material is formed on the gate dielectric material layer；Etch the layer of gate electrode material and gate dielectric material layer, shape
Gate electrode 22 at gate dielectric layer 21 and on gate dielectric layer 21.
The material of the gate dielectric layer 21 is silica, and the material of the gate electrode 22 is polysilicon.In its of the invention
In his embodiment, the material of the gate dielectric layer can be high-k dielectric material, such as hafnium oxide etc., the material of the gate electrode
Can to be metal, such as tungsten etc..
With continued reference to FIG. 2, forming the first side wall 204 on the two sides side wall of the gate structure 203；With the grid
Structure 203 and the first side wall 204 are exposure mask, are shallowly adulterated to the fin 201 of 204 two sides of gate structure 203 and the first side wall
Ion implanting forms shallow doped region in the fin 201 of 204 two sides of the gate structure 203 and the first side wall and (does not show in figure
Out).
The foreign ion of the shallow Doped ions injection injection is the foreign ion of N-type or the foreign ion of p-type, inject from
The dosage range of son is 1E13atom/cm2~2E15atom/cm2, the energy range of injection is 0.5KeV~10KeV.When to shape
At fin formula field effect transistor be p-type fin formula field effect transistor when, shallow Doped ions inject injecting p-type foreign ion；When
When fin formula field effect transistor to be formed is N-type fin formula field effect transistor, shallow Doped ions injection injection N-type impurity from
Son.
It is the schematic diagram of the section structure of the Fig. 2 along the direction cutting line AB, the fin in conjunction with reference Fig. 2 and Fig. 4, described Fig. 4
The second side wall 202 is also formed on 201 two sides side wall, second side wall 202 is subsequent at 203 liang of gate structure for limiting
The fin 201 of side forms the position of groove and stress source/drain region.
Second side wall 202 can be single-layer or multi-layer stacked structure, and the material of the second side wall 202 can be oxidation
Silicon, silicon nitride etc..
In one embodiment, second side wall 202 is the silicon nitride of single layer, and the second side wall 202 and the first side wall 204 are logical
It crosses same processing step to be formed, detailed process are as follows: form the side wall for covering the fin 201 and top surface and grid knot
The spacer material layer of 203 side wall of structure and top surface；Without spacer material layer described in mask etching, in the gate structure 203
The first side wall 204 is formed on the side wall of two sides, and the second side wall 202 is formed on the two sides side wall of the fin 201.
With reference to Fig. 5, the side wall for covering the fin 201 and top surface and gate structure sidewall and top surface are formed
Etching stop layer 206.It should be noted that Fig. 5 and subsequent drawings are to carry out on the basis of fig. 4 in the embodiment of the present invention
The schematic diagram of the section structure that the forming process of fin formula field effect transistor obtains.
The etching stop layer 206 is as the subsequent stop-layer in mask layer when the first opening of formation.
206 material of etching stop layer is nitrogen silicon compound, such as silicon nitride or silicon oxynitride etc., etching stop layer
206 with a thickness of 100~1000 angstroms.The etching stop layer 206 is formed by chemical vapor deposition process.
With reference to Fig. 6, mask layer is formed on the etching stop layer 206.
The exposure mask when mask layer is as etching stop layer 206 described in subsequent etching and part fin 201.
In the present embodiment, the mask layer includes: filled layer 207, the dielectric antireflective coatings on filled layer 207
208, the organic antireflective coating 209 in dielectric antireflective coatings 208, the photoetching on organic antireflective coating 209
Glue-line 210.
The filled layer 207 has good filling capacity, and has preferable surface smoothness, so as to form photoresist
Layer 210 has preferable the thickness uniformity.The material of the filled layer 207 is silica, can use mobility chemical gaseous phase
Depositing operation forms filled layer 207.
The dielectric antireflective coatings (Dielectric Anti-Reflection Coating) 208 and organic antireflecting
Coating (Organic Anti-Reflective Coating) 209 is for reducing bottom when being exposed to photoresist layer 210
The reflection of light so that the size and position precision of the opening formed in photoresist layer 210 are higher, and has good side wall
Pattern, to improve so that the precision of the positions and dimensions of the first opening, the second opening and the groove that are subsequently formed is higher.
208 material of dielectric antireflective coatings is containing nitrogen compound, such as titanium nitride or silicon nitride etc., the dielectric anti-reflective
It penetrates coating 208 and passes through plasma reinforced chemical vapour deposition (PECVD, Plasma Enhanced Chemical Vapour
Deposition it) is formed, the material of the organic antireflective coating 209 is organic matter, is formed by spin coating proceeding.
In other embodiments of the invention, the mask layer can be other structures or material.
With reference to Fig. 7, the first opening 211 is formed in the mask layer, first opening 211 exposes gate structure two
The etching stop layer 206 on 201 surface of fin of side.
The first son opening is formed in photoresist layer 210 by exposure development technique, then uses plasma etching industrial
The organic antireflective coating 209, dielectric antireflective coatings 208 and filled layer 207 are etched along the first son opening, described organic
The second son opening, the first son opening and the are formed in anti-reflection coating 209, dielectric antireflective coatings 208 and filled layer 207
Two son openings constitute the first opening 211.
Etch the organic antireflective coating 209, etching gas that dielectric antireflective coatings 208 use is CHF3And O2, carve
Etching gas that the filled layer 207 uses is lost for CF4、CHF3And Ar.
It is formed in the etching stop layer 206 with reference to Fig. 8 along the 211 etching etching stop layer 206 of the first opening
The second opening 212 of 201 top surface of fin is exposed, remains quarter in the fin 201 of second opening, 212 bottom-exposeds
The impurity element generated during erosion.
Etch the 206 using plasma etching technics of etching stop layer.The etching that the plasma etching uses
Gas is CH3F、O2And Ar, CH3The flow of F is 50~500sccm, O2Flow be 5~200sccm, the flow of Ar is 5~
200sccm, source power are 500~2500W, and bias power is 0~300W.
After the completion of etching, second opening 212 bottoms fin 201 in can remain impurity element, comprising: carbon and
The reason of fluorine element (with the state presence of ion), carbon and fluorine element remain are as follows: on the one hand, due to carbon and fluorine element
Activity it is stronger, and atomic radius is smaller, readily diffuses into etching stopping in the etching process to etching stop layer 206
In the fin 201 of 206 bottom of layer, on the other hand, during plasma etching, the plasma of source power and bias power to formation
Acceleration can be generated, carbon and fluorine element can be also injected into the fin 201 of the second open bottom exposure.
Remaining carbon and fluorine element not only will affect the surface uniformity for the groove being subsequently formed in fin 201, also
The performance of the stress source/drain region of epitaxial growth in groove can be had an impact.
In other embodiments of the invention, the plasma etching use pulsed plasma etching, pulsed etc. from
The etching gas that son etching uses is CH3F、O2And Ar, CH3The flow of F is 10~200sccm, O210~500sccm of flow,
The flow of Ar is 10~200sccm, and bias power source exports bias power in a pulsed fashion, and radio frequency power source is with the side of pulse
The frequency of formula output radio-frequency power, bias power source and radio frequency power source is 10Hz~50KHz, and duty ratio is 10%~80%,
The density and energy that can be very good the plasma that control is formed using pulsed plasma etching are completed to etching stop layer
When 206 etching, remaining impurity element in fin 201 is reduced as early as possible.
With reference to Fig. 9, the first impurity elimination prime element processing 23 is carried out to the fin 201 of the second 212 bottom-exposeds of opening, removes fin
Remaining impurity element in portion 201.
The first impurity elimination prime element processing 23 is corona treatment.
The gas that the corona treatment uses is H2And N2, H2Flow is 10~200sccm, N2Flow be 50~
1000sccm (standard milliliters/point), treatment temperature is 0~100 DEG C, and source power is 100~1000W, and bias power is 0~300W
(watt), time are 10~600S (second), in more effectively removal fin while impurity element, prevent the damage to fin 201
Wound.When corona treatment, the hydrogeneous and nitrogenous plasma active enhancing of formation is more conducively miscellaneous in removal fin 201
Prime element has stronger reproducibility containing hydrogen plasma, and remaining fluorine element then has an oxidisability in fin 201, hydrogen from
Son enters in fin 201, in conjunction with fluorine element remaining in fin 201, forms fluorocarbon and fin 201 is discharged, and contains
Nitrogen plasma is then easy in conjunction with carbon, carboritride arrangement fin 201 is formed, thus in subsequent etching fin 201
When forming groove, influence of the factors such as remaining carbon and fluorine element density unevenness to etch rate in fin 201 is prevented, from
And make the flatness of the recess sidewall to be formed and bottom surface higher, in addition prevent residual in the fin for the bottom portion of groove to be formed
Carbon ion and fluorine ion introduce defect, ensure that the growing environment of stressor layers, reduce in the stress source/drain region of formation generate lack
It falls into.
With reference to Figure 10, it is etched back to removal part fin 201 along the second opening 212, forms groove 214 in fin 201.
The fin 201 is etched back to using plasma etching industrial, the etching gas that plasma etching industrial uses for
HBr、O2And NF3。
It after forming groove 214 in fin 201, further include that the second decontamination is carried out to the fin 201 of the exposure of groove 214
Processing.The purpose for carrying out the second impurity treatment is: failing to completely remove when being on the one hand further removal the first decontamination processing
Remain in carbon and fluorine element in fin 201；On the other hand it is to be etched back to part fin 201, when forming groove 214, draws
The new impurity element entered, such as fluorine element.
The second decontamination processing is corona treatment.
The gas that the corona treatment uses is H2And N2, H2Flow is 10~200sccm, N2Flow be 50~
1000sccm, treatment temperature be 0~100 DEG C, source power be 100~1000W, bias power be 0~300W, the time be 10~
600S。
In other embodiments of the invention, if the quantity of remaining impurity element is more in fin 201, position compared with
It is deep, it is difficult to remove by a decontamination processing, in order to more effectively remove remaining impurity element in fin 201, is being etched
The etching stop layer 206, it is alternate to carry out decontamination step and quarter after forming the second opening 212 in etching stop layer 206
Step is lost, until forming groove 214, specific step in the fin 201 of gate structure two sides are as follows: carry out first step decontamination
Step removes part of impurity elements in the fin of the second open bottom exposure (impurity element includes carbon and fluorine element)；Into
Row first step etch step forms the first sub- groove along the fin of the second opening etching removal segment thickness；Second step is carried out to go
Impurity step removes the impurity element in the fin of the first sub- bottom portion of groove；Second step etch step is carried out, along the first sub- groove
The fin of etching removal segment thickness, forms the second sub- groove；Carry out N (N >=3) step decontamination step, removal N-1 (N >=
3) impurity element in the fin of sub- bottom portion of groove；N (N >=3) step etch step is carried out, along the second sub- recess etch removal portion
Divide the fin of thickness, forms groove 214.
By alternately carrying out decontamination step and etch step, thus in entire etching process, so that each step is carved
Erosion step not will receive the influence of impurity element, so that the flatness of the side wall of the groove formed and bottom surface is more
It is good.
Deimpurity effect is preferably gone in order to reach, improves the side wall of the groove of formation and the flatness of bottom surface,
The gas that first step decontamination step, second step decontamination step ... N (N >=3) step decontamination step use is H2And N2,
H2Flow is 10~200sccm, N2Flow be 50~1000sccm, treatment temperature be 0~100 DEG C, source power be 100~
1000W, bias power are 0~300W, and each step time is 5~500S；First step etch step, second step etch step ...
The gas that N (N >=3) step etch step uses is HBr, O2And NF3, the flow of HBr is 50-500sccm, O2Flow be 10-
500sccm, NF3Flow be 10-500sccm, source power be 100~1000W, bias power be 0~300W, each step time
For 5~500S.
With reference to Figure 11, the stress source/drain region 213 filled in full groove 214 (referring to Figure 10) is formed.
The material of the stress source/drain region 213 is SiGe or silicon carbide.In the particular embodiment, when to be formed
When fin formula field effect transistor is the fin formula field effect transistor of N-type, the material of the stress source/drain region 213 is silicon carbide, when
When fin formula field effect transistor to be formed is the fin formula field effect transistor of p-type, the material of the stress source/drain region 213 is
SiGe.
Form the process selectivity epitaxy technique of the stress source/drain region 213.
Doped with foreign ion in the stress source/drain region 213, by doping process in situ when can choose epitaxy technique
It is formed, or is formed by ion implantation technology.
The foreign ion includes N-type impurity ion and p type impurity ion, and the N-type impurity ion is phosphonium ion, arsenic
One or more of ion, antimony ion, the p type impurity ion are one of boron ion, gallium ion, indium ion or several
Kind.In the particular embodiment, when fin formula field effect transistor to be formed is the fin formula field effect transistor of N-type, stress
The foreign ion adulterated in source/drain region 213 is N-type impurity ion, when the fin that fin formula field effect transistor to be formed is p-type
When field effect transistor, the foreign ion adulterated in stress source/drain region 213 is p type impurity ion.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of fin formula field effect transistor characterized by comprising
Semiconductor substrate is provided, is formed with fin in the semiconductor substrate；
It is developed across the gate structure of the side wall and top section surface that cover the fin；
Form the etching stop layer of the side wall and top surface and gate structure sidewall and top surface that cover the fin；
Mask layer is formed on the etching stop layer, there is the first opening in the mask layer, and first opening exposes
The etching stop layer of the fin portion surface of gate structure two sides；
The etching stop layer is etched along the first opening, is formed in the etching stop layer and exposes the of fin top surface
Two are open, and remain the impurity element entered in etching process in the fin of the second open bottom exposure；
The processing of first impurity elimination prime element is carried out to the fin of the second open bottom exposure, removal second is open residual in the fin of exposure
The impurity element stayed；
It is etched back to removal part fin along the second opening, forms groove in the fin；
Form the stress source/drain region filled in full groove.
2. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that etch the etching stopping
Layer using plasma etching technics.
3. the forming method of fin formula field effect transistor as claimed in claim 2, which is characterized in that the plasma etching
The etching gas used is CH3F、O2And Ar.
4. the forming method of fin formula field effect transistor as claimed in claim 3, which is characterized in that the plasma etching is adopted
With pulsed plasma etching, CH3The flow of F is 10~200sccm, O2Flow 10~500sccm, Ar flow be 10~
200sccm, bias power source export bias power in a pulsed fashion, and radio frequency power source exports radio frequency function in a pulsed fashion
The frequency of rate, bias power source and radio frequency power source is 10Hz~50KHz, and duty ratio is 10%~80%.
5. the forming method of fin formula field effect transistor as claimed in claim 3, which is characterized in that the impurity element is carbon
Element and fluorine element.
6. the forming method of fin formula field effect transistor as claimed in claim 5, which is characterized in that the first decontamination member
Element processing is corona treatment.
7. the forming method of fin formula field effect transistor as claimed in claim 6, which is characterized in that the corona treatment
The gas used is H2And N2, H2Flow is 10~200sccm, N2Flow is 50~1000sccm, and treatment temperature is 0~100
DEG C, source power is 100~1000W, and bias power is 0~300W, and the time is 10~600S.
8. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that be etched back to the fin and adopt
With plasma etching industrial, the etching gas that plasma etching industrial uses is HBr, O2And NF3。
9. the forming method of fin formula field effect transistor as claimed in claim 8, which is characterized in that be etched back to removal part
Fin further includes carrying out the second decontamination processing to the fin of groove exposure after forming groove in the fin.
10. the forming method of fin formula field effect transistor as claimed in claim 9, which is characterized in that second decontamination
Element processing is corona treatment.
11. the forming method of fin formula field effect transistor as claimed in claim 10, which is characterized in that at the plasma
The gas used is managed as H2And N2, H2Flow is 10~200sccm, N2Flow is 50~1000sccm, and treatment temperature is 0~100
DEG C, source power is 100~1000W, and bias power is 0~300W, and the time is 10~600S.
12. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the etching stop layer
Material be silicon nitride or silicon oxynitride.
13. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that forming gate structure
Afterwards, the first side wall is formed in the two sides sidewall surfaces of the gate structure, forms second in the two sides sidewall surfaces of the fin
Side wall.
14. the forming method of fin formula field effect transistor as claimed in claim 13, which is characterized in that with first side wall
It is exposure mask with gate structure, forms shallow doped region in the fin of gate structure and the first side wall two sides.
15. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the mask layer includes:
Filled layer, the organic antireflecting figure layer in dielectric antireflective coatings, is located at the dielectric antireflective coatings on filled layer
Photoresist layer on organic antireflective coating.
16. the forming method of fin formula field effect transistor as claimed in claim 15, which is characterized in that dielectric antireflective coatings
Material is containing nitrogen compound.
17. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the stress source/drain region
Material be SiGe or silicon carbide.
18. the forming method of fin formula field effect transistor as claimed in claim 17, which is characterized in that the stress source/drain
The formation process in area is doping selective epitaxial process in situ.
19. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the fin field effect
Transistor is the fin formula field effect transistor of N-type or the fin formula field effect transistor of p-type.
20. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the gate structure packet
Include gate dielectric layer and the gate electrode on gate dielectric layer.
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| CN107275215B (en) * | 2016-04-08 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fin field effect transistor |
| US10978351B2 (en) * | 2017-11-17 | 2021-04-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch stop layer between substrate and isolation structure |
| CN109872953B (en) * | 2017-12-04 | 2022-02-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN110349913B (en) * | 2018-04-08 | 2021-05-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110858544B (en) * | 2018-08-22 | 2023-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN112447510A (en) * | 2019-08-30 | 2021-03-05 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure and transistor |
| CN110752152B (en) * | 2019-10-17 | 2021-10-15 | 上海华力集成电路制造有限公司 | Process method for cutting off polysilicon gate of fin transistor |
| CN111509048A (en) * | 2020-04-28 | 2020-08-07 | 上海华力集成电路制造有限公司 | N-type fin transistor and manufacturing method thereof |
| US20230402286A1 (en) * | 2022-06-10 | 2023-12-14 | Applied Materials, Inc. | Method and apparatus for etching a semiconductor substrate in a plasma etch chamber |
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| CN101393842A (en) * | 2007-09-20 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Slot forming method |
| CN102983079A (en) * | 2011-09-06 | 2013-03-20 | 联华电子股份有限公司 | Semiconductor technology |
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| US7265053B2 (en) * | 2004-04-26 | 2007-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Trench photolithography rework for removal of photoresist residue |
| JP6045285B2 (en) * | 2011-10-24 | 2016-12-14 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101393842A (en) * | 2007-09-20 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Slot forming method |
| CN102983079A (en) * | 2011-09-06 | 2013-03-20 | 联华电子股份有限公司 | Semiconductor technology |
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