CN106158641A - FinFET device and preparation method thereof - Google Patents
FinFET device and preparation method thereof Download PDFInfo
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- CN106158641A CN106158641A CN201510158698.4A CN201510158698A CN106158641A CN 106158641 A CN106158641 A CN 106158641A CN 201510158698 A CN201510158698 A CN 201510158698A CN 106158641 A CN106158641 A CN 106158641A
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- 150000002500 ions Chemical class 0.000 claims description 141
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 13
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- 239000000463 material Substances 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
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- 230000002093 peripheral effect Effects 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 9
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 7
- 239000007790 solid phase Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
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- 238000002513 implantation Methods 0.000 claims description 3
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- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- 239000002019 doping agent Substances 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
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- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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- 239000010937 tungsten Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
This application provides a kind of finFET device and preparation method thereof.This manufacture method includes: arrange fin and oxide layer on substrate, district, heavy doping well region and second is lightly doped near the first of substrate setting successively doped with the first foreign ion and formation district is lightly doped in fin；Fin arranges grid structure and side wall；With grid structure and side wall as mask, etching fin is to form depressed part on fin, and the end face of depressed part is positioned in heavy doping well region；Depressed part carrying out the second foreign ion and injects formation ion implanted region, the second foreign ion is the transoid ion of the first foreign ion；And source electrode and drain electrode are set at ion implanted region.Above-mentioned manufacture method does not interferes with original effect improving short-channel effect, and effectively reduces leakage current between source electrode, drain electrode and the substrate that heavily doped existence causes.
Description
Technical field
The application relates to technical field of manufacturing semiconductors, in particular to a kind of finFET device and preparation method thereof.
Background technology
Existing complementary metal oxide semiconductors (CMOS) (CMOS) transistor is two-dimentional, along with constantly reducing of channel dimensions, with
The relevant problem of short-channel effect is increasingly difficult to overcome.Therefore, chip manufacturer developing have higher effect three-dimensional stand
The transistor of body formula, such as fin formula field effect transistor (FinFET), it can better adapt to scaled the wanting of device size
Ask.
The method of existing formation FinFET generally includes following processing step: the shape of the formation of fin (Fin) → well region injection → grid
The selective growth of the formation → source/drain region of the formation of one-tenth → sidewall → expansion area injection → sidewall → source/drain region injection → autoregistration
The formation of the formation → contact hole of silicide and other front end operation.In above-mentioned processing step, fin (Fin) be formed with two kinds
Method.A kind of method is: be initially formed a silicon oxide layer on silicon substrate to form silicon-on-insulator (SOI) structure, then absolutely
Above epitaxial growth one silicon layer of edge body silicon-on, etching silicon layer is to form fin；The shortcoming of the method is: manufacturing cost is the highest,
The thermal diffusivity of silicon oxide layer relatively silicon substrate is poor simultaneously, can cause the heat in raceway groove can not be the most lost, causes temperature to raise,
Affect mobility, device performance is had negative effect.
Another kind of method is: directly etch fin on silicon substrate, then on silicon substrate deposition oxide to isolate fin.In shape
After becoming fin, use the flow process shown in Fig. 1 to form finFET device, wherein, after silicon substrate forms fin, fin is carried out
Well region injects, and on fin, formation first shown in Fig. 2 is lightly doped district 111 ', heavy doping well region and second and district 131 ' is lightly doped, with
Control the generation of short-channel effect, improve the grid structure 103 ' control ability to raceway groove, reduce grid voltage pinch off (pinch off)
The difficulty of raceway groove, it is to avoid the generation of sub-threshold leakage (Subthreshold leakage) phenomenon；Then, on the fin surface shown in Fig. 2
On grid structure 103 ' is set, this grid structure includes the hard mask 133 ' shown in Fig. 3, grid 132 ' and gate oxide 131 '；
The side wall 104 ' shown in Fig. 4 is formed in the both sides of the grid structure 103 ' shown in Fig. 3；With the grid structure shown in Fig. 4 and side wall
For mask, etch fin, form the device with cross-section structure shown in Fig. 5；At fin Epitaxial growth exposed shown in Fig. 5,
Form the source area 106 ' shown in Fig. 6 and drain region 107 '；With grid structure 103 ' with side wall 104 ' as mask, to shown in Fig. 6
Source area 106 ' and drain region 107 ' carry out ion implanting, form the source electrode 108 ' shown in Fig. 7 and drain electrode 109 '.
As seen from Figure 7, well region injects the existence of the heavy doping well region formed, and causes between source electrode, drain electrode and silicon substrate
Leakage current increase, this leakage current be formed device open-circuit current main reason.
Summary of the invention
The application aims to provide a kind of finFET device and preparation method thereof, leads solving the existence of heavy doping well region in prior art
Cause source electrode, problem that leakage current between drain electrode and silicon substrate increases.
To achieve these goals, according to an aspect of the application, it is provided that the manufacture method of a kind of finFET device, this system
Include as method: fin and oxide layer are set on substrate, doped with the first foreign ion and formed successively near substrate in fin
First arranged is lightly doped district, heavy doping well region and second and district is lightly doped；Fin arranges grid structure and side wall；With grid
Structure and side wall are mask, and etching fin is to form depressed part on fin, and the end face of depressed part is positioned in heavy doping well region；Right
Depressed part carries out the second foreign ion and injects formation ion implanted region, and the second foreign ion is the transoid ion of the first foreign ion；
And source electrode and drain electrode are set at ion implanted region.
Further, first district and second is lightly doped in the district concentration of first foreign ion to be lightly doped be n1, in heavy doping well region
The concentration of one foreign ion is n2, and n1＜ n2, in ion implanted region, the concentration of the second foreign ion is n3, and n3＜ n2, wherein,
n2With n3Difference and n1Ratio be 0.9:1～1:1.1.
Further, n1For 1E13～1E14atoms/cm3, n2For 1E15～1E17atoms/cm3, n3For
5E14～1E16atoms/cm3。
Further, in the step that the second foreign ion injects, Implantation Energy is 40～80KeV, and implantation dosage is
1E12～1E14atoms/cm2。
Further, the first foreign ion is p-type ion, and the second foreign ion is N-type ion；Or the first foreign ion is
N-type ion, the second foreign ion is p-type ion, and N-type ion is P or As, and p-type ion is B.
Further, the process arranging source/drain includes: carry out epitaxial growth at ion implanted region, forms source area and drain region；
Source area and drain region are carried out ion implanting and forms source electrode and drain electrode.
Further, epitaxial growth is solid-phase epitaxial growth or laser epitaxial growth.
Further, the setting up procedure of grid structure includes: arrange oxide on exposed fin and oxide layer；At oxide
Upper deposit polycrystalline silicon；Deposition of dielectric materials on the polysilicon, dielectric material be silicon oxide, hafnium oxide, aluminium oxide, silicon nitride or
Silicon oxynitride；It is sequentially etched dielectric material, polysilicon and oxide, forms grid structure, wherein, shape after dielectric material etching
Become the gate dielectric layer of grid structure, after etching polysilicon, form the grid of grid structure, after oxide etching, form grid structure
Gate oxide.
Further, gate oxide uses chemical vapour deposition technique, physical vaporous deposition or thermal oxidation method setting to form.
Further, the setting up procedure of side wall includes: deposit spacer material in grid structure, exposed fin and oxide layer,
Spacer material is silicon nitride and the composite of silicon oxide, silicon nitride or silicon oxide；Spacer material is performed etching formation side wall.
Present invention also provides a kind of finFET device, this finFET device includes: substrate, the fin being arranged on substrate and oxygen
Change layer, be provided with in fin and district, heavy doping well region and second be lightly doped near substrate and the first of the first foreign ion that adulterates successively
District is lightly doped, and fin has center knob and peripheral recesses portion, and the surface away from substrate in peripheral recesses portion is positioned at heavy doping trap
Qu Zhong, finFET device also includes grid structure and the side wall being positioned on center knob, and the source electrode of peripherally located depressed part
And drain electrode, doped with the second foreign ion in the heavy doping well region of peripherally located depressed part, the second foreign ion be the first impurity from
The transoid ion of son.
The technical scheme of application the application, depressed part to form depressed part on fin, and is carried out by the application by etching fin
Second foreign ion injects and forms ion implanted region, and the second foreign ion is the transoid ion of the first foreign ion, thus decreases
The valid density of the first foreign ion being positioned in the heavy doping well region below source electrode and drain electrode, and it is positioned at the weight below grid structure
In doped well region, the first foreign ion remains in that high valid density is adulterated, and therefore, does not interferes with and original improves short-channel effect
Effect, and effectively reduce leakage current between source electrode, drain electrode and the substrate that heavily doped existence causes.
Accompanying drawing explanation
The Figure of description of the part constituting the application is used for providing further understanding of the present application, and the application's is schematic real
Execute example and illustrate for explaining the application, being not intended that the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the Making programme schematic diagram of finFET device in prior art；
The device profile structural representation that Fig. 2 to Fig. 7 obtains after showing each flow process shown in enforcement Fig. 1, wherein,
Fig. 2 shows after forming fin and oxide layer on silicon substrate, carries out the cross-sectional view after well region injection；
Fig. 3 shows the cross-sectional view after arranging grid structure on the fin surface shown in Fig. 2, and Fig. 3 is along Fig. 2's
The cross-sectional view of line A-A；
Fig. 4 shows the cross-sectional view after the both sides of the grid structure shown in Fig. 3 form side wall；
Fig. 5 shows the cross-sectional view as mask, after etching fin with the grid structure shown in Fig. 4 and side wall；
Fig. 6 shows at fin Epitaxial growth exposed shown in Fig. 5, forms the cross-sectional view behind source area and drain region；
Fig. 7 shows with the grid structure shown in Fig. 6 and side wall as mask, and source area and drain region are carried out ion implanting, shape
Become the cross-sectional view after source electrode and drain electrode；
Fig. 8 shows the Making programme schematic diagram of the finFET device that the application provides；
The device profile structural representation that Fig. 9 to Figure 15 obtains after showing each flow process shown in enforcement Fig. 8, wherein,
Fig. 9 shows and arranges fin and oxide layer on substrate, and fin carries out the cross-sectional view after well region injection；
Figure 10 shows the cross-sectional view after arranging grid structure on the fin shown in Fig. 9, Figure 11 be Figure 10 along A-A
The cross-sectional view of line；
Figure 11 shows the cross-sectional view after the side formation side wall of grid structure；
Figure 12 shows with the grid structure shown in Figure 11 and side wall as mask, after etching fin is to form depressed part on fin
Cross-sectional view；
Figure 13 shows that the depressed part in Figure 12 carries out the cross-section structure after the second foreign ion injects formation ion implanted region to be shown
It is intended to；
Figure 14 shows that the cross-section structure that the ion implanted region shown in Figure 13 is carried out after being epitaxially-formed source area and drain region shows
It is intended to；And
Figure 15 shows and the source area shown in Figure 14 and drain region carries out the cross-section structure after ion implanting forms source electrode and drain electrode
Schematic diagram.
Detailed description of the invention
It it is noted that described further below is all exemplary, it is intended to provide further instruction to the application.Unless otherwise finger
Bright, all technology used herein and scientific terminology have and are generally understood that with the application person of an ordinary skill in the technical field
Identical meanings.
It should be noted that term used herein above merely to describe detailed description of the invention, and be not intended to restricted root according to this Shen
Illustrative embodiments please.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to
Including plural form, additionally, it should be understood that, when using term " to comprise " in this manual and/or time " including ", its
Indicate existing characteristics, step, operation, device, assembly and/or combinations thereof.
For the ease of describing, space relative terms here can be used, as " ... on ", " ... top ", " ...
Upper surface ", " above " etc., be used for describing such as a device shown in the figure or feature and other devices or the space bit of feature
Put relation.It should be appreciated that space relative terms is intended to comprise using in addition to the orientation that device is described in the drawings
Or the different azimuth in operation.Such as, " above other devices or structure " if the device in accompanying drawing is squeezed, then it are described as
Or will be positioned as after the device of " on other devices or structure " " at other devices or below constructing " or " at other devices or
Under structure ".Thus, exemplary term " in ... top " can include " in ... top " and " in ... lower section " two kinds of orientation.
This device can also other different modes location (90-degree rotation or be in other orientation), and to space used herein above phase
Respective explanations is made in description.
As background technology is introduced, the concentration impurity ion in existing finFET device fin between the source and drain is relatively
Greatly, the leakage current being easily caused between source electrode, drain electrode and silicon substrate increases, and this leakage current is the master forming device open-circuit current
Want the origin cause of formation, in order to avoid the generation of above-mentioned leakage current, present applicant proposes a kind of finFET device and preparation method thereof.
As shown in Figure 8, the manufacture method of this finFET device includes: arrange fin 101 and oxide layer 102 on the substrate 100,
District 111, heavy doping trap are lightly doped near the first of substrate 100 setting successively doped with the first foreign ion and formation in fin 101
District 121 and second is lightly doped district 131；Fin 101 arranges grid structure 103 and side wall 104；With grid structure 103 He
Side wall 104 is mask etching fin 101 to form depressed part on fin 101, and the end face of depressed part is positioned at heavy doping well region 121
In；Depressed part carrying out the second foreign ion and injects formation ion implanted region 105, the second foreign ion is the anti-of the first foreign ion
Type ion；And source electrode 108 and drain electrode 109 are set at ion implanted region 105.
Above-mentioned manufacture method to form depressed part on fin 101, and carries out the second foreign ion to depressed part by etching fin
Injecting and form ion implanted region 105, the second foreign ion is the transoid ion of the first foreign ion, thus decreases and be positioned at source electrode
108 and drain electrode 109 below heavy doping well region 105 in the valid density of the first foreign ion, and be positioned at grid structure 103 times
In the heavy doping well region 121 of side, the first foreign ion remains in that the doping of high valid density, therefore, does not interferes with original changing
The effect of kind short-channel effect, and effectively reduce leakage current between source electrode, drain electrode and the substrate that heavily doped existence causes.
It should be appreciated by the person skilled in the art that above-mentioned transoid ion refers to provide the ion in hole and can provide freely
The ion of electronics, the application is p-type according to the structure design characteristic of conventional finFET device, the most above-mentioned first foreign ion
Ion, the second foreign ion is N-type ion；Or the first foreign ion is N-type ion, the second foreign ion is p-type ion.
Preferably, N-type ion is P or As, and described p-type ion is B.
Now, the illustrative embodiments according to the application it is more fully described with reference to the accompanying drawings.But, these exemplary enforcements
Mode can be implemented by multiple different form, and should not be construed to be limited solely to embodiments set forth herein.Should
When being understood by, it is provided that these embodiments are so that disclosure herein is thorough and complete, and by these exemplary realities
The design executing mode is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expands layer and region
Thickness, and make to be presented with like reference characters identical device, thus description of them will be omitted.
First, fin 101 and oxide layer 102 it is set on the substrate 100, and fin 101 is carried out well region is infused in fin 101
Interior doping the first foreign ion and formed successively near substrate arrange first that district 111, heavy doping well region 121 and second are lightly doped is light
Doped region 131, forms the device with cross-section structure shown in Fig. 9.
Above-mentioned substrate 100 can be any semi-conducting material commonly used in the art, such as IV race's quasiconductor, such as silicon or germanium,
Or III race-V compound semiconductor, such as GaAs, indium phosphide, gallium nitride or carborundum, the application preferably employs body silicon and makees
For substrate 100.
Above-mentioned substrate 100 performs etching formation fin 101, and on substrate 100 the most after etching, deposition oxide is to isolate fin
Sheet 101；Then performing etching oxide, the partial sidewall making fin 101 is exposed, forms oxide layer 102；To fin 101
Carrying out well region injection, form first and district 111 is lightly doped, heavy doping well region 121 and second is lightly doped district 131, above-mentioned each doped region
Formation can be same as the prior art, realized by the regulation angle of ion implanting, energy and dosage, do not repeat them here.
Fin 101 is formed above-mentioned first and is lightly doped after district 111, heavy doping well region 121 and second be lightly doped district 131, at figure
Grid structure 103 shown in Figure 10 is set on the fin 101 shown in 10.Wherein, Figure 10 is the section along line A-A of Fig. 9
Structural representation.The forming process of this grid structure 103 can become according to the type difference of formed grid structure 103
Change, the forming process of grid structure 103 will be described separately below.
When the grid 132 of grid structure 103 is polysilicon gate, the forming process of this grid structure 103 includes: exposed
Fin 101 and oxide layer 102 on oxide is set；Deposit polycrystalline silicon on oxides；Deposition of dielectric materials on the polysilicon,
Photoresist is set on the dielectric material, and exposure imaging is graphical, is sequentially etched dielectric material, polysilicon with photoresist for mask
And oxide, form the gate dielectric layer 133 of grid structure 103, grid 132 and gate oxide 131.The most above-mentioned formation grid oxygen
The oxide changing layer 131 uses chemical vapour deposition technique, physical vaporous deposition or thermal oxidation method setting to form, above-mentioned polysilicon
All can use chemical vapour deposition technique or physical vaporous deposition deposition with dielectric material, above-mentioned dielectric material is silicon oxide, oxidation
Hafnium, alumina layer, silicon nitride or silicon oxynitride.
When the grid 131 of grid structure 103 is dummy grid, the forming process of this grid structure 103 includes: at exposed fin
On sheet 101 and oxide layer 102, polysilicon is set；Photoresist is set on the polysilicon, and exposure imaging is graphical, with photoresist
Dummy grid is formed for mask etching polysilicon.
After forming the grid structure 103 shown in Figure 10, form the side wall 104 shown in Figure 11 in the side of grid structure 103,
The forming process of the most above-mentioned side wall 104 includes: deposit side in grid structure 103, exposed fin 101 and oxide layer 102
Walling material；Spacer material is performed etching formation side wall 104.Above-mentioned spacer material be preferably silicon nitride and silicon oxide composite,
Silicon nitride or silicon oxide, and preferably employ chemical vapour deposition technique or the physical vaporous deposition above-mentioned spacer material of deposition.
After completing the making of side wall 104, with the grid structure shown in Figure 11 and side wall as mask, etching fin 101 is with at fin
The depressed part shown in Figure 12 is formed, during the end face of this depressed part is positioned at heavy doping well region 121 as shown in figure 12 on sheet 101.
After forming depressed part, the depressed part in Figure 12 is carried out the second foreign ion and injects the ion note formed shown in Figure 13
Entering district 105, the second foreign ion is the transoid ion of the first foreign ion.As described above, the second foreign ion injected
Be the transoid ion of the first foreign ion, thus decrease be positioned at source electrode and drain electrode below heavy doping well region in the first impurity from
The valid density of son, and be positioned at the first foreign ion in the heavy doping well region 121 below grid structure and remain in that high valid density
Doping, therefore, does not interferes with original effect improving short-channel effect, and effectively reduces what heavily doped existence caused
Leakage current between source electrode, drain electrode and substrate.
Those skilled in the art, can be according to the design requirement of the finFET device formed when depressed part is carried out ion implanting
Select the implementation condition of corresponding ion implanting.The most above-mentioned first is lightly doped district 111 and second, and to be lightly doped in district 131 first miscellaneous
The concentration of matter ion is n1, in heavy doping well region 121, the concentration of the first foreign ion is n2, and n1＜ n2, ion implanted region 105
In the concentration of the second foreign ion be n3, and n3＜ n2, wherein, n2With n3Difference and n1Ratio be 0.9:1～1:1.1.Pin
Performance to finFET device commonly used in the art, the most above-mentioned n1For 1E13～1E14atoms/cm3, n2For
1E15～1E17atoms/cm3, n3For 5E14～1E16atoms/cm3。
After forming above-mentioned ion implanted region 105, carry out epitaxial growth at the ion implanted region 105 shown in Figure 13, form Figure 14
Shown source area 106 and drain region 107.Use the source area 106 and the lattice surface shape of drain region 107 being epitaxially-formed
State is complete, its internal and and ion implanted region 105 between there is not gap, effectively improve the performance of finFET device；
And formed source area 106 and the height of drain region 107 can be controlled, meet the finFET device that different performance design requires
Demand.
The preferred solid-phase epitaxial growth of above-mentioned epitaxial growth or laser epitaxial growth.Wherein, in solid-phase epitaxial growth, high annealing
Temperature is 500～900 DEG C, and the time is 0.5～30h.In annealing process, ion implanted region 105 and the first exposed strip structure
The sidewall of 11 as the growth source of solid-phase epitaxial growth, using the surface of ion implanted region 105 as seed crystal, grows from top to bottom,
Thus form above-mentioned source area 106 and drain region 107.
Additionally, well known to a person skilled in the art laser epitaxial growth technique for ion implanted region 105 is heated with laser,
Semi-conducting material is made to start to Epitaxial growth from the surface of ion implanted region 105, in order to obtain good crystal lattice state, preferably
In the growth of above-mentioned laser epitaxial, epitaxial growth temperature is 300～1400 DEG C, and the time is 1min～10h.Outside laser epitaxial growth method
Epitaxial growth speed produces than the quantization of the fast growth of solid phase epitaxial growth, beneficially device.
After forming above-mentioned source area 106 and drain region 107, the source area 106 shown in Figure 14 and drain region 107 are carried out
Ion implanting forms the source electrode 108 shown in Figure 15 and drain electrode 109.Above-mentioned ion implantation process uses this area to form finFET device
The common process of part source-drain electrode is implemented, and does not repeats them here.
Above, grid structure 103 is described, if the grid in above-mentioned grid structure 103 is dummy grid, complete
After becoming the making of source electrode 108 and drain electrode 109, the manufacture method of the application also includes: arrange protection at dummy grid and side wall periphery
Layer；Etching is removed dummy grid and is formed opening；Deposited oxide zirconium or hafnium oxide in opening, form gate dielectric layer；At gate dielectric layer
Upper deposition copper, tungsten, aluminum, titanium, titanium nitride, nitridation thallium or tantalum nitride, form grid；And removal protective layer.Said process
It is referred to prior art carry out, the most not shown.
Present invention also provides a kind of finFET device, refer to Figure 15, this finFET device includes: substrate 100, be arranged on
Fin 101 on substrate 100 and oxide layer 102, be provided with in fin 101 successively near substrate 100 and doping the first impurity from
The first of son is lightly doped district 111, heavy doping well region 121 and second and district 131 is lightly doped, and fin 101 has center knob with outer
Enclosing depressed part, the surface away from substrate 100 in peripheral recesses portion is positioned in heavy doping well region 121, and this finFET device also includes
Grid structure 103 (referring to the sign of Figure 11) and the side wall 104 being positioned on center knob, and peripherally located depressed part
Source electrode 108 and drain electrode 109, doped with the second foreign ion in the heavy doping well region 121 of peripherally located depressed part, the second impurity from
Son is the transoid ion of the first foreign ion.
Adulterate the second foreign ion of promising transoid ion and first miscellaneous at the heavy doping well region 121 being positioned at peripheral recesses portion simultaneously
Matter ion, thus decrease having of the first foreign ion in the heavy doping well region 105 being positioned at below source electrode 108 and drain electrode 109
Effect concentration, and be positioned at the first foreign ion in the heavy doping well region 105 below grid structure 103 and remain in that high valid density
Doping, therefore, does not interferes with original effect improving short-channel effect, and effectively reduces what heavily doped existence caused
Leakage current between source electrode, drain electrode and substrate.
As can be seen from the above description, the application the above embodiments achieve following technique effect:
1), the application by etching fin with on fin formed depressed part, and depressed part is carried out second foreign ion inject shape
Becoming ion implanted region, the second foreign ion is the transoid ion of the first foreign ion, thus decreases and be positioned at below source electrode and drain electrode
Heavy doping well region in ion concentration, and be positioned at the heavy doping well region below grid structure and remain in that high-concentration dopant, therefore,
Do not interfere with original effect improving short-channel effect, and effectively reduce source electrode that heavily doped existence causes, drain electrode with
Leakage current between substrate；
2), relative to the manufacture method of current making finFET device increase only a step flow process, and existing technique will not be made
Become negative effect, therefore be applicable to the popularization and application existing technique.
3) finFET device of the application, adulterate the of promising transoid ion at the heavy doping well region being positioned at peripheral recesses portion simultaneously
Two foreign ions and the first foreign ion, thus decrease be positioned at source electrode and drain electrode below heavy doping well region in the first impurity from
The valid density of son, and be positioned at the first foreign ion in the heavy doping well region below grid structure and remain in that mixing of high valid density
Miscellaneous, therefore, do not interfere with original effect improving short-channel effect, and effectively reduce the source that heavily doped existence causes
Leakage current between pole, drain electrode and substrate.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for those skilled in the art
For, the application can have various modifications and variations.All within spirit herein and principle, any amendment of being made, etc.
With replacement, improvement etc., within should be included in the protection domain of the application.
Claims (11)
1. the manufacture method of a finFET device, it is characterised in that described manufacture method includes:
Substrate arranges fin and oxide layer, doped with the first foreign ion and formed successively near described in described fin
The first of substrate setting is lightly doped district, heavy doping well region and second and district is lightly doped；
Described fin arranges grid structure and side wall；
With described grid structure and side wall as mask, etch described fin to form depressed part on described fin, described recessed
The end face in the portion of falling into is positioned in described heavy doping well region；
Described depressed part carrying out the second foreign ion inject and form ion implanted region, described second foreign ion is described the
The transoid ion of one foreign ion；And
At described ion implanted region, source electrode and drain electrode are set.
Manufacture method the most according to claim 1, it is characterised in that described first is lightly doped district and second is lightly doped Qu Zhong
The concentration of one foreign ion is n1, described in described heavy doping well region, the concentration of the first foreign ion is n2, and n1＜ n2,
In described ion implanted region, the concentration of the second foreign ion is n3, and n3＜ n2, wherein, n2With n3Difference and n1Ratio
Value is 0.9:1～1:1.1.
Manufacture method the most according to claim 2, it is characterised in that described n1For 1E13～1E14atoms/cm3, described n2
For 1E15～1E17atoms/cm3, described n3For 5E14～1E16atoms/cm3。
Manufacture method the most according to claim 1, it is characterised in that in the step that described second foreign ion injects, inject
Energy is 40～80KeV, and implantation dosage is 1E12～1E14atoms/cm2。
Manufacture method the most according to any one of claim 1 to 4, it is characterised in that described first foreign ion is p-type
Ion, described second foreign ion is N-type ion；Or the first foreign ion is N-type ion, the second foreign ion is
P-type ion, described N-type ion is P or As, and described p-type ion is B.
Manufacture method the most according to claim 1, it is characterised in that the described process arranging source/drain includes:
Carry out epitaxial growth at described ion implanted region, form source area and drain region；
Described source area and described drain region are carried out ion implanting and forms source electrode and drain electrode.
Manufacture method the most according to claim 6, it is characterised in that described epitaxial growth is outside solid-phase epitaxial growth or laser
Epitaxial growth.
Manufacture method the most according to claim 1, it is characterised in that the setting up procedure of described grid structure includes:
Exposed described fin and described oxide layer arrange oxide；
Deposit polycrystalline silicon on described oxide；
Deposition of dielectric materials on described polysilicon, described dielectric material is silicon oxide, hafnium oxide, aluminium oxide, silicon nitride
Or silicon oxynitride；
It is sequentially etched described dielectric material, polysilicon and oxide, forms described grid structure, wherein, described dielectric material
Form the gate dielectric layer of described grid structure after material etching, after described etching polysilicon, form the grid of described grid structure,
The gate oxide of described grid structure is formed after described oxide etching.
Manufacture method the most according to claim 8, it is characterised in that described gate oxide uses chemical vapour deposition technique, thing
Physical vapor deposition method or thermal oxidation method arrange and form.
Manufacture method the most according to claim 1, it is characterised in that the setting up procedure of described side wall includes:
Depositing spacer material in described grid structure, described exposed fin and described oxide layer, described spacer material is
Silicon nitride and the composite of silicon oxide, silicon nitride or silicon oxide；
Described spacer material is performed etching the described side wall of formation.
11. 1 kinds of finFET device, described finFET device includes: substrate, arrange fin over the substrate and oxide layer, institute
Be provided with in stating fin successively near described substrate and doping the first foreign ion first be lightly doped district, heavy doping well region and
Second is lightly doped district, and described fin has center knob and peripheral recesses portion, described peripheral recesses portion away from described lining
The surface at the end is positioned in described heavy doping well region, and described finFET device also includes the grid being positioned on described center knob
Structure and side wall, and it is positioned at source electrode and the drain electrode in described peripheral recesses portion, it is characterised in that it is positioned at described peripheral recesses
Doped with the second foreign ion in the described heavy doping well region in portion, described second foreign ion is described first foreign ion
Transoid ion.
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| CN108573869A (en) * | 2017-03-07 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect pipe and forming method thereof |
| CN108630523A (en) * | 2017-03-22 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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