TW201318073A - Structure of field effect transistor with fin structure and fabricating method thereof - Google Patents

Abstract

A method for fabricating a field effect transistor with fin structure includes the following steps. A substrate having an ion well with a first conductivity type is provided, wherein the ion well has a first doping concentration. At least a fin structure disposed on the substrate is formed. At least a first ion implantation is performed to form an anti-punch doped region with first conductivity type between the substrate and the channel layer, wherein the anti-punch doped region has a third doping concentration higher than the first doping concentration. At least a channel layer disposed along at least one surface of the fin structure is formed after the first ion implantation is performed. A gate covering part of the fin structure is formed. A source and a drain disposed in the fin structure beside the gate are formed, wherein the source and the drain have a second conductivity type.

Description

Structure of field effect transistor with fin structure and manufacturing method thereof

The invention relates to a structure and a manufacturing method of a field effect transistor, in particular to a structure of a field effect transistor having a fin structure and a manufacturing method thereof.

As the size of field effect transistors (FETs) components continues to shrink, the development of conventional planar field effect transistor components has faced process limitations. In order to overcome the process limitation, the replacement of planar transistor components with non-planar field effect transistor components, such as fin field effect transistor (Fin FET) components, has become the mainstream trend. . Since the three-dimensional structure of the fin field effect transistor element can increase the contact area between the gate and the fin structure, the control of the gate to the carrier channel region can be further increased, thereby reducing the source-induced surface of the small-sized component. The drain induced barrier lowering (DIBL) effect can suppress the short channel effect (SCE). And because the fin field effect transistor element has a wider channel width at the same gate length, a doubled drain drive current can be obtained. Even the threshold voltage of the transistor element can be regulated by adjusting the work function of the gate.

In the process of the conventional fin field effect transistor device, after the fin structure is formed, an anti-punch ion implantation process is usually performed to prevent the source/drain or the substrate. The creation of a punch-through effect. However, for the fin structure whose top surface is covered by the patterned mask layer, since the sidewall of the fin structure is not shielded, in the anti-penetration ion implantation process, the dopant is not only implanted in the source/ Below the bungee, it is also implanted in the carrier channel region on the side of the fin structure, causing an uncontrollable variation in the dopant concentration in the carrier channel region. This variation affects the power of the fin field effect transistor component. Sexual performance, resulting in a significant reduction in process yield.

The present invention provides a structure of a field effect transistor having a fin structure and a method of fabricating the same to avoid uncontrollable variations in the dopant concentration of the channel region.

In order to achieve the above object, according to an embodiment of the present invention, a method for fabricating a field effect transistor having a fin structure includes providing a substrate, forming a first conductivity type ion well in the substrate, and first The conductive ion well has a first dopant concentration, forms at least one fin structure, is disposed on the substrate, performs at least one first ion implantation process, and is formed to form a first conductive type of penetration resistance on the substrate ( An anti-punch ion implantation zone, wherein the anti-penetration ion implantation zone has a third dopant concentration, and the third dopant concentration is greater than the first dopant concentration, and at least one is formed after the first ion implantation process The channel layer is disposed along at least one surface of the fin structure to form a gate, covers a portion of the fin structure, and forms a source and a drain, and is disposed in the fin structure on both sides of the gate.

According to another embodiment of the present invention, there is provided a structure of a field effect transistor having a fin structure, comprising a substrate, a first conductivity type ion well disposed in the substrate, wherein the first conductivity type ion well has a first dopant concentration, at least one fin structure, disposed on the substrate, at least one channel layer disposed along at least one surface of the fin structure, wherein the channel layer has a second doping concentration, and the second doping concentration The anti-internal ion implantation region having a maximum concentration lower than the first dopant concentration and at least one first conductivity type is disposed between the substrate and the channel layer, wherein the anti-penetration ion implantation region has a third dopant concentration, and the The triple dopant concentration is greater than the first dopant concentration, a gate, a portion of the fin structure, and a source and a drain are disposed in the fin structure on both sides of the gate, wherein the source and the drain are It has a second conductivity type.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

1 is a flow chart for preparing a field effect transistor having a fin structure according to various embodiments of the present invention. The preparation process is sequentially: forming the fin structure 1a, forming the insulating layer 1b, performing the planarization process 1c, performing the etch back process 1d, and removing the patterned hard mask 1e. Further, the present invention further includes a first ion implantation process 2 for forming an anti-punch ion implantation region and a process for forming the channel layer 3. It should be noted here that the technical feature of the present invention is that the time at which the channel layer 3 is formed must be later than the point at which the first ion implantation 2 is performed. For example, when the first ion implantation process is performed as indicated by the first ion implantation process 2a, 2b, 2c, 2d, 2e, 2f, the time at which the channel layer is formed is preferably as shown in the channel formation layer 3b. At the office. However, when the first ion implantation process is performed as indicated by the first ion implantation process 2a, 2b, the timing of forming the channel layer is preferably at the position where the channel layer 3b is formed. In order to make the above-mentioned preparation process easier to understand, the following is a detailed description of different implementation aspects:

The first embodiment:

Please refer to FIG. 1 to FIG. 8 , wherein FIG. 2 to FIG. 8 are schematic diagrams showing a fin structure according to a preferred embodiment of the present invention. In the first embodiment, the first ion implantation process 2 is performed before the fin structure 1a is formed. As shown in FIG. 2, a semiconductor substrate 10 covered with a patterned photoresist layer 18 is first provided, wherein the patterned photoresist layer 18 is used to define the position of the ion well 9 and the anti-ion ion implantation region 21. That is, the process of the ion well 9 and the anti-penetration ion implantation zone 21 can share the same mask process. However, according to other embodiments, the ion well 9 and the anti-penetration ion implantation zone 21 can also be separately fabricated through different masks. Next, a first conductivity type (for example, P type) ion well 9 is formed in the semiconductor substrate 10, and the ion well 9 has a first concentration of 10 ¹² -10 ¹³ atoms/cm 2 (atoms/cm ² ). Doping concentration. In addition, a second conductivity type (for example, N-type) ion well (not shown) may be present in the semiconductor substrate 10 such that the ion wells respectively correspond to the N-type MOS transistor (NMOS) region (Fig. Not shown) and a P-type MOS transistor (PMOS) region (not shown). The semiconductor substrate 10 may comprise a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, wherein a silicon-on-insulator (SOI) substrate provides better insulation. Cooling and grounding effects, and help reduce costs and suppress noise.

Next, under the coverage of the patterned photoresist layer 18, a first ion implantation process 2 is performed to form at least one anti-penetration ion implantation region 21 having a first conductivity type in the ion well 9 . The anti-penetration ion implantation zone 21 has a third dopant concentration, and the third dopant concentration is higher than the first dopant concentration of the ion well 9. It should be noted here that the first ion implantation process may comprise a multi-ion ion implantation process. Further, according to the present embodiment, an oxide layer 16 is further included on the surface of the semiconductor substrate 10 to prevent high-energy ions from directly striking the surface of the semiconductor substrate 10 to cause defects.

Next, as shown in FIG. 3, the patterned photoresist layer 18 and the oxide layer 16 are removed to expose the surface of the semiconductor substrate 10. Subsequent to selectively performing an epitaxial growth process, a semiconductor layer 23 is formed on the surface of the semiconductor substrate 10, which may include germanium, tantalum carbide, antimony telluride or a group III-V compound of the periodic table. But it is not limited to this. In addition, according to different process requirements, the semiconductor layer 23 having appropriate stress (extension or compression) or doping concentration can be formed to adjust the electrical performance of the carrier channel layer.

Next, as shown in FIG. 4, a second patterned mask layer 29 including at least one patterned stress buffer layer 25 and at least one patterned hard mask layer 27 is formed on the semiconductor layer 23 for defining The position of each fin structure 11. The patterned stress buffer layer 25 comprises hafnium oxide and the patterned hard mask layer 27 comprises tantalum nitride. Next, an etching process is performed to form at least one fin structure 11 on the semiconductor substrate 10, and the fin structures 11 are separated by shallow trenches 13. At this time, the top surface 12 of the patterned semiconductor layer 23a is provided with a second patterned mask layer 29, and the patterned semiconductor layer 23a has an anti-interference ion implantation region 21 under the patterned semiconductor layer 23a, wherein the anti-ion ion implantation region The distance between 21 and top surface 12 is preferably less than 400 angstroms.

Next, as shown in FIG. 5, an insulating layer 31, such as a ruthenium dioxide layer, is formed on the semiconductor substrate 10, and the insulating layer 31 covers the fin structures 11 and fills the shallow trenches 13. The above process for forming the insulating layer 31 may include high density plasma chemical vapor deposition (HDPCVD), sub-atmospheric chemical vapor deposition (SACVD) or spin-on dielectric material (spin on Dielectric, SOD) and other processes. Thereafter, as shown in FIG. 6, an etching process 1d is performed on the insulating layer 31 to remove a portion of the insulating layer 31 until the top surface of the insulating layer 31 is lower than the top surface 12 of the fin structure 11. In addition, a planarization process 1c can be selectively performed before the etch back to make the insulating layer 31 and the second patterned mask layer 29 equal or slightly lower. Therefore, at least one shallow trench insulating structure 33 is formed on the semiconductor substrate 10 between the fin structures 11.

As shown in FIG. 7, an etching process is performed to remove the second patterned mask layer 29. In an embodiment of the invention, when the second patterned mask layer 29 comprises tantalum nitride, it can be removed by using hot phosphoric acid. This is a prior art and will not be further described herein. Next, a channel layer 35 is formed on the surface of each of the fin structures 11 by an epitaxial process. According to different process requirements, the channel layer 35 can be selectively subjected to a second ion implantation process, which can include a process such as tilted-angle ion implantation to adjust the doping of the channel layer 35. The concentration, in turn, adjusts the threshold voltage (V _th ) of the transistor. The channel layer 35 described above comprises germanium, germanium germanium or other semiconductor material that can serve as a carrier channel. It should be noted that, according to other embodiments of the present invention, the channel layer 35 may be directly disposed inside the surface of the fin structure 11 (not shown) by means of ion implantation, that is, the channel layer 35 is not Covering the surface of the fin structure 11.

Thereafter, as shown in FIG. 8, at least one dielectric layer 37 and a gate material layer 39 covering each of the fin structures 11 are sequentially formed on the semiconductor substrate 10. The dielectric layer 37 may include a dielectric material such as yttrium oxide (SiO), tantalum nitride (SiN), yttrium oxynitride (SiON) or the like or other high dielectric constant material according to different process requirements. The gate material layer 39 may comprise a polysilicon material, a metal halide or a metal, or the like.

It should be noted here that the above-mentioned channel layer 35 is formed at a point after the insulating layer 31 fills the shallow trench 13. However, in another embodiment, the point at which the channel layer 3 is formed is continued after the formation of the fin structure 1a. According to this embodiment, at least one channel layer 35 is formed on the surface of the fin structure 11 after forming each fin structure 11 and before the insulating layer 31 fills the shallow trench 13 through an epitaxial growth process. Since the top surface 12 of the fin structure 11 is covered by the second patterned mask layer 29, the channel layer 35 is formed only on the sidewall of the fin structure 11 (not shown). In addition, according to different process requirements, the channel layer 35 can be selectively subjected to a second ion implantation process to adjust the doping concentration of the channel layer 35.

Second implementation aspect:

Referring to FIG. 1 and FIG. 3 to FIG. 8 , the embodiment of the second embodiment is similar to the first embodiment, except that in the second embodiment, the fin structure 1 a is formed. The first ion implantation process 2 is performed after the formation of the insulating layer 1b. Similarly, as shown in Fig. 3, a semiconductor substrate 10 is provided which is selectively covered with a layer of semiconductor layer 23, and at which time the semiconductor substrate 10 is still free of penetration through the ion implantation region. Next, similarly to FIG. 4, a second patterned mask layer 29 is formed on the semiconductor layer 23 to define the position of each fin structure 11. An etching process is performed to form at least one fin structure 11 on the substrate 10, and the fin structures 11 are separated by shallow trenches 13. At this time, the top surface 12 of the patterned semiconductor layer 23a is provided with a patterned mask layer 29. Next, a first ion implantation process 2 is performed to form an anti-ion ion implantation region 21 under the patterned semiconductor layer 23a. According to another embodiment of the present invention, if the semiconductor substrate 10 is not covered with the semiconductor layer 23 before forming the fin structures 11, the anti-penetration ion implantation region 21 is present in the fin structure 11. Then, similar to the first embodiment, an insulating layer 31 is formed, a planarization process 1c, an etch back process 1d, a second patterned mask layer 29, and an epitaxial growth channel layer 35 are formed. And the subsequent processes are corresponding to the fifth to eighth figures of the first embodiment, and will not be described herein. Further, similarly to the first embodiment, the time at which the epitaxial growth channel layer 35 is advanced may be advanced to a point after the first ion implantation process 2 and before the formation of the insulating layer 1b.

It should be noted that in the second embodiment, since the first ion implantation process is performed after the fin structure 11 is formed, in order to avoid the dopant concentration of the carrier channel, the first ion implantation process is adopted. The channel layer 35 is preferably additionally covered on the surface of the fin structure 11 in an epitaxial process, and is not disposed on the inner side of the surface of the fin structure 11 (not shown) by ion implantation. In addition, according to different process requirements, the channel layer 35 can be selectively subjected to a second ion implantation process to adjust the doping concentration of the channel layer 35.

The third embodiment:

Referring to FIG. 1 and FIG. 3 to FIG. 8 , the third embodiment is similar to the second embodiment, and the difference is that, in the third embodiment, after the formation of the insulating layer 1 b and the planarization process The first ion implantation process 2 is performed before 1c. Similarly to FIGS. 3 to 4, at least one fin structure 11 is formed on the semiconductor substrate 10, and at this time, no anti-penetration ion implantation region 21 is present in the semiconductor substrate 10. Next, similarly to FIG. 5, an insulating layer 31, such as a ceria layer, is formed on the substrate 10, and the insulating layer 31 covers the fin structure 11 and fills the shallow trench 13. Next, a first ion implantation process 2 is performed to form a primary anti-ion implantation region 21 below the patterned semiconductor layer 23a. According to another embodiment of the present invention, if the semiconductor substrate 10 is not covered with the semiconductor layer 23 before the fin structure 11 is formed, the anti-penetration ion implantation region 21 is present in the fin structure 11. Then, similar to the second embodiment, a planarization process 1c, an etch back process 1d, a second patterned mask layer 29, and an epitaxial growth channel layer 35 are performed, and the processes and subsequent processes are corresponding to each other. In the sixth embodiment to the eighth embodiment of the second embodiment, no further details will be described herein.

It should be noted that, similarly to the second embodiment, since the first ion implantation process 2 is performed after the fin structure 11 is formed, in order to avoid the dopant concentration of the carrier channel, the first ion implantation process is performed. As a result, the channel layer 35 is preferably additionally covered on the surface of the fin structure 11 in an epitaxial process, and is not disposed on the inner side of the surface of the fin structure 11 (not shown) by ion implantation. In addition, according to different process requirements, the channel layer 35 can be selectively subjected to a second ion implantation process to adjust the doping concentration of the channel layer 35.

Fourth implementation aspect:

Referring to FIG. 1 and FIG. 3 to FIG. 8 , the embodiment of the fourth embodiment is similar to the second embodiment, and the difference is that in the fourth embodiment, the flattening process 1c is performed. The first ion implantation process 2 is then performed and before the etch back process 1d. Similarly, as shown in FIGS. 3 to 5, at least one fin structure 11 is formed on the semiconductor substrate 10, and an insulating layer 31 is formed on the semiconductor substrate 10. The insulating layer 31 covers the fin structure 11 and fills up. Shallow ditch 13. It should be noted here that at this time, there is no anti-penetrating ion implantation region present in the fin structure 11.

Thereafter, similarly to FIG. 6, after the planarization process, a first ion implantation process 2 is performed to form a primary diffusion ion implantation region 21 below the patterned semiconductor layer 23a. According to another embodiment of the present invention, the semiconductor substrate 10 is not covered with the semiconductor layer 23 before the fin structures 11 are formed, and the anti-penetration ion implantation region 21 is present in the fin structure 11. Moreover, in the above embodiments, the distance between the through-ion implanting region 21 and the top surface 12 is preferably less than 400 angstroms. Thereafter, an etching process 1d is performed, the second patterned mask layer 29 and the epitaxial growth channel layer 35 are removed, and the processes and subsequent processes are corresponding to the sixth embodiment to the eighth embodiment of the second embodiment. Figure, will not be repeated here.

Similarly, in the fourth embodiment, since the first ion implantation process 2 is performed after the fin structure 11 is formed, in order to prevent the dopant concentration of the carrier channel from being affected by the first ion implantation process, the channel The layer 35 is preferably additionally covered on the surface of the fin structure 11 in an epitaxial process, and is not disposed on the inner side of the surface of the fin structure 11 (not shown) by ion implantation. In addition, according to different process requirements, the channel layer 35 can be selectively subjected to a second ion implantation process to adjust the doping concentration of the channel layer 35.

Fifth embodiment:

Referring to FIG. 1 and FIG. 3 to FIG. 8 , the fifth embodiment is similar to the second embodiment, and the difference is that, in the fifth embodiment, after the etch back process and the second process is removed. The first ion implantation process is performed before the patterned mask layer 29 is formed. Similarly, as shown in FIGS. 3 to 6, at least one fin structure 11 is formed on the semiconductor substrate 10, and an insulating layer 31 is formed on the substrate 10. The insulating layer 31 covers the fin structure 11 and fills the shallow Ditch 13. Next, an etching process 1d is performed on the insulating layer 31 to remove a portion of the insulating layer 31 until the top surface of the insulating layer 31 is lower than the top surface 12 of the fin structure 11. In addition, a planarization process 1c can be selectively performed before the etch-back process 1d to make the insulating layer 31 and the second patterned mask layer 29 equal or slightly lower. It should be noted here that at this time, there is no anti-penetrating ion implantation region present in the fin structure 11.

Next, similarly as shown in FIG. 6, a first ion implantation process 2 is performed to form a primary diffusion ion implantation region 21 below the patterned semiconductor layer 23a. According to another embodiment of the present invention, if the semiconductor substrate 10 is not covered with the semiconductor layer 23 before the fin structure 11 is formed, the anti-penetration ion implantation region 21 is present in the fin structure 11. Thereafter, the second patterned mask layer 29 is removed and the channel layer 35 is epitaxially grown.

Similarly, in the fifth embodiment, since the first ion implantation process 2 is performed after the fin structure 11 is formed, in order to prevent the dopant concentration of the carrier channel from being affected by the first ion implantation process, the channel Preferably, the layer 35 is additionally covered on the surface of the fin structure 11 in an epitaxial process, and is not disposed on the inner side of the surface of the fin structure 11 (not shown) by ion implantation. In addition, according to different process requirements, the channel layer 35 can be selectively subjected to a second ion implantation process to adjust the doping concentration of the channel layer 35.

Sixth implementation aspect:

Referring to FIG. 1 and FIG. 3 to FIG. 8 , the sixth embodiment is similar to the second embodiment, and the difference is that in the sixth embodiment, the second patterned mask layer 29 is removed. The first ion implantation process is then started. Similarly, as shown in FIGS. 3 to 6, at least one fin structure 11 is formed on the semiconductor substrate 10, and an insulating layer 31 such as a ceria layer is formed on the substrate 10, and the insulating layer 31 covers the fins. Structure 11 fills shallow trenches 13. Next, a planarization process and an etch back process are performed on the insulating layer 31 to remove a portion of the insulating layer 31 until the top surface of the insulating layer 31 is lower than the top surface 12 of the fin structure 11. It should be noted here that at this time, there is no anti-penetrating ion implantation region present in the fin structure 11.

Similar to that shown in FIG. 7, an etching process is performed to remove the second patterned mask layer 29. Next, a first ion implantation process is performed to form a primary anti-ion implantation region 21 below the patterned semiconductor layer 23a. Next, a channel layer 35 is formed to cover the surface of the fin structure 11 by an epitaxial process. According to different process requirements, the channel layer 35 can be selectively subjected to an ion implantation process to adjust the doping concentration of the channel layer 35.

It should be noted that, in the sixth embodiment, since the first ion implantation process 2 is performed after the fin structure 1a is formed, in order to prevent the dopant concentration of the carrier channel from being affected by the penetration process, Preferably, the channel layer 35 is additionally covered on the surface of the fin structure 11 in an epitaxial process, and is not disposed on the inner side of the surface of the fin structure 11 (not shown) by ion implantation. In addition, according to different process requirements, the channel layer 35 can be selectively subjected to a second ion implantation process to adjust the doping concentration of the channel layer 35.

Further, according to the first to sixth embodiments described above, the surface of the semiconductor substrate 10 has a semiconductor layer 23 which may have appropriate stress (stretch or compression) or a suitable doping concentration. In order to adjust the electrical performance of the carrier channel layer. However, according to another preferred embodiment of the present invention, the semiconductor layer 23 is not present on the surface of the semiconductor substrate 10, and the patterned semiconductor layer 23a in the fin structure 11 is replaced by a protrusion 36, wherein the protrusion The 36 series is obtained by etching the semiconductor substrate 10. Therefore, the channel layer 35 is provided along the surface of the protrusion 36, and its structure can be referred to FIG.

The seventh embodiment:

Similarly to the first embodiment, in the present embodiment, the fin structure 11 is formed on the semiconductor substrate 10 in an epitaxial growth manner. The process steps are similar to those shown in FIG. 1 and FIG. 3 to FIG. 9, and only the differences will be described below. First, as shown in FIG. 10, a semiconductor substrate 10 covered with a patterned mask layer 15 is provided to define the locations of subsequent fin structures 11. The semiconductor substrate 10 has a first conductivity type (for example, P type) ion well 9 having a first dopant concentration having a concentration of 10 ¹² -10 ¹³ atoms/cm 2 (atoms/cm ² ). . And a second conductivity type (for example, N type) ion well (not shown) may be present in the semiconductor substrate 10, so that the ion wells respectively correspond to the N-type MOS transistor (NMOS) region (Fig. And P-type MOS transistor (PMOS) region (not shown). Furthermore, the patterned mask layer 15 described above comprises a multilayer structure comprising at least one stress buffer layer 16, such as hafnium oxide, and at least one hard mask layer 18, such as tantalum nitride.

Then, as shown in FIG. 10, the first ion implantation process 2 is performed to form a permeation-resistant ion implantation region 21 having a first conductivity type, and the dopant concentration against the ion implantation region 21 is high. The first dopant concentration in the ion well 9. In addition, an oxide layer (not shown) may be formed on the surface of the semiconductor substrate 10 before the first ion implantation process 2 is performed to prevent high-energy ions from directly hitting the surface of the substrate 10 to cause defects. In the present embodiment, the region resistant to the penetrating ion implantation region 21 is defined by the patterned mask layer 15, however, according to other preferred embodiments, the anti-penetration ion implantation region 21 may be the same as the ion well 9 The reticle, that is, the patterned mask layer 15 is not used to define an area that is resistant to penetration through the ion implantation zone 21.

Next, as shown in FIG. 11, a selective epitaxial growth process is performed to expose the surface of the substrate 10 from the patterned mask layer 15 as a seed layer to form a fin structure 11 in each trench 32. Each of the fin structures 11 is grown by the surface of the semiconductor substrate 10 at the bottom of the trench 32 and grows upward to protrude from the top surface of the patterned mask layer 15. According to the process requirements, after the selective epitaxial growth is completed, a cyclic thermal annealing (CTA) may be performed to reduce the defects in the fin structure 11. The fin structure 11 described above may include a tantalum layer (Si), a tantalum layer (SiGe), or a combination thereof. It should be noted that, in this embodiment, the top surface 12 of the fin structure 11 does not cover the mask layer (not shown), so the process of removing the mask layer is not required. In addition, according to other preferred embodiments, if the anti-ion ion implantation area 21 and the ion well 9 are shared by the same photomask, a patterned mask layer (not shown) is additionally formed to define the fins. The formation area of the structure 11. The subsequent processes are similar to the corresponding figures 4 to 8, and will not be described here.

In addition, the present embodiment can also be applied to the corresponding second embodiment to the fifth embodiment, that is, after the epitaxial growth fin structure 11 is on the semiconductor substrate 10, the first ion implantation process is performed. The time points may be respectively after: forming the fin structure 1a, after forming the insulating layer 1b, after the planarization process 1c, or after the etchback process 1d. For the sake of brevity, the similar processes may correspond to Figures 4 through 9, and will not be described herein.

After the first to seventh embodiments described above are completed, a semiconductor process required for each type, such as a MOS process having a polysilicon gate or a metal gate, may be performed. As shown in FIG. 12, an embodiment of the present invention is a schematic diagram of a multi-gate field effect transistor integrated in a gate first process. First, a patterned cap layer 46 is formed on the gate material layer 39 having a metal composition for defining the positions of at least one NMOS region (not shown) and each gate of at least one PMOS region (not shown). Subsequently, the gate material layer 39 and the dielectric layer 37 having a high dielectric constant are etched by using the patterned cap layer 46 as an etch mask, and at least one gate covering each fin structure 11 is formed on the semiconductor substrate 10. Pole structure 28. Next, a lightly doped source/drain region (not shown) is selectively formed in the fin structure 11 not covered by the gate. Then, a sidewall 47 is formed on the surrounding sidewall of the gate structure 28, and the sidewall 47 may be a single layer or a multilayer structure, or may include a liner or the like. Thereafter, the side wall sub-47 and the cap layer 46 are used as a mask, and an ion implantation process is performed to incorporate an appropriate dopant. The dopant may include an N-type or a P-type dopant to implant a corresponding source/drain on the fin structure 11 exposed on both sides of the gate structure 28 in the NMOS region and the PMOS region. The dopant is doped and combined with an annealing process to activate the source/drain regions (not shown). Although the present embodiment preferably forms the lightly doped source/drain regions, the sidewalls 27, and the source/drain regions in sequence, the present invention is not limited thereto, and the present invention can arbitrarily adjust the above formation according to the requirements of the process. The order of the sidewalls and the doped regions is within the scope of the present invention.

According to another embodiment of the present invention, similarly to FIG. 12, a gate-gate multi-gate field effect transistor of a metal gate is used. When the gate material layer 39 shown in FIG. 8 is polysilicon, the gate post process system receives the gate first process of the polysilicon gate. After the polysilicon gate of the gate structure 28 is replaced by a metal gate, the channel region (not shown) of the fin structure 11 is sequentially covered with at least one high dielectric constant gate dielectric layer (not shown). At least one work function metal layer (not shown) and at least one metal conductive layer (not shown). Regardless of whether it is a gate post process or a gate priority process, the material of the high dielectric constant gate dielectric layer may be selected from, for example, hafnium oxide (HfO ₂ ), hafnium silicon (hafnium silicon). Oxide, HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (tantalum oxide, Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (zirconium silicon oxide, ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _{1- x} O ₃ , PZT) is a group consisting of barium strontium titanate (Ba _x Sr _1-x TiO ₃ , BST), but is not limited thereto. The above metal conductive layer comprises a low resistance material or a combination thereof. In addition, between the work function metal layer and the high dielectric constant gate dielectric layer and between the work function metal layer and the metal conductive layer, titanium (Ti) and titanium nitride (TiN) may be selectively formed separately. A barrier layer of a material such as tantalum (Ta) or tantalum nitride (TaN) (not shown).

A multi-gate MOSFET having a fin structure has been completed by the above-described gate priority process or gate post process. It should be noted that in the above embodiments, the fin structure 11 and the dielectric layer 23 have three direct contact surfaces, for example, two contact sides (not shown) and a contact top surface (not shown). ), and thus can be referred to as a tri-gate MOSFET. Compared with the planar field effect transistor, the three-gate field effect crystal system has the wider carrier channel width under the same gate length by using the above three direct contact surfaces as the channel through which the carrier flows. This results in a doubled drain drive current at the same drive voltage. However, the above-mentioned multi-gate field effect transistor is not limited to the three-gate field effect transistor, and there may be a pattern between the top surface 12 of the fin structure 11 and the dielectric layer 23 according to the requirements of the process. The hard mask layer 15, that is, only the side faces 34 on both sides of the fin structure 11 have a direct contact surface with the dielectric layer 23. Therefore, the multi-gate field effect crystal system having two direct contact faces constitutes a fin field effect transistor (Fin FET).

In summary, the present invention provides a method for fabricating a field effect transistor having a fin structure, wherein the point of performing the first ion implantation process 2 is prior to forming the channel layer 3, that is, the anti-ion ion implantation region. The dopant does not affect the dopant concentration distribution in the channel layer 35, thereby reducing the variation in the electrical properties of the fin field effect transistor component.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1a. . . Fin structure

1b. . . Forming an insulating layer

1c. . . Flattening process

1d. . . Etch process

1e. . . Remove patterned hard mask

2. . . First ion implantation process

2a, 2b. . . First ion implantation process

2c, 2d. . . First ion implantation process

2e, 2f. . . First ion implantation process

3. . . Channel layer

3a. . . Channel layer

3b. . . Channel layer

9. . . Ion well

10. . . Semiconductor substrate

11. . . Fin structure

12. . . Top surface

13. . . Shallow ditch

15. . . Patterned mask layer

16. . . Oxide layer

17. . . Patterned stress buffer layer

18. . . Patterned photoresist layer

19. . . Patterned hard mask layer

twenty one. . . Anti-penetration implant area

twenty three. . . Semiconductor layer

23a. . . Patterned semiconductor layer

25. . . Patterned stress buffer layer

27. . . Patterned hard mask layer

28. . . Gate structure

29. . . Second patterned mask layer

31. . . Insulation

32. . . ditch

33. . . Shallow trench insulation structure

34. . . side

35. . . Channel layer

36. . . Protruding

37. . . Dielectric layer

39. . . Gate material layer

46. . . Patterned cover

47. . . Side wall

Figure 1 is a flow chart for the preparation of a field effect transistor having a fin structure.

2 to 12 are schematic views showing a manufacturing method of forming a field effect transistor having a fin structure according to a preferred embodiment of the present invention.

Claims (20)

A method for fabricating a field effect transistor having a fin structure, comprising: providing a substrate; forming an ion well of a first conductivity type in the substrate, and the ion well has a first dopant concentration; forming at least one a fin structure disposed on the substrate; performing at least one first ion implantation process to form an anti-punch ion implantation region of the first conductivity type of the substrate, wherein the anti-punch ion The implantation zone has a third dopant concentration, and the third dopant concentration is greater than the first dopant concentration; after the first ion implantation process, at least one channel layer is formed along at least one of the fin structures Forming a surface; forming a gate covering the portion of the fin structure; and forming a source and a drain disposed in the fin structure on both sides of the gate. The method for fabricating a field effect transistor having a fin structure according to claim 1, wherein the step of forming the fin structure comprises: forming a semiconductor layer on the substrate; and etching the semiconductor layer, To form the fin structure. The method for fabricating a field effect transistor having a fin structure according to claim 1, wherein the step of forming the fin structure comprises: forming a patterned hard mask layer on the substrate; and growing one A semiconductor layer is formed on the substrate exposed to the patterned hard mask layer to form the fin structure. The method for fabricating a field effect transistor having a fin structure according to claim 1, wherein after forming the fin structure, the method further comprises: forming an insulating layer covering the fin structure; and performing the insulating layer a polishing process; and an etching process for the insulating layer. The method for fabricating a field effect transistor having a fin structure according to claim 4, wherein after performing the etch back process, the method further comprises: removing the patterned hard mask layer. The method for fabricating a field effect transistor having a fin structure according to claim 1, wherein the first ion implantation process is performed before the fin structure is formed. The method for fabricating a field effect transistor having a fin structure according to claim 4, wherein the first ion implantation process is performed at a time between forming the insulating layer and performing the polishing process. The method for fabricating a field effect transistor having a fin structure according to claim 4, wherein the first ion implantation process is performed between the polishing process and the etchback process. The method for fabricating a field effect transistor having a fin structure according to claim 5, wherein the first ion implantation process is performed at the time of performing the etch back process and removing the hard mask layer. between. The method for fabricating a field effect transistor having a fin structure according to claim 5, wherein the first ion implantation process is performed between removing the hard mask layer and forming the channel region. . The method for fabricating a field effect transistor having a fin structure according to claim 1, wherein the first ion implantation process comprises a multi-ion ion implantation process. The method for fabricating a field effect transistor having a fin structure as described in claim 1, wherein the channel layer is laterally covered on the surface of the fin structure. The method for fabricating a field effect transistor having a fin structure according to claim 1, wherein the channel layer is disposed inside the surface of the fin structure. The method for fabricating a field effect transistor having a fin structure according to claim 1, wherein the channel layer is selected from the group consisting of a tantalum layer, a tantalum layer, a tantalum carbide layer, or a combination thereof. The method for fabricating a field effect transistor having a fin structure according to claim 1, wherein after forming the channel layer, further comprising: performing a second ion implantation process to adjust the dopant of the channel layer concentration. The method for fabricating a field effect transistor having a fin structure according to claim 15, wherein the second ion implantation process comprises a tilted-angle ion implantation process. A structure of a field effect transistor having a fin structure, comprising: a substrate; a first conductivity type ion well disposed in the substrate, wherein the first conductivity type ion well has a first dopant concentration; a fin structure disposed on the substrate; at least one channel layer disposed along at least one surface of the fin structure, wherein the channel layer has a second doping concentration, and the highest concentration of the second doping concentration is less than The first dopant concentration; the at least one first conductivity type anti-internal ion implantation region is disposed between the substrate and the channel layer, wherein the anti-penetration ion implantation region has a third dopant concentration, and the The third dopant concentration is greater than the first dopant concentration; a gate covering the portion of the fin structure; and a source and a drain disposed in the fin structure on both sides of the gate, wherein The source and the drain have a second conductivity type. The structure of a field effect transistor having a fin structure as described in claim 17, wherein the substrate comprises an insulating layer adjacent to the fin structure. The structure of the field effect transistor having a fin structure as described in claim 17, wherein a distance between a top surface of the fin structure and the anti-penetration ion implantation region is less than 400 angstroms. The structure of the field effect transistor having a fin structure as described in claim 17, wherein the highest concentration of the second doping concentration is less than 10 ¹² atoms/cm 2 (atoms/cm ² ).