CN103107139B - Structure of field-effect transistor with fin structure and preparation method thereof - Google Patents
Structure of field-effect transistor with fin structure and preparation method thereof Download PDFInfo
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- CN103107139B CN103107139B CN201110351959.6A CN201110351959A CN103107139B CN 103107139 B CN103107139 B CN 103107139B CN 201110351959 A CN201110351959 A CN 201110351959A CN 103107139 B CN103107139 B CN 103107139B
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- 230000005669 field effect Effects 0.000 title claims abstract description 51
- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 claims abstract description 139
- 230000035515 penetration Effects 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000002019 doping agent Substances 0.000 claims abstract description 36
- 238000005040 ion trap Methods 0.000 claims abstract description 23
- 150000002500 ions Chemical class 0.000 claims description 103
- 239000004065 semiconductor Substances 0.000 claims description 61
- 230000004888 barrier function Effects 0.000 claims description 38
- 238000000059 patterning Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 16
- 238000000034 method Methods 0.000 description 15
- 108010085603 SFLLRNPND Proteins 0.000 description 12
- 230000037361 pathway Effects 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
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- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 229910052735 hafnium Inorganic materials 0.000 description 3
- -1 hafnium silicate oxygen compound Chemical class 0.000 description 3
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000011435 rock Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 229910015846 BaxSr1-xTiO3 Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910020696 PbZrxTi1−xO3 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- QEQWDEBBDASYQQ-UHFFFAOYSA-N [O--].[O--].[O--].[O--].[O--].[Sr++].[Ta+5].[Bi+3] Chemical compound [O--].[O--].[O--].[O--].[O--].[Sr++].[Ta+5].[Bi+3] QEQWDEBBDASYQQ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- WOIHABYNKOEWFG-UHFFFAOYSA-N [Sr].[Ba] Chemical compound [Sr].[Ba] WOIHABYNKOEWFG-UHFFFAOYSA-N 0.000 description 1
- VNSWULZVUKFJHK-UHFFFAOYSA-N [Sr].[Bi] Chemical compound [Sr].[Bi] VNSWULZVUKFJHK-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005130 electrotropism Effects 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910000167 hafnon Inorganic materials 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- 229910052845 zircon Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention discloses a kind of structure of field-effect transistor with fin structure and preparation method thereof.Preparation method includes one substrate of offer, the ion trap of one first dopant concentration is formed in substrate, form an at least fin structure, it is arranged in substrate, carry out at least one first ion implanting manufacture craft, to form the penetration resistance ion implanted region of first conductivity type for being located at substrate, wherein penetration resistance ion implanted region has one the 3rd dopant concentration, and the 3rd dopant concentration be more than first dopant concentration, after the first ion implanting manufacture craft, an at least channel layer is formed to be set along an at least surface of fin structure, form a grid, cover the fin structure of part, and form a source electrode and a drain electrode, it is arranged in the fin structure of the both sides of grid.
Description
Technical field
It is more particularly to a kind of with fin structure the present invention relates to the structure and preparation method of a kind of field-effect transistor
Structure of field-effect transistor and preparation method thereof.
Background technology
It is existing as field-effect transistor (field effect transistors, FETs) component size constantly reduces
The development of plane formula (planar) field effect transistor element has faced the limit in manufacture craft.In order to overcome manufacture craft to limit
System, with the field effect transistor element of on-plane surface (non-planar), such as fin-shaped field-effect transistor (fin field effect
Transistor, Fin FET) element substitution flat crystal tube elements have turned into current mainstream development and have become trend.Due to fin-shaped
The stereochemical structure of field effect transistor element can increase the contact area of grid and fin structure, therefore, can further increase grid
For the control in carrier pathway region, so as to reduce the energy band reduction (drain triggered by source electrode that small-sized component faces
Induced barrier lowering, DIBL) effect, it is possible to suppress short-channel effect (short channel effect,
SCE).And because fin-shaped field-effect transistor element is under same grid length, with broader channel width, thus can obtain
The drain drives electric current for doubling.Even, the critical voltage (threshold voltage) of transistor unit also can be by adjusting grid
The work function of pole and regulated and controled.
In the manufacture craft of existing fin-shaped field-effect transistor element, after fin structure formation, it will usually apply again
Row one penetration resistance (anti-punch) ion implanting manufacture craft, to prevent source/drain between or to the perforation effect of substrate
The generation of (punch-through effect).However, for top surface is patterned the fin structure of mask layer covering, by
It is not shielded in the side wall of fin structure, therefore in penetration resistance ion implanting manufacture craft, admixture can not only be implanted in
The lower section of source/drain, while can also be implanted in the carrier pathway region of fin structure side, causes carrier pathway region
Dopant concentration produce uncontrollable variation, this variation can influence the electrical performance of fin-shaped field-effect transistor element so that system
It is greatly reduced as process yields.
The content of the invention
It is an object of the invention to provide a kind of structure of field-effect transistor with fin structure and preparation method thereof, with
The dopant concentration of passage area is avoided to produce uncontrollable variation.
To reach above-mentioned purpose, an embodiment of the invention, there is provided a kind of field-effect transistor with fin structure
Preparation method, comprising providing a substrate, form the ion trap of one first conductivity type in substrate, and the first conductivity type ion
Trap has one first dopant concentration, forms an at least fin structure, is arranged in substrate, carries out at least one first ion implanting system
Make technique, to form penetration resistance (anti-punch) ion implanted region of first conductivity type for being located at substrate, wherein penetration resistance
Ion implanted region has one the 3rd dopant concentration, and the 3rd dopant concentration more than first dopant concentration, in the first ion implanting
After manufacture craft, form an at least channel layer and set along an at least surface of fin structure, form a grid, cover portion
The fin structure and one source electrode of formation that divide and a drain electrode, are arranged in the fin structure of the both sides of grid.
According to another embodiment of the present invention, there is provided a kind of structure of the field-effect transistor with fin structure, include
One substrate, one first conduction type ion trap, are arranged in substrate, and wherein the first conduction type ion trap has one first admixture dense
Degree, an at least fin structure, are arranged in substrate, an at least channel layer, are set along an at least surface of fin structure, wherein
The maximum concentration that channel layer has one second doping concentration, the second doping concentration is led less than the first dopant concentration, at least 1 first
The penetration resistance ion implanted region of electric type, is arranged between substrate and channel layer, and wherein penetration resistance ion implanted region has one the
Three dopant concentrations, and the 3rd dopant concentration is more than the first dopant concentration, a grid, covers fin structure, the Yi Jiyi of part
Source electrode and a drain electrode, are arranged in the fin structure of grid both sides, and wherein source electrode and drain electrode has one second conductivity type.
Brief description of the drawings
Fig. 1 is the preparation flow figure of the field-effect transistor with fin structure；
What Fig. 2 to Figure 12 was illustrated is to imitate crystal according to a kind of field with fin structure of formation of present pre-ferred embodiments
The manufacture method schematic diagram of pipe.
Main element symbol description
Specific embodiment
To enable the general technology person for being familiar with the technical field of the invention to be further understood that the present invention, hereafter spy enumerates
Presently preferred embodiments of the present invention, and coordinate appended accompanying drawing, describe constitution content of the invention and the effect to be reached in detail.
Fig. 1 is the preparation flow figure according to the different field-effect transistors with fin structure for implementing aspect of the invention.Its
Preparation flow is sequentially：Formation fin structure 1a, formation insulating barrier 1b, implementation planarization manufacture craft 1c, implementation eatch-back are scribed
Make technique 1d and remove hard mask 1e.Additionally, the present invention additionally comprises to form penetration resistance (anti-punch) ion note
The the first ion implanting manufacture craft 2 for entering area and the manufacture craft for forming channel layer 3.Herein it is noted that of the invention
It is technically characterized in that the time point to form channel layer 3 must be later than the time point for implementing the first ion implanting 2.For example, execution is worked as
When the time point of the first ion implanting manufacture craft is as shown in the first ion implanting manufacture craft 2a, 2b, 2c, 2d, 2e, 2f, formed
The time point of channel layer is preferably forming place shown in channel layer 3b.But when implementing the time point such as the of the first ion implanting manufacture craft
When shown in one ion implanting manufacture craft 2a, 2b, the time point for forming channel layer preferably locate shown in channel layer 3b that can separately be formed.For
It is more easily understood above-mentioned preparation flow, just different implementation aspects is stated in detail below：
First implements aspect：
Fig. 1 to Fig. 8 is refer to, wherein, Fig. 2 to Fig. 8 shows for the fin structure of formation one of a preferred embodiment of the present invention
It is intended to.In implementing aspect first, the time point of the first ion implanting manufacture craft 2 of execution is before fin structure 1a is formed.Such as
Shown in Fig. 2, a semiconductor base 10 for being coated with a patterning photoresist layer 18 is provided first, wherein, pattern photic
Resist layer 18 is used to the position for defining ion trap 9 and penetration resistance ion implanted region 21, that is, ion trap 9 and penetration resistance
The manufacture craft of ion implanted region 21 can share the photomask manufacture craft along with.However, according to other embodiment, ion trap 9
And penetration resistance ion implanted region 21 also can be respectively obtained by not people having a common goal's photomask.Then, formed in semiconductor base 10
The ion trap 9 of one first conductivity type (such as p-type), this ion trap 9 has a concentration between 1012-1013Atom/square centimeter
(atoms/cm2) the first dopant concentration.Additionally, separately there may be in semiconductor base 10 having one second conductivity type (such as N
Type) ion trap (not shown) so that above-mentioned ion trap be respectively corresponding to N-type MOS transistor (NMOS) area (figure
Do not show) and p-type MOS transistor (PMOS) area (not shown).Semiconductor base 10 can include one piece of silicon (bulk
Silicon) substrate or silicon-on-insulator (silicon-on-insulator, SOI) substrate, wherein silicon-on-insulator
(silicon-on-insulator, SOI) substrate can provide preferably radiating and earthing effect, and contribute to reduces cost with suppression
Noise processed.
Then, under the covering of patterning photoresist layer 18, after to carry out one first ion implanting manufacture craft 2,
There is the penetration resistance ion implanted region 21 of the first conductivity type, wherein penetration resistance ion implanting with formation at least one in ion trap 9
Area 21 has one the 3rd dopant concentration, and the 3rd dopant concentration higher than the first dopant concentration of ion trap 9.Should be noted herein
It is that the first ion implanting manufacture craft can include multiple tracks ion implanting manufacture craft.Additionally, according to the present embodiment, in semiconductor
The surface of substrate 10 has additionally comprised an oxide layer 16, is produced scarce with preventing energetic ion from directly clashing into the surface of semiconductor base 10
Fall into.
Then, as shown in figure 3, removal patterning photoresist layer 18 and oxide layer 16, semiconductor-based to expose
The surface at bottom 10.After optionally to carry out an epitaxial growth (epitaxial growth) manufacture craft, in semiconductor base
10 surface forms semi-conductor layer 23, and it can include the iii-v chemical combination in silicon, carborundum, germanium silicide or the periodic table of elements
Thing, but not limited to this.Additionally, according to different manufacture craft demands, can also be formed with appropriate stress (uphold or compress) or
The semiconductor layer 23 of doping concentration, the electrical performance for adjusting carrier pathway layer.
Then, as shown in figure 4, on semiconductor layer 23 formed one include at least one patterning stress-buffer layer 25 and
Second patterned mask layer 29 of an at least patterning hard mask layer 27, is used to define the position of each fin structure 11.Wherein
Patterning stress-buffer layer 25 includes silica, and patterning hard mask layer 27 includes silicon nitride.Then, an etching making is carried out
Technique, is formed an at least fin structure 11 and is completely cut off with shallow trench 13 on semiconductor base 10, and between each fin structure 11.This
When, the top surface 12 of patterned semiconductor layer 23a is provided with the second patterned mask layer 29, and under patterned semiconductor layer 23a
Side has a penetration resistance ion implanted region 21, wherein, penetration resistance ion implanted region 21 is preferably less than 400 with the distance of top surface 12
Angstrom.
Then, as shown in figure 5, in forming an insulating barrier 31, such as silicon dioxide layer, insulating barrier 31 on semiconductor base 10
Cover each fin structure 11 and fill up each shallow trench 13.The manufacture craft of above-mentioned formation insulating barrier 31 can comprising high density etc. from
Daughter chemical vapor deposition (high density plasma CVD, HDPCVD), sub-atmospheric pressure chemical vapor deposition (sub
Atmosphere CVD, SACVD) or the manufacture craft such as spun-on dielectric (spin on dielectric, SOD).Afterwards,
As shown in fig. 6, implementing an etch-back manufacture craft 1d to insulating barrier 31, it is used to remove the insulating barrier 31 of part, until insulating barrier
Top surface 12 of 31 top surface less than fin structure 11.Additionally, a planarization was optionally carried out before etch-back makes work
Skill 1c, makes insulating barrier 31 contour or lower slightly with the second patterned mask layer 29.Therefore it is semiconductor-based between each fin structure 11
An at least insulation structure of shallow groove 33 is formed on bottom 10.
As shown in fig. 7, carry out an etching process being removed with by the second patterned mask layer 29.Implement in the present invention one
In example, when the second patterned mask layer 29 is comprising silicon nitride, removed using hot phosphoric acid, this is prior art, herein
Seldom repeat.Then, using extension manufacture craft, a channel layer 35 is formed respectively and is covered in the surface of each fin structure 11.According to
Different manufacture craft demands, optionally carry out one second ion implanting manufacture craft to channel layer 35 again, and it can be comprising oblique
To manufacture crafts such as ion implantations (tilted-angle ion implantation), to regulate and control the doping concentration of channel layer 35,
And then adjust critical voltage (the threshold voltage, V of transistorth).Above-mentioned channel layer 35 comprising silicon, germanium silicide or
Other can be used as the semi-conducting material of carrier pathway.Herein it is noted that according to other embodiments of the invention, can also adopt
With the mode of ion implanting, channel layer 35 is directly arranged on the inner side surface (not shown) of fin structure 11, that is, channel layer 35
Not it is covered in the surface of fin structure 11.
Afterwards, as shown in figure 8,10 sequentially forming at least each fin-shaped knot of the covering of a dielectric layer 37, on a semiconductor substrate
The gate material layers 39 of structure 11.According to different manufacture craft demands, above-mentioned dielectric layer 37 can include silica (SiO), nitrogen
The dielectric material or other high dielectric constant materials of SiClx (SiN), silicon oxynitride (SiON) etc..And gate material layers 39 can be included
Polycrystalline silicon material, metal silicide or metal etc..
Herein it is noted that the time point of the above-mentioned formation of channel layer 35 is after insulating barrier 31 fills up shallow trench 13.However,
In another embodiment, formed channel layer 3 time point be connected in and to form fin structure 1a after.According to this embodiment, can pass through
One epitaxial growth manufacture craft, in the time point after forming each fin structure 11 and before insulating barrier 31 fills up shallow trench 13, forms
An at least channel layer 35 in the surface of fin structure 11, now because the top surface 12 of fin structure 11 is subject to the second pattern mask
The covering of layer 29, therefore channel layer 35 can only be formed at the side wall (not shown) of fin structure 11.Further accordance with different manufacture crafts
Demand, optionally carries out one second ion implanting manufacture craft to channel layer 35, to regulate and control the doping concentration of channel layer 35.
Second implements aspect：
Fig. 1, Fig. 3 to Fig. 8 are refer to, the second implementation method similar such as first for implementing aspect implements aspect, and its difference is only
It is：In implementing aspect second, begin to carry out the first ion after forming fin structure 1a and before forming insulating barrier 1b
Injection manufacture craft 2.It is similar as shown in Figure 3, there is provided semiconductor substrate 10, alternative Land cover on this semiconductor surface
Have an one semiconductor layer 23, and now semiconductor base 10 still without penetration resistance ion implanted region.Then, it is similar to as shown in figure 4, shape
Into one second patterned mask layer 29 in the position on semiconductor layer 23, being used to define each fin structure 11.Carry out an etching
Manufacture craft, is formed an at least fin structure 11 and is completely cut off with shallow trench 13 in substrate 10, and between fin structure 11.Now, scheme
The top surface 12 of case semiconductor layer 23a is provided with patterned mask layer 29.Then, one first ion implanting manufacture craft 2 is carried out,
With in the penetration resistance ion implanted region 21 formed below of patterned semiconductor layer 23a.According to another embodiment of the present invention, if
Semiconductor base 10 is before each fin structure 11 is formed and is not covered with semiconductor layer 23, then now penetration resistance ion implanted region 21
Can then be present in fin structure 11.Then, it is similar to first and implements aspect, an insulating barrier 31 is formed respectively, a planarization is carried out
Manufacture craft 1c, one etch-back manufacture craft 1d of execution, the second patterned mask layer 29 of removal, epitaxial growth channel layer 35, should
A little manufacture crafts and follow-up manufacture craft correspond to Fig. 5 to Fig. 8 of the first implementation aspect, are not just repeated here herein.
Additionally, similar as first implements aspect, the time point of epitaxial growth channel layer 35 can be advanced to carries out the first ion implanting making work
Time point after skill 2 and before formation insulating barrier 1b.
Herein it is noted that second implement aspect in, because the first ion implanting manufacture craft is in fin structure 11
Begin to carry out after formation, in order to avoid the dopant concentration of carrier pathway is influenceed by the first ion implanting manufacture craft, passage
Layer 35 is preferably covered in the surface of fin structure 11 in addition in the way of extension manufacture craft, without being set in the way of ion implanting
In the inner side surface (not shown) of fin structure 11.Further accordance with different manufacture craft demands, optionally channel layer 35 is carried out
One second ion implanting manufacture craft, to regulate and control the doping concentration of channel layer 35.
3rd implements aspect：
Fig. 1, Fig. 3 to Fig. 8 are refer to, the 3rd implements aspect similar such as second implements aspect, and its difference is：It is real the 3rd
Apply in aspect, begin to carry out the first ion implanting manufacture craft after forming insulating barrier 1b and before planarizing manufacture craft 1c
2.It is similar such as Fig. 3 to Fig. 4, formed an at least fin structure 11 on semiconductor base 10, do not have now any penetration resistance from
Sub- injection region 21 is present in semiconductor base 10.Then, it is similar to as shown in figure 5, in forming an insulating barrier 31, example in substrate 10
Such as silicon dioxide layer, insulating barrier 31 covers fin structure 11 and fills up shallow trench 13.Then, one first ion implanting system is carried out
Make technique 2, to form a penetration resistance ion implanted region 21 in the lower section of patterned semiconductor layer 23a.It is of the invention another
Embodiment, if before fin structure 11 is formed, on semiconductor base 10 and being not covered with semiconductor layer 23, now penetration resistance ion
Injection region 21 can then be present in fin structure 11.Then, be similar to second implement aspect, carry out a planarization manufacture craft 1c,
Implement an etch-back manufacture craft 1d, removal the second patterned mask layer 29, epitaxial growth channel layer 35, those manufacture crafts with
And follow-up manufacture craft corresponds to Fig. 6 to Fig. 8 of the second implementation aspect, is not just repeated here herein.
Herein it is noted that similar such as second implements aspect, because the first ion implanting manufacture craft 2 is in fin structure
Begin to carry out after 11 formation, in order to avoid the dopant concentration of carrier pathway is influenceed by the first ion implanting manufacture craft, lead to
Channel layer 35 is preferably covered in the surface of fin structure 11 in addition in the way of extension manufacture craft, without being set in the way of ion implanting
Put in the inner side surface (not shown) of fin structure 11.Further accordance with different manufacture craft demands, optionally channel layer 35 is entered
The ion implanting manufacture craft of row one second, to regulate and control the doping concentration of channel layer 35.
4th implements aspect：
Fig. 1, Fig. 3 to Fig. 8 are refer to, the 4th implementation method as such like such as second for implementing aspect implements aspect, its
Difference is：In implementing aspect the 4th, begin after planarization manufacture craft 1c and before etch-back manufacture craft 1d
Carry out the first ion implanting manufacture craft 2.It is similar to as shown in Figures 3 to 5, forms an at least fin structure 11 in semiconductor base
On 10, and in an insulating barrier 31 is formed on semiconductor base 10, insulating barrier 31 covers fin structure 11 and fills up shallow trench 13.
Herein it is noted that not there is now any penetration resistance ion implanted region to be present in fin structure 11.
Afterwards, be similar to as shown in fig. 6, planarize manufacture craft after, carry out one first ion implanting manufacture craft 2,
To form a penetration resistance ion implanted region 21 in the lower section of patterned semiconductor layer 23a.According to another embodiment of the present invention, if
Before each fin structure 11 is formed, on semiconductor base 10 and semiconductor layer 23 is not covered with, now penetration resistance ion implanted region
21 can be present in fin structure 11.Additionally, in the above embodiments, the distance of penetration resistance ion implanted region 21 and top surface 12
Preferably less than 400 angstroms.Afterwards, then carry out an etch-back manufacture craft 1d, removal the second patterned mask layer 29 and extension into
Long-channel layer 35, those manufacture crafts and follow-up manufacture craft correspond to Fig. 6 to Fig. 8 of the second implementation aspect, herein
Just it is not repeated here.
Similarly, in implementing aspect the 4th, because the first ion implanting manufacture craft 2 begins after the formation of fin structure 11
Carry out, in order to avoid the dopant concentration of carrier pathway is influenceed by the first ion implanting manufacture craft, channel layer 35 is preferable
The surface of fin structure 11 is covered in addition in the way of extension manufacture craft, without being arranged on fin-shaped knot in the way of ion implanting
The inner side surface (not shown) of structure 11.Further accordance with different manufacture craft demands, optionally channel layer 35 is carried out one second from
Son injection manufacture craft, to regulate and control the doping concentration of channel layer 35.
5th implements aspect：
Fig. 1, Fig. 3 to Fig. 8 are refer to, the 5th implements aspect similar such as second implements aspect, and its difference is：It is real the 5th
Apply in aspect, begin to carry out the first ion implanting after etch-back manufacture craft and before removing the second patterned mask layer 29
Manufacture craft.It is similar to form an at least fin structure 11 on semiconductor base 10 as shown in Figures 3 to 6, and in substrate 10
An insulating barrier 31 is formed, insulating barrier 31 covers fin structure 11 and fills up shallow trench 13.Then, insulating barrier 31 is implemented one time
Etching process 1d, is used to remove the insulating barrier 31 of part, until top surface of the top surface of insulating barrier 31 less than fin structure 11
12.Additionally, optionally carrying out a planarization manufacture craft 1c before etch-back manufacture craft 1d, make insulating barrier 31 and
Two patterned mask layers 29 are contour or lower slightly.Herein it is noted that now not with the presence of any penetration resistance ion implanted region
In fin structure 11.
Then, still it is similar to as shown in fig. 6, carry out one first ion implanting manufacture craft 2, to form penetration resistance ion note
Enter area 21 in the lower section of patterned semiconductor layer 23a.According to another embodiment of the present invention, if formed fin structure 11 before,
On semiconductor base 10 and semiconductor layer 23 is not covered with, now penetration resistance ion implanted region 21 can then be present in fin structure 11
In.Afterwards, the second patterned mask layer 29 and epitaxial growth channel layer 35 are removed.
Similarly, in implementing aspect the 5th, because the first ion implanting manufacture craft 2 begins after the formation of fin structure 11
Carry out, in order to avoid the dopant concentration of carrier pathway is influenceed by the first ion implanting manufacture craft, channel layer 35 is preferable
The surface of fin structure 11 is covered in the way of extension manufacture craft in addition, without being arranged on fin-shaped knot in the way of ion implanting
The inner side surface (not shown) of structure 11.Further accordance with different manufacture craft demands, optionally channel layer 35 is carried out one second from
Son injection manufacture craft, to regulate and control the doping concentration of channel layer 35.
6th implements aspect：
Fig. 1, Fig. 3 to Fig. 8 are refer to, the 6th implements aspect similar such as second implements aspect, and its difference is：It is real the 6th
Apply in aspect, begin to carry out the first ion implanting manufacture craft after the second patterned mask layer 29 is removed.Similar such as Fig. 3 extremely schemes
Shown in 6, an at least fin structure 11 is formed on semiconductor base 10, and in forming an insulating barrier 31, such as two in substrate 10
Silicon oxide layer, insulating barrier 31 covers fin structure 11 and fills up shallow trench 13.Then, a planarization system is implemented to insulating barrier 31
Make technique and an etch-back manufacture craft, be used to remove the insulating barrier 31 of part, until the top surface of insulating barrier 31 is less than fin-shaped
The top surface 12 of structure 11.Herein it is noted that not there is now any penetration resistance ion implanted region to be present in fin structure 11
In.
It is similar to be removed with by the second patterned mask layer 29 as shown in fig. 7, carrying out an etching process.Then, carry out
One first ion implanting manufacture craft, to form a penetration resistance ion implanted region 21 in the lower section of patterned semiconductor layer 23a.Connect
, using extension manufacture craft, form a channel layer 35 and be covered in the surface of fin structure 11.According to different manufacture craft demands,
An ion implanting manufacture craft is optionally carried out to channel layer 35, to regulate and control the doping concentration of channel layer 35.
Herein it is noted that the 6th implement aspect in, due to the first ion implanting manufacture craft 2 formed fin-shaped knot
After structure 1a begin carry out, in order to avoid the dopant concentration of carrier pathway is influenceed by penetration resistance manufacture craft, channel layer 35 compared with
It is good that the surface of fin structure 11 is covered in the way of extension manufacture craft in addition, without being arranged on fin-shaped in the way of ion implanting
The inner side surface (not shown) of structure 11.Further accordance with different manufacture craft demands, one second optionally is carried out to channel layer 35
Ion implanting manufacture craft, to regulate and control the doping concentration of channel layer 35.
Additionally, implementing aspect according to the first above-mentioned implementation aspect to the 6th, the surface of semiconductor base 10 has half
Conductor layer 23, the semiconductor layer 23 can have appropriate stress (uphold or compress) or with appropriate doping concentration, for adjusting
The electrical performance of carrier pathway layer.However, another preferred embodiment of the invention, the surface of semiconductor base 10 is not deposited
There is semiconductor layer 23, and the patterned semiconductor layer 23a in fin structure 11 is replaced by a protuberance 36, wherein, it is prominent
Portion 36 is obtained by etching semiconductor base 10.Therefore, channel layer 35 is set along the surface of protuberance 36, and its structure can refer to
Fig. 9.
7th implements aspect：
Similar such as first implements aspect, and in this implementation aspect, fin structure 11 is with epitaxial growth (epitaxial
Growth mode) is formed on semiconductor substrate 10.Its manufacturing process steps is similar as shown in Fig. 1, Fig. 3 to Fig. 9, and hereafter
Only to being been described by difference.First, as shown in Figure 10, there is provided one is coated with the semiconductor base 10 of patterned mask layer 15,
It is used to define the position of follow-up each fin structure 11.In semiconductor base 10 with one first conductivity type (such as p-type) from
Sub- trap 9, this ion trap 9 has a concentration between 1012-1013Atom/square centimeter (atoms/cm2) the first dopant concentration.And
Separately there may be the ion trap (not shown) for having one second conductivity type (such as N-type) in semiconductor base 10 so that it is above-mentioned from
Sub- trap is respectively corresponding to N-type MOS transistor (NMOS) area's (not shown) and p-type MOS transistor
(PMOS) area's (not shown).Additionally, above-mentioned patterned mask layer 15 includes sandwich construction, it includes an at least stress-buffer layer
16, such as silica, and an at least hard mask layer 18, such as silicon nitride.
Then, still as shown in Figure 10, the first ion implanting manufacture craft 2 is carried out, there is the first conductivity type to form one
Penetration resistance ion implanted region 21, and penetration resistance ion implanted region 21 dopant concentration higher than ion trap 9 the first dopant concentration.This
Outward, before one first ion implanting manufacture craft 2 is carried out, (figure is not can to form an oxide layer on the surface of semiconductor base 10 in advance
Show), prevent the direct surface of impact basement 10 of energetic ion and produce defect.In the present embodiment, by patterned mask layer 15
The region of penetration resistance ion implanted region 21 is defined, however, according to other preferred embodiments, penetration resistance ion implanted region 21 can be with
Ion trap 9 shares the photomask along with, that is, patterned mask layer 15 is not used to define the area of penetration resistance ion implanted region 21
Domain.
Then, as shown in figure 11, a selective epitaxial growth manufacture craft is carried out, to expose for patterned mask layer 15
The surface of substrate 10 be crystal seed layer, formed fin structure 11 in each groove 32.Each fin structure 11 can be by the bottom of groove 32
The surface of semiconductor base 10 is grown up, and is grown up upwards and protruded from the top surface of patterned mask layer 15.According to manufacture craft demand,
Selective epitaxial grow up finish after, can separately carry out a cycle annealing manufacture craft (cyclic thermal annealing,
CTA), reducing the defect in fin structure 11.Above-mentioned fin structure 11 can comprising silicon layer (Si), germanium-silicon layer (SiGe) or on
The combination stated.Herein it is noted that because in this implementation aspect, (figure is not without coverage mask layer for the top surface 12 of fin structure 11
Show), therefore it is not required to be removed the manufacture craft of mask layer.Additionally, according to other preferred embodiments, if penetration resistance ion implanting
Area 21 shares the photomask along with and is obtained with ion trap 9, then need to be additionally formed a patterned mask layer (not shown) to define
Go out the forming region of fin structure 11.Follow-up manufacture craft, is similar to such as corresponding Fig. 4 to Fig. 8, is not just gone to live in the household of one's in-laws on getting married herein
State.
Additionally, this implementation aspect also applies to the second corresponding implementation aspect to the 5th implementation aspect, that is, outside
Prolong growth fin structure 11 after on semiconductor base 10, the time point for implementing the first ion implanting manufacture craft 2 can be respectively at：Shape
After into fin structure 1a, after formation insulating barrier 1b, after planarization manufacture craft 1c or after etch-back manufacture craft 1d.
For simplicity, those similar manufacture crafts can correspond to Fig. 4 to Fig. 9, just not be repeated here herein.
After above-mentioned first to the 7th implementation aspect is completed, various required semiconductor fabrication process, example can be then carried out
Such as there is the MOS manufacture crafts of polysilicon gate or metal gates.As shown in figure 12, an embodiment of the invention, be
The one multi-gate field effect transistor structure schematic diagram for being integrated in preferential (gate first) manufacture craft of grid.First, in having
In the gate material layers 39 of metal ingredient formed one pattern cap rock 46, be used to define an at least nmos area (not shown) with least
The position of each grid in one PMOS areas (not shown).Then, grid material is etched using cap rock 46 is patterned as etching mask
The bed of material 39 and the dielectric layer 37 with high-k, and in forming each fin-shaped knot of an at least covering part on semiconductor base 10
The grid structure 28 of structure 11.Then, in not by grid cover fin structure 11 in respectively selectively formed one be lightly doped source electrode/
Drain region (not shown).Then, the peripheral side wall in grid structure 28 forms a clearance wall 47, clearance wall 47 can for simple layer or
Sandwich construction, or may include that lining (liner) etc. is constituted together.Afterwards, ion is carried out as mask with clearance wall 47 and cap rock 46
Injection manufacture craft, mixes appropriate admixture.Wherein, admixture may include N-type or p-type admixture, with nmos area and PMOS areas
The exposed at both sides of grid structure 28 fin structure 11 out on be implanted into the source/drain admixture of relative electrotropism respectively, and take
With an annealing manufacture craft source/drain regions (not shown) is formed to activate.Although the present embodiment is preferably to sequentially form gently mixing
Miscellaneous source/drain regions, clearance wall 27 and source/drain regions, but this is not limited to, the present invention again can be according to the need in manufacture craft
The order of any above-mentioned formation clearance wall of adjustment and doped region is sought, this belongs to the scope that the present invention is covered.
According to another embodiment of the present invention, still it is similar to as shown in figure 12, is the rearmounted (gate of grid of a metal gates
Last) the preparation method of multi-gate field-effect transistor.When the gate material layers 39 shown in foregoing Fig. 8 are polysilicon, grid
Rearmounted manufacture craft then accepts preferential (gate first) manufacture craft of grid of above-mentioned polysilicon gate.In substitution grid knot
After the polysilicon gate of a structure 28 extremely metal gates, the top of the passage area (not shown) of fin structure 11 is sequentially coated with
An at least high dielectric constant gate dielectric layer (not shown), at least a workfunction layers (not shown) and an at least metal
Conductive layer (not shown).Regardless of whether being the rearmounted manufacture craft of grid or grid first fabrication process, high K gate therein
The material of pole dielectric layer all may be selected from such as hafnium oxide (hafnium oxide, HfO2), hafnium silicate oxygen compound (hafnium
Silicon oxide, HfSiO4), hafnium silicate nitrogen oxide (hafnium silicon oxynitride, HfSiON), oxygen
Change aluminium (aluminum oxide, Al2O3), lanthana (lanthanum oxide, La2O3), tantalum oxide (tantalum
Oxide, Ta2O5), yittrium oxide (yttrium oxide, Y2O3), zirconium oxide (zirconium oxide, ZrO2), strontium titanates
(strontium titanate oxide, SrTiO3), zirconium silicate oxygen compound (zirconium silicon oxide,
ZrSiO4), zirconic acid hafnium (hafnium zirconium oxide, HfZrO4), strontium bismuth tantalum pentoxide (strontium bismuth
Tantalate, SrBi2Ta2O9, SBT), lead zirconate titanate (lead zirconate titanate, PbZrxTi1-xO3, PZT) and titanium
Sour barium strontium (barium strontium titanate, BaxSr1-xTiO3, BST) and the group that is constituted, but not limited to this.And on
State metal conducting layer and include low electrical resistant material or its combination.Additionally, in workfunction layers and high dielectric constant gate dielectric layer
Between and workfunction layers and metal conducting layer between, it is also possible to selectivity respectively formed one include titanium (Ti), titanium nitride
(TiN), barrier layer (barrier layer) (not shown) of the material such as tantalum (Ta), tantalum nitride (TaN).
By above-mentioned grid first fabrication process or the rearmounted manufacture craft of grid, one has been completed in fact has fin structure
Multi-gate field-effect transistor (multi-gate MOSFET).Herein it is noted that in the above-described embodiment, fin structure
There is three direct contact surfaces, such as two contact side (not shown) and a contact top surface (not shown) between 11 and dielectric layer 23,
Three gate field effect transistors (tri-gate MOSFET) thus can be referred to as.Compared to plane field-effect transistor, this three gate field
The passage that effect transistor is circulated by three above-mentioned direct contact surfaces as carrier, therefore have under same grid length
Carrier pathway width wider so that the drain drives electric current for doubling can be obtained under identical driving voltage.However, above-mentioned
Multi-gate field-effect transistor be not limited to three gate field effect transistors, according to the demand in manufacture craft, fin structure 11
Top surface 12 and dielectric layer 23 between can also have a patterning hard mask layer 15, that is, the only side on the two sides of fin structure 11
There is direct contact surface between 34 and dielectric layer 23.Therefore, the multi-gate field-effect transistor that should have two direct contact surfaces constitutes one
Fin field-effect transistor (fin field effect transistor, Fin FET).
Summary, the present invention provides a kind of preparation method of the field-effect transistor with fin structure, wherein carrying out the
The time point of one ion implanting manufacture craft 2 prior to formed channel layer 3, that is, the admixture of penetration resistance ion implanted region will not shadow
The dopant concentration distribution in channel layer 35 is rung, therefore the electrical variation of fin-shaped field-effect transistor element can be reduced.
The foregoing is only presently preferred embodiments of the present invention, all impartial changes done according to the claims in the present invention with repair
Decorations, should all belong to covering scope of the invention.
Claims (20)
1. a kind of preparation method of the field-effect transistor with fin structure, includes：
One substrate is provided；
The ion trap of one first conductivity type is formed in the substrate, and the ion trap has one first dopant concentration；
An at least fin structure is formed, is arranged in the substrate；
At least one first ion implanting manufacture craft is carried out, to form the penetration resistance of first conductivity type for being located at the substrate
(anti-punch) ion implanted region, wherein the penetration resistance ion implanted region have one the 3rd dopant concentration, and the 3rd admixture
Concentration is more than first dopant concentration；
After the first ion implanting manufacture craft, an at least channel layer is formed along the fin-shaped knot by extension manufacture craft
An at least surface of structure is set；
A grid is formed, the fin structure of part is covered；And
A source electrode and a drain electrode are formed, is arranged in the fin structure of the both sides of the grid.
2. there is the preparation method of the field-effect transistor of fin structure as claimed in claim 1, wherein forming the fin structure
The step of include：
Semi-conductor layer is formed in the substrate；And
The semiconductor layer is etched, to form the fin structure.
3. there is the preparation method of the field-effect transistor of fin structure as claimed in claim 1, wherein forming the fin structure
The step of include：
A patterning hard mask layer is made in the substrate；And
In the substrate of growth semi-conductor layer in exposure for the patterning hard mask layer, to form the fin structure.
4. there is the preparation method of the field-effect transistor of fin structure as claimed in claim 3, wherein forming the fin structure
Afterwards, additionally comprised：
An insulating barrier is formed, the fin structure is covered；
A grinding manufacture craft is carried out to insulating barrier；And
An etch-back manufacture craft is carried out to insulating barrier.
5. there is the preparation method of the field-effect transistor of fin structure as claimed in claim 4, wherein carrying out the etch-back
After manufacture craft, additionally comprise：
Remove the patterning hard mask layer.
6. there is the preparation method of the field-effect transistor of fin structure as claimed in claim 1, wherein carrying out first ion
The time point for injecting manufacture craft is before the fin structure is formed.
7. there is the preparation method of the field-effect transistor of fin structure as claimed in claim 4, wherein carrying out first ion
The time point for injecting manufacture craft is between forming the insulating barrier and carrying out the grinding manufacture craft.
8. there is the preparation method of the field-effect transistor of fin structure as claimed in claim 4, wherein carrying out first ion
The time point for injecting manufacture craft is between carrying out the grinding manufacture craft and carrying out the etch-back manufacture craft.
9. there is the preparation method of the field-effect transistor of fin structure as claimed in claim 5, wherein carrying out first ion
The time point for injecting manufacture craft is between carrying out the etch-back manufacture craft and removing the hard mask layer.
10. there is the preparation method of the field-effect transistor of fin structure as claimed in claim 5, wherein carrying out first ion
The time point for injecting manufacture craft is between removing the hard mask layer and forming the channel layer.
The preparation method of 11. field-effect transistors with fin structure as claimed in claim 1, wherein first ion implanting
Manufacture craft includes multiple tracks ion implanting manufacture craft.
The preparation method of 12. field-effect transistors with fin structure as claimed in claim 1, the wherein channel layer is forward
It is covered on the surface of the fin structure to property.
The preparation method of 13. field-effect transistors with fin structure as claimed in claim 1, the wherein channel layer are to set
In the inner side surface of the fin structure.
The preparation method of 14. field-effect transistors with fin structure as claimed in claim 1, the wherein channel layer is to be selected from
Silicon layer, germanium silicide layer, silicon carbide layer or combinations of the above.
The preparation method of 15. field-effect transistors with fin structure as claimed in claim 1, wherein forming the channel layer
Afterwards, additionally comprised：
One second ion implanting manufacture craft is carried out, regulates and controls the dopant concentration of the channel layer.
The preparation method of 16. field-effect transistors with fin structure as claimed in claim 15, wherein second ion note
Enter manufacture craft and include oblique ion implanting (tilted-angle ion implantation) manufacture craft.
A kind of 17. structures of the field-effect transistor with fin structure, include：
Substrate；
First conduction type ion trap, is arranged in the substrate, and wherein the first conduction type ion trap has one first dopant concentration；
An at least fin structure, is arranged in the substrate；
An at least channel layer, is set along an at least surface of the fin structure, and wherein the channel layer passes through extension manufacture craft
Formed and with one second doping concentration, the maximum concentration of second doping concentration is less than first dopant concentration；
At least the penetration resistance ion implanted region of one first conductivity type, is arranged between the substrate and the channel layer, and wherein this resists
There is one the 3rd dopant concentration through ion implanted region, and the 3rd dopant concentration is more than first dopant concentration；
Grid, covers the fin structure of part；And
Source electrode and a drain electrode, are arranged in the fin structure of the grid both sides, and wherein the source electrode and the drain electrode have one
Second conductivity type.
The structure of 18. field-effect transistors with fin structure as claimed in claim 17, wherein includes one in the substrate
Insulating barrier, the adjacent fin structure.
The structure of 19. field-effect transistors with fin structure as claimed in claim 17, the wherein top surface of the fin structure
Distance with the penetration resistance ion implanted region is less than 400 angstroms.
The structure of 20. field-effect transistors with fin structure as claimed in claim 17, wherein second doping concentration
Maximum concentration is less than 1012Atom/square centimeter (atoms/cm2)。
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| CN106611710A (en) | 2015-10-22 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | A formation method of a semiconductor structure |
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