TWI707387B - Silicon-on-insulator field effect transistor and manufacturing method thereof - Google Patents

Abstract

A silicon-on-insulator field effect transistor includes a substrate, an ion implantation region, and a gate structure. The substrate includes a semiconductor substrate, an insulating layer, and a semiconductor layer. The semiconductor substrate has a first conductive type. The insulating layer is disposed on the semiconductor substrate. The semiconductor layer is disposed on the insulating layer. The semiconductor layer has a second conductive type, a first surface, and a second surface opposite the first surface. The first conductive type is different from the second conductive type. The ion implantation region is disposed at the bottom of the semiconductor layer and has the first conductive type. The gate structure is disposed on the first surface of the semiconductor layer. The gate structure includes a gate dielectric layer and a gate. The gate is disposed on the gate dielectric layer.

Description

Field effect transistor of silicon on insulating layer and manufacturing method thereof

The present invention relates to a field effect transistor with silicon on an insulating layer, and particularly relates to a field effect transistor with silicon on an insulating layer, which has an ion implantation area disposed at the bottom of a semiconductor layer.

In the current semiconductor industry, compared with the three-dimensional fin field-effect transistor (FinFET), the planar fully depleted silicon on insulator (FD-SOI) field-effect transistor A field-effect transistor with similar performance to FinFET can be made with lower manufacturing cost.

Although the field-effect transistors of FD-SOI that have attracted more attention at this stage include ultra-thin-body field effect transistor (UTBFET) and recessed channel field effect transistor (RCFET) ), but the manufacturing cost of UTBFET with channel structure thickness of less than 25 nm is high. In addition to the fact that the source/channel/drain structure of RCFET is not coplanar, the thickness of the channel layer cannot be precisely controlled and may be caused by plasma Structural damage caused by etching.

The present invention provides a field-effect transistor of silicon on an insulating layer, which has a channel layer thinned by ion implantation, which can improve gate control, reduce leakage current, reduce subcritical swing (SS), and reduce drain initiation Drain induced barrier lowering (DIBL) effect.

The present invention provides a method for manufacturing a field-effect transistor of silicon on an insulating layer, which is used for manufacturing the above-mentioned field-effect transistor of silicon on an insulating layer, and has the advantage of low manufacturing cost.

The silicon field effect transistor on the insulating layer of the present invention includes a substrate, an ion implantation area and a gate structure. The substrate includes a semiconductor base, an insulating layer, and a semiconductor layer. The semiconductor substrate has a first conductivity type. The insulating layer is configured on the semiconductor substrate. The semiconductor layer is disposed on the insulating layer. The semiconductor layer has a second conductivity type, a first surface, and a second surface opposite to the first surface. The first conductivity type is different from the second conductivity type. The ion implantation area is disposed at the bottom of the semiconductor layer and has the first conductivity type. The gate structure is disposed on the first surface of the semiconductor layer. The gate structure includes a gate dielectric layer and a gate. The gate electrode is arranged on the gate dielectric layer.

In an embodiment of the present invention, a distance between the ion implantation area and the first surface of the semiconductor layer is 1.5 nm to 10 nm.

In an embodiment of the present invention, the orthographic projection of the gate structure on the semiconductor substrate overlaps the orthographic projection of the ion implantation region on the semiconductor substrate.

In an embodiment of the present invention, the orthographic projection area of the aforementioned gate structure on the semiconductor substrate is less than or equal to the orthographic projection area of the ion implantation region on the semiconductor substrate.

In an embodiment of the present invention, the aforementioned ion implantation region is in contact with the insulating layer and is aligned with the second surface of the semiconductor layer.

In an embodiment of the present invention, the length of the aforementioned ion implantation region is 10 nm to 140 nm.

In an embodiment of the present invention, the aforementioned semiconductor layer and the semiconductor substrate are respectively located on opposite sides of the insulating layer.

The method for manufacturing a silicon field-effect transistor on an insulating layer of the present invention includes the following steps. First, provide a substrate. The substrate includes a substrate including a semiconductor base, an insulating layer, and a semiconductor layer. The semiconductor substrate has a first conductivity type. The insulating layer is configured on the semiconductor substrate. The semiconductor layer is disposed on the insulating layer. The semiconductor layer has a second conductivity type, a first surface, and a second surface opposite to the first surface. The first conductivity type is different from the second conductivity type. Next, an ion implantation area is formed at the bottom of the semiconductor layer, and the ion implantation area has the first conductivity type. Then, a gate structure is formed on the first surface of the semiconductor layer. The gate structure includes a gate dielectric layer and a gate electrode, and the gate electrode is disposed on the gate dielectric layer.

In an embodiment of the present invention, the step of forming the ion implantation region at the bottom of the semiconductor layer includes the following steps. A photoresist pattern is formed on the semiconductor layer of the substrate. Perform ion implantation procedures on part of the semiconductor layer exposed by the photoresist pattern. Remove the photoresist pattern.

In an embodiment of the present invention, the parameters of the aforementioned ion implantation program include: implantation energy is 2 keV to 20 keV, implantation dose is 10 ¹² cm ^-2 to 10 ¹⁴ cm ^-2 , and angle is 0 degree to 60 degrees, annealing temperature is 900 ℃ to 1100 ℃, annealing time is less than 60 seconds.

In an embodiment of the present invention, the parameters of the above ion implantation program include: implantation energy is 9.5 keV, implantation dose is 8×10 ¹³ cm ^-2 , angle is 60 degrees, annealing temperature is 1050 ℃, annealing The time is 5 seconds.

In an embodiment of the present invention, the implantation impurity of the ion implantation area is boron, aluminum, gallium, phosphorus, arsenic, antimony, oxygen or nitrogen.

In an embodiment of the present invention, the step of forming the gate structure on the first surface of the semiconductor layer includes the following steps. A dielectric layer and a gate material layer are sequentially formed on the semiconductor layer of the substrate. A photoresist pattern is formed on the gate material layer. A part of the gate material layer exposed by the photoresist pattern and a part of the dielectric layer under it are removed to form a gate and a gate dielectric layer.

In an embodiment of the present invention, the above-mentioned method for manufacturing a field-effect transistor of silicon on an insulating layer further includes the following steps. A spacer material is formed on the substrate to cover the semiconductor layer, the photoresist pattern, the sidewall of the gate electrode and the sidewall of the gate dielectric layer. Remove part of the spacer material and the photoresist pattern to form the spacer.

Based on the above, in the field-effect transistor of silicon on the insulating layer and its manufacturing method of the present invention, the thickness of the semiconductor layer (channel layer) is thinned by forming an ion implantation region at the bottom of the semiconductor layer (channel layer), Furthermore, the silicon field-effect transistor on the insulating layer of the present invention has the effects of improving gate control, reducing leakage current, reducing subcritical swing, and reducing the energy barrier reduction effect caused by drain.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

1A to 1G are schematic cross-sectional views showing a manufacturing process of a silicon-on-insulating field effect transistor according to an embodiment of the invention. Fig. 1H is a schematic perspective view of Fig. 1G.

Please refer to FIG. 1A. First, a substrate 120 is provided. In this embodiment, the substrate 120 includes a semiconductor base 122, an insulating layer 124, and a semiconductor layer 126. The semiconductor substrate 122 has a first conductivity type. The insulating layer 124 is disposed on the semiconductor substrate 122. The semiconductor layer 126 is disposed on the insulating layer 124, and the semiconductor layer 126 has a second conductivity type, a first surface 126a, and a second surface 126b opposite to the first surface 126a. Among them, the first conductivity type is different from the second conductivity type. The semiconductor layer 126 and the semiconductor substrate 122 are respectively located on opposite sides of the insulating layer 124. For example, the semiconductor substrate 122 of this embodiment is, for example, a silicon substrate with a P-type semiconductor, the insulating layer 124 is, for example, a silicon oxide layer, and the semiconductor layer 126 is, for example, an N-type semiconductor layer, but it is not limited thereto. In other embodiments, the semiconductor substrate may also be a silicon substrate with an N-type semiconductor, and the semiconductor layer may also be a P-type semiconductor layer. In addition, in this embodiment, the thickness of the semiconductor layer 126 is, for example, 25 nm. The thickness of the insulating layer 124 is, for example, 25 nm.

Next, referring to FIG. 1B, a photoresist pattern 130 is formed on the first surface 126a of the semiconductor layer 126 so that a portion of the semiconductor layer 126 exposed by the photoresist pattern 130 and defines the ion implantation region 127 to be formed subsequently Length L1. Next, using the optimized parameters of the ion implantation procedure, the ion implantation procedure I is performed on the part of the semiconductor layer 126 exposed by the photoresist pattern 130 to dope implant impurities of a different conductivity type from the semiconductor layer 126 to The bottom of the semiconductor layer 126. Then, the photoresist pattern 130 is removed to form an ion implantation region 127 having the first conductivity type at the bottom of the semiconductor layer 126. At this time, the regions on the left and right sides of the semiconductor layer 126 that do not include the ion implantation region 127 can be regarded as the source region 128 and the drain region 129.

In this embodiment, the implantation impurity is, for example, boron, but it is not limited thereto. That is to say, in other embodiments, the implantation impurity can also be aluminum, gallium, phosphorus, arsenic, antimony, oxygen, or nitrogen, as long as the conductivity type of the doped ion implantation region 127 is compatible with the semiconductor layer 126 The conductivity type is different. In addition, the parameters of the optimized ion implantation program will be described in subsequent embodiments.

Furthermore, in this embodiment, the ion implantation region 127 having the first conductivity type may be located at the bottom of the semiconductor layer 126. In some embodiments, the ion implantation region 127 may also contact the insulating layer 124 and be aligned with the second surface 126 b of the semiconductor layer 126. In addition, there is a distance between the ion implantation region 127 and the first surface 126a of the semiconductor layer 126, and the distance is, for example, 1.5 nm to 10 nm. The length L1 of the ion implantation region 127 is, for example, 10 nm to 140 nm. Preferably, the length L1 of the ion implantation region 127 is 120 nm.

Then, referring to FIG. 1C, a dielectric layer 141 and a gate material layer 143 are sequentially formed on the first surface 126a of the semiconductor layer 126. In this embodiment, the material of the dielectric layer 141 is, for example, a high dielectric constant material, but it is not limited thereto. The method of forming the dielectric layer 141 is, for example, chemical vapor deposition or atomic layer deposition, but is not limited thereto. The material of the gate material layer 143 includes polysilicon or metal materials, such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, TaC, TiC, NiSi, CoSi, other suitable metal materials or combinations thereof. The formation method of the gate material layer 143 is, for example, physical vapor deposition, chemical vapor deposition, or atomic layer deposition, but is not limited thereto.

1D to 1E, a photoresist pattern 131 is formed on the gate material layer 143 to expose a part of the gate material layer 143. Then, the photoresist pattern 131 is used as a mask, and for example, by etching, a part of the gate material layer 143 exposed by the photoresist pattern 131 and a part of the dielectric layer 141 below it are removed to form a gate dielectric The electrical layer 142 and the gate 144. In this embodiment, the gate dielectric layer 142 and the gate electrode 144 can be regarded as the gate structure 140, wherein the gate structure 140 is disposed on the first surface 126a of the semiconductor layer 126, and the gate electrode 144 is disposed on the gate dielectric On the electrical layer 142. In this embodiment, the dielectric layer thickness t _{ox of the} gate dielectric layer 142 is, for example, 3 nm. In some embodiments, the orthographic projection of the gate structure 140 on the semiconductor substrate 122 overlaps the orthographic projection of the ion implantation region 127 on the semiconductor substrate 122, and the orthographic projection area of the gate structure 140 on the semiconductor substrate 122 is less than or equal to The orthographic projection area of the ion implantation region 127 on the semiconductor substrate 122. In addition, since the semiconductor layer 126 under the gate structure 140 can be regarded as a channel layer, in addition, since the semiconductor layer 126 under the gate structure 140 can be regarded as a channel layer, this embodiment is formed by forming The ion implantation region 127 thins the thickness of the channel layer, so that the channel thickness t _ch of the initial channel layer of this embodiment becomes the effective channel thickness D, and the effective channel thickness D is also the ion implantation region 127 and the semiconductor layer 126 The distance between the first surfaces 126a, that is, the channel thickness t _ch of the channel layer in this embodiment is reduced from 25 nm to the effective channel thickness D, for example, 1.5 nm to 10 nm.

1F, a spacer material 150 is formed on the substrate 120 so that the spacer material 150 conformally covers the first surface 126a of the semiconductor layer 126, the photoresist pattern 131, the sidewalls of the gate electrode 144, and the gate dielectric layer 142 The sidewall. In this embodiment, the spacer material 150 is, for example, an insulating material, including silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The formation method of the spacer material 150 is, for example, a chemical vapor deposition method, but is not limited thereto.

1G and 1H at the same time, part of the spacer material 150 and the photoresist pattern 131 are removed by an anisotropic etching to expose the top surface of the gate electrode 144 and part of the first surface 126a of the semiconductor layer 126. And a spacer 151 is formed. In this embodiment, the spacer 151 covers the sidewalls of the gate electrode 144 and the sidewalls of the gate dielectric layer 142. So far, the silicon-on-insulating field effect transistor 100 of this embodiment has been manufactured.

In short, the silicon-on-insulating field-effect transistor 100 of this embodiment includes a substrate 120, an ion implantation region 127, and a gate structure 140. The substrate 120 includes a semiconductor base 122, an insulating layer 124, and a semiconductor layer 126. The semiconductor substrate 122 has a first conductivity type. The insulating layer 124 is disposed on the semiconductor substrate 122. The semiconductor layer 126 is disposed on the insulating layer 124. The semiconductor layer 126 has a second conductivity type, a first surface 126a, and a second surface 126b opposite to the first surface 126a. The first conductivity type is different from the second conductivity type. The ion implantation region 127 is disposed at the bottom of the semiconductor layer 126 and has the first conductivity type. The gate structure 140 is disposed on the first surface 126 a of the semiconductor layer 126. The gate structure 140 includes a gate dielectric layer 142 and a gate 144. The gate electrode 144 is disposed on the gate dielectric layer 142.

Example

Example 1 : Parameter optimization of ion implantation program

The following uses different simulation analysis to optimize the parameters of the ion implantation process, so that the silicon field-effect transistor on the insulating layer of this embodiment can improve gate control, reduce leakage current, and reduce subcriticality. Swing (SS) and reducing the drain induced energy barrier reduction effect (DIBL) effect. The parameters of the ion implantation program include implantation energy (Energy), implantation dose (Dosage), angle (Tilt degree), wafer rotation number, annealing temperature (Temp.), annealing time (Time).

Specifically, the following simulation analysis is performed using the 2016 version of Sentaurus TCAD (technology computer aided design) software. The component size structure follows the ITRS 90 nm node process blueprint specification. The channel length used is 90 nm, the channel thickness is 25 nm, and the maximum gate and drain voltage is 1.2 V. Quantum confinement (QC) effect mode has been added to all TCAD simulation processes to fully reflect the special characteristics of nanostructures. In terms of electrical characteristics, the gate structure adopts a metal/SiO ₂ (t _ox =3 nm) structure. In addition, the simulation range of the parameters of the ion implantation program is: implantation energy (Energy) is 2~180keV, implantation dose (Dosage) is 10 ¹¹ ~10 ¹⁶ cm ^-2 , and angle (Tilt degree) is 0 ^o ~90 ^o , annealing temperature (Temp.) is 900~1100℃, annealing time (Time) is 60 seconds or less. Planting impurity is boron

2A and FIG. 2B are diagrams showing the relationship between different implantation energy and the transfer characteristics of silicon field effect transistors on the insulating layer, SS and DIBL, respectively. Table 1 shows the simulation results of the electrical characteristic parameters of the silicon field-effect transistor on the insulating layer with different implantation energy.

Table 1 Dosage (cm ^-2 ) Energy (keV) WF (eV) I _on (A) I _off (A) I _on /I _off SS (mV/dec) DIBL (mV/V) 8.0×10 ¹³ 3.98 4.459 2.81×10 ^-5 1.99×10 ^-12 1.41×10 ⁷ 76.7 159.1 3.99 4.457 2.77×10 ^-5 2.25×10 ^-12 1.23×10 ⁷ 77.5 190.4 4.00 4.488 2.98×10 ^-5 1.27×10 ^-12 2.35×10 ⁷ 74.9 129.6 4.01 4.479 2.81×10 ^-5 2.10×10 ^-12 1.34×10 ⁷ 77.1 133.0 4.02 4.505 2.98×10 ^-5 1.16×10 ^-12 2.57×10 ⁷ 74.6 106.9

From the results of Figure 2A, Figure 2B and Table 1, it can be seen that compared to the implantation energy (Energy) of 3.98, 3.99, 4.00, 4.01 keV, the implantation energy of 4.02 keV, the silicon field effect transistor on the insulating layer has Better device characteristics, that is, a lower leakage current (I _off =1.16×10 ^-12 A), a higher current on-off ratio (I _on /I _off = 2.57×10 ⁷ ), and a smaller subcritical Swing (SS=74.6 mV/dec) and less drain lead to energy barrier reduction effect (DIBL=106.9 mV/V).

3A and 3B are the relationship diagrams of the transfer characteristics, SS and DIBL of silicon field effect transistors on the insulating layer with different implant doses. Table 2 shows the simulation results of different implant doses on the electrical characteristics of silicon field-effect transistors on the insulating layer.

Table 2 Energy (keV) Dosage (cm ^-2 ) WF (eV) I _on (A) I _off (A) I _on /I _off SS (mV/dec) DIBL (mV/V) 4.02 7.0×10 ¹³ 5.149 5.53×10 ^-5 1.01×10 ^-11 5.48×10 ⁷ 92.9 93.9 7.5×10 ¹³ 4.790 5.24×10 ^-5 1.50×10 ^-12 3.49×10 ⁷ 80.0 61.7 8.0×10 ¹³ 4.505 2.98×10 ^-5 1.16×10 ^-12 2.57×10 ⁷ 74.6 106.9 8.3×10 ¹³ 4.155 1.99×10 ^-5 5.33×10 ^-10 3.73×10 ⁴ 157.0 707.8 8.5×10 ¹³ 3.900 1.31×10 ^-5 2.02×10 ^-9 6.49×10 ³ 178.3 1546.9

From the results in Figure 3A, Figure 3B and Table 2, it can be seen that compared to the implantation dose (Dosage) of 7.0×10 ¹³ , 7.5×10 ¹³ , 8.3×10 ¹³ , 8.5×10 ¹³ cm ^-2 , the implantation dose is The silicon field effect transistor on the insulating layer at 8.0×10 ¹³ cm ^-2 has better device characteristics, that is, it has relatively low leakage current (I _off =1.16×10 ^-12 A) and relatively high current switching The ratio (I _on /I _off =2.57×10 ⁷ ), the smaller subcritical swing (SS=74.6 mV/dec), and the relatively small drain cause the energy barrier reduction effect (DIBL=106.9 mV/V).

In addition, in the parameters of the ion implantation procedure, the angle of ion implantation and the number of wafer rotations will also affect the position and shape of the implantation, which indirectly affects the electric field intensity distribution and channel electrostatic performance. Table 3 shows the simulation of the electrical characteristic parameters of the silicon field-effect transistor on the insulating layer with different ion implantation angles when the number of wafer rotations is 4 (indicating that the wafer will undergo ion implantation every 90 degrees) result. Table 4 shows the simulation results of the electrical characteristic parameters of the silicon field-effect transistor on the insulating layer with different ion implantation angles when the number of wafer rotations is 0.

Table 3 (The number of wafer rotations is 4) Dosage (cm ^-2 ) Energy (keV) Tilt (degree) WF (eV) I _on (A) I _off (A) I _on /I _off SS (mV/dec) DIBL (mV/V) 8.0×10 ¹³ 4.02 0 4.505 2.98 ×10 ^-5 1.16 ×10 ^-12 2.57 ×10 ⁷ 74.6 106.9 5.25 30 4.400 1.61 ×10 ^-5 1.37 ×10 ^-12 1.18 ×10 ⁷ 171.5 133.9 4 45 4.600 3.92 ×10 ^-5 2.03 ×10 ^-12 1.93 ×10 ⁷ 81.1 70.4 3.7 60 4.600 4.73 ×10 ^-5 2.15 ×10 ^-12 2.20 ×10 ⁷ 81.9 70.4

Table 4 (The number of wafer rotations is 0) Dosage (cm ^-2 ) Energy (keV) Tilt (degree) WF (eV) I _on (A) I _off (A) I _on /I _off SS (mV/dec) DIBL (mV/V) 8.0×10 ¹³ 4.02 0 4.591 3.76 ×10 ^-5 5.48 ×10 ^-13 3.86 ×10 ⁷ 73.3 74.7 7 30 4.463 3.22 ×10 ^-5 8.11 ×10 ^-13 3.97 ×10 ⁷ 73.2 116.5 8.5 45 4.612 4.97 ×10 ^-5 4.01 ×10 ^-13 1.24 ×10 ⁸ 72.9 54.7 9.5 60 4.600 4.91 ×10 ^-5 3.83 ×10 ^-13 1.28 ×10 ⁸ 72.5 54.7 9.8 65 4.362 2.80 ×10 ^-5 1.75 ×10 ^-13 1.60 ×10 ⁷ 85.1 96.5 13.5 75 4.610 6.07 ×10 ^-5 3.36 ×10 ^-13 1.81 ×10 ⁸ 72.5 54.7

From the results in Table 3 and Table 4, it can be seen that under the same implantation energy (4.02 keV), the field effect of silicon on the insulating layer when the number of wafer rotations is 0 compared to 4 wafer rotations Transistor has better component characteristics. In addition, when the number of wafer rotations is 0, although the angle is 0, 30, 45, 60, 65 degrees, the silicon field effect transistor on the insulating layer at the angle of 75 degrees has better components characteristic. However, in the simulation results (not shown) of the ion concentration distribution in the field-effect transistor of silicon on the insulating layer according to the angle of ion implantation, compared with the angle of 60 degrees, the ion implantation area at an angle of 75 degrees The shape is less complete. Therefore, according to the above simulation results, the parameters of the optimal ion implantation program are: the number of wafer rotations is 0, the angle is 60 degrees, and the energy is 9.5 keV. At this time, the silicon field effect transistor on the insulating layer has better device characteristics, that is, it has a lower leakage current (I _off =3.83×10 ^-13 A) and a higher current on-off ratio (I _on /I _off =1.28×10 ⁸ ), a smaller subcritical swing (SS=72.5 mV/dec), and a smaller drain cause the energy barrier reduction effect (DIBL=54.7 mV/V).

Then, in order to suppress the diffusion of ion implantation during annealing, nitrogen gas is added during annealing to slow down the diffusion of atoms. Therefore, among the parameters of the ion implantation program, the annealing temperature and annealing time will also affect the effect of ion implantation.

4A and FIG. 4B are the relationship diagrams of I _off , I _on /I _off , SS and DIBL of the silicon field effect transistor on the insulating layer at different annealing temperatures. 5A and FIG. 5B are the relationship diagrams of I _off , I _on /I _off , SS and DIBL of the silicon field effect transistor on the insulating layer with different annealing times. Table 5 shows the simulation results of the electrical characteristic parameters of the silicon field-effect transistor on the insulating layer at different annealing temperatures. Table 6 shows the simulation results of the electrical characteristic parameters of the silicon field effect transistor on the insulating layer with different annealing times.

Table 5 (The implantation dose is 8.0×10 ¹³ cm ^-2 and the implantation energy is 9.5 keV) Gas Tilt (degree) Temp. (°C) WF (eV) I _on (A) I _off (A) I _on /I _off SS (mV/dec) DIBL (mV/V) N ₂ 60 900 4.315 2.86 ×10 ^-5 4.77 ×10 ^-12 6.00 ×10 ⁶ 82.7 207.8 950 4.353 2.97 ×10 ^-5 2.46 ×10 ^-12 1.21 ×10 ⁷ 77.8 168.7 1000 4.456 3.52 ×10 ^-5 6.01 ×10 ^-13 5.86 ×10 ⁷ 72.5 87.8 1050 4.616 5.22 ×10 ^-5 3.93 ×10 ^-13 1.33 ×10 ⁸ 73.0 51.3 1100 4.911 7.13 ×10 ^-5 2.81 ×10 ^-12 2.54 ×10 ⁷ 84.5 64.3

Table 6 (The implantation dose is 8.0×10 ¹³ cm ^-2 , the implantation energy is 9.5 keV, and the annealing temperature is 1050℃) Gas Tilt (degree) Time (sec) WF (eV) I _on (A) I _off (A) I _on /I _off SS (mV/dec) DIBL (mV/V) N ₂ 60 5 4.616 5.22 ×10 ^-5 3.93 ×10 ^-13 1.33 ×10 ⁸ 73.0 51.3 10 4.775 6.67 ×10 ^-5 1.65 ×10 ^-13 4.04 ×10 ⁸ 78.6 54.8 30 5.128 6.96 ×10 ^-5 6.31 ×10 ^-12 1.10 ×10 ⁷ 90.2 80.9 60 5.369 6.48 ×10 ^-5 1.10 ×10 ^-11 5.89 ×10 ⁶ 94.3 96.5

From the results in Figure 4A, Figure 4B and Table 5, it can be seen that in a nitrogen annealing environment, compared to the annealing temperature of 900, 950, 1000, 1100 ℃, the annealing temperature of the silicon field effect transistor on the insulating layer at 1050 ℃ Have better component characteristics. Next, from the results in Figures 5A, 5B, and Table 6, it can be seen that in a nitrogen annealing environment at an annealing temperature of 1050°C, compared to the annealing time of 10, 30, and 60 seconds (sec), the annealing time is 5 seconds. The silicon field effect transistor on the insulating layer has better device characteristics. Therefore, when nitrogen is added during annealing and the annealing temperature is set to 1050 ^o C and the annealing time is 5 seconds, the best device characteristics are obtained, that is, it has relatively low leakage current (I _off =3.93×10 ^-13 A), Relatively high current switching ratio (I _on /I _off =1.33×10 ⁸ ), small subcritical swing (SS=73.0 mV/dec), and less drain lead to energy barrier reduction effect (DIBL=51.3 mV /V).

Based on the above, in this embodiment, the parameters of the ion implantation program can be, for example, implantation energy of 2 keV to 20 keV, implantation dose of 10 ¹² cm ^-2 to 10 ¹⁴ cm ^-2 , and angle of 0° to 60 The annealing temperature is 900 ℃ to 1100 ℃ and the annealing time is less than 60 seconds. Preferably, the parameters of the ion implantation procedure are implantation energy of 9.5 keV, implantation dose of 8×10 ¹³ cm ^-2 , angle of 60 degrees, annealing temperature of 1050° C. and annealing time of 5 seconds.

real Give example 2 : Compare the silicon field effect transistor on the insulating layer of this embodiment and the conventional Ultra-thin channel field effect transistor (UTBFET) , Boring field effect transistor (RCFET)

The following simulation analysis is performed using the 2016 version of Sentaurus TCAD (technology computer aided design) software. The component size structure follows the ITRS 90 nm node process blueprint specification. The channel length L2 used is 90 nm, the channel thickness t _ch is 10-25 nm, and the maximum gate and drain voltage is 1.2 V. Quantum confinement (QC) effect mode has been added to all TCAD simulation processes to fully reflect the special characteristics of nanostructures. In terms of electrical characteristics, for reasonable and fair comparison, the following example 1 (the field-effect transistor of silicon on the insulating layer of this example), comparative example 1 (UTBFET), comparative example 2 (UTBFET) and comparative example 3 ( The gate structure of the RCFET adopts a metal/SiO ₂ (t _ox =3 nm) structure. In the comparison of the transfer characteristic curve and the device characteristic parameters, the threshold voltage V _{th of} the four devices are adjusted to be as equal as possible by adjusting the gate metal work function WF, or the gate metal work functions of the four devices are all used Adjust the threshold voltage to make it as equal as possible.

Table 7 shows the structural parameters used in the simulation analysis of Example 1 (the field effect transistor of silicon on the insulating layer of this embodiment), Comparative Example 1 (UTBFET), Comparative Example 2 (UTBFET) and Comparative Example 3 (RCFET) .

Table 7 element L2 (nm) W (μm) t _ox (nm) t _ch (nm) N _A (cm ^-3 ) N _D (cm ^-3 ) Example 1 90 1 3 25 1×10 ¹⁹ 1×10 ¹⁹ Comparative example 1 25 Comparative example 2 10 Comparative example 3 10

Specifically, Example 1 is the silicon-on-insulating field effect transistor 100 of this embodiment, as shown in FIG. 1H. The silicon-on-insulation field effect transistor 100 includes a substrate 120, an ion implantation region 127, and a gate structure 140. The substrate 120 includes a P-type semiconductor base 122, an insulating layer 124, and an N-type semiconductor layer 126. The N-type semiconductor layer 126 is disposed on the insulating layer 124 and the P-type semiconductor substrate 122. The gate structure 140 (including the gate dielectric layer 142 and the gate electrode 144) is disposed on the N-type semiconductor layer 126. The ion implantation region 127 is disposed at the bottom of the semiconductor layer 126. In addition, the regions on the left and right sides of the semiconductor layer 126 that do not include the ion implantation region 127 are regarded as the source region 128 and the drain region 129. The semiconductor layer 126 under the gate structure 140 is regarded as a channel layer, and the channel layer has a channel length L2 of 90 nm, a channel width W of 1 μm, and a channel thickness t _ch of 25 nm. The gate dielectric layer 142 has a dielectric layer thickness _tox of 3 nm. The distance (effective channel thickness D) between the ion implantation area 127 and the semiconductor layer 126 is 10 nm, and the length L1 of the ion implantation area 127 is 120 nm.

Comparative Example 1 is an ultra-thin channel field effect transistor (UTBFET), as shown in FIG. 6A. The ultra-thin channel field effect transistor 200 includes a substrate 220 and a gate structure 240. The substrate 220 includes a P-type semiconductor base 222, an insulating layer 224, and an N-type semiconductor layer 226. The N-type semiconductor layer 226 is disposed on the insulating layer 224 and the P-type semiconductor substrate 222. The gate structure 240 (including the gate dielectric layer 242 and the gate electrode 244) is disposed on the N-type semiconductor layer 226. In addition, the regions on the left and right sides of the semiconductor layer 226 are regarded as the source region 228 and the drain region 229. The semiconductor layer 226 corresponding to the gate structure 240 is regarded as a channel layer, and the channel layer has a channel length L2 of 90 nm, a channel width W of 1 μm, and a channel thickness t _ch of 25 nm. The gate dielectric layer 242 has a dielectric layer thickness _tox of 3 nm.

Comparative example 2 is an ultra-thin channel field effect transistor. Similar to the ultra-thin channel field effect transistor 200 of Comparative Example 1, the difference between the two is: the channel thickness t _ch of the ultra-thin channel field effect transistor of Comparative Example 2 It is 10 nm.

Comparative example 3 is a boring field effect transistor (RCFET), as shown in FIG. 6B. The tunnel field effect transistor 300 includes a substrate 320 and a gate structure 340. The substrate 320 includes a P-type semiconductor base 322, an insulating layer 324, and an N-type semiconductor layer 326. The N-type semiconductor layer 326 is disposed on the insulating layer 324 and the P-type semiconductor substrate 322. The gate structure 340 (including the gate dielectric layer 342 and the gate electrode 344) is disposed on the N-type semiconductor layer 326. In addition, the regions on the left and right sides of the semiconductor layer 326 are regarded as the source region 328 and the drain region 329. The semiconductor layer 326 under the gate structure 340 is regarded as a channel layer, and the channel layer has a channel length L2 of 90 nm, a channel width W of 1 μm, and a channel thickness t _ch of 10 nm. The gate dielectric layer 342 has a dielectric layer thickness _tox of 3 nm.

FIG. 7A is a graph of the transfer characteristics of Example 1, Comparative Example 1, Comparative Example 2, and Comparative Example 3 under the same threshold voltage. FIG. 7B is a graph of the transfer characteristics of Example 1, Comparative Example 1, Comparative Example 2, and Comparative Example 3 under the same work function. 7C is a diagram showing the relationship between DIBL, SS, and I _on /I _off in Example 1, Comparative Example 2, and Comparative Example 3. Table 8 shows the simulation results of the electrical characteristic parameters of Example 1, Comparative Example 1, Comparative Example 2, and Comparative Example 3 under the same threshold voltage. Table 9 shows the simulation results of the electrical characteristic parameters of Example 1, Comparative Example 1, Comparative Example 2, and Comparative Example 3 under the same work function.

Table 8 (Critical voltage V _th =0.5 V) element t _ch (nm) I _on (A) I _off (A) I _on /I _off SS (mV/dec) DIBL (mV/V) Example 1 25 5.22×10 ^-5 3.93×10 ^-13 1.33×10 ⁸ 73.0 51.3 Comparative example 1 25 1.29×10 ^-3 1.10×10 ^-3 1.17 - - Comparative example 2 10 8.60×10 ^-5 1.20×10 ^-11 7.17×10 ⁶ 76.9 45.2 Comparative example 3 10 1.36×10 ^-5 1.21×10 ^-11 1.12×10 ⁶ 78.6 45.2

Table 9 (Work function WF=5.1 eV (Au)) element t _ch (nm) Vth (V) I _on (A) I _off (A) I _on /I _off SS (mV/dec) DIBL (mV/V) Example 1 25 0.98 1.09×10 ^-5 1.84×10 ^-15 5.92×10 ⁹ 73.1 51.3 Comparative example 1 25 - 1.21×10 ^-3 1.03×10 ^-3 1.17 - - Comparative example 2 10 -0.76 3.87×10 ^-4 9.84×10 ^-5 3.93 547.4 53.0 Comparative example 3 10 -0.78 4.02×10 ^-4 1.05×10 ^-4 3.83 552.4 44.3

From the results of FIGS. 7A to 7C, Table 8 and Table 9, it can be seen that compared to Comparative Example 1, Comparative Example 2, and Comparative Example 3, Example 1 has better device characteristics. In other words, Example 1 has a good on-current (I _on =5.22×10 ^-5 A), a relatively low leakage current (I _off =3.93×10 ^-13 A), and a very high current on-off ratio (I _on / I _off =1.33×10 ⁸ A), a smaller subcritical swing (SS=73.0 mV/dec) and a smaller drain lead to an energy barrier reduction effect (DIBL=51.3 mV/V).

In addition, according to the simulation results of leakage current distribution (not shown), it can be seen that when the device is turned off (V _GS =0 and V _DS =1.2 V), Comparative Example 1 provides a larger leakage current conduction space (leakage current). The thickness of the current distribution area is about 25 nm), so it has a large leakage current (1.10×10 ^-3 A) and cannot be turned off. Conversely, because Example 1 can block the leakage current conduction area by its ion implantation area, it has a lower leakage current (3.93×10 ^-13 A), and its value is 9 lower than that of Comparative Example 1. The order obviously has the effect of reducing the leakage current.

It is worth noting that in the field-effect transistor of silicon on the insulating layer of the present embodiment, the ion implantation procedure and the optimized ion implantation procedure parameters are used to form an ion implantation area at the bottom of the channel layer, thereby The thickness of the channel layer is thinned, and the silicon field-effect transistor on the insulating layer of this embodiment can improve gate control, reduce leakage current, reduce subcritical swing (SS), and reduce drain-induced energy barrier reduction (drain induced barrier lowering, DIBL) effect. In other words, by forming an ion implantation area (thinning the thickness of the channel layer) at the bottom of the channel layer, the technology node (device characteristics) of the silicon field-effect transistor on the insulating layer of this embodiment can be greatly improved from 90nm to 28nm.

In summary, in the field-effect transistor of silicon on the insulating layer and its manufacturing method of the present invention, the semiconductor layer (channel layer) is thinned by forming an ion implantation area at the bottom of the semiconductor layer (channel layer) The thickness, in turn, enables the silicon-on-insulating field-effect transistor of the present invention to improve gate control, reduce leakage current, reduce subcritical swing, and reduce the energy barrier reduction effect caused by drain.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: field effect transistors of silicon on the insulating layer 120, 220, 320: substrate 122, 222, 322: semiconductor substrate 124, 224, 324: insulating layer 126, 226, 326: semiconductor layer 126a: first surface 126b: first Second surface 127: ion implantation area 128, 228, 328: source area 129, 229, 329: drain area 130, 131: photoresist pattern 140, 240, 340: gate structure 141: dielectric layer 142, 242 , 342: gate dielectric layer 143: gate material layer 144, 244, 344: gate 150: spacer material 151: spacer 200: ultra-thin channel field effect transistor 300: tunnel field effect transistor D: effective Channel thickness I: ion implantation program L1: length L2: channel length t _ch : channel thickness t _ox : dielectric layer thickness W: channel width

1A to 1G are schematic cross-sectional views showing a manufacturing process of a silicon-on-insulating field effect transistor according to an embodiment of the invention. Fig. 1H is a schematic perspective view of Fig. 1G. 2A and FIG. 2B are diagrams showing the relationship between different implantation energy and the transfer characteristics of silicon field effect transistors on the insulating layer, SS and DIBL, respectively. 3A and 3B are the relationship diagrams of the transfer characteristics, SS and DIBL of silicon field effect transistors on the insulating layer with different implant doses. 4A and FIG. 4B are the relationship diagrams of I _off , I _on /I _off , SS and DIBL of the silicon field effect transistor on the insulating layer at different annealing temperatures. 5A and FIG. 5B are the relationship diagrams of I _off , I _on /I _off , SS and DIBL of the silicon field effect transistor on the insulating layer with different annealing times. 6A is a three-dimensional schematic diagram of an ultra-thin channel field effect transistor (UTBFET) of Comparative Example 1. FIG. 6B is a three-dimensional schematic diagram of the RCFET of Comparative Example 3. FIG. FIG. 7A is a graph of the transfer characteristics of Example 1, Comparative Example 1, Comparative Example 2, and Comparative Example 3 under the same threshold voltage. FIG. 7B is a graph of the transfer characteristics of Example 1, Comparative Example 1, Comparative Example 2, and Comparative Example 3 under the same work function. 7C is a diagram showing the relationship between DIBL, SS, and I _on /I _off in Example 1, Comparative Example 2, and Comparative Example 3.

100: Field effect transistor of silicon on the insulating layer

120: substrate

122: Semiconductor substrate

124: Insulation layer

126: Semiconductor layer

126a: first surface

126b: second surface

127: Ion implantation area

128: source region

129: Drain Area

140: gate structure

142: Gate Dielectric Layer

144: Gate

151: Clearance Wall

D: Effective channel thickness

L1: length

Claims (14)

A field effect transistor of silicon on an insulating layer, comprising: A substrate, including: A semiconductor substrate having a first conductivity type; An insulating layer disposed on the semiconductor substrate; and A semiconductor layer, disposed on the insulating layer, having a second conductivity type, a first surface, and a second surface opposite to the first surface, wherein the first conductivity type is different from the second conductivity type; An ion implantation area disposed at the bottom of the semiconductor layer and having the first conductivity type; and A gate structure is arranged on the first surface of the semiconductor layer, and includes a gate dielectric layer and a gate electrode, wherein the gate electrode is arranged on the gate dielectric layer. The field-effect transistor of silicon on the insulating layer according to claim 1, wherein there is a distance between the ion implantation area and the first surface of the semiconductor layer, and the distance is 1.5 nm to 10 nm . The field-effect transistor of silicon-on-insulating layer described in claim 1, wherein the orthographic projection of the gate structure on the semiconductor substrate overlaps the orthographic projection of the ion implantation area on the semiconductor substrate. The silicon-on-insulating field-effect transistor described in claim 3, wherein the orthographic area of the gate structure on the semiconductor substrate is less than or equal to the orthographic area of the ion implantation area on the semiconductor substrate . The field effect transistor of silicon on the insulating layer according to the first item of the scope of patent application, wherein the ion implantation region is in contact with the insulating layer and is aligned with the second surface of the semiconductor layer. In the field effect transistor of silicon on the insulating layer as described in item 1 of the scope of patent application, the length of the ion implantation region is 10 nm to 140 nm. According to the first item of the scope of patent application, the silicon-on-insulating field effect transistor, wherein the semiconductor layer and the semiconductor substrate are respectively located on opposite sides of the insulating layer. A method for manufacturing a silicon field-effect transistor on an insulating layer includes: A substrate is provided, and the substrate includes: A semiconductor substrate having a first conductivity type; An insulating layer disposed on the semiconductor substrate; and A semiconductor layer, disposed on the insulating layer, having a second conductivity type, a first surface, and a second surface opposite to the first surface, wherein the first conductivity type is different from the second conductivity type; Forming an ion implantation area at the bottom of the semiconductor layer, the ion implantation area having the first conductivity type; and A gate structure is formed on the first surface of the semiconductor layer, the gate structure includes a gate dielectric layer and a gate, and the gate is disposed on the gate dielectric layer. According to the method for manufacturing a field-effect transistor of silicon on an insulating layer as described in item 8 of the scope of patent application, the step of forming the ion implantation region at the bottom of the semiconductor layer includes: Forming a photoresist pattern on the semiconductor layer of the substrate; Performing an ion implantation process on the part of the semiconductor layer exposed by the photoresist pattern; and Remove the photoresist pattern. As described in item 9 of the scope of patent application, the method for manufacturing a field-effect transistor of silicon on an insulating layer, wherein the parameters of the ion implantation procedure include: implantation energy of 2 keV to 20 keV, implantation dose of 10 ¹² cm ^-2 to 10 ¹⁴ cm ^-2 , the angle is 0 degrees to 60 degrees, the annealing temperature is 900 ℃ to 1100 ℃, and the annealing time is less than 60 seconds. The method of manufacturing a field effect transistor is of the silicon on the insulating layer of the range as defined in claim 9, wherein the parameters of the ion implantation process comprising: implanting energy of 9.5 keV, implantation dose of 8 × 10 ¹³ cm ^{- 2. The} angle is 60 degrees, the annealing temperature is 1050 ℃, and the annealing time is 5 seconds. According to item 8 of the scope of patent application, the method for manufacturing a field-effect transistor of silicon on an insulating layer, wherein the implanted impurity in the ion implantation area is boron, aluminum, gallium, phosphorus, arsenic, antimony, oxygen or nitrogen. The method for manufacturing a field-effect transistor of silicon on an insulating layer as described in claim 8, wherein the step of forming the gate structure on the first surface of the semiconductor layer includes: Sequentially forming a dielectric layer and a gate material layer on the semiconductor layer of the substrate; Forming a photoresist pattern on the gate material layer; and Removing a part of the gate material layer exposed by the photoresist pattern and a part of the dielectric layer under the photoresist pattern to form the gate and the gate dielectric layer. As described in item 13 of the scope of patent application, the method for manufacturing a field-effect transistor of silicon on an insulating layer also includes: Forming a spacer material on the substrate to cover the semiconductor layer, the photoresist pattern, the sidewall of the gate electrode and the sidewall of the gate dielectric layer; and Remove part of the spacer material and the photoresist pattern to form a spacer.

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