CN107591327B - Method for forming fin field effect transistor - Google Patents
Method for forming fin field effect transistor Download PDFInfo
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- CN107591327B CN107591327B CN201610527809.9A CN201610527809A CN107591327B CN 107591327 B CN107591327 B CN 107591327B CN 201610527809 A CN201610527809 A CN 201610527809A CN 107591327 B CN107591327 B CN 107591327B
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Abstract
A method for forming a fin field effect transistor comprises the following steps: forming N-region mask side walls on the side walls of the fin parts of the NMOS region; forming a supporting layer close to the side wall of the mask side wall of the N region on the isolation structure; etching to remove fin parts with partial thicknesses on two sides of the NMOS region grid electrode structure, and enclosing the etched fin parts of the NMOS region and the N region mask side wall to form an N region groove; after the N-region groove is formed, removing the supporting layer; and forming an N-type doped epitaxial layer which fills the N-region groove. The supporting layer plays a role in supporting the N-region mask side wall, and the N-region mask side wall is prevented from collapsing, so that the performance of the formed fin field effect transistor is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a fin field effect transistor.
Background
With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following moore's law is continuously reduced. To accommodate the reduction in process nodes, the channel length of MOSFET fets has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip, increasing the switching speed of the MOSFET field effect transistor and the like.
However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage pinch-off (ping off) channel is increased, and the sub-threshold leakage (SCE) phenomenon, i.e. the so-called short-channel effect (SCE) is more likely to occur.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar MOSFET transistors to three-dimensional transistors with higher performance, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, the control capability of the gate on a channel is much stronger than that of a planar MOSFET device, and the short channel effect can be well inhibited; and compared with other devices, the FinFET has better compatibility of the existing integrated circuit manufacturing technology.
However, the performance of the finfet formed by the prior art needs to be further improved.
Disclosure of Invention
The invention aims to provide a method for forming a fin field effect transistor, which improves the performance of the formed fin field effect transistor.
In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, including: providing a substrate comprising an NMOS region, wherein the substrate is provided with a protruding fin part, an isolation structure covering the side wall of the fin part is arranged on the substrate, and the top of the isolation structure is lower than the top of the fin part; forming a grid electrode structure on the NMOS region isolation structure, wherein the grid electrode structure stretches across the fin part and covers partial top and side walls of the fin part; forming N-region mask side walls on the side walls of the fin parts of the NMOS region; forming a supporting layer next to the N-region mask side wall on the isolation structure; etching to remove fin parts with partial thicknesses on two sides of the NMOS region grid electrode structure, and enclosing the etched fin parts of the NMOS region and the N region mask side wall to form an N region groove; after the N-region groove is formed, removing the supporting layer; and forming an N-type doped epitaxial layer which fills the N-region groove.
Optionally, before the N-region groove is formed, the top of the support layer is flush with the top of the N-region mask sidewall.
Optionally, the top of the support layer is higher than the bottom of the N-region groove.
Optionally, the distance between the top of the support layer and the bottom of the N-region groove is greater than or equal to 5 angstroms.
Optionally, the material of the support layer includes an ODL material, a BARC material, or a DUO material.
Optionally, before forming the N-type doped epitaxial layer, thinning the N-region mask sidewall on the fin sidewall, where the thinning is suitable for increasing the width of the N-region groove.
Optionally, before the thinning process, the support layer is removed.
Optionally, after the N-type doped epitaxial layer is formed, the support layer is removed.
Optionally, the N-type doped epitaxial layer is made of SiP or SiCP; and forming the N-type doped epitaxial layer by adopting an in-situ doped selective epitaxial process.
Optionally, the formed N-region mask sidewall is further located on the isolation structure and on the top of the fin portion in the NMOS region; and before etching and removing the fin parts with partial thicknesses at two sides of the gate structure of the NMOS region, etching and removing the N region mask side walls at the tops of the fin parts at two sides of the gate structure of the NMOS region.
Optionally, the process step of forming the N region mask sidewall includes: forming N-region mask side walls on the top and the side walls of the fin part of the NMOS region and on the isolation structure; and etching and removing the N-region mask side wall on the top of the NMOS region fin part and part of the isolation structure by using a maskless etching process.
Optionally, the substrate further includes a PMOS region, and the PMOS region has a fin portion on the substrate; a grid structure is formed on the isolation structure of the PMOS region, crosses the fin part of the PMOS region and covers part of the top and the side wall of the fin part; the forming method further includes: forming a P area mask side wall on the side wall of the fin part of the PMOS area; etching to remove fin parts with the first thickness positioned on two sides of the grid electrode structure of the PMOS region, etching to remove the mask side wall of the P region with the first thickness, and forming a groove of the P region in the etched fin parts of the PMOS region; and forming a P-type doped epitaxial layer filling the P-region groove.
Optionally, the P region mask sidewall is further located on the isolation structure and on the top of the fin portion in the PMOS region; and before etching and removing the fin parts with the first thickness at the two sides of the grid electrode structure of the PMOS region, etching and removing the P region mask side walls at the tops of the fin parts at the two sides of the grid electrode structure of the PMOS region.
Optionally, the P-region groove is formed first, and then the N-region groove is formed; the process steps for forming the P area mask side wall, the P area groove, the N area mask side wall and the N area groove comprise: forming a P area mask side wall on the fin part side wall of the PMOS area, wherein the P area mask side wall is also positioned on the fin part side wall of the NMOS area; etching and removing the fin part with the first thickness in the PMOS region and the P region mask side wall with the first thickness on the fin part side wall to form the P region groove; forming a P-type doped epitaxial layer filling the P-region groove; after the P-type doped epitaxial layer is formed, reserving a P-region mask side wall positioned in the NMOS region as an N-region mask side wall; and forming the supporting layer, the N-region groove and the N-type doped epitaxial layer.
Optionally, before forming the P-region groove, forming a first pattern layer on the NMOS region fin and the P-region mask sidewall; when the P area mask side wall is also positioned on the top of the NMOS area fin part, removing the first graphic layer before or after forming the P type doped epitaxial layer; and when the P region mask side wall exposes the top of the NMOS region fin part, removing the first graphic layer after the P type doped epitaxial layer is formed.
Optionally, after the P-type doped epitaxial layer is formed and before the support layer is formed, a first mask sidewall is formed on the P-region mask sidewall of the NMOS region, and the P-region mask sidewall and the first mask sidewall in the NMOS region are used as the N-region mask sidewall.
Optionally, the process step of forming the support layer includes: forming a support film on the N-region mask side wall, wherein the support film is also positioned on the P-type doped epitaxial layer and the isolation structure; forming a second graphic layer on the support film of the PMOS region; and etching and removing the support film with partial thickness in the NMOS area by taking the second pattern layer as a mask, wherein the support film etched in the NMOS area is taken as the support layer.
Optionally, the top of the support film is flush with the top of the P-type doped epitaxial layer; or the top of the support film is higher than the P-type doped epitaxial layer.
Optionally, with the second pattern layer as a mask, etching the fin portions with partial thickness on two sides of the gate structure of the NMOS region to form the N-region groove; and in the process step of removing the support layer, removing the second graphic layer and the support film of the PMOS region.
Optionally, the N-region groove is formed first, and then the P-region groove is formed.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme of the forming method of the fin field effect transistor, after N-region mask side walls are formed on the side walls of the fins of an NMOS region and before N-region grooves are formed by etching the fins of the NMOS region, a supporting layer close to the N-region mask side walls is formed on an isolation structure, and the supporting layer plays a supporting role in supporting the N-region mask side walls; particularly, in the process of removing the fin parts with the thicknesses of the two sides of the gate structure of the NMOS region by etching, the N region mask side wall higher than the N region groove loses the supporting function of the fin parts, but the supporting layer can still support the N region mask side wall, so that the N region mask side wall is prevented from collapsing in the process of forming the N region groove, and the appearance of the formed N region groove meets the process requirements. Therefore, the N-type doped epitaxial layer formed in the N-region groove has good performance, so that the electrical performance of the formed fin field effect transistor is improved.
In an alternative scheme, the N-region mask side wall is further subjected to thinning treatment to increase the width size of the N-region groove, so that the volume of the N-region groove is increased, the volume of an N-type doped epitaxial layer formed in the N-region groove is correspondingly increased, the surface area of the top of the N-type doped epitaxial layer is increased, the contact resistance between the surface of the formed N-type doped epitaxial layer and metal silicide is reduced, and the performance of the formed fin field effect transistor is improved.
In an alternative scheme, before the thinning treatment, the supporting layer is removed, and the N-region mask side wall is ensured to have a relatively large thickness size when the supporting layer is removed, so that the N-region mask side wall has relatively strong mechanical strength in the process of removing the supporting layer, and the N-region mask side wall is prevented from collapsing in the technological process of removing the supporting layer.
Drawings
Fig. 1 to 17 are schematic structural diagrams of a finfet formation process according to an embodiment of the present invention.
Detailed Description
As known from the background art, the performance of the finfet formed in the prior art needs to be further improved, and particularly, the electrical performance of the NMOS finfet is poor.
Through analysis, the forming process of the NMOS fin field effect transistor comprises the following steps: forming a mask side wall on the side wall of the fin part in the NMOS region; etching to remove fin parts with partial thicknesses on two sides of the gate structure of the NMOS region, and forming N-region grooves in the fin parts of the NMOS region; and forming an N-type doped epitaxial layer filling the N-region groove. In order to limit the appearance and the volume of the formed N-region doped epitaxial layer, when fin parts with partial thicknesses on two sides of a gate structure of an NMOS region are removed by etching, mask side walls on the side walls of the fin parts are reserved, so that two opposite side walls of a formed N-region groove are mask side walls; in the process of forming the N-type doped epitaxial layer, the mask side wall plays a role in limiting the growth of the N-type doped layer.
However, in the process of forming the N-region groove by etching, the mask sidewall on the sidewall of the fin portion in the NMOS region is prone to collapse or tilt, which results in poor electrical properties of the formed fin field effect transistor.
In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, including: providing a substrate comprising an NMOS region, wherein the substrate is provided with a protruding fin part, an isolation structure covering the side wall of the fin part is arranged on the substrate, and the top of the isolation structure is lower than the top of the fin part; forming a grid electrode structure on the NMOS region isolation structure, wherein the grid electrode structure stretches across the fin part and covers partial top and side walls of the fin part; forming N-region mask side walls on the side walls of the fin parts of the NMOS region; forming a supporting layer next to the N-region mask side wall on the isolation structure; etching to remove fin parts with partial thicknesses on two sides of the NMOS region grid electrode structure, and enclosing the etched fin parts of the NMOS region and the N region mask side wall to form an N region groove; after the N-region groove is formed, removing the supporting layer; and forming an N-type doped epitaxial layer which fills the N-region groove.
The invention avoids or reduces the probability of collapse of the side wall of the mask, thereby improving the electrical performance of the formed fin field effect transistor.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 17 are schematic structural diagrams of a finfet formation process according to an embodiment of the present invention.
Referring to fig. 1 and 2, fig. 1 is a schematic perspective view, and fig. 2 is a schematic cross-sectional view taken along a cutting line AA1 in fig. 1, providing a substrate 101 including an NMOS region II, wherein the substrate 101 has a protruding fin 102 thereon, and the substrate 101 has an isolation structure 103 covering sidewalls of the fin 102, and a top of the isolation structure 103 is lower than a top of the fin 102.
In this embodiment, taking the formed finfet as a CMOS device as an example, the substrate 101 further includes a PMOS region I, and discrete fin portions 102 are formed on the substrate 101 in both the PMOS region I and the NMOS region II. In other embodiments, when the finfet is formed to include only NMOS devices, the substrate includes only NMOS regions.
The substrate 101 is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate 101 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the material of the fin 102 includes silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 101 is a silicon substrate, and the fin portion 102 is made of silicon.
In this embodiment, the process steps for forming the substrate 101 and the fin portion 102 include: providing an initial substrate; forming a graphical hard mask layer on the surface of the initial substrate; and etching the initial substrate by taking the hard mask layer as a mask, wherein the etched initial substrate is taken as the substrate 101, and the protrusion on the surface of the substrate 101 is taken as the fin part 102.
The isolation structure 103 covers a portion of the sidewall surface of the fin 102, and the top of the isolation structure 103 is lower than the top of the fin 102. The isolation structure 103 serves to electrically isolate the adjacent fins 102, and the isolation structure 103 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride. In this embodiment, the isolation structure 103 is made of silicon oxide.
Referring to fig. 3, a gate structure 110 is formed on the NMOS region II isolation structure 103, and the gate structure 110 crosses over the fin 102 and covers a portion of the top and sidewalls of the fin 102.
In this embodiment, the isolation structures 103 in the NMOS region II and the PMOS region I are both formed with gate structures 110. Specifically, the gate structure 110 of the PMOS region I is located on the surface of the partial isolation structure 103 of the PMOS region I, crosses the PMOS region I fin portion 102, and covers the partial top surface and the sidewall surface of the PMOS region I fin portion 102; the gate structure 110 of the NMOS region II is located on the surface of the isolation structure 103 of the NMOS region II, and crosses over the NMOS region II fin 102, and also covers a portion of the top surface and the sidewall surface of the NMOS region II fin 102.
In this embodiment, the gate structure 110 is a dummy gate structure (dummy gate), the dummy gate structure 110 is subsequently removed, and then a metal gate structure of a semiconductor device is formed again at the position of the gate structure 110, where the gate structure 110 is a single-layer structure or a stacked-layer structure, the gate structure 110 includes a dummy gate layer, or the gate structure 110 includes a dummy oxide layer and a dummy gate layer located on the surface of the dummy oxide layer, where the dummy gate layer is made of polysilicon or amorphous carbon, and the dummy oxide layer is made of silicon oxide or silicon oxynitride.
In other embodiments, the gate structure can also be a metal gate structure of a semiconductor device, and the gate structure includes a gate dielectric layer and a gate electrode layer located on the surface of the gate dielectric layer, where the gate dielectric layer is made of silicon oxide or a high-k gate dielectric material, the gate electrode layer is made of polysilicon or a metal material, and the metal material includes one or more of Ti, Ta, TiN, TaN, TiAl, TiAlN, Cu, Al, W, Ag, or Au.
In this embodiment, the process steps for forming the gate structure 110 include: forming a pseudo gate film on the isolation structure 103, wherein the pseudo gate film crosses over the fin portion 102 and covers the top surface and the sidewall surface of the fin portion 102; forming a hard mask layer 104 on the surface of the pseudo gate film, wherein the hard mask layer 104 defines a pattern of a gate structure 110 to be formed; and patterning the pseudo gate film by taking the hard mask layer 104 as a mask, forming a gate structure 110 on the surface of the PMOS region I isolation structure 103, and forming the gate structure 110 on the surface of the NMOS region II isolation structure 103.
In this embodiment, the hard mask layer 104 on the top surface of the gate structure 110 is retained, so that the hard mask layer 104 plays a role in protecting the top of the gate structure 110 in the subsequent process. The hard mask layer 104 is made of silicon nitride, silicon oxynitride, silicon carbide or boron nitride.
After the gate structure 110 is formed, a step of forming offset spacers (offset spacers) on the sidewall surfaces of the gate structure 110 is further included; forming P-type source-drain lightly doped regions in the fin portions 102 on two sides of the gate structure 110 of the PMOS region I by taking the offset side walls of the PMOS region I as masks; and forming N-type source-drain lightly doped regions in the fin portions 102 on two sides of the gate structure 110 of the NMOS region II by taking the offset side walls of the NMOS region II as masks.
The subsequent process steps further comprise: forming a P area mask side wall on the side wall of the fin part of the PMOS area; etching to remove fin parts with the first thickness positioned on two sides of the grid electrode structure of the PMOS region, etching to remove the mask side wall of the P region with the first thickness, and forming a groove of the P region in the etched fin parts of the PMOS region; forming a P-type doped epitaxial layer filling the P-region groove; forming N-region mask side walls on the side walls of the fin parts of the NMOS region; forming a supporting layer next to the N-region mask side wall on the isolation structure; etching to remove fin parts with partial thicknesses on two sides of the NMOS region grid electrode structure, and enclosing the etched fin parts of the NMOS region and the N region mask side wall to form an N region groove; after the N-region groove is formed, removing the supporting layer; and forming an N-type doped epitaxial layer which fills the N-region groove.
In this embodiment, the following description will take the example of forming the P-region recess and the P-type doped epitaxial layer first and then forming the N-region recess and the N-type doped epitaxial layer as an example.
Referring to fig. 4 and 5, fig. 4 is a schematic structural view based on fig. 3, fig. 5 is a schematic structural view based on a schematic sectional structure along a cutting line BB1 in fig. 1, and AA1 and BB1 are parallel to each other, a P-region mask sidewall 106 is formed on the sidewall of the fin 102 in the PMOS region I, and the P-region mask sidewall 106 is also located on the sidewall of the fin 102 in the NMOS region II.
In this embodiment, the P-region mask sidewall 106 is formed by a deposition process, thereby reducing the number of etching process steps. The P-region mask sidewall spacers 106 are also located on the tops of the PMOS region I fin portions 102 and the tops of the NMOS region II fin portions 102; the P-region mask spacers 106 are also located on the top and sidewalls of the gate structure 110 in the PMOS region I and the top and sidewalls of the gate structure 110 in the NMOS region II, and the P-region mask spacers 106 are also located on the isolation structure 103. The P-region mask sidewall 106 is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the P-region mask sidewall 106 is formed by an atomic layer deposition process.
The functions of the P-region mask sidewall spacers 106 include: when the fin portion 102 with the first thickness in the PMOS region I is etched subsequently, the P region mask sidewall 106 on the sidewall of the fin portion 102 in the PMOS region I is used as a mask, so that a certain distance is formed between the subsequently formed second groove and the formed P type source drain lightly doped region, and the P type source drain lightly doped region is prevented from being completely etched and removed; moreover, the P region mask sidewall 106 on the sidewall of the I fin portion 102 in the PMOS region can protect the sidewall of the fin portion 102, and can also avoid a subsequent epitaxial growth process on the sidewall of the I fin portion 102 in the PMOS region; in addition, the P-region mask sidewall spacers 106 located in the NMOS region II will subsequently be used as part of the N-region mask sidewall spacers.
The P region mask sidewall 1066 is made of silicon nitride, silicon oxide, boron nitride or silicon oxynitride. The material of the P-region mask sidewall 106 is different from that of the fin portion 102, and the material of the P-region mask sidewall 106 is different from that of the isolation structure 103. In this embodiment, the P-region mask sidewall 106 is made of silicon nitride, and the thickness of the P-region mask sidewall 106 is 3nm to 6 nm.
It should be further noted that, in other embodiments, the P region mask sidewall may also be located only on the PMOS region fin sidewall, the NMOS region fin sidewall, and the gate structure sidewall; correspondingly, the process for forming the P area mask side wall comprises the following steps: forming P area mask side walls on the top and the side walls of the PMOS area fin portion, the top and the side walls of the NMOS area fin portion, the isolation structure, the top and the side walls of the grid structure; and etching and removing the P region mask side walls on the top of the PMOS region fin part, the top of the NMOS region fin part, the top of the grid structure and part of the isolation structure by adopting a maskless etching process.
Referring to fig. 6 and 7 in combination, fig. 6 is a schematic diagram based on fig. 5, and fig. 7 is a schematic diagram based on a schematic cross-sectional structure along a cutting line CC1 in fig. 1, the fin 102 of the PMOS region I with the first thickness and the P-region mask sidewall 106 of the first thickness on the sidewall of the fin 102 are removed by etching, and a P-region recess 202 is formed in the etched PMOS region I of the fin 102.
In this embodiment, the P region mask sidewall 106 is also located on the isolation structure 103 and on the top of the I fin portion 102 of the PMOS region; and before the fins 102 with the first thickness on the two sides of the PMOS region I-gate structure 110 are etched and removed, the P region mask side walls on the tops of the fins 102 on the two sides of the PMOS region I-gate structure 110 are etched and removed.
Before etching the P-region mask side walls 106 on the tops of the fins 102 on the two sides of the PMOS region I gate structure 110, a first pattern layer 107 is formed on the NMOS region II, and the first pattern layer 107 covers the P-region mask side walls 106 of the NMOS region II. The first pattern layer 107 plays a role in protecting the P region mask sidewall 106 of the NMOS region II, and the first pattern layer 107 may also cover an area not to be etched in the PMOS region I.
In this embodiment, the first pattern layer 107 is made of a photoresist material. After the P-region groove 202 is formed, the first pattern layer 107 is removed, and the first pattern layer 107 is removed by a wet photoresist removal or ashing process.
It should be further noted that, in other embodiments, when the P-region mask sidewall exposes the top of the fin portion in the NMOS region, the first pattern layer is removed after the P-type doped epitaxial layer is formed subsequently, so as to prevent a thin film from epitaxially growing on the top of the fin portion in the NMOS region during a subsequent process for forming the P-type doped epitaxial layer. When the P-region mask side wall is positioned at the top of the NMOS region fin portion, the first pattern layer can be removed after a P-type doped epitaxial layer is formed in the subsequent process.
And etching and removing the P-region mask side walls 106 on the tops of the fins 102 on the two sides of the PMOS region I-gate structure 110 by using a dry etching process, and also etching and removing the P-region mask side walls 106 on the tops of the fins 120 on the two sides of the PMOS region I-gate structure 110 and on part of the isolation structure 103 in the process of etching and removing the P-region mask side walls 106 on the tops of the PMOS region I-gate structure 110. In addition, in the embodiment, in the process of removing the fin portion 102 with the first thickness in the PMOS region I by etching, the P region mask sidewall 106 on the sidewall of the fin portion 102 in the PMOS region I is also removed by etching, so that the remaining P region mask sidewall 106 on the sidewall of the fin portion 102 in the PMOS region I is flush with the top of the etched fin portion 102.
In this embodiment, while the PMOS region I-fin 102 with the first thickness is etched and removed, the P region mask sidewall 106 on the sidewall of the fin 102 with the first thickness is also etched and removed, and the advantages include: since the P region mask sidewall 106 on the sidewall of the P region groove 202 is removed, when a P-type doped epitaxial layer is formed in the P region groove 106 subsequently, the growth of the P-type doped epitaxial layer is less limited, so that the formed P-type doped epitaxial layer has a larger volume.
In this embodiment, the fin portion 102 with the first thickness in the PMOS region I is removed by etching using an anisotropic etching process, where the anisotropic etching process is reactive ion etching, and the process parameters of the reactive ion etching process are as follows: the reaction gas comprises CF4、SF6And Ar, CF4The flow rate is 50sccm to 100sccm, SF6The flow rate is 10sccm to 100sccm, the flow rate of Ar is 100sccm to 300sccm, the source power is 50 watts to 1000 watts, the bias power is 50 watts to 250 watts, the chamber pressure is 50 mTorr to 200 mTorr, and the chamber temperature is 20 ℃ to 90 ℃.
In addition, it should be noted that, in other embodiments, the P region mask sidewall on the fin sidewall with the first thickness removed by etching may also be retained.
As illustrated in particular, the schematic diagrams provided subsequently are all structural schematic diagrams based on fig. 6.
Referring to fig. 8, a P-type doped epitaxial layer 212 is formed to fill the P-region recess 202 (see fig. 6).
Forming the P-type doped epitaxial layer 212 by using a selective epitaxial process; the P-type doped epitaxial layer 212 is made of P-type doped Si or SiGe. In this embodiment, a stress layer is formed in the P-type doped epitaxial layer 212, and the stress layer provides a compressive stress effect for the channel region of the PMOS region I, so as to improve the carrier mobility of the PMOS region II. The top of the P-doped epitaxial layer 212 is higher than the top of the P-region recess 202.
In this embodiment, the stress layer is formed by a selective epitaxy process, and the P-type doped epitaxial layer 212 is formed by in-situ self-doping P-type ions in the process of forming the stress layer. In other embodiments, after the stress layer is formed, P-type ions may be doped into the stress layer to form the P-type doped epitaxial layer 212.
In this embodiment, the top of the P-type doped epitaxial layer 212 is higher than the top of the P-region groove 202, and due to the characteristics of the selective epitaxy process, the surface of the sidewall of the P-type doped epitaxial layer 212 higher than the P-region groove 202 has a top angle protruding in a direction away from the fin 102. In other embodiments, the top of the P-type source/drain doped region may be flush with the top of the P-region groove.
In order to avoid process damage to the surface of the P-type doped epitaxial layer 212 caused by a subsequent process, after the P-type doped epitaxial layer 212 is formed and before a subsequent N-region mask sidewall is formed, oxidation treatment may be performed on the surface of the P-type doped epitaxial layer 212, and an oxidation protection layer (not shown) is formed on the surface of the P-type doped epitaxial layer 212, where the oxidation treatment is dry oxygen oxidation, wet oxygen oxidation, or water vapor oxidation.
In this embodiment, after the P-type doped epitaxial layer 212 is formed, the P-region mask sidewall 106 located in the NMOS region II is reserved as an N-region mask sidewall. The P-region mask sidewall 106 located in the NMOS region II may be used as an N-region mask sidewall alone; or, a first mask side wall may be further formed on the P-region mask side wall 106 of the NMOS region II, so that the P-region mask side wall 106 of the NMOS region II and the first mask side wall are jointly used as an N-region mask side wall, and the thickness of the formed N-region mask side wall is relatively thick, thereby reducing or avoiding the risk of collapse of the N-region mask side wall when the N-region mask side wall is subsequently thinned. The following detailed description will be made in conjunction with the accompanying drawings.
Referring to fig. 9, N-region mask spacers are formed on the sidewalls of the fin 102 in the NMOS region II.
Specifically, in this embodiment, the first mask sidewall 108 is formed on the P-region mask sidewall 106 of the NMOS region II, and the P-region mask sidewall 106 and the first mask sidewall 108 located in the NMOS region II are used as the N-region mask sidewall.
In this embodiment, the first mask sidewall 108 is further located on the P-type doped epitaxial layer 212 and the isolation structure 103 of the PMOS region I, and is further located on the top of the gate structure 110 of the PMOS region I.
Reference may be made to the materials and the formation processes of the P-region mask spacers 106 with respect to the materials and the formation processes of the first mask spacers 108. In this embodiment, the first mask sidewall 108 is made of silicon nitride, and the first mask sidewall 108 is formed by using an atomic layer deposition process.
If the thickness of the N-region mask side wall is too thin and the mechanical strength of the N-region mask side wall on the side wall of the NMOS region II fin part 102 is weak, the N-region mask side wall is easy to collapse in the subsequent thinning treatment process of the N-region mask side wall; if the thickness of the N-region mask sidewall is too thick, the filling effect of the N-region mask sidewall at the corner where the isolation structure 103 and the fin 102 are connected becomes poor.
Therefore, in this embodiment, before performing the subsequent thinning process, the thickness of the N-region mask sidewall is 60 to 120 angstroms.
The thickness of the first mask sidewall 108 is determined according to the thickness of the P region mask sidewall 106 on the NMOS region II fin 102 and the requirement for the thickness of the N region mask sidewall. In this embodiment, the thickness of the first mask sidewall 108 is 30 to 60 angstroms.
In this embodiment, the formed N-region mask sidewall is also located on the isolation structure 103 and on the top of the NMOS region II fin portion 102, so that the N-region mask sidewall can be formed by a deposition process, and etching process steps are reduced, thereby saving process cost and avoiding adverse effects caused by the etching process.
It should be further noted that, in other embodiments, the N-region mask sidewall spacer may further expose the top of the fin portion in the NMOS region; correspondingly, the process for forming the N-region mask side wall comprises the following steps: forming N-region mask side walls on the top and the side walls of the fin part of the NMOS region and on the isolation structure; and etching and removing the N-region mask side wall on the top of the NMOS region fin part and part of the isolation structure by adopting a maskless etching process.
Referring to fig. 10 and 11, a support layer 23 next to the sidewall of the N-region mask is formed on the isolation structure 103.
In this embodiment, the top of the support layer 23 is flush with the top of the N region mask sidewall, so that the support layer 23 has a strong supporting effect on the N region mask sidewall on the sidewall of the NMOS region II fin 102 in the subsequent process of etching the NMOS region II fin 102.
The fin portion 102 of the NMOS region II with a partial thickness is subsequently etched, and an N-region recess is formed in the fin portion 102 of the NMOS region II. In other embodiments, the top of the support layer may also be determined according to the position of the bottom of the N-region groove formed subsequently, and the top of the support layer is higher than the bottom of the N-region groove. Specifically, in order to ensure that the support layer has a sufficient supporting effect on the N region mask side wall on the N region groove side wall and prevent the N region mask side wall from collapsing in the process of forming the N region groove, the distance between the top of the support layer and the bottom of the N region groove is greater than or equal to 5 angstroms.
The material of the support layer 23 is a material which is easy to remove, and the material which removes the support layer 23 has little damage to the N-region mask side wall, so that the N-region mask side wall is prevented from collapsing in the process of removing the support layer 23. In this embodiment, the supporting layer 23 is made of an odl (organic Dielectric layer) materialA BARC (Bottom Anti-Reflective Coating) material or a DUO (deep UV Light Absorbing oxide) material, said DUO material being a siloxane polymer material comprising CH3-SiOXSi-OH, or SiOH3And the like.
In this embodiment, the process of forming the support layer 23 includes: forming a support film 21 on the N region mask sidewall, wherein the support film 21 is also positioned on the P-type doped epitaxial layer 212 and the isolation structure 103; forming a second pattern layer 22 on the support film 21 of the PMOS region I; and etching to remove the support film 21 with partial thickness of the NMOS region II by using the second pattern layer 22 as a mask, wherein the support film 21 after the NMOS region II is etched is used as the support layer 23, and a boundary between the support layer 23 and the support film 21 is shown by a dotted line in the figure.
In this embodiment, the second pattern layer 22 is used not only as a mask for forming the supporting layer 23, but also as a mask for subsequently etching the fin portion 102 in the NMOS region II. The second graphic layer 22 also covers the gate structure 110 of the PMOS region I and the first mask sidewall 108 of the PMOS region; the second patterning layer 22 serves to protect the PMOS region I and may also cover regions of the NMOS region that are not desired to be etched.
The material of the second patterning layer 22 is a photoresist material; the material of the support film 21 is the aforementioned ODL material, BARC material or DUO material.
In addition, in this embodiment, the top of the support film 21 is flush with the top of the P-type doped epitaxial layer 212, or the top of the support film 21 is higher than the P-type doped epitaxial layer 212, so as to reduce the influence of standing waves or reflection during the process of forming the second pattern layer 22, and improve the position accuracy and the topography accuracy of the second pattern layer 22.
Referring to fig. 12, the fin portions 102 located at two sides of the NMOS region II gate structure 110 are removed by etching, and the N region groove 201 is defined by the etched NMOS region II fin portions 102 and the N region mask sidewall.
Specifically, the second pattern layer 22 is used as a mask to etch the fin portion 102 with partial thickness on both sides of the NMOS region II gate structure 110, so as to form the N region groove 201.
In this embodiment, the fin portion 102 in the NMOS region II with a partial thickness is removed by etching using a dry etching process. Before the fins 102 on two sides of the NMOS region II gate structure 110 are etched and removed, N region mask spacers on the tops of the fins 102 on two sides of the NMOS region II gate structure 110 are also etched and removed, and the N region mask spacers on the top of the NMOS region II gate structure 110 and on a part of the isolation structure 103 are also removed.
In this embodiment, the etching rate of the etching process for forming the N-region groove 201 on the N-region mask sidewall is less than the etching rate of the fin portion 102, so that after the N-region groove 201 is formed, the top of the N-region mask sidewall on the sidewall of the N-region groove 201 is higher than the bottom of the N-region groove 201, and thus two sidewalls of the N-region groove 201 opposite to each other are the N-region mask sidewalls.
In the process of forming the N-region groove 201 by etching, the N-region mask sidewall on the sidewall of the fin 102 is supported by the support layer 23, so as to prevent the N-region mask sidewall from collapsing in the etching process, for example, the N-region mask sidewall is prevented from collapsing under the bombardment of etching reactive ions.
Referring to fig. 13, the support layer 23 is removed (refer to fig. 12).
In this embodiment, the supporting layer 23 is removed by one or two of an ashing process and a wet photoresist removal process.
In the process step of removing the support layer 23, the second pattern layer 22 (refer to fig. 12) and the support film 21 (refer to fig. 12) of the PMOS region I are also removed.
And subsequently, thinning the N-region mask side wall to increase the width of the N-region groove 201. In this embodiment, before the N region mask sidewall is thinned, the support layer 23 is removed. The N-region mask side wall has a relatively large width, so that the N-region mask side wall has relatively strong mechanical strength in the process of removing the supporting layer 23, and the N-region mask side wall is prevented from collapsing in the process of removing the supporting layer 23.
Referring to fig. 14, after the N-region groove 201 is formed, the N-region mask sidewall on the NMOS region II fin 102 is thinned, and the thinning is adapted to increase the width of the N-region groove 201.
In the process of thinning the N-region mask sidewall on the NMOS region II fin 102, the thickness of the first mask sidewall 108 of the PMOS region I exposed in the thinning process environment is also thinned; and the height of the N-region mask sidewall on the NMOS region II fin 102 is also reduced accordingly.
In this embodiment, in order to avoid the fin portion 102 at the bottom of the N-region groove 201 from being damaged by the thinning process, before the thinning process is performed, an oxidation process is performed on the surface of the fin portion 102 exposed by the N-region groove 201, and an oxide layer (not shown) is formed on the fin portion 102 exposed by the N-region groove 201. The oxidation treatment is dry oxygen oxidation, wet oxygen oxidation or water vapor oxidation.
The thinning treatment is suitable for increasing the width size of the N-region groove 201, so that after the thinning treatment is carried out, the volume capacity of the N-region groove 201 is increased, the volume of an N-type doped epitaxial layer formed in the N-region groove 201 is increased subsequently, and the N-type doped epitaxial layer is used for forming an N-type source drain doped region; accordingly, the resistance of the N-type source-drain doped region is reduced, the surface area of the N-type source-drain doped region is increased, and then the contact resistance between the surface of the N-type source-drain doped region and the metal silicide is reduced, so that the performance of the NMOS region II device is improved.
The thinning treatment adopts a wet etching process. In this embodiment, the etching rate of the thinning process is 0.5 a/s to 2 a/s. In this embodiment, the N-type mask sidewall is made of silicon nitride, the etching liquid used for the thinning process is a phosphoric acid solution, the concentration of phosphoric acid in the phosphoric acid solution is 75% to 85%, and the solution temperature is 80 ℃ to 200 ℃. In order to make the etching rate of the thinning treatment smaller, suspended particles, such as nano silica particles, can also be added to the phosphoric acid solution.
An N-type doped epitaxial layer is formed in the N-type groove 201 in the following process, so that the problem that the N-region mask side wall on the NMOS region II fin part 102 cannot fall off in the process of forming the N-type doped epitaxial layer is solved, and the thickness of the thinned N-region mask side wall is not small; moreover, the effect of reducing the surface contact resistance of the N-type doped epitaxial layer is not obvious in consideration of the fact that the thickness size of the thinned N-region mask side wall is still large. Therefore, in this embodiment, after the thinning process is performed, the thickness of the N region mask sidewall is 20 angstroms to 60 angstroms.
In addition, in this embodiment, the support layer 23 is removed before the thinning process is performed (refer to fig. 12). In other embodiments, the support layer may be removed after the thinning process is performed; or removing the supporting layer after the N-type doped epitaxial layer is formed subsequently.
Referring to fig. 15, an N-type doped epitaxial layer 211 filling the N-region recess 201 (refer to fig. 14) is formed.
Before forming the N-type doped epitaxial layer 211, the method further includes cleaning the N-region groove 201, where the cleaning is suitable for removing impurities on the surface of the N-region groove 201 and removing an oxide layer on the fin portion 102 exposed by the N-region groove 201.
In this embodiment, the top of the N-type doped epitaxial layer 211 is higher than the top of the N-region groove 201. Forming the N-type doped epitaxial layer 211 by using an in-situ doped selective epitaxy process; the material of the N-type doped epitaxial layer 211 is SiP or SiCP.
Since the N-type doped epitaxial layer 211 is doped with N-type ions, the N-type ions are beneficial to increasing the growth rate of the selective epitaxial process, so that the film growth rate of the selective epitaxial process is higher in the process of forming the N-type doped epitaxial layer by using the selective epitaxial process. In this embodiment, because the two opposite sidewalls in the N-region groove 201 are N-region mask sidewalls, the N-region mask sidewalls play a role in limiting the overgrowth of the N-type doped epitaxial layer 211, and the N-type doped epitaxial layer 211 is limited in the region surrounded by the N-region mask sidewalls and the NMOS region II fin 102, so as to avoid the too large width of the N-type doped epitaxial layer 211 on the NMOS region II fin 102.
Moreover, since the growth of the N-type doped epitaxial layer 211 in the N-region groove 201 is limited, the corresponding top surface area of the N-type doped epitaxial layer 211 higher than the N-region groove 201 will be smaller. Therefore, in this embodiment, the N-region mask sidewall is thinned to increase the width of the N-region groove 201, so that the width of the N-type doped epitaxial layer 211 grown in the N-region groove 201 is also increased, the top surface area of the N-type doped epitaxial layer 211 higher than the N-region groove 201 is relatively large, and the N-region mask sidewall can still be used for limiting the excessive growth of the N-type doped epitaxial layer 211.
When the N-type doped epitaxial layer 211 is formed by an in-situ doped selective epitaxial process, the surface area of the top of the N-type doped epitaxial layer 211 is related to the width of the N-region groove 201; the larger the width dimension of the N-region groove 201, the larger the surface area of the top of the N-type doped epitaxial layer 211.
In this embodiment, the top of the N-type doped epitaxial layer 211 is higher than the top of the N-region groove 201, and is affected by the characteristics of the selective epitaxy process, and the top surface of the N-type doped epitaxial layer 211 is a smooth-transition umbrella-shaped surface. It should be further noted that, in other embodiments, when the distance between the top of the N-type doped epitaxial layer and the top of the N-region groove is relatively large, the sidewall of the N-type doped epitaxial layer higher than the top of the N-region groove has a top angle protruding in a direction away from the fin.
After the N-type doped epitaxial layer 211 is formed, N-type doping may be performed on the N-type doped epitaxial layer 211, so as to improve the doping concentration of the formed N-type source/drain doped region, and doping may be performed into the fin portion 102 below the N-type doped epitaxial layer 211.
In order to avoid process damage to the surface of the N-type doped epitaxial layer 211 caused by a subsequent process, the method may further include oxidizing the surface of the N-type doped epitaxial layer 211, and forming an oxidation protection layer on the surface of the N-type doped epitaxial layer 211.
It should be noted that, in this embodiment, the P-region groove is formed first and then the N-region groove is formed, and in other embodiments, the N-region groove may be formed first and then the P-region groove is formed.
Referring to fig. 16, the N region mask sidewall spacers are removed.
In this embodiment, the first mask sidewall 108 (refer to fig. 15) and the P-region mask sidewall 106 (refer to fig. 15) are removed by etching, and the N-region mask sidewall is removed by etching using a wet etching process, wherein an etching liquid used in the wet etching process is a phosphoric acid solution.
And etching to remove the N-region mask side wall, and providing a process foundation for the subsequent formation of the interlayer dielectric layer, so that the process window for the subsequent formation of the interlayer dielectric layer is larger.
Referring to fig. 17, an interlayer dielectric layer 301 covering the gate structure 110 (refer to fig. 4), the isolation structure 103 and the N-type doped epitaxial layer 211 is formed.
In this embodiment, the interlayer dielectric layer 301 is further located on the P-type doped epitaxial layer 212. Before the interlayer dielectric layer 301 is formed, an etching stop layer may be further formed on the gate structure 110, the isolation structure 103, the N-type doped epitaxial layer 211, and the P-type doped epitaxial layer 212, where the material of the etching stop layer is different from that of the interlayer dielectric layer 301.
In this embodiment, the gate structure 110 is a dummy gate structure, and after the interlayer dielectric layer 301 is formed, the method further includes the steps of: etching to remove the gate structure 110, forming a first opening in the interlayer dielectric layer 301 of the PMOS region I, and forming a second opening in the interlayer dielectric layer 301 of the NMOS region II; forming a first metal gate structure filling the first opening; and forming a second metal gate structure filling the second opening.
In the fin field effect transistor formed in this embodiment, in the process of forming the N-region groove 201 (refer to fig. 14) by etching, the N-region mask sidewall on the sidewall of the NMOS region II fin 102 is supported by the support layer 23 (refer to fig. 12), so that the N-region mask sidewall is prevented from collapsing due to etching damage in the etching process, and thus, the electrical performance of the formed fin field effect transistor is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A method for forming a fin field effect transistor (FinFET) is characterized by comprising the following steps:
providing a substrate comprising an NMOS region, wherein the substrate is provided with a protruding fin part, an isolation structure covering the side wall of the fin part is arranged on the substrate, and the top of the isolation structure is lower than the top of the fin part;
forming a grid electrode structure on the NMOS region isolation structure, wherein the grid electrode structure stretches across the fin part and covers partial top and side walls of the fin part;
forming N-region mask side walls on the side walls of the fin parts of the NMOS region;
forming a supporting layer close to the side wall of the mask side wall of the N region on the isolation structure;
etching to remove fin parts with partial thicknesses on two sides of the NMOS region grid electrode structure, and enclosing the etched fin parts of the NMOS region and the N region mask side wall to form an N region groove;
after the N-region groove is formed, removing the supporting layer;
and forming an N-type doped epitaxial layer which fills the N-region groove.
2. The method of claim 1, wherein a top of the support layer is flush with a top of the N-region mask sidewall before forming the N-region recess.
3. The method of claim 1, wherein after forming the N-region recess, a top of the support layer is higher than a bottom of the N-region recess.
4. The method of claim 3, wherein a distance between a top of the support layer and a bottom of the N-region recess is greater than or equal to 5 angstroms after the N-region recess is formed.
5. The method of claim 1, wherein the material of the support layer comprises an ODL material, a BARC material, or a DUO material.
6. The method of claim 1, further comprising, prior to forming the N-type doped epitaxial layer, thinning an N-region mask sidewall on the fin sidewall, the thinning adapted to increase a width dimension of the N-region recess.
7. The method of claim 6, wherein the support layer is removed prior to the thinning.
8. The method of claim 1, wherein the support layer is removed after the N-doped epitaxial layer is formed.
9. The method of claim 1, wherein the N-type doped epitaxial layer is SiP or SiCP; and forming the N-type doped epitaxial layer by adopting an in-situ doped selective epitaxial process.
10. The method of claim 1, wherein the N-region mask sidewall spacers are further formed on the isolation structure and on top of the NMOS region fin; and before etching and removing the fin parts with partial thicknesses at two sides of the gate structure of the NMOS region, etching and removing the N region mask side walls at the tops of the fin parts at two sides of the gate structure of the NMOS region.
11. The method of claim 1, wherein the step of forming the N-region mask sidewall comprises: forming N-region mask side walls on the top and the side walls of the fin part of the NMOS region and on the isolation structure; and etching and removing the N-region mask side wall on the top of the NMOS region fin part and part of the isolation structure by using a maskless etching process.
12. The method of claim 1, wherein the substrate further comprises a PMOS region having a fin on the substrate; a grid structure is formed on the isolation structure of the PMOS region, crosses the fin part of the PMOS region and covers part of the top and the side wall of the fin part; the forming method further includes:
forming a P area mask side wall on the side wall of the fin part of the PMOS area; etching to remove fin parts with the first thickness positioned on two sides of the grid electrode structure of the PMOS region, etching to remove the mask side wall of the P region with the first thickness, and forming a groove of the P region in the etched fin parts of the PMOS region; and forming a P-type doped epitaxial layer filling the P-region groove.
13. The method of claim 12, wherein the P-region mask sidewall is further on the isolation structure and on top of the PMOS region fin; and before etching and removing the fin parts with the first thickness at the two sides of the grid electrode structure of the PMOS region, etching and removing the P region mask side walls at the tops of the fin parts at the two sides of the grid electrode structure of the PMOS region.
14. The method of claim 12, wherein the P-region recess is formed first and the N-region recess is formed second; the process steps for forming the P area mask side wall, the P area groove, the N area mask side wall and the N area groove comprise: forming a P area mask side wall on the fin part side wall of the PMOS area, wherein the P area mask side wall is also positioned on the fin part side wall of the NMOS area; etching and removing the fin part with the first thickness in the PMOS region and the P region mask side wall with the first thickness on the fin part side wall to form the P region groove; forming a P-type doped epitaxial layer filling the P-region groove; after the P-type doped epitaxial layer is formed, reserving a P-region mask side wall positioned in the NMOS region as an N-region mask side wall; and forming the supporting layer, the N-region groove and the N-type doped epitaxial layer.
15. The method of claim 14, further comprising, prior to forming the P-region recess, forming a first pattern layer on the NMOS region fin and a P-region mask sidewall; when the P area mask side wall is also positioned on the top of the NMOS area fin part, removing the first graphic layer before or after forming the P type doped epitaxial layer; and when the P region mask side wall exposes the top of the NMOS region fin part, removing the first graphic layer after the P type doped epitaxial layer is formed.
16. The method of claim 14, further comprising, after forming the P-type doped epitaxial layer and before forming the support layer, forming a first mask sidewall on the P-region mask sidewall of the NMOS region, wherein the P-region mask sidewall and the first mask sidewall in the NMOS region serve as the N-region mask sidewall.
17. The method of claim 14, wherein the step of forming the support layer comprises: forming a support film on the N-region mask side wall, wherein the support film is also positioned on the P-type doped epitaxial layer and the isolation structure; forming a second graphic layer on the support film of the PMOS region; and etching and removing the support film with partial thickness in the NMOS area by taking the second pattern layer as a mask, wherein the support film etched in the NMOS area is taken as the support layer.
18. The method of claim 17, wherein a top of the support film is flush with a top of the P-doped epi layer; or the top of the support film is higher than the P-type doped epitaxial layer.
19. The method of claim 17, wherein the second pattern layer is used as a mask to etch a portion of the thickness fin at two sides of the gate structure of the NMOS region to form the N-region recess; and in the process step of removing the support layer, removing the second graphic layer and the support film of the PMOS region.
20. The method of claim 12, wherein the N-region recess is formed first and the P-region recess is formed second.
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