CN110164968B - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device and a method for forming the same, wherein the semiconductor device comprises: a substrate; an isolation structure located in the substrate; a gate structure located on the substrate, and the gate structure extends to the isolation structure; a substrate located on both sides of the gate structure source and drain doped layers inside; conductive structures respectively located on both sides of the gate structure, the conductive structures extend from the source and drain doped layers to the isolation structure, and the conductive structures include: a first layer covering the source and drain doped layers A plug portion and a second plug portion covering the isolation structure, the side wall of the first plug portion has a first distance from the side wall of the adjacent gate structure, and the side wall of the second plug portion is adjacent to the gate structure. The gate structure sidewall has a second distance, the first distance is smaller than the second distance, and the width of the first plug portion is greater than the width of the second plug portion. The performance of the semiconductor device is improved.

Description

Semiconductor device and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a method for forming the same.

Background technique

MOS (Metal-Oxide-Semiconductor) transistors are one of the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure including: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; The source and drain doped layers in the semiconductor substrate on both sides of the pole structure.

With the development of semiconductor technology, the control ability of traditional planar MOS transistors on channel current becomes weak, resulting in serious leakage current. Fin Field Effect Transistor (Fin FET) is an emerging multi-gate device, which generally includes a fin protruding from the surface of a semiconductor substrate, a gate structure covering part of the top surface and sidewalls of the fin, Source and drain doped layers in the fins on both sides of the gate structure.

However, the performance of the semiconductor device formed by the fin field effect transistor in the prior art still needs to be improved.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, so as to improve the performance of the semiconductor device.

In order to solve the above technical problems, the present invention provides a semiconductor device, comprising: a substrate; an isolation structure located in the substrate; a gate structure located on the substrate, and the gate structure extends to the isolation structure; source and drain doping layers in the side substrate; conductive structures respectively located on both sides of the gate structure, the conductive structures extending from the source and drain doping layers to the isolation structure, the conductive structures comprising: covering the source and drain doping layers a first plug portion and a second plug portion covering the isolation structure, the sidewall of the first plug portion has a first distance from the sidewall of the adjacent gate structure, and the sidewall of the second plug portion is The sidewalls of adjacent gate structures have a second distance, the first distance is smaller than the second distance, and the width of the first plug portion is greater than the width of the second plug portion.

Optionally, the width of the first plug portion is 17 nm to 62 nm.

Optionally, the width of the second plug portion is 15 nm˜50 nm.

Optionally, the difference between the width of the first plug portion and the width of the second plug portion is 2 nm˜12 nm. Optionally, the first distance is 20 nm to 100 nm.

Optionally, the second distance is 22 nm to 112 nm.

Optionally, the difference between the second distance and the first distance is 2 nm˜12 nm.

The present invention also provides a method for forming a semiconductor device, comprising: providing a substrate with an isolation structure; forming a gate structure on the substrate, the gate structure extending to the isolation structure; A source-drain doped layer is formed in the substrate; a conductive structure is formed on both sides of the gate structure, the conductive structure spans the source-drain doped layer and extends to the isolation structure, and the conductive structure covers part of the top surface of the source-drain doped layer and part of the sidewall surface and part of the surface of the isolation structure, the wire structure includes: a first plug part covering the source and drain doped layers and a second plug part covering the isolation structure, the sidewall of the first plug part There is a first distance from the sidewall of the adjacent gate structure, the sidewall of the first plug portion has a second distance from the sidewall of the adjacent gate structure, the first distance is smaller than the second distance, and the self-gate In the direction from the source-drain doped layer on one side of the pole structure to the source-drain doped layer on the other side, the size of the first plug portion is larger than the size of the second plug portion.

Optionally, the difference between the width of the first plug portion and the width of the second plug portion is 2 nm˜12 nm.

Optionally, before forming the conductive structure, a dielectric layer is formed on the isolation structure, the gate structure and the source-drain doping layer, the dielectric layer covers the top surface of the gate structure; the conductive structure is located in the dielectric layer .

Optionally, the method for forming the conductive structure includes: forming a trench across the source-drain doped layer in the dielectric layer on both sides of the gate structure, and the extension direction of the trench is parallel to the extension direction of the gate structure. The trench exposes part of the top surface and part of the sidewall surface of the source-drain doped layer and part of the surface of the isolation structure, the trench includes a first trench region and a second trench region, and the first trench region exposes Part of the top surface and part of the sidewall surface of the source-drain doped layer, the second trench region exposes part of the surface of the isolation structure, and the second trench sidewall is recessed relative to the first trench sidewall; A first plug portion is formed in the groove, and a second plug portion is formed in the second groove.

Optionally, the method for forming the trench includes: forming a first patterned mask layer on the dielectric layer, and the first patterned mask layer exposes the position and shape of the trench, and the first patterned mask layer exposes the position and shape of the trench. The mask layer is a mask, and the dielectric layer is etched to expose part of the surface of the source and drain doped layers and part of the surface of the isolation structure, and the dielectric layers on both sides of the gate structure are formed to cross the source along the extension direction of the gate structure. Drain doped trenches.

Optionally, the method for forming the trench includes: forming an initial trench in the dielectric layer, and the portion of the initial trench exposing part of the top surface and part of the sidewall surface of the source-drain doped layer is the initial first trench , the part of the initial trench exposing the surface of the part of the isolation structure is the second trench, the initial first trench is adjacent to the second trench, and the sidewall of the initial first trench is flush with the sidewall of the second trench; After the initial trenches are formed, the initial first trenches are processed so that the sidewalls of the initial first trenches are widened relative to the sidewalls of the second trenches along the widths perpendicular to the extension direction of the gate structure and the direction perpendicular to the substrate surface, thereby The trenches are formed.

Optionally, the method for forming the initial trench includes: forming a second patterned mask layer on the dielectric layer, and using the second patterned mask layer as a mask, etching the dielectric layer to expose the source Part of the surface of the drain doped layer and part of the surface of the isolation structure, an initial trench is formed in the dielectric layer on both sides of the gate structure across the source and drain doped layer along the extension direction of the gate structure, and the initial trench exposes the source The part of the top surface and part of the sidewall surface of the drain doped layer is the initial first trench, the part of the trench that exposes the part of the surface of the isolation structure is the second trench, and the initial first trench is the same as the second trench. Adjacent, initially the first trench sidewall is flush with the second trench sidewall.

Optionally, the method for forming the trench includes: forming a third patterned mask layer on the dielectric layer, and the third patterned mask layer is positioned at the position of the first trench, so that the third patterned mask layer The patterned mask layer is a mask, and the dielectric layer is etched until a part of the surface of the source-drain doped layer and part of the surface of the isolation structure is exposed, and a first trench is formed; A fourth patterned mask layer is formed on the groove and the third patterned mask layer, the fourth patterned mask layer is positioned at the position of the second trench, and the fourth patterned mask layer is used as a mask film, and etching the dielectric layer until a part of the surface of the isolation structure is exposed to form a second trench, thereby forming the trench.

Optionally, the method for forming the first plug portion in the first trench, and forming the second plug portion in the second trench includes: forming a plug material layer in the first trench and the second trench; After the plug material layer is formed, the plug material layer is planarized to expose the surface of the dielectric layer, a first plug portion is formed in the first trench, and a second plug portion is formed in the second trench.

Optionally, the first distance is 20 nm to 100 nm.

Optionally, the second distance is 22 nm to 112 nm.

Optionally, the difference between the second distance and the first distance is 2 nm˜12 nm.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the semiconductor device provided by the present invention, a first plug portion covering the source-drain doped layer and a second plug portion covering the isolation structure, the second plug portion is far away from the adjacent gate structure, and the second plug portion is far away from the adjacent gate structure. The second parasitic capacitance between the portion and the gate structure is small. The size of the first plug portion is larger, the contact area between the first plug portion and the source-drain doped layer is larger, and the contact resistance between the first plug portion and the source-drain doped layer is smaller. The parasitic capacitance of the semiconductor device is composed of a first parasitic capacitance and a second parasitic capacitance. By controlling the size of the first plug portion and the second plug portion, a smaller parasitic capacitance and a smaller contact resistance can be obtained, thereby improving the device. performance.

Description of drawings

1 is a schematic structural diagram of a semiconductor device formation process;

2 to 12 are schematic structural diagrams of a semiconductor device forming process in an embodiment of the present invention.

Detailed ways

As mentioned in the background, semiconductor devices formed by the prior art have poor performance.

FIG. 1 is a schematic structural diagram of a semiconductor device forming process.

Referring to FIG. 1, a substrate 100 is provided, the substrate 100 has a fin 110 and an isolation structure, and the isolation structure covers part of the sidewall of the fin 110; a gate structure 120, a source-drain doped layer and a dielectric layer are formed, and the gate structure 110 is located at The substrate 100 spans the fins 110 , the source and drain doped layers are located in the fins 110 on both sides of the gate structure 120 , the dielectric layer is located on the source and drain doped layers and the gate structure 120 ; A through hole extending from the source and drain doped layer to the isolation structure and exposing part of the surface of the source and drain doped layer and a part of the surface of the isolation structure is formed in the dielectric layer on the side; a plug 130 is formed in the through hole.

The gate structure and the plug are isolated by a dielectric layer, and a parasitic capacitance is formed between the two. The parasitic capacitance consists of two parts, the parasitic capacitance between the plug located above the source and drain doped layers and the gate structure Capacitance and parasitic capacitance between the plug and gate structures above the isolation structures. The resistance between the source-drain doped layer and the plug is the contact resistance.

The plug has a width along the extending direction of the fin and a direction perpendicular to the surface of the substrate, and the width of the plug on the surface of the source-drain doped layer is the same as that on the surface of the isolation structure. The greater the width of the plug located on the source-drain doped layer, the smaller the contact resistance between the source-drain doped layer and the plug, the closer the distance between the plug and the gate structure, the closer the plug and the gate structure are. the larger the parasitic capacitance between them. Therefore, in order to balance the contact resistance and parasitic capacitance of the semiconductor device, the width of the plug is constant. At this time, the contact resistance between the source-drain doped layer and the plug is relatively large, and the parasitic capacitance between the plug and the gate structure is also relatively large. large, poor semiconductor performance.

The present invention reduces the parasitic capacitance and parasitic resistance of the semiconductor device through different designs of the size of the plug on the source and drain doped regions and the size of the plug on the isolation structure.

In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

2 to 12 are schematic structural diagrams of a semiconductor device forming process in an embodiment of the present invention.

Referring to Figure 2, a substrate is provided.

In this embodiment, the semiconductor device is an example of a fin field effect transistor for description. In other embodiments, the semiconductor device is a planar MOS transistor.

In this embodiment, the base includes a semiconductor substrate 200 and fins 210 on the semiconductor substrate 200. In other embodiments, when the semiconductor device is a planar MOS transistor, the substrate is a planar semiconductor substrate.

In this embodiment, the semiconductor substrate 200 further has an isolation structure 201 , the isolation structure 201 covers part of the sidewalls of the fins 210 , and the top surface of the isolation structure 201 is lower than the top surface of the fins 210 . The material of the isolation structure 201 includes silicon oxide.

Continuing to refer to FIG. 2, a gate structure 220, a source-drain doped layer 250 and a dielectric layer are formed, the gate structure 220 is located on the substrate, the source-drain doped layer 250 is located in the substrate on both sides of the gate structure 220, and the dielectric layer is located on the source On the drain doped layer 250 and the gate structure 220 , the source and drain doped layers 250 have source and drain ions.

In this embodiment, the gate structure 220 includes an interface layer on the substrate, a gate dielectric layer on the interface layer, and a gate electrode layer on the gate dielectric layer. The interface layer is made of silicon oxide, the gate dielectric layer is made of high-K (K is greater than 3.9) dielectric material, and the gate electrode layer is made of metal, such as tungsten. In other embodiments, the gate structure 220 further includes a gate protection layer on top of the gate structure 220 body.

In this embodiment, the gate structure 220 spans the fin 210 and covers part of the top surface and part of the sidewall surface of the fin 210. The gate dielectric layer is located on a part of the surface of the isolation structure 201, and covers part of the top surface and part of the sidewall surface of the fin part 210.

In this embodiment, the substrate further includes a first spacer 221 located on the sidewall of the gate structure 220 and a second spacer 222 located on the sidewall of the first spacer 221.

The dielectric layer includes a bottom dielectric layer 240 and a top dielectric layer 241, the bottom dielectric layer 240 is located on the substrate and covers the sidewall of the gate structure 220, and the top dielectric layer 241 is located on the bottom dielectric layer 240 and the gate structure 220.

Specifically, the dummy gate structure 220 is formed on the substrate; the first sidewall spacer 221 and the second sidewall spacer 222 are sequentially formed on the sidewall of the dummy gate structure 220 ; The source-drain doped layer 250 is formed in the base of the doped source and drain; after the source-drain doped layer 250 is formed, an initial protective layer is formed on the source-drain doped layer 250 and the substrate, and the initial protective layer covers the sidewalls of the second spacers 222 and the base. the top surface and the top surface of the dummy gate structure 220; after the protective layer is formed, an initial underlying dielectric layer is formed on the surface of the source-drain doping layer 250 and the protective layer on the substrate surface; after the initial underlying dielectric layer is formed, the initial underlying layer is planarized The dielectric layer is until the top surface of the dummy gate structure 220 is exposed to form an underlying dielectric layer 240 and a protective layer 230 , the underlying dielectric layer 240 covers the sidewalls of the second spacer 222 and exposes the top surface of the second spacer 22 and the protective layer 230 . The top surface of the dummy gate structure 220; after forming the underlying dielectric layer 240, the dummy gate structure 220 is removed, and a gate opening is formed in the underlying dielectric layer 240; the gate structure 220 is formed in the gate opening; A top dielectric layer 241 is formed on the dielectric layer 240 , the first spacer 221 and the second spacer 222 .

The material of the bottom dielectric layer 240 and the top dielectric layer 241 is silicon oxide.

The protective layer 230 protects the source and drain doped layers when the second trench is subsequently formed.

The material of the protective layer 230 is different from that of the dielectric layer. The material of the protective layer includes: silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

In this embodiment, the material of the protective layer 230 is silicon nitride. The material of the dielectric layer is silicon oxide. Compared with silicon oxide, silicon nitride has a good etching selectivity ratio. When the dielectric layer is subsequently etched, it can ensure that the silicon oxide is removed and the silicon nitride is etched less. The source and drain doped layers can be well protected.

The source and drain doped layers 250 are located in the substrates on both sides of the gate structure 220 . Specifically, the source and drain doped layers 250 are located in the fins 210 on both sides of the gate structure 220 .

The source-drain doped layer 250 has source-drain ions.

When the type of the semiconductor device is N type, the conductivity type of the source and drain ions is N type, such as phosphorus ions; when the type of the semiconductor device is P type, the conductivity type of the source and drain ions is P type, such as boron ion.

In this embodiment, the source-drain doping layer 250 is formed by an epitaxial growth process. Correspondingly, when the type of the semiconductor device is N-type, the material of the source-drain doped layer 250 is silicon with source and drain ions; when the type of the semiconductor device is P-type, the material of the source-drain doped layer 250 is The material is germanium silicon with source and drain ions. In other embodiments, the source-drain doping layer 250 is formed by an ion implantation process.

A trench across the source and drain doped layers is formed in the dielectric layers on both sides of the gate structure, the trench extends in the same direction as the gate structure, and the trench exposes part of the top surface of the source and drain doped layers and part of the sidewall surface and part of the surface of the isolation structure.

For the formation method of the trench, please refer to FIG. 3 to FIG. 6 .

Referring to FIG. 3, a first patterned mask layer 231 is formed on the dielectric layer, and the first patterned mask layer 231 exposes the position and shape of the trench 260 to be formed subsequently.

In this embodiment, the step of forming the first patterned mask layer 231 includes: forming a first mask layer (not shown) on the dielectric layer; The film layer is subjected to exposure treatment, the exposure template is a patterned template, and the patterned template exposes the position and shape of the grooves that need to be formed later, and the first mask layer is developed to expose the subsequent needs to be formed. According to the position and shape of the trench, the first patterned mask layer 231 is formed.

The material of the first patterned mask layer 231 includes photoresist.

In one embodiment, the material of the first patterned mask layer 231 is silicon nitride. The step of forming the first patterned mask layer 231 includes: forming an initial mask layer (not shown) on the dielectric layer; after forming the initial mask layer, forming a patterned layer on the initial mask layer, the The patterned layer exposes the position and shape of the trench to be formed later, and the initial mask layer is etched using the patterned layer as a mask to form a first patterned mask layer 231 . The material of the imaged layer includes photoresist.

The first patterned mask layer 231 determines the shape and size of the subsequently formed trench, and a conductive structure is subsequently formed in the trench, that is, the first patterned mask layer 231 determines the shape and size of the subsequent conductive structure. size.

Referring to FIGS. 4 and 5 , FIG. 5 is a top view of the semiconductor device, and FIG. 4 is a cross-sectional view taken along the tangent line A-A1 in FIG. 5 . After the first patterned mask layer 231 is formed, the first patterned The mask layer 231 is a mask, and the dielectric layer is etched to expose part of the surface of the source-drain doped layer 250 and part of the surface of the isolation structure 201 , and trenches 260 are formed in the dielectric layer on both sides of the gate structure 220 .

The extending direction of the trench 260 is consistent with the extending direction of the gate structure 220, and the trench 260 exposes part of the top surface and part of the sidewall surface of the source-drain doped layer 250 and part of the surface of the isolation structure 201.

The part of the trench 260 exposing part of the top surface and part of the sidewall surface of the source-drain doping layer 250 is the first trench region 261 , and the part of the trench 260 exposing the part of the surface of the isolation structure is the second trench region 262 , the first trench region 261 is adjacent to the second trench region 262 , and the sidewall of the second trench region 262 is recessed relative to the sidewall of the first trench region 261 .

The width of the first trench region 261 in the direction from the source-drain doped layer 250 on one side of the gate structure 220 to the source-drain doped layer 250 on the other side is the first width, and the second trench region The width of 262 in the direction from the source-drain doped layer 250 on one side of the gate structure 220 to the source-drain doped layer 250 on the other side is the second width, and the second width is smaller than the first width.

A first plug portion 301 is subsequently formed in the first trench region 261, and a second plug portion 302 is subsequently formed in the second trench region 262. The positions and widths of the first trench region 261 and the second trench region 262 determine the positions and widths of the first plug portion 301 and the second plug portion 302 to be formed subsequently.

The distance between the center of the trench 260 and the center of the gate structure 220 is fixed, the width of the second trench region 262 on the isolation structure 201 is narrow, the second plug portion 302 formed subsequently is farther from the gate structure 220, The second parasitic capacitance between the plug portion 302 and the gate structure 220 is relatively small, and the width of the first trench region 261 on the source-drain doped layer 250 is wider, and the first plug portion 301 and the source-drain dopant are formed later. The contact area of the impurity layer 250 is larger, and the contact resistance is smaller. The parasitic capacitance of the semiconductor device is composed of a first parasitic capacitance and a second parasitic capacitance. By controlling the size of the first plug portion 301 and the second plug portion 302, small parasitic capacitance and small contact resistance can be obtained, thereby improving the semiconductor performance. device performance.

Specifically, in the method for forming the trench 260 , etching the dielectric layer is to etch the dielectric layers on both sides of the gate structure 220 , and the trench 260 is formed in the dielectric layers on both sides of the gate structure 220 .

The process of etching the dielectric layers on both sides of the gate structure 220 includes an anisotropic dry etching process.

In this embodiment, the parameters of using the anisotropic dry etching process to etch the dielectric layers on both sides of the gate structure 220 include: the gas used includes CF ₄ gas, CH ₃ F gas and O ₂ , and the flow rate of the CF ₄ gas is 5 sccm ~100sccm, the flow rate of _CH3F gas is 8sccm~50sccm, the flow rate of _O2 is 10sccm~100sccm, the chamber pressure is 10mtorr~2000mtorr, the radio frequency power is 50W~300W, the voltage is 30V~100V, and the time is 4 seconds~50 second.

In other embodiments, the method for forming the trench 260 may also be two mask formation.

In one embodiment, the method for forming the trench 260 includes: forming an initial trench in the dielectric layer, and the portion of the initial trench exposing part of the top surface and part of the sidewall surface of the source-drain doped layer 250 is the initial trench. The first trench, the part of the initial trench that exposes part of the surface of the isolation structure 201 is the second trench region 262, the initial first trench is adjacent to the second trench region 262, and the sidewall of the initial first trench is The sidewalls of the second trench region 262 are flush; after the initial trenches are formed, the initial first trenches are processed so that the sidewalls of the initial first trenches are opposite to the sidewalls of the second trench region 262 from the gate structure 220 The width in the direction from the source-drain doped layer 250 on one side to the source-drain doped layer 250 on the other side is widened to form a first trench region 261 , thereby forming the trench 260 .

The method for forming the initial trench includes: forming a second patterned mask layer on the dielectric layer, and using the second patterned mask layer as a mask, etching the dielectric layer to expose the source and drain doped layers Part of the surface of 250 and part of the surface of the isolation structure, in the dielectric layer on both sides of the gate structure 220, an initial trench is formed across the source and drain doped layer 250 along the extension direction of the gate structure 220 body 220 structure, the initial trench The part exposing part of the top surface and part of the sidewall surface of the source-drain doping layer 250 is the initial first trench, the part of the trench exposing part of the surface of the isolation structure 201 is the second trench region 262 , and the initial first trench The trench is adjacent to the second trench region 262 , and initially the sidewalls of the first trench are flush with the sidewalls of the second trench region 262 .

The shape of the pattern in the second patterned mask layer is a rectangle.

In another embodiment, the method for forming the trench 260 includes: forming a third patterned mask layer on the dielectric layer, and the third patterned mask layer is positioned at a position out of the first trench region 261 , Using the third patterned mask layer as a mask, the dielectric layer is etched until part of the surface of the source-drain doped layer and part of the surface of the isolation structure are exposed, forming a first trench region 261; forming a first trench After the trench area 261, a fourth patterned mask layer is formed on the first trench area 261 and the third patterned mask layer. The fourth patterned mask layer is a mask, and the dielectric layer is etched until a part of the surface of the isolation structure 201 is exposed to form a second trench region 262 , thereby forming the trench 260 .

Referring to FIG. 6 , after the trenches 260 are formed, the first patterned mask layer 231 is removed.

The process of removing the first patterned mask layer 231 includes an ashing process.

In this embodiment, the formation process of the trench 260 further includes: after removing the first patterned mask layer 231 , etching and removing the protective layer 230 on the surface of the source-drain doped layer 250 exposed by the first trench region 261 , exposing the surface of the source-drain doping layer 250 . In other embodiments, the protective layer 230 is not formed on the surface of the source-drain doping layer 250, and the protective layer 230 does not need to be removed.

Removing the protective layer 230 after removing the first patterned mask layer 231 can avoid the influence of the ashing process on the source-drain doping layer 250.

The process of etching and removing the protective layer 230 on the surface of the source-drain doping layer 250 exposed by the first trench region 261 is an isotropic dry etching process, and the process parameters include: the gas used includes _CF4 gas, The flow rate of CH ₂ F ₂ gas and O ₂ , CF ₄ gas is 30sccm～200sccm, the flow rate of CH ₂ F ₂ gas is 8sccm～50sccm, the flow rate of O ₂ is 2sccm～30sccm, the chamber pressure is 10mtorr～2000mtorr, the RF power It is 100W~1000W, the DC current is 30V~500V, and the time is 4 seconds~50 seconds.

Referring to FIG. 7 , after the trench 260 is formed, a metal layer 270 is formed on the bottom surface and sidewall surface of the trench 260 .

The material of the metal layer 270 includes Ti, Co or Ni.

The metal layer 270 is also located on the dielectric layer.

The process of forming the metal layer 270 is a deposition process, such as a sputtering process.

Referring to FIG. 8 , after the metal layer 270 is formed, the metal layer 270 and the source-drain doped layer 250 are annealed, and a metal silicide layer 280 is formed on the surface of the source-drain doped layer 250 exposed in the first trench region 261 .

In this embodiment, during the annealing process, the atoms of the metal layer 270 diffuse into the source-drain doped layer 250 and react with the material of the source-drain doped layer 250 to form the metal silicide layer 280 .

The effect of the annealing treatment further includes: activating the second ions in the source-drain doping layer 250 .

In this embodiment, since the surface material of the source-drain doped layer 250 is doped with source and drain ions, the metal silicide layer 280 is doped with source and drain ions, which reduces the resistance of the metal silicide layer 280 .

The annealing treatment includes laser annealing or spike annealing.

The advantages of using laser annealing or spike annealing for the annealing treatment include: laser annealing and spike annealing have a faster heating process, avoid greater diffusion of ions in the doped region of the semiconductor device caused by the heating process, and improve the stability of the doped region .

In this embodiment, before the subsequent annealing treatment, a barrier layer (not shown) is also formed on the surface of the metal layer 270 . The material of the barrier layer includes titanium nitride or tantalum nitride. The process of forming the barrier layer is a deposition process, such as a sputtering process.

In this embodiment, the barrier layer is formed before the annealing treatment. During the annealing treatment, the barrier layer can protect the metal layer 270, and the barrier annealing treatment causes the metal layer 270 to be oxidized.

In one embodiment, in order to prevent the material of the barrier layer from recrystallizing at the annealing temperature, which leads to the problem of poor performance stability of the barrier layer, the temperature of the annealing treatment is selected to be below 900 degrees Celsius.

In other embodiments, the barrier layer is formed after annealing.

In other embodiments, no barrier layer is formed.

Referring to Figure 9, after the annealing process, a layer 290 of conductive structural material is formed within trench 260 (refer to Figure 8) and on the dielectric layer.

In this embodiment, the conductive structural material layer 290 is located on the surface of the barrier layer.

The material of the conductive structural material layer 290 is metal, such as tungsten.

The process for forming the conductive structural material layer 290 is a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

10 to 12, FIG. 10 is a top view of the device, FIG. 11 is a cross-sectional view of FIG. 10 along the tangent line A-A1, and FIG. 12 is a cross-sectional view of FIG. 10 along the tangent line A2-A3. The conductive structure material layer 290 is planarized to expose the top surface of the dielectric layer to form the conductive structure 300 .

The extension direction of the conductive structure 300 is consistent with the extension direction of the gate structure 220 , the conductive structure 300 covers part of the top surface and part of the sidewall surface of the source-drain doping layer 250 and part of the surface of the isolation structure 201 ; the conductive structure 300 covers Part of the top surface and part of the sidewall surface of the source-drain doped layer 250 is the first plug portion 301 , and the portion of the conductive structure 300 covering the surface of the isolation structure 201 is the second plug portion 302 , the first plug portion 301 Adjacent to the second plug portion 302 , the side wall of the second plug portion 302 is recessed relative to the side wall of the first plug portion 301 .

In this embodiment, the conductive structure material layer 290 and the metal layer 270 are planarized until the top surface of the dielectric layer is exposed, so that the conductive structure material layer 290 in the first trench region 261 forms the first plug portion 301, and the second plug portion 301 is formed. The conductive structural material layer 290 in the trench region 262 forms the second plug portion 302 .

The distance from the sidewall of the first plug portion 301 to the sidewall of the adjacent gate structure 220 is the first distance, and the distance from the sidewall of the second plug portion 302 to the sidewall of the adjacent gate structure 220 is The second distance, the first distance is smaller than the second distance.

There is a first distance L3 between the sidewall of the first plug portion 301 and the sidewall of the adjacent gate structure 220, and L3 is 20 nm˜100 nm

There is a second distance L4 between the sidewall of the second plug portion 302 and the sidewall of the adjacent gate structure 220 , and L4 is 22 nm˜112 nm.

The difference between the first distance L3 and the second distance L4 is 2 nm˜12 nm.

The distance between the conductive structure 300 and the gate structure 220 affects the magnitude of the parasitic capacitance therebetween. The second plug portion 302 is farther away from the adjacent gate structure 220 , and the second plug portion 302 and the gate structure 220 are farther away. The second parasitic capacitance between them is relatively small; the distance between the first plug portion 301 and the adjacent gate structure 220 is relatively short, and the first parasitic capacitance between the first plug portion 301 and the gate structure 220 is relatively large; the parasitic capacitance of the semiconductor device is determined by the first The parasitic capacitance and the second parasitic capacitance are formed. By controlling the size of the first plug portion 301 and the second plug portion 302 , the semiconductor device can obtain smaller parasitic capacitance, thereby improving the performance of the semiconductor device.

The difference between the first distance L3 and the second distance L4 is determined by the first plug portion 301 and the second plug portion 302 from the source and drain doped layers on one side of the gate structure 220 to the source and drain doped layers on the other side of the gate structure 220 The width difference in the direction is determined.

The width of the first plug portion 301 in the direction from the source-drain doped layer on one side of the gate structure 220 to the source-drain doped layer on the other side is the same as the width of the first trench region 261 , which is the first width. L1 and L1 are 17 nm to 62 nm.

The width of the second plug portion 302 in the direction from the source-drain doped layer on one side of the gate structure 220 to the source-drain doped layer on the other side is the same as the width of the second trench region 262 and is the second width L2 and L2 are 15 nm to 50 nm.

The second width is smaller than the first width, and the width of the second plug portion in the direction from the source-drain doped layer on one side of the gate structure 220 to the source-drain doped layer on the other side is smaller than the width of the first plug portion.

The difference between the first width and the second width is 2 nm˜12 nm.

When the difference between the first width and the second width is greater than 12 nm, the parasitic resistance of the second plug portion 292 is too large, which is not conducive to the performance of the device. When the difference between the first width and the second width is less than 2 nm, the second plug portion 292 The parasitic capacitance with the gate structure 220 is not significantly improved, and the device performance is not significantly improved.

The distance between the center of the conductive structure 300 and the center of the gate structure 220 is fixed. The second parasitic capacitance is smaller, and the width of the first plug portion 301 on the source-drain doped layer 250 is wider, the contact area between the first plug portion 301 and the source-drain doped layer 250 is larger, and the contact resistance is smaller . The parasitic capacitance of the semiconductor device is composed of a first parasitic capacitance and a second parasitic capacitance. By controlling the size of the first plug portion 301 and the second plug portion 302, a smaller parasitic capacitance and a smaller contact resistance can be obtained, thereby Improve device performance.

Correspondingly, the present embodiment also provides a structure of a semiconductor device, please refer to FIG. 10 to FIG. 12 , including: providing a substrate; an isolation structure 201 located in the substrate; a gate structure 220 located on the substrate, and the gate The structure 220 extends on the isolation structure 201; the source and drain doped layers 250 are located in the substrate on both sides of the gate structure 220; 250 extends to the isolation structure 201, and the conductive structure 300 includes: a first plug portion 301 covering the source-drain doping layer 250 and a second plug portion 302 covering the isolation structure 201, the first plug portion 301 The sidewall of the adjacent gate structure 220 has a first distance, and the sidewall of the second plug portion 302 has a second distance from the sidewall of the adjacent gate structure 220, and the first distance is smaller than the second distance distance, and in the direction from the source-drain doped layer 250 on one side of the gate structure 220 to the source-drain doped layer 250 on the other side, the size of the first plug portion 301 is larger than the size of the second plug portion 302 .

The width of the first plug portion 301 in the direction from the source-drain doped layer on one side of the gate structure 220 to the source-drain doped layer on the other side is the same as that of the first trench, which is the first width L1, L1 It is 17nm～62nm.

The width of the second plug portion 302 in the direction from the source-drain doped layer on one side of the gate structure 220 to the source-drain doped layer on the other side is the same as that of the second trench, which is the second width L2, L2 It is 15nm～50nm.

The second width is smaller than the first width, and the width of the second plug portion in the direction from the source-drain doped layer on one side of the gate structure 220 to the source-drain doped layer on the other side is smaller than that of the first plug portion.

The difference between the first width L1 and the second width L2 is 2 nm˜12 nm.

The first distance L3 is 20 nm˜100 nm.

The second distance L4 is 22 nm˜112 nm.

The difference between the second distance L4 and the first distance L3 is 2 nm˜12 nm.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined by the claims.

Claims (13)

1. a semiconductor device, is characterized in that, comprises: a base, the base has a fin, and the fin includes a first fin, and a second fin and a third fin adjacent to the first fin; an isolation structure located in the base, the isolation structure covers part of the sidewalls of the fins of the first fin, the second fin and the third fin; a gate structure on the substrate, the gate structure extending onto the isolation structure, the gate structure spanning the first fin, the second fin and the third fin; source and drain doped layers in the first fin, the second fin and the third fin on both sides of the gate structure; Conductive structures respectively located on both sides of the gate structure, the conductive structures extend from the source and drain doped layers to the isolation structure, and the conductive structures include: A first plug portion covering the source-drain doping layer and a second plug portion covering the isolation structure, the second plug portion including a portion between the first fin portion and the second fin portion, and a first plug portion A portion between a fin and a third fin, the sidewall of the first plug has a first distance from the sidewall of the adjacent gate structure, and the sidewall of the second plug is from the adjacent gate The pole structure sidewall has a second distance, the first distance is smaller than the second distance, and the width of the first plug portion is greater than the width of the second plug portion; the first distance is 20nm˜100nm; The second distance is 22nm～112nm; The difference between the second distance and the first distance is 2 nm˜12 nm. 2 . The semiconductor device of claim 1 , wherein the width of the first plug portion is 17 nm˜62 nm. 3 . 3 . The semiconductor device of claim 2 , wherein the width of the second plug portion is 15 nm˜50 nm. 4 . 4 . The semiconductor device of claim 1 , wherein the difference between the width of the first plug portion and the width of the second plug portion is 2 nm˜12 nm. 5 . 5. A method for forming a semiconductor device, comprising: A base is provided, the base has a fin, the fin includes a first fin, and a second fin and a third fin adjacent to the first fin, the base has an isolation structure, the The isolation structure covers part of the fin sidewalls of the first fin, the second fin and the third fin; forming a gate structure on the substrate, the gate structure extending onto the isolation structure; forming source-drain doping layers in the first fin portion, the second fin portion and the third fin portion on both sides of the gate structure; Conductive structures are formed on both sides of the gate structure, the conductive structures span the source and drain doped layers and extend to the isolation structure, the conductive structures cover part of the top surface and part of the sidewall surfaces of the source and drain doped layers and part of the isolation structure surface, the conductive structure includes: A first plug portion covering the source-drain doping layer and a second plug portion covering the isolation structure, the second plug portion including a portion between the first fin portion and the second fin portion, and a first plug portion A portion between a fin and a third fin, the sidewall of the first plug has a first distance from the sidewall of the adjacent gate structure, and the sidewall of the second plug is from the adjacent gate The sidewall of the gate structure has a second distance, the first distance is smaller than the second distance, and in the direction from the source and drain doped layers on one side of the gate structure to the source and drain doped layers on the other side, the first insertion The size of the plug portion is larger than the size of the second plug portion; the first distance is 20nm˜100nm; The second distance is 22nm～112nm; The difference between the second distance and the first distance is 2 nm˜12 nm. 6 . The method for forming a semiconductor device according to claim 5 , wherein the difference between the width of the first plug portion and the width of the second plug portion is 2 nm˜12 nm. 7 . 7 . The method for forming a semiconductor device according to claim 5 , wherein, before forming the conductive structure, a dielectric layer is formed on the isolation structure, the gate structure and the source-drain doping layer, and the dielectric layer covers the gate. 8 . the top surface of the pole structure; the conductive structure is located within the dielectric layer. 8. The method for forming a semiconductor device according to claim 7, wherein the method for forming the conductive structure comprises: forming trenches across the source and drain doped layers in the dielectric layers on both sides of the gate structure, The extension direction of the trench is parallel to the extension direction of the gate structure, the trench exposes part of the top surface and part of the sidewall surface of the source-drain doped layer and part of the surface of the isolation structure, the trench includes a first trench region and a second trench region, the first trench region exposes part of the top surface and part of the sidewall surface of the source-drain doped layer, the second trench region exposes part of the surface of the isolation structure, the second trench side The wall is recessed relative to the sidewall of the first trench; a first plug portion is formed in the first trench, and a second plug portion is formed in the second trench. 9 . The method for forming a semiconductor device according to claim 8 , wherein the method for forming the trench comprises: forming a first patterned mask layer on the dielectric layer, and the first patterned mask layer is exposed. 10 . The position and shape of the trench are etched using the first patterned mask layer as a mask to expose part of the surface of the source-drain doping layer and part of the surface of the isolation structure. A trench spanning the source and drain doped layers along the extension direction of the gate structure is formed in the dielectric layer on the side. 10 . The method for forming a semiconductor device according to claim 8 , wherein the method for forming the trench comprises: forming an initial trench in the dielectric layer, the initial trench exposing a portion of the source-drain doped layer. 11 . The part of the top surface and part of the sidewall surface is the initial first trench, the part of the initial trench that exposes part of the surface of the isolation structure is the second trench, the initial first trench is adjacent to the second trench, the initial first trench is The sidewall of a trench is flush with the sidewall of the second trench; after the initial trench is formed, the initial first trench is processed so that the sidewall of the initial first trench is perpendicular to the gate along the sidewall of the second trench relative to the sidewall of the second trench. The extension direction of the pole structure and the width of the direction perpendicular to the surface of the substrate are widened to form a first trench. 11. The method for forming a semiconductor device according to claim 10, wherein the method for forming the initial trench comprises: forming a second patterned mask layer on the dielectric layer, using the second patterned mask The layer is a mask, and the dielectric layer is etched to expose part of the surface of the source-drain doping layer and part of the surface of the isolation structure, and the dielectric layer on both sides of the gate structure is formed to cross the source-drain dopant along the extension direction of the gate structure. The initial trench of the impurity layer, the part of the initial trench that exposes part of the top surface and part of the sidewall surface of the source-drain doping layer is the initial first trench, and the part of the trench that exposes the part of the surface of the isolation structure is the first trench. Two trenches, the initial first trench is adjacent to the second trench, and the sidewall of the initial first trench is flush with the sidewall of the second trench. 12. The method for forming a semiconductor device according to claim 8, wherein the method for forming the trench comprises: forming a third patterned mask layer on the dielectric layer, the third patterned mask layer Determined at the position of the first trench, using the third patterned mask layer as a mask, the dielectric layer is etched until part of the surface of the source-drain doped layer and part of the surface of the isolation structure are exposed, forming the first step. a trench; after the first trench is formed, a fourth patterned mask layer is formed on the first trench and the third patterned mask layer, and the fourth patterned mask layer is positioned on the second trench At the position where the fourth patterned mask layer is used as a mask, the dielectric layer is etched until a part of the surface of the isolation structure is exposed to form a second trench. 13 . The method for forming a semiconductor device according to claim 8 , wherein the method for forming the first plug portion in the first trench, and the method for forming the second plug portion in the second trench comprises: A plug material layer is formed in a groove and a second groove; after the plug material layer is formed, the plug material layer is planarized to expose the surface of the dielectric layer, and a first plug portion is formed in the first groove, A second plug portion is formed in the second groove.

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