CN110164968B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

Info

Publication number
CN110164968B
CN110164968B CN201810141390.2A CN201810141390A CN110164968B CN 110164968 B CN110164968 B CN 110164968B CN 201810141390 A CN201810141390 A CN 201810141390A CN 110164968 B CN110164968 B CN 110164968B
Authority
CN
China
Prior art keywords
layer
groove
source
forming
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810141390.2A
Other languages
Chinese (zh)
Other versions
CN110164968A (en
Inventor
周飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, SMIC Advanced Technology R&D Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201810141390.2A priority Critical patent/CN110164968B/en
Publication of CN110164968A publication Critical patent/CN110164968A/en
Application granted granted Critical
Publication of CN110164968B publication Critical patent/CN110164968B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device and a method of forming the same, wherein the semiconductor device comprises: a substrate; an isolation structure located within the substrate; a gate structure on the substrate and extending onto the isolation structure; source-drain doped layers positioned in the substrates at two sides of the grid structure; the conducting structure who is located grid structure both sides respectively, conducting structure extends to isolation structure from source-drain doping layer on, conducting structure includes: the first plug portion of covering source leakage doping layer and the second plug portion of covering isolation structure, the lateral wall of first plug portion has first distance to adjacent grid structure lateral wall, the lateral wall of second plug portion has the second distance to adjacent grid structure lateral wall, first distance is less than the second distance, and the width of first plug portion is greater than the width of second plug portion. The performance of the semiconductor device is improved.

Description

Semiconductor device and method of forming the same
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
MOS (metal-oxide-semiconductor) transistors are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; a gate structure located on a surface of a semiconductor substrate, the gate structure comprising: the gate electrode layer is positioned on the surface of the gate dielectric layer; and the source-drain doped layers are positioned in the semiconductor substrate at two sides of the grid structure.
With the development of semiconductor technology, the conventional planar MOS transistor has a weak ability to control channel current, resulting in a serious leakage current. A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from the surface of a semiconductor substrate, a gate structure covering a portion of the top surface and sidewalls of the Fin portion, and source-drain doped layers in the Fin portion located on both sides of the gate structure.
However, the performance of the semiconductor device formed by the finfet in the prior art still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of the semiconductor device.
To solve the above technical problem, the present invention provides a semiconductor device, comprising: a substrate; an isolation structure located within the substrate; the grid structure is positioned on the substrate and extends to the isolation structure; source and drain doping layers positioned in the substrates at two sides of the grid structure; the conducting structure that is located grid structure both sides respectively, the conducting structure extends to the isolation structure on from source drain doping layer, the conducting structure includes: the first plug portion of covering source leakage doping layer and the second plug portion of covering isolation structure, the lateral wall of first plug portion has first distance to adjacent grid structure lateral wall, the lateral wall of second plug portion has the second distance to adjacent grid structure lateral wall, first distance is less than the second distance, and the width of first plug portion is greater than the width of second plug portion.
Optionally, the width of the first plug portion is 17nm to 62 nm.
Optionally, the width of the second plug portion is 15nm to 50 nm.
Optionally, a difference between the width of the first plug portion and the width of the second plug portion is 2nm to 12 nm. Optionally, the first distance is 20nm to 100 nm.
Optionally, the second distance is 22nm to 112 nm.
Optionally, the difference between the second distance and the first distance is 2nm to 12 nm.
The invention also provides a method for forming a semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate is provided with an isolation structure; forming a gate structure on the substrate, wherein the gate structure extends to the isolation structure; forming source and drain doping layers in the substrate on two sides of the grid structure; form conductive structure in grid structure both sides, conductive structure crosses source-drain doping layer and extends to on the isolation structure, conductive structure covers source-drain doping layer part top surface and partial lateral wall surface and isolation structure part surface, the wire structure includes: the first plug portion of covering source leakage doping layer and the second plug portion of covering isolation structure, the lateral wall of first plug portion has first distance to adjacent grid structure lateral wall, the lateral wall of first plug portion has the second distance to adjacent grid structure lateral wall, first distance is less than the second distance, and in the direction from the source leakage doping layer of grid structure one side to the source leakage doping layer of opposite side, the size of first plug portion is greater than the size of second plug portion.
Optionally, a difference between the width of the first plug portion and the width of the second plug portion is 2nm to 12 nm.
Optionally, before forming the conductive structure, forming a dielectric layer on the isolation structure, the gate structure and the source-drain doping layer, wherein the dielectric layer covers the top surface of the gate structure; the conductive structure is located within the dielectric layer.
Optionally, the forming method of the conductive structure includes: forming a groove crossing the source drain doping layer in the dielectric layers on two sides of the grid structure, wherein the extending direction of the groove is parallel to the extending direction of the grid structure, the groove exposes partial top surface and partial side wall surface of the source drain doping layer and partial surface of the isolation structure, the groove comprises a first groove area and a second groove area, the first groove area exposes partial top surface and partial side wall surface of the source drain doping layer, the second groove area exposes partial surface of the isolation structure, and the side wall of the second groove is sunken relative to the side wall of the first groove; a first plug portion is formed in the first trench, and a second plug portion is formed in the second trench.
Optionally, the forming method of the trench includes: and forming a first graphical mask layer on the dielectric layer, wherein the first graphical mask layer exposes the position and the shape of the groove, etching the dielectric layer by taking the first graphical mask layer as a mask, exposing partial surface of the source-drain doping layer and partial surface of the isolation structure, and forming a groove crossing the source-drain doping layer along the extension direction of the gate structure in the dielectric layers at two sides of the gate structure.
Optionally, the forming method of the trench includes: forming an initial trench in the dielectric layer, wherein the part of the initial trench, which exposes the partial top surface and partial side wall surface of the source-drain doping layer, is an initial first trench, the part of the initial trench, which exposes the partial surface of the isolation structure, is a second trench, the initial first trench is adjacent to the second trench, and the side wall of the initial first trench is flush with the side wall of the second trench; after the initial groove is formed, the initial first groove is processed, so that the width of the side wall of the initial first groove relative to the side wall of the second groove along the direction vertical to the extension direction of the gate structure and the direction vertical to the surface of the substrate is widened, and the groove is formed.
Optionally, the forming method of the initial trench includes: and etching the dielectric layer by taking the second graphical mask layer as a mask, exposing partial surface of the source-drain doping layer and partial surface of the isolation structure, forming an initial groove crossing the source-drain doping layer along the extension direction of the gate structure in the dielectric layers at two sides of the gate structure, exposing the part of the top surface and partial side wall surface of the source-drain doping layer of the initial groove as an initial first groove, exposing the part of the surface of the isolation structure of the groove as a second groove, wherein the initial first groove is adjacent to the second groove, and the side wall of the initial first groove is flush with the side wall of the second groove.
Optionally, the forming method of the trench includes: forming a third graphical mask layer on the dielectric layer, wherein the third graphical mask layer is positioned at the position where the first groove is formed, and etching the dielectric layer by taking the third graphical mask layer as a mask until part of the surface of the source-drain doping layer and part of the surface of the isolation structure are exposed to form a first groove; and after the first groove is formed, forming a fourth graphical mask layer on the first groove and the third graphical mask layer, wherein the fourth graphical mask layer is positioned at the position of the second groove, and etching the dielectric layer by taking the fourth graphical mask layer as a mask until the partial surface of the isolation structure is exposed to form the second groove, thereby forming the groove.
Optionally, the method of forming the first plug portion in the first trench and forming the second plug portion in the second trench includes: forming a plug material layer in the first trench and the second trench; and after the plug material layer is formed, flattening the plug material layer to expose the surface of the dielectric layer, forming a first plug part in the first groove and forming a second plug part in the second groove.
Optionally, the first distance is 20nm to 100 nm.
Optionally, the second distance is 22nm to 112 nm.
Optionally, the difference between the second distance and the first distance is 2nm to 12 nm.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the semiconductor device provided by the invention, the first plug part covering the source-drain doping layer and the second plug part covering the isolation structure are far away from the adjacent grid structure, and the second parasitic capacitance between the second plug part and the grid structure is small. The first plug portion is large in size, the contact area of the first plug portion and the source-drain doping layer is large, and the contact resistance of the first plug portion and the source-drain doping layer is small. The parasitic capacitance of the semiconductor device is composed of the first parasitic capacitance and the second parasitic capacitance, and by controlling the sizes of the first plug portion and the second plug portion, smaller parasitic capacitance and smaller contact resistance can be obtained, so that the performance of the device is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor device formation process;
fig. 2 to 12 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of semiconductor devices formed by the prior art is poor.
Fig. 1 is a schematic structural view of a semiconductor device formation process.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 has a fin 110 and an isolation structure, and the isolation structure covers a portion of a sidewall of the fin 110; forming a gate structure 120, a source-drain doping layer and a dielectric layer, wherein the gate structure 110 is positioned on the substrate 100 and transversely spans the fin portion 110, the source-drain doping layer is positioned in the fin portion 110 at two sides of the gate structure 120, and the dielectric layer is positioned on the source-drain doping layer and the gate structure 120; forming through holes extending from the source-drain doping layer to the isolation structure and exposing partial surfaces of the source-drain doping layer and the isolation structure in the dielectric layers on two sides of the gate structure 120; a plug 130 is formed within the via.
The grid structure and the plug are isolated by a dielectric layer, a parasitic capacitor is formed between the grid structure and the plug, the parasitic capacitor consists of two parts, namely a parasitic capacitor between the plug and the grid structure above the source-drain doping layer and a parasitic capacitor between the plug and the grid structure above the isolation structure. And the resistance between the source drain doped layer and the plug is contact resistance.
The plug is provided with a width along the extending direction of the fin part and a width perpendicular to the surface direction of the substrate, and the width of the plug, which is positioned on the surface of the source drain doping layer, is consistent with that of the plug, which is positioned on the surface of the isolation structure. The larger the width of the plug positioned on the source drain doping layer is, the smaller the contact resistance between the source drain doping layer and the plug is, the closer the distance between the plug and the grid structure is, and the larger the parasitic capacitance between the plug and the grid structure is. Therefore, in order to balance the contact resistance and the parasitic capacitance of the semiconductor device, the width of the plug is constant, the contact resistance between the source-drain doping layer and the plug is large, the parasitic capacitance between the plug and the gate structure is also large, and the semiconductor performance is poor.
The invention reduces the parasitic capacitance and the parasitic resistance of the semiconductor device by different designs of the size of the plug positioned on the source-drain doped layer region and the size of the plug on the isolation structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 12 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 2, a substrate is provided.
In this embodiment, the semiconductor device is exemplified as a fin field effect transistor, and in other embodiments, the semiconductor device is a planar MOS transistor.
In this embodiment, the base includes a semiconductor substrate 200 and a fin 210 on the semiconductor substrate 200. In other embodiments, when the semiconductor device is a planar MOS transistor, the base is a planar semiconductor substrate.
In this embodiment, the semiconductor substrate 200 further has an isolation structure 201 thereon, the isolation structure 201 covers a portion of the sidewall of the fin 210, and a top surface of the isolation structure 201 is lower than a top surface of the fin 210. The material of the isolation structure 201 includes silicon oxide.
Continuing to refer to fig. 2, a gate structure 220, a source-drain doping layer 250 and a dielectric layer are formed, the gate structure 220 is located on the substrate, the source-drain doping layer 250 is located in the substrate at two sides of the gate structure 220, the dielectric layer is located on the source-drain doping layer 250 and the gate structure 220, and source-drain ions are located in the source-drain doping layer 250.
In this embodiment, the gate structure 220 includes an interface layer on the substrate, a gate dielectric layer on the interface layer, and a gate electrode layer on the gate dielectric layer. The interface layer is made of silicon oxide, the gate dielectric layer is made of a high-K (K is larger than 3.9) dielectric material, and the gate electrode layer is made of metal such as tungsten. In other embodiments, the gate structure 220 further comprises a gate protection layer on top of the body of the gate structure 220.
In the present embodiment, gate structure 220 spans fin 210 and covers a portion of the top surface and a portion of the sidewall surface of fin 210. The gate dielectric layer is located on a portion of the surface of the isolation structure 201, a portion of the top surface of the covering fin 210, and a portion of the sidewall surface.
In this embodiment, the substrate further includes a first sidewall 221 located on a sidewall of the gate structure 220 and a second sidewall 222 located on a sidewall of the first sidewall 221.
The dielectric layers include a bottom dielectric layer 240 and a top dielectric layer 241, the bottom dielectric layer 240 is located on the substrate and covers the sidewall of the gate structure 220, and the top dielectric layer 241 is located on the bottom dielectric layer 240 and the gate structure 220.
Specifically, a dummy gate structure 220 is formed on the substrate; sequentially forming a first sidewall 221 and a second sidewall 222 on sidewalls of the dummy gate structure 220; forming a source-drain doping layer 250 in the substrate at two sides of the dummy gate structure 220 and the second sidewall 222; after the source-drain doping layer 250 is formed, an initial protection layer is formed on the source-drain doping layer 250 and the substrate, and the initial protection layer covers the side wall and the top surface of the second side wall 222 and the top surface of the dummy gate structure 220; after the protective layer is formed, an initial bottom dielectric layer is formed on the source-drain doping layer 250 and the surface of the protective layer on the surface of the substrate; after the initial bottom dielectric layer is formed, flattening the initial bottom dielectric layer until the top surface of the dummy gate structure 220 is exposed, forming a bottom dielectric layer 240 and a protection layer 230, wherein the bottom dielectric layer 240 covers the side wall of the second sidewall 222 and exposes the top surface of the second sidewall 22 and the top surface of the dummy gate structure 220; after the bottom dielectric layer 240 is formed, the dummy gate structure 220 is removed, and a gate opening is formed in the bottom dielectric layer 240; forming a gate structure 220 in the gate opening; a top dielectric layer 241 is formed on the gate structure 220, the bottom dielectric layer 240, the first sidewall 221 and the second sidewall 222.
The bottom dielectric layer 240 and the top dielectric layer 241 are made of silicon oxide.
The protection layer 230 protects the source-drain doped layer when a second trench is formed subsequently.
The material of the protection layer 230 is different from that of the dielectric layer. The material of the protective layer comprises: silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the material of the protection layer 230 is silicon nitride. The dielectric layer is made of silicon oxide, silicon nitride has a good etching selection ratio relative to silicon oxide, and when the dielectric layer is etched subsequently, the silicon oxide can be removed, the silicon nitride is etched less, and the source-drain doped layer can be well protected.
The source-drain doping layer 250 is located in the substrate at two sides of the gate structure 220, and specifically, the source-drain doping layer 250 is located in the fin portion 210 at two sides of the gate structure 220.
The source drain doped layer 250 has source drain ions.
When the type of the semiconductor device is N type, the conductivity type of the source and drain ions is N type, such as phosphorus ions; when the type of the semiconductor device is P type, the conductivity type of the source and drain ions is P type, such as boron ions.
In this embodiment, the source-drain doping layer 250 is formed by an epitaxial growth process. Correspondingly, when the type of the semiconductor device is N-type, the source-drain doping layer 250 is made of silicon with source-drain ions; when the type of the semiconductor device is P-type, the source-drain doping layer 250 is made of silicon germanium with source-drain ions. In other embodiments, the source drain doped layer 250 is formed using an ion implantation process.
And forming a groove crossing the source-drain doped layer in the dielectric layers on two sides of the grid structure, wherein the extending direction of the groove is consistent with the extending direction of the grid structure, and the groove exposes the top surface and partial side wall surface of the source-drain doped layer part and partial surface of the isolation structure.
Please refer to fig. 3 to fig. 6 for a method for forming the trench.
Referring to fig. 3, a first patterned mask layer 231 is formed on the dielectric layer, and the first patterned mask layer 231 exposes the position and shape of the trench 260 to be formed subsequently.
In this embodiment, the step of forming the first patterned mask layer 231 includes: forming a first mask layer (not shown) on the dielectric layer; after the first mask layer is formed, exposure processing is performed on the first mask layer, the exposure template is a graphical template, the position and the shape of a groove to be formed subsequently are exposed through the graphical template, the first mask layer is developed, the position and the shape of the groove to be formed subsequently are exposed, and the first graphical mask layer 231 is formed.
The material of the first patterned mask layer 231 includes photoresist.
In an embodiment, the first patterned mask layer 231 is made of silicon nitride. The step of forming the first patterned mask layer 231 includes: forming an initial mask layer (not shown) on the dielectric layer; after the initial mask layer is formed, a patterning layer is formed on the initial mask layer, the patterning layer exposes the position and the shape of a trench to be formed subsequently, and the patterning layer is used as a mask to etch the initial mask layer to form a first patterning mask layer 231. The material of the imaging layer comprises photoresist.
The first patterned mask layer 231 determines the shape and size of a subsequently formed trench in which a conductive structure is subsequently formed, i.e., the first patterned mask layer 231 determines the shape and size of the subsequently formed conductive structure.
Referring to fig. 4 and 5, fig. 5 is a top view of the semiconductor device, fig. 4 is a cross-sectional view of fig. 5 along a direction of a tangent line a-a1, after a first patterned mask layer 231 is formed, the dielectric layer is etched by using the first patterned mask layer 231 as a mask, a portion of the surface of the source-drain doping layer 250 and a portion of the surface of the isolation structure 201 are exposed, and a trench 260 is formed in the dielectric layer at two sides of the gate structure 220.
The extending direction of the trench 260 is the same as the extending direction of the gate structure 220, and the trench 260 exposes a part of the top surface and a part of the sidewall surface of the source-drain doping layer 250 and a part of the surface of the isolation structure 201.
The part of the trench 260, which exposes part of the top surface and part of the sidewall surface of the source-drain doping layer 250, is a first trench region 261, the part of the trench 260, which exposes part of the surface of the isolation structure, is a second trench region 262, the first trench region 261 is adjacent to the second trench region 262, and the sidewall of the second trench region 262 is recessed relative to the sidewall of the first trench region 261.
The width of the first trench region 261 in the direction from the source-drain doping layer 250 on one side of the gate structure 220 to the source-drain doping layer 250 on the other side is a first width, the width of the second trench region 262 in the direction from the source-drain doping layer 250 on one side of the gate structure 220 to the source-drain doping layer 250 on the other side is a second width, and the second width is smaller than the first width.
A first plug portion 301 is subsequently formed in the first trench region 261, and a second plug portion 302 is subsequently formed in the second trench region 262. The positions and widths of the first and second trench regions 261 and 262 determine the positions and widths of the subsequently formed first and second plug portions 301 and 302.
The distance from the center of the trench 260 to the center of the gate structure 220 is fixed, the width of the second trench region 262 on the isolation structure 201 is narrow, the second plug portion 302 formed subsequently is far from the gate structure 220, the second parasitic capacitance between the second plug portion 302 and the gate structure 220 is small, meanwhile, the width of the first trench region 261 on the source-drain doping layer 250 is wide, the contact area between the first plug portion 301 formed subsequently and the source-drain doping layer 250 is large, and the contact resistance is small. The parasitic capacitance of the semiconductor device is composed of the first parasitic capacitance and the second parasitic capacitance, and by controlling the sizes of the first plug portion 301 and the second plug portion 302, a small parasitic capacitance and a small contact resistance can be obtained, thereby improving the performance of the semiconductor device.
Specifically, in the method for forming the trench 260, the etching of the dielectric layers is to etch the dielectric layers on two sides of the gate structure 220, and the trench 260 is formed in the dielectric layers on two sides of the gate structure 220.
The process of etching the dielectric layers on both sides of the gate structure 220 includes an anisotropic dry etching process.
In this embodiment, the parameters of etching the dielectric layers on both sides of the gate structure 220 by using the anisotropic dry etching process include: the gas used comprises CF 4 Gas, CH 3 F gas and O 2 ，CF 4 The flow rate of the gas is 5 sccm-100 sccm, CH 3 The flow rate of the F gas is 8-50 sccm, O 2 The flow rate of the gas source is 10-100 sccm, the pressure of the chamber is 10-2000 mtorr, the radio frequency power is 50-300W, the voltage is 30-100V, and the time is 4-50 seconds.
In other embodiments, the method for forming the trench 260 may also be a two-mask formation.
In one embodiment, the method for forming the trench 260 includes: forming an initial trench in the dielectric layer, wherein the part of the initial trench, which exposes part of the top surface and part of the sidewall surface of the source-drain doping layer 250, is an initial first trench, the part of the initial trench, which exposes part of the surface of the isolation structure 201, is a second trench region 262, the initial first trench is adjacent to the second trench region 262, and the sidewall of the initial first trench is flush with the sidewall of the second trench region 262; after the initial trench is formed, the initial first trench is processed, so that the width of the sidewall of the initial first trench, relative to the sidewall of the second trench region 262, in the direction from the source-drain doped layer 250 on one side of the gate structure 220 to the source-drain doped layer 250 on the other side is widened, and a first trench region 261 is formed, thereby forming the trench 260.
The forming method of the initial groove comprises the following steps: and etching the dielectric layer by taking the second patterned mask layer as a mask, exposing partial surfaces of the source-drain doping layer 250 and the isolation structure, forming an initial groove crossing the source-drain doping layer 250 along the extension direction of the body 220 of the gate structure 220 in the dielectric layer on two sides of the gate structure 220, exposing partial top surfaces and partial side wall surfaces of the source-drain doping layer 250 to form an initial first groove, exposing partial surfaces of the isolation structure 201 to form a second groove area 262, wherein the initial first groove is adjacent to the second groove area 262, and the side wall of the initial first groove is flush with the side wall of the second groove area 262.
The shape of the graph in the second graphical mask layer is a rectangle.
In another embodiment, the method for forming the trench 260 includes: forming a third patterned mask layer on the dielectric layer, wherein the third patterned mask layer is fixed at the position of the first trench region 261, and etching the dielectric layer by taking the third patterned mask layer as a mask until the partial surface of the source drain doped layer and the partial surface of the isolation structure are exposed to form the first trench region 261; after the first trench area 261 is formed, a fourth patterned mask layer is formed on the first trench area 261 and the third patterned mask layer, the fourth patterned mask layer is located at a position where the second trench is formed, the dielectric layer is etched by taking the fourth patterned mask layer as a mask until part of the surface of the isolation structure 201 is exposed, and a second trench area 262 is formed, so that the trench 260 is formed.
Referring to fig. 6, after the trench 260 is formed, the first patterned mask layer 231 is removed.
The process of removing the first patterned mask layer 231 includes an ashing process.
In this embodiment, the forming process of the trench 260 further includes: after the first patterned mask layer 231 is removed, the protection layer 230 on the surface of the source/drain doping layer 250 exposed by the first trench region 261 is removed by etching, and the surface of the source/drain doping layer 250 is exposed. In other embodiments, the protection layer 230 is not formed on the surface of the source-drain doped layer 250, and the protection layer 230 does not need to be removed.
The first patterned mask layer 231 is removed and then the protection layer 230 is removed, so that the influence of the ashing process on the source drain doping layer 250 can be avoided.
The process of removing the protection layer 230 on the surface of the source-drain doping layer 250 exposed by the first trench region 261 by etching is an isotropic dry etching process, and the process parameters include: the gas used comprises CF 4 Gas, CH 2 F 2 Gas and O 2 ，CF 4 The flow rate of the gas is 30 sccm-200 sccm, CH 2 F 2 The flow rate of the gas is 8-50 sccm, O 2 The flow rate of the gas source is 2-30 sccm, the pressure of the chamber is 10-2000 mtorr, the radio frequency power is 100-1000W, the direct current is 30-500V, and the time is 4-50 seconds.
Referring to fig. 7, after forming the trench 260, a metal layer 270 is formed on the bottom surface and the sidewall surface of the trench 260.
The material of the metal layer 270 includes Ti, Co, or Ni.
The metal layer 270 is also located on the dielectric layer.
The process of forming the metal layer 270 is a deposition process, such as a sputtering process.
Referring to fig. 8, after the metal layer 270 is formed, annealing is performed on the metal layer 270 and the source/drain doping layer 250, and a metal silicide layer 280 is formed on the surface of the source/drain doping layer 250 exposed by the first trench region 261.
In this embodiment, during the annealing process, atoms of the metal layer 270 diffuse into the source/drain doping layer 250 and react with the source/drain doping layer 250 to form the metal silicide layer 280.
The annealing treatment further comprises the following functions: the second ions in the source drain doped layer 250 are activated.
In this embodiment, since the surface material of the source-drain doping layer 250 is doped with the source drain ions, the metal silicide layer 280 is doped with the source drain ions, which reduces the resistance of the metal silicide layer 280.
The annealing treatment includes laser annealing or spike annealing.
The benefits of using laser annealing or spike annealing for the annealing process include: the laser annealing and the peak annealing are faster in temperature rising process, so that ions in a doped region of the semiconductor device are prevented from being diffused greatly in the temperature rising process, and the stability of the doped region is improved.
In this embodiment, before the subsequent annealing process, a barrier layer (not shown) is further formed on the surface of the metal layer 270. The material of the barrier layer comprises titanium nitride or tantalum nitride. The process of forming the barrier layer is a deposition process, such as a sputtering process.
In this embodiment, the barrier layer is formed before the annealing process, and in the annealing process, the barrier layer can protect the metal layer 270 and prevent the annealing process from oxidizing the metal layer 270.
In one embodiment, the annealing temperature is selected to be less than 900 degrees celsius in order to prevent the material of the barrier layer from recrystallizing and causing poor stability of the barrier layer.
In other embodiments, the barrier layer is formed after annealing.
In other embodiments, no barrier layer is formed.
Referring to fig. 9, after an annealing process is performed, a layer 290 of conductive structure material is formed within the trenches 260 (see fig. 8) and on the dielectric layer.
In this embodiment, the conductive structure material layer 290 is located on the surface of the barrier layer.
The material of the conductive structure material layer 290 is a metal, such as tungsten.
The process of forming the conductive structure material layer 290 is a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Referring to fig. 10 to 12, fig. 10 is a top view of the device, fig. 11 is a cross-sectional view taken along a line a-a1 of fig. 10, and fig. 12 is a cross-sectional view taken along a line a2-A3 of fig. 10. The conductive structure material layer 290 is planarized to expose the top surface of the dielectric layer, thereby forming the conductive structure 300.
The extending direction of the conductive structure 300 is consistent with the extending direction of the gate structure 220, and the conductive structure 300 covers part of the top surface and part of the sidewall surface of the source-drain doping layer 250 and part of the surface of the isolation structure 201; the part of the conductive structure 300 covering the partial top surface and partial side wall surface of the source-drain doping layer 250 is a first plug portion 301, the part of the conductive structure 300 covering the surface of the isolation structure 201 is a second plug portion 302, the first plug portion 301 is adjacent to the second plug portion 302, and the side wall of the second plug portion 302 is recessed relative to the side wall of the first plug portion 301.
In this embodiment, the conductive structure material layer 290 and the metal layer 270 are planarized until the top surface of the dielectric layer is exposed, so that the conductive structure material layer 290 in the first trench region 261 forms the first plug 301, and the conductive structure material layer 290 in the second trench region 262 forms the second plug 302.
The distance from the sidewall of the first plug portion 301 to the sidewall of the adjacent gate structure 220 is a first distance, the distance from the sidewall of the second plug portion 302 to the sidewall of the adjacent gate structure 220 is a second distance, and the first distance is smaller than the second distance.
The sidewall of the first plug 301 has a first distance L3 from the sidewall of the adjacent gate structure 220, and L3 is 20 nm-100 nm
The sidewall of the second plug portion 302 has a second distance L4 from the sidewall of the adjacent gate structure 220, and L4 is 22nm to 112 nm.
The difference between the first distance L3 and the second distance L4 is 2 nm-12 nm.
The distance between the conductive structure 300 and the gate structure 220 affects the magnitude of parasitic capacitance therebetween, the second plug portion 302 is further away from the adjacent gate structure 220, and the second parasitic capacitance between the second plug portion 302 and the gate structure 220 is smaller; the first plug portion 301 is closer to the adjacent gate structure 220, and the first parasitic capacitance with the gate structure 220 is larger; the parasitic capacitance of the semiconductor device is composed of a first parasitic capacitance and a second parasitic capacitance, and the size of the first plug part 301 and the second plug part 302 is controlled, so that the semiconductor device can obtain smaller parasitic capacitance, and the performance of the semiconductor device is improved.
The difference between the first distance L3 and the second distance L4 is determined by the width difference between the first plug 301 and the second plug 302 in the direction from the source-drain doped layer on one side of the gate structure 220 to the source-drain doped layer on the other side.
The width of the first plug 301 in the direction from the source-drain doping layer on one side of the gate structure 220 to the source-drain doping layer on the other side is the same as the width of the first trench region 261, and is a first width L1, and L1 is 17nm to 62 nm.
The width of the second plug portion 302 in the direction from the source-drain doped layer on one side of the gate structure 220 to the source-drain doped layer on the other side is the same as the width of the second trench region 262, i.e., the second width L2, and L2 is 15nm to 50 nm.
The second width is smaller than the first width, and the width of the second plug portion in the direction from the source-drain doped layer on one side of the gate structure 220 to the source-drain doped layer on the other side is smaller than the width of the first plug portion.
The difference between the first width and the second width is 2nm to 12 nm.
When the difference between the first width and the second width is greater than 12nm, the parasitic resistance of the second plug portion 292 is too large, which is not favorable for the performance of the device, and when the difference between the first width and the second width is less than 2nm, the improvement of the parasitic capacitance between the second plug portion 292 and the gate structure 220 is not obvious, and the performance of the device is not significantly improved.
The distance from the center of the conductive structure 300 to the center of the gate structure 220 is fixed, the width of the second plug portion 302 on the isolation structure is narrow, the second plug portion is far away from the gate structure 220, the second parasitic capacitance between the second plug portion 302 and the gate structure 220 is small, meanwhile, the width of the first plug portion 301 on the source-drain doping layer 250 is wide, the contact area between the first plug portion 301 and the source-drain doping layer 250 is large, and the contact resistance is small. The parasitic capacitance of the semiconductor device is composed of a first parasitic capacitance and a second parasitic capacitance, and by controlling the sizes of the first plug portion 301 and the second plug portion 302, a smaller parasitic capacitance and a smaller contact resistance can be obtained, thereby improving the performance of the device.
Accordingly, the present embodiment further provides a structure of a semiconductor device, referring to fig. 10 to 12, including: providing a substrate; an isolation structure 201 located within the substrate; a gate structure 220 located on the substrate, wherein the gate structure 220 extends to the isolation structure 201; source-drain doped layers 250 in the substrate on both sides of the gate structure 220; the conductive structures 300 are respectively located on two sides of the gate structure 220, the conductive structures 300 extend from the source-drain doping layer 250 to the isolation structure 201, and the conductive structures 300 include: the first plug portion 301 covering the source-drain doping layer 250 and the second plug portion 302 covering the isolation structure 201, a first distance is formed between the side wall of the first plug portion 301 and the side wall of the adjacent gate structure 220, a second distance is formed between the side wall of the second plug portion 302 and the side wall of the adjacent gate structure 220, the first distance is smaller than the second distance, and in the direction from the source-drain doping layer 250 on one side of the gate structure 220 to the source-drain doping layer 250 on the other side, the size of the first plug portion 301 is larger than that of the second plug portion 302.
The width of the first plug 301 in the direction from the source-drain doped layer on one side of the gate structure 220 to the source-drain doped layer on the other side is the same as the first width L1, and L1 is 17nm to 62 nm.
The width of the second plug portion 302 in the direction from the source-drain doped layer on one side of the gate structure 220 to the source-drain doped layer on the other side is the same as the second trench and is a second width L2, and L2 is 15nm to 50 nm.
The second width is smaller than the first width, and the width of the second plug portion in the direction from the source-drain doped layer on one side of the gate structure 220 to the source-drain doped layer on the other side is smaller than that of the first plug portion.
The difference between the first width L1 and the second width L2 is 2nm to 12 nm.
The first distance L3 is 20 nm-100 nm.
The second distance L4 is 22 nm-112 nm.
The difference between the second distance L4 and the first distance L3 is 2 nm-12 nm.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (13)

1. A semiconductor device, comprising:
the semiconductor device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate is provided with a fin part, and the fin part comprises a first fin part, a second fin part and a third fin part which are adjacent to the first fin part;
the isolation structure is positioned in the substrate and covers partial fin part side walls of the first fin part, the second fin part and the third fin part;
the grid structure is positioned on the substrate and extends onto the isolation structure, and the grid structure stretches across the first fin part, the second fin part and the third fin part;
the source-drain doping layers are positioned in the first fin portion, the second fin portion and the third fin portion on two sides of the grid structure;
the conducting structure who is located grid structure both sides respectively, conducting structure extends to isolation structure from source-drain doping layer on, conducting structure includes:
the first plug portion covers the source-drain doping layer, and the second plug portion covers the isolation structure, the second plug portion comprises a portion located between the first fin portion and the second fin portion, and a portion located between the first fin portion and the third fin portion, a first distance is formed between a side wall of the first plug portion and a side wall of an adjacent grid structure, a second distance is formed between a side wall of the second plug portion and a side wall of an adjacent grid structure, the first distance is smaller than the second distance, and the width of the first plug portion is larger than that of the second plug portion;
the first distance is 20 nm-100 nm;
the second distance is 22 nm-112 nm;
the difference between the second distance and the first distance is 2 nm-12 nm.
2. The semiconductor device according to claim 1, wherein a width of the first plug portion is 17nm to 62 nm.
3. The semiconductor device according to claim 2, wherein a width of the second plug portion is 15nm to 50 nm.
4. The semiconductor device according to claim 1, wherein a difference between a width of the first plug portion and a width of the second plug portion is 2nm to 12 nm.
5. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises a first fin part, a second fin part and a third fin part, the second fin part and the third fin part are adjacent to the first fin part, the substrate is provided with an isolation structure, and the isolation structure covers partial fin part side walls of the first fin part, the second fin part and the third fin part;
forming a gate structure on the substrate, the gate structure extending onto the isolation structure;
forming source-drain doped layers in the first fin portion, the second fin portion and the third fin portion on two sides of the grid structure;
form conductive structure in grid structure both sides, conductive structure crosses source-drain doping layer and extends to the isolation structure on, conductive structure covers source-drain doping layer part top surface and partial lateral wall surface and isolation structure part surface, conductive structure includes:
the first plug part covers the source drain doping layer and the second plug part covers the isolation structure, the second plug part comprises a part positioned between the first fin part and the second fin part and a part positioned between the first fin part and the third fin part, a first distance is formed between the side wall of the first plug part and the side wall of the adjacent grid structure, a second distance is formed between the side wall of the second plug part and the side wall of the adjacent grid structure, the first distance is smaller than the second distance, and in the direction from the source drain doping layer on one side of the grid structure to the source drain doping layer on the other side of the grid structure, the size of the first plug part is larger than that of the second plug part;
the first distance is 20 nm-100 nm;
the second distance is 22 nm-112 nm;
the difference between the second distance and the first distance is 2 nm-12 nm.
6. The method for forming a semiconductor device according to claim 5, wherein a difference between a width of the first plug portion and a width of the second plug portion is 2nm to 12 nm.
7. The method for forming a semiconductor device according to claim 5, wherein before the conductive structure is formed, a dielectric layer is formed on the isolation structure, the gate structure and the source-drain doping layer, and the dielectric layer covers the top surface of the gate structure; the conductive structure is located within the dielectric layer.
8. The method for forming a semiconductor device according to claim 7, wherein the method for forming the conductive structure comprises: forming a groove crossing a source-drain doping layer in dielectric layers on two sides of a grid structure, wherein the extending direction of the groove is parallel to the extending direction of the grid structure, the groove exposes partial top surface and partial side wall surface of the source-drain doping layer and partial surface of an isolation structure, the groove comprises a first groove area and a second groove area, the first groove area exposes partial top surface and partial side wall surface of the source-drain doping layer, the second groove area exposes partial surface of the isolation structure, and the side wall of the second groove is sunken relative to the side wall of the first groove; a first plug portion is formed in the first trench, and a second plug portion is formed in the second trench.
9. The method for forming a semiconductor device according to claim 8, wherein the method for forming the trench comprises: and etching the dielectric layer by taking the first graphical mask layer as a mask to expose partial surfaces of the source-drain doping layer and the isolation structure, and forming a groove crossing the source-drain doping layer along the extension direction of the gate structure in the dielectric layers at two sides of the gate structure.
10. The method for forming a semiconductor device according to claim 8, wherein the method for forming the trench comprises: forming an initial trench in the dielectric layer, wherein the part of the initial trench, which exposes the partial top surface and partial side wall surface of the source-drain doping layer, is an initial first trench, the part of the initial trench, which exposes the partial surface of the isolation structure, is a second trench, the initial first trench is adjacent to the second trench, and the side wall of the initial first trench is flush with the side wall of the second trench; and after the initial groove is formed, processing the initial first groove to widen the width of the side wall of the initial first groove relative to the side wall of the second groove along the direction vertical to the extension direction of the gate structure and the direction vertical to the surface of the substrate, so as to form the first groove.
11. The method for forming a semiconductor device according to claim 10, wherein the method for forming the initial trench comprises: and etching the dielectric layer by taking the second graphical mask layer as a mask, exposing partial surface of the source-drain doping layer and partial surface of the isolation structure, forming an initial groove crossing the source-drain doping layer along the extension direction of the gate structure in the dielectric layer at two sides of the gate structure, exposing partial top surface and partial side wall surface of the source-drain doping layer by the initial groove, and taking the part of the groove, which exposes the partial surface of the isolation structure, as a second groove, wherein the initial first groove is adjacent to the second groove, and the side wall of the initial first groove is flush with the side wall of the second groove.
12. The method for forming a semiconductor device according to claim 8, wherein the method for forming the trench comprises: forming a third graphical mask layer on the dielectric layer, wherein the third graphical mask layer is positioned at the position where the first groove is formed, and etching the dielectric layer by taking the third graphical mask layer as a mask until part of the surface of the source-drain doping layer and part of the surface of the isolation structure are exposed to form a first groove; and after the first groove is formed, forming a fourth graphical mask layer on the first groove and the third graphical mask layer, wherein the fourth graphical mask layer is positioned at the position of the second groove, and etching the dielectric layer by taking the fourth graphical mask layer as a mask until the partial surface of the isolation structure is exposed to form the second groove.
13. The method for forming a semiconductor device according to claim 8, wherein the method for forming the first plug portion in the first trench and the method for forming the second plug portion in the second trench includes: forming a plug material layer in the first trench and the second trench; and after the plug material layer is formed, flattening the plug material layer to expose the surface of the dielectric layer, forming a first plug part in the first groove and forming a second plug part in the second groove.
CN201810141390.2A 2018-02-11 2018-02-11 Semiconductor device and method of forming the same Active CN110164968B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810141390.2A CN110164968B (en) 2018-02-11 2018-02-11 Semiconductor device and method of forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810141390.2A CN110164968B (en) 2018-02-11 2018-02-11 Semiconductor device and method of forming the same

Publications (2)

Publication Number Publication Date
CN110164968A CN110164968A (en) 2019-08-23
CN110164968B true CN110164968B (en) 2022-08-26

Family

ID=67635042

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810141390.2A Active CN110164968B (en) 2018-02-11 2018-02-11 Semiconductor device and method of forming the same

Country Status (1)

Country Link
CN (1) CN110164968B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113540019B (en) * 2020-04-20 2023-07-21 中芯国际集成电路制造(上海)有限公司 Variable capacitor and method for forming variable capacitor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104037226A (en) * 2013-03-08 2014-09-10 台湾积体电路制造股份有限公司 Finfet With An Asymmetric Source/drain Structure And Method Of Making Same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3048823B2 (en) * 1994-02-28 2000-06-05 日本電気株式会社 Semiconductor integrated circuit device
US9431492B2 (en) * 2014-02-21 2016-08-30 Samsung Electronics Co., Ltd. Integrated circuit devices including contacts and methods of forming the same
CN104979201B (en) * 2014-04-03 2018-03-06 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor devices
KR102238951B1 (en) * 2014-07-25 2021-04-12 에스케이하이닉스 주식회사 Semiconductor device with air gap and method for fabricating the same
KR102399023B1 (en) * 2015-06-22 2022-05-16 삼성전자주식회사 Semiconductor device
US10366989B2 (en) * 2016-02-10 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a contact bar over an S/D structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104037226A (en) * 2013-03-08 2014-09-10 台湾积体电路制造股份有限公司 Finfet With An Asymmetric Source/drain Structure And Method Of Making Same

Also Published As

Publication number Publication date
CN110164968A (en) 2019-08-23

Similar Documents

Publication Publication Date Title
JP5410666B2 (en) Semiconductor device
JP5017795B2 (en) Method for manufacturing field effect transistor
US7915167B2 (en) Fabrication of channel wraparound gate structure for field-effect transistor
US8936986B2 (en) Methods of forming finfet devices with a shared gate structure
KR101263648B1 (en) Fin field effect transistor and method of manufacturing the same
US10971590B2 (en) Transistor layout to reduce kink effect
CN111354641B (en) Semiconductor device and method of forming the same
CN109830438B (en) Semiconductor device and method of forming the same
CN108807177B (en) Semiconductor device and method of forming the same
CN110164968B (en) Semiconductor device and method of forming the same
CN109841507B (en) Semiconductor device and method of forming the same
CN107591327B (en) Method for forming fin field effect transistor
CN107579108B (en) Method for forming semiconductor structure
US11348921B2 (en) Semiconductor structure and method of manufacturing the same
CN109285811A (en) Semiconductor structure and forming method thereof
CN109285876B (en) Semiconductor structure and forming method thereof
CN109599366B (en) Semiconductor device and method of forming the same
CN109285889B (en) Semiconductor structure and forming method thereof
CN110060931B (en) Semiconductor device and method of forming the same
CN109273407B (en) Semiconductor device and method of forming the same
CN108206205B (en) Semiconductor device and method of forming the same
CN111697051A (en) Semiconductor structure and forming method thereof
CN113113310B (en) Semiconductor device and method of forming the same
CN113555284B (en) Method for forming semiconductor structure
KR100467812B1 (en) Semiconductor device and fabrication method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant