CN109599366B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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CN109599366B
CN109599366B CN201710918629.8A CN201710918629A CN109599366B CN 109599366 B CN109599366 B CN 109599366B CN 201710918629 A CN201710918629 A CN 201710918629A CN 109599366 B CN109599366 B CN 109599366B
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fin
layer
side wall
doping layer
forming
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CN109599366A (en
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李勇
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

A semiconductor device and a method of forming the same, wherein the method comprises: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first fin part; forming a first initial doping layer in the first fin portion; performing a groove treatment process to enable the first initial doping layer to form a first doping layer, wherein a groove is formed in the first doping layer, the top surface of the first doping layer is exposed out of the groove, and the side wall surfaces of the groove on the two sides in the width direction of the first fin portion are the surfaces of the first doping layer; and forming a first metal silicide layer on the outer side wall and the top surface of the first doped layer and the inner wall surface of the groove. The method improves the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
MOS (metal-oxide-semiconductor) transistors, are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; a gate structure located on a surface of a semiconductor substrate, the gate structure comprising: the gate electrode layer is positioned on the surface of the gate dielectric layer; and the source and drain doped regions are positioned in the semiconductor substrate at two sides of the grid structure.
With the development of semiconductor technology, the conventional planar MOS transistor has a weak ability to control channel current, resulting in a serious leakage current. A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source-drain doped regions in the Fin portion located at both sides of the gate structure.
However, the performance of the semiconductor device formed by the finfet in the prior art still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first fin part; forming a first initial doping layer in the first fin portion; performing a groove treatment process to enable the first initial doping layer to form a first doping layer, wherein a groove is formed in the first doping layer, the top surface of the first doping layer is exposed out of the groove, and the side wall surfaces of the groove on the two sides in the width direction of the first fin portion are the surfaces of the first doping layer; and forming a first metal silicide layer on the outer side wall and the top surface of the first doped layer and the inner wall surface of the groove.
Optionally, the method further includes: before the groove processing technology is carried out, forming first fin side walls, wherein the first fin side walls are positioned on the side walls of the first initial doping layer on the two sides of the first fin portion in the width direction and expose the top surface of the first initial doping layer; the step of performing the recess treatment process includes: etching back part of the first initial doping layer to reduce the height of the first initial doping layer, so that the first initial doping layer forms a first transition doping layer, wherein a recess positioned in the first fin part is formed in the first transition doping layer, and two side walls of the recess in the width direction of the first fin part are provided with first fin side walls; forming a mask side wall on the side wall of the recess, wherein the mask side wall is in contact with the first fin side wall; etching the first transition doping layer by taking the mask side wall and the first fin side wall as masks, so that the first transition doping layer forms the first doping layer; removing the mask side wall after etching the first transition doping layer by taking the mask side wall and the first fin side wall as masks; the method for forming the semiconductor device further comprises the following steps: removing the first fin side wall after etching the first transition doping layer by taking the mask side wall and the first fin side wall as masks; and after removing the first fin side wall and the mask side wall, forming the first metal silicide layer.
Optionally, the method further includes: before forming a first initial doping layer, forming an isolation layer covering partial side walls of a first fin part on the semiconductor substrate, wherein the first fin part exposed by the isolation layer comprises a first replacement region; the method for forming the first fin sidewall and the first initial doping layer comprises the following steps: forming a first fin side wall positioned on the surface of the isolation layer on the side wall of the first replacement region; etching to remove a first replacement region covered by the first fin side wall, forming a first initial replacement groove in the first fin part, wherein the side walls of two sides of the first initial replacement groove are respectively provided with the first fin side wall in the width direction of the first fin part; etching the first fin side wall on the inner wall of the first initial replacement groove to increase the size of the first initial replacement groove in the width direction of the first fin part to form a first replacement groove; forming the first preliminary doping layer in a first replacement trench.
Optionally, the first fin sidewall is made of SiN, siCN, siBN, or SiON; the mask side wall is made of SiN, siCN, siBN or SiON.
Optionally, the thickness of the mask side wall is 2nm to 10nm.
Optionally, the thickness of the first fin side wall is 2nm to 8nm.
Optionally, the step of forming the mask sidewall on the side wall of the recess includes: forming a mask side wall material layer on the side wall and the bottom of the recess, the surface of the first fin side wall and the semiconductor substrate; and etching the mask side wall material layer until the top surface of the first transition doping layer and the top surface of the first fin side wall are exposed to form the mask side wall.
Optionally, the process of etching the first transition doping layer by using the mask sidewall and the first fin sidewall as masks includes an anisotropic dry etching process.
Optionally, the depth of the first transition doping layer etched by using the mask sidewall and the first fin sidewall as masks occupies 20% to 100% of the thickness of the first transition doping layer.
Optionally, the depth of the back-etched part of the first initial doping layer is 3nm to 10nm.
Optionally, the first fin sidewall is removed in the process of removing the mask sidewall.
Optionally, a cross-sectional shape of the groove in the width direction of the first fin portion includes a "U" shape.
Optionally, the method further includes: before the first initial doping layer is formed, forming a first grid electrode structure crossing the first fin portion on the semiconductor substrate, wherein the first grid electrode structure covers part of the top surface and part of the side wall surface of the first fin portion; the first initial doping layers are respectively positioned in the first fin parts at two sides of the first gate structure; after the first doping layer is formed, the first doping layer is respectively located in the first fin portions on two sides of the first gate structure.
Optionally, the semiconductor substrate includes a first region and a second region, the first fin portion is located on the first region of the semiconductor substrate, and the second region of the semiconductor substrate has a second fin portion; the method for forming the semiconductor device further comprises the following steps: forming a second doped layer in the second fin portion before forming the first preliminary doped layer; and forming a second metal silicide layer on the surface of the second doped layer after the first doped layer is formed.
Optionally, the semiconductor substrate has an isolation layer covering a partial sidewall of the second fin portion, and the second fin portion exposed by the isolation layer includes a second replacement region; the method for forming the semiconductor device further comprises the following steps: forming a second fin side wall positioned on the surface of the isolation layer on the side wall of the second replacement region of the second fin part; etching to remove a second replacement region covered by the second fin side wall, forming a second initial replacement groove in the second fin portion, wherein the side walls of two sides of the second initial replacement groove are respectively provided with the second fin side wall in the width direction of the second fin portion; etching the second fin side wall of the inner wall of the second initial replacement groove to increase the size of the second initial replacement groove in the width direction of the second fin part to form a second replacement groove; forming a second doping layer in the second replacement tank; and after removing the second fin side wall on the side wall of the second doping layer, forming the second metal silicide layer.
Optionally, the first region is used to form an N-type transistor, and the second region is used to form a P-type transistor.
Optionally, after the first initial doping layer is formed and before the groove processing process is performed, a bottom dielectric layer is formed, and the bottom dielectric layer is located on the semiconductor substrate, the first initial doping layer and the second doping layer; forming a first medium opening penetrating through the bottom medium layer in the bottom medium layer, wherein the first medium opening is positioned on the first initial doping layer; forming a second dielectric opening penetrating through the bottom dielectric layer in the bottom dielectric layer, wherein the second dielectric opening is positioned on the second doping layer; after a first medium opening and a second medium opening are formed, the groove processing technology is carried out; and after the groove processing technology is carried out, a first metal silicide layer is formed on the outer side wall and the top surface of the first doping layer and the inner wall of the groove, and a second metal silicide layer is formed on the top surface and the side wall surface of the second doping layer.
Optionally, the method further includes: after the first metal silicide layer and the second metal silicide layer are formed, a first plug is formed in the first dielectric opening, and a second plug is formed in the second dielectric opening.
The present invention also provides a semiconductor device comprising: the semiconductor device comprises a semiconductor substrate, a first fin part and a second fin part, wherein the semiconductor substrate is provided with the first fin part; the first doping layer is positioned in the first fin part, a groove is formed in the first doping layer, the groove is exposed out of the top surface of the first doping layer, and the surfaces of the side walls of the groove on the two sides of the width direction of the first fin part are the surfaces of the first doping layer; and the first metal silicide layer is positioned on the outer side wall and the top surface of the first doping layer and the inner wall surface of the groove.
Optionally, a cross-sectional shape of the groove in the width direction of the first fin portion includes a "U" shape.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor device provided by the technical scheme of the invention, after the groove processing technology is carried out, the first initial doping layer is formed into the first doping layer, the first doping layer is provided with the groove, and the groove is exposed on the top surface of the first doping layer, so that the surface area of the first doping layer is larger than that of the first initial doping layer. Because the surfaces of the side walls of the groove at the two sides of the width direction of the first fin part are the surfaces of the first doping layer, the area of the side wall of the groove is larger, and the surface area of the first doping layer is larger. The area of the first metal silicide layer in contact with the first doped layer is large. The cross-sectional area in the current conduction direction from the first doped layer to the first metal silicide layer is large, and thus the contact resistance between the first metal silicide layer and the first doped layer is reduced, thereby improving the performance of the semiconductor device.
In the semiconductor device provided by the technical scheme of the invention, the first doping layer is provided with a groove, and the groove is exposed on the top surface of the first doping layer. The side wall surfaces of the groove on two sides of the width direction of the first fin part are the surfaces of the first doping layer, so that the surface area of the first doping layer is larger, and the area of the first metal silicide layer contacting with the first doping layer is larger. The cross-sectional area in the current conduction direction from the first doped layer to the first metal silicide layer is large, and thus the contact resistance between the first metal silicide layer and the first doped layer is reduced, thereby improving the performance of the semiconductor device.
Drawings
Fig. 1 to 22 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of semiconductor devices formed by the prior art is poor.
A method of forming a semiconductor device, comprising: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a fin part; forming a grid structure crossing the fin part on the semiconductor substrate; forming a source drain doping layer in fin parts of fin parts on two sides of the grid structure; forming an interlayer dielectric layer on the source-drain doping layer and the grid structure; forming openings exposing the side wall surface and the top surface of the source-drain doping layer in the interlayer dielectric layers on the two sides of the grid structure; etching the source-drain doping layer at the bottom of the opening to form a groove in the source-drain doping layer; then, forming metal silicide layers on the side wall and the top surface of the source-drain doped layer; after the metal silicide layer is formed, a plug is formed in the opening.
However, the performance of the semiconductor device formed by the method is poor, and researches show that the reason is that:
the metal silicide layer is used for reducing a contact barrier between the source drain doping layer and the plug. And forming a groove in the source drain doping layer at the bottom of the opening to increase the total surface of the source drain doping layer exposed by the opening, thereby increasing the contact area of the metal silicide layer and the source drain doping layer.
Before etching the source-drain doped layer at the bottom of the opening, the opening exposes the side wall surface and the top surface of the source-drain doped layer. After the source-drain doping layer at the bottom of the opening is etched, the formed groove at least penetrates through the source-drain doping layer in the width direction of the fin portion, namely the bottom surface of the groove is connected with the outer side wall of the source-drain doping layer in the width direction of the fin portion.
On the basis, along with the continuous reduction of the characteristic dimension of the semiconductor device, the distance between the adjacent grid structures is continuously reduced, correspondingly, the dimension of the source-drain doped region in the length direction of the channel is continuously reduced, the total area of the source-drain doped region and the metal silicide layer is reduced, and the contact resistance between the source-drain doped region and the metal silicide layer is larger.
In order to solve the above problems, the present invention provides a method of forming a semiconductor device, including: forming a first initial doping layer in the first fin portion; performing a groove treatment process to enable the first initial doping layer to form a first doping layer, wherein a groove is formed in the first doping layer, the groove is exposed out of the top surface of the first doping layer, and the surfaces of the side walls of the groove in the width direction of the first fin portion are the surfaces of the first doping layer; and forming a first metal silicide layer on the outer side wall and the top surface of the first doped layer and the inner wall surface of the groove. The method improves the performance of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 22 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 1 and fig. 2 in combination, a first region in fig. 2 is a cross-sectional view along a cutting line M1-M2 in fig. 1, and a second region in fig. 2 is a cross-sectional view along a cutting line N1-N2 in fig. 1, providing a semiconductor substrate 100 having a first fin portion 111 on the semiconductor substrate 100.
In the present embodiment, a semiconductor device is exemplified as a fin field effect transistor. In other embodiments, the semiconductor device is a transistor or a diode.
The semiconductor substrate 100 may be single crystalline silicon, polycrystalline silicon, or amorphous silicon. The semiconductor substrate 100 may be a semiconductor material such as silicon, germanium, or silicon germanium. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon.
The semiconductor substrate 100 includes a first region a, and the first fin 111 is located on the first region a of the semiconductor substrate 100. The semiconductor substrate 100 further includes a second region B. The semiconductor substrate 100 has a second fin 112 on the second region B.
In other embodiments, the semiconductor substrate does not include the second region.
In this embodiment, the first region a is used to form an N-type finfet, and the second region B is used to form a P-type finfet.
The first fin portion 111 and the second fin portion 112 are made of monocrystalline silicon or monocrystalline silicon germanium. In this embodiment, the number of the first fin portions 111 is several, and the number of the second fin portions 112 is several. In other embodiments, the number of the first fins 111 is one, and the number of the second fins 112 is one.
In this embodiment, the method further includes: an isolation layer 103 covering partial side walls of the first fin portion 111 and the second fin portion 112 is formed on the semiconductor substrate 100, and a top surface of the isolation layer 103 is lower than top surfaces of the first fin portion 111 and the second fin portion 112. The material of the isolation layer 103 comprises silicon oxide.
The first fin portion 111 exposed by the isolation layer 103 includes a first replacement region and a first non-replacement region, the first replacement region is adjacent to and located at two sides of the first non-replacement region, and a direction from the first replacement region to the first non-replacement region is parallel to an extending direction of the first fin portion 111. The second fin portion 112 exposed by the isolation layer 103 includes a second replacement region and a second non-replacement region, the second replacement region is adjacent to and located at two sides of the second non-replacement region, and a direction from the second replacement region to the second non-replacement region is parallel to an extending direction of the second fin portion 112.
With continuing reference to fig. 1 and fig. 2, a first gate structure 121 is formed on the semiconductor substrate 100 and the isolation layer 103, wherein the first gate structure 121 crosses over the first non-replacement region of the first fin 111 and covers a top surface and a sidewall surface of the first non-replacement region of the first fin 111; a second gate structure 122 is formed on the semiconductor substrate 100 and the isolation layer 103, wherein the second gate structure 122 crosses over the second non-replaced region of the second fin 112 and covers a top surface and a sidewall surface of the second non-replaced region of the second fin 112.
The first gate structure 121 includes a first gate dielectric layer crossing the first fin portion 111 and a first gate electrode layer on the first gate dielectric layer. The second gate structure 122 includes a second gate dielectric layer crossing the second fin 112 and a second gate electrode layer on the second gate dielectric layer. The first gate dielectric layer is located on a portion of the surface of the first region a isolation layer 103 and covers the top surface and the sidewall surface of the first non-replacement region of the first fin 111. The second gate dielectric layer is located on a portion of the surface of the second region B isolation layer 103 and covers the top surface and the sidewall surface of the second non-replaced region of the second fin 112.
In this embodiment, the first gate dielectric layer and the second gate dielectric layer are made of silicon oxide. In other embodiments, the material of the first gate dielectric layer and the second gate dielectric layer is a high-K dielectric material (K is greater than 3.9). The material of the first gate electrode layer and the second gate electrode layer is polysilicon.
In this embodiment, the top surface of the first gate structure 121 further has a first gate protection layer 131, and the top surface of the second gate structure 122 further has a second gate protection layer 132. The first gate protection layer 131 and the second gate protection layer 132 are made of SiN, siCN, siBN, or SiON.
Next, a first preliminary doping layer located in the first fin portion 111 is formed.
In this embodiment, the method further includes: before the subsequent groove processing process is performed, first fin sidewalls are formed, and the first fin sidewalls are located on sidewalls of two sides of the first initial doping layer in the width direction of the first fin portion 111 and expose a top surface of the first initial doping layer. The method for forming the first fin sidewall spacer and the first initial doping layer comprises the following steps: forming a first fin side wall on the surface of the isolation layer 103 on the side wall of the first replacement region; etching to remove the first replacement region covered by the first fin side wall, forming a first initial replacement groove in the first fin portion 111, wherein the side walls of two sides of the first initial replacement groove are respectively provided with the first fin side wall in the width direction of the first fin portion 111; etching the first fin side wall of the inner wall of the first initial replacement groove to increase the size of the first initial replacement groove in the width direction of the first fin part 111 to form a first replacement groove; forming the first preliminary doping layer in the first replacement trench.
In this embodiment, the method further includes: before the first initial doping layer and the first fin sidewall are formed, a second doping layer located in the second fin portion 112 is formed.
In this embodiment, the method further includes: forming a second fin side wall on the surface of the isolation layer 103 on the side wall of the second replacement region of the second fin portion 112; etching to remove the second replacement region covered by the second fin side wall, forming a second initial replacement groove in the second fin portion 112, wherein the side walls on two sides of the second initial replacement groove are respectively provided with the second fin side wall in the width direction of the second fin portion 112; etching the second fin side wall of the inner wall of the second initial replacement groove to increase the size of the second initial replacement groove in the width direction of the second fin portion 112, so as to form a second replacement groove; forming a second doped layer in the second replacement tank; and removing the second fin side wall on the side wall of the second doped layer.
With reference to fig. 3 and fig. 4 in combination, fig. 3 is a schematic diagram based on fig. 1, and fig. 4 is a schematic diagram based on fig. 2, wherein a first sidewall film 140 is formed on the surfaces of the isolation layers 103 in the first region a and the second region B, the surface of the first replacement region of the first fin 111, the sidewalls of the first gate structure 121 and the first gate protection layer 131, the top of the first gate protection layer 131, the surface of the second replacement region of the second fin 112, the sidewalls of the second gate structure 122 and the second gate protection layer 132, and the top of the second gate protection layer 132; the first sidewall film 140 of the second region B is etched back until the top surfaces of the second region B isolation layer 103, the second gate protection layer 132 and the second fin portion 112 are exposed, so as to form a second fin sidewall 142 and a second gate sidewall 141, where the second fin sidewall 142 is located on the sidewall of the second replacement region of the second fin portion 112 and on the surface of the isolation layer 103, and the second gate sidewall 141 is located on the sidewall of the second gate structure 122.
In this embodiment, the method further includes: before the first sidewall film 140 of the second area B is etched back, a first mask layer is formed on the first area a, the first mask layer covers the first sidewall film 140 of the first area a, and the first mask layer does not cover the first sidewall film 140 of the second area B; and etching the first sidewall film 140 of the second region B by using the first mask layer as a mask until the top surfaces of the second region B isolation layer 103, the second gate protection layer 132 and the second fin portion 112 are exposed, so as to form a second fin sidewall 142 and a second gate sidewall 141.
The material of the first sidewall film 140 is SiN, siCN, siBN, or SiON. The process of forming the first sidewall film 140 is a deposition process, such as a plasma chemical vapor deposition process or an atomic layer deposition process.
The material of the first mask layer comprises photoresist.
With reference to fig. 5 and fig. 6, fig. 5 is a schematic diagram based on fig. 3, and fig. 6 is a schematic diagram based on fig. 4, the second replacement region covered by the second fin sidewall 142 is removed by etching, a second initial replacement trench (not shown) is formed in the second fin portion 112, and the second fin sidewall 142 is respectively disposed on two sidewalls of the second initial replacement trench in the width direction of the second fin portion 112; etching the second fin sidewall 142 of the inner wall of the second initial replacement trench to increase the dimension of the second initial replacement trench in the width direction of the second fin portion 112, thereby forming a second replacement trench; a second doping layer 182 is formed in the second replacement trench.
Specifically, after the first side wall film 140 in the second region B is etched by using the first mask layer as a mask, the second replacement region covered by the second fin side wall 142 is removed by etching by using the first mask layer as a mask, so as to form a second initial replacement trench; etching the second fin sidewall 142 on the inner wall of the second initial replacement trench by using the first mask layer as a mask to increase the dimension of the second initial replacement trench in the width direction of the second fin portion 112; then, removing the first mask layer; after removing the first mask layer, a second doping layer 182 is formed. The process of etching the second fin sidewall 142 on the inner wall of the second initial replacement trench is a wet etching process.
The process of forming the second doping layer 182 includes an epitaxial growth process. The second doping layers 182 are respectively located in the second fins 112 at two sides of the second gate structure 122.
In this embodiment, the material of the second doping layer 182 is silicon germanium doped with second ions, and the conductivity type of the second ions is P-type.
The second initial replacement trench is formed by removing the second replacement region covered by the second fin sidewall 142, the second replacement trench is formed by enlarging the dimension of the second initial replacement trench in the width direction of the second fin portion 112, and the second doping layer 182 is formed in the second replacement trench. Therefore, the dimension of the second doping layer 182 in the width direction of the second fin 112 is larger than the width of the second replacement region of the second fin 112, which increases the surface area of the second doping layer 182. Since the second fin sidewall 142 limits the formation space of the second doping layer 182 during the formation of the second doping layer 182, the second doping layer 182 is prevented from protruding outward along the width direction of the second fin portion 112, and thus the distance between the edges of the second doping layer 182 adjacent to each other in the width direction of the second fin portion 112 is prevented from being too small. The material of the subsequent second plug and the second metal silicide layer are easy to fill in the region between the adjacent second doping layers 182 in the width direction of the second fin 112.
Referring to fig. 7 and 8 in combination, fig. 7 is a schematic view based on fig. 5, and fig. 8 is a schematic view based on fig. 6, after the second doping layer 182 is formed, a second sidewall film 190 is formed on the surface of the isolation layer 103 in the second region B, the surfaces of the second fin sidewall 142 and the second doping layer 182, the top of the second gate protection layer 132, the surface of the second gate sidewall 141, and the surface of the first sidewall film 140 in the first region a.
The material and forming method of the second sidewall film 190 refer to those of the first sidewall film 140.
Referring to fig. 9 and 10 in combination, fig. 9 is a schematic view based on fig. 7, and fig. 10 is a schematic view based on fig. 8, the second sidewall film 190 and the first sidewall film 140 of the first region a are etched back until the surface of the isolation layer 103 of the first region a and the top surfaces of the first gate protection layer 131 and the first fin portion 111 are exposed, so as to form a first fin sidewall 191 and a first gate sidewall 192, the first fin sidewall 191 is located on the sidewall of the first replacement region of the first fin portion 111 and on the surface of the isolation layer 103, and the first gate sidewall 192 is located on the sidewall of the first gate structure 121.
In this embodiment, the method further includes: before the second sidewall film 190 and the first sidewall film 140 of the first area a are etched back, a second mask layer is formed on the second area B, the second mask layer covers the second sidewall film 190 of the second area B, and the second mask layer does not cover the second sidewall film 190 of the first area a. And etching the second sidewall film 190 and the first sidewall film 140 in the first region a by using the second mask layer as a mask to form a first fin sidewall 191 and a first gate sidewall 192. The material of the second mask layer refers to the material of the first mask layer.
In this embodiment, the first gate sidewall 192 includes a first sub-gate sidewall 140a located on the sidewall of the first gate structure 121, and a second sub-gate sidewall 190a located on the sidewall of the first sub-gate sidewall 140 a. The first sub-gate sidewall 140a is formed by the first sidewall film 140 of the first region a, and the second sub-gate sidewall 190a is formed by the second sidewall film 190 of the first region a.
In this embodiment, the first fin sidewall 191 includes a first sub-fin sidewall 140b located on the sidewall of the first replacement region of the first fin portion 111 and on the surface of the isolation layer 103, and a second sub-fin sidewall 190b located on the sidewall of the first sub-fin sidewall 140 b. The first sub-fin sidewall 140b is formed by the first sidewall film 140 of the first region a, and the second sub-fin sidewall 190b is formed by the second sidewall film 190 of the first region a.
With reference to fig. 11 and 12 in combination, fig. 11 is a schematic diagram based on fig. 9, and fig. 12 is a schematic diagram based on fig. 10, in which the first replacement region covered by the first fin sidewall 191 is removed, a first initial replacement trench is formed in the first fin portion 111, and in the width direction of the first fin portion 111, two sidewalls of the first initial replacement trench respectively have first fin sidewalls 191; etching the first fin sidewall 191 on the inner wall of the first initial replacement groove to increase the dimension of the first initial replacement groove in the width direction of the first fin portion 111, so as to form a first replacement groove; a first preliminary doping layer 181 is formed in the first replacement trench.
Specifically, after the second side wall film 190 and the first side wall film 140 in the first region a are etched by using the second mask layer as a mask, the first replacement region covered by the first fin side wall 191 is removed by etching by using the second mask layer as a mask; etching the first fin sidewall 191 on the inner wall of the first initial replacement groove by using the second mask layer as a mask to increase the dimension of the first initial replacement groove in the width direction of the first fin portion 111; then, removing the second mask layer; after removing the second mask layer, the first preliminary doping layer 181 is formed. The process of etching the first fin sidewall 191 of the inner wall of the first initial replacement trench is a wet etching process.
The process of forming the first initially doped layer 181 includes an epitaxial growth process. The first initial doping layers 181 are respectively located in the first fin portions 111 at two sides of the first gate structure 121. In this embodiment, the material of the first initial doping layer 181 is silicon doped with first ions, and the conductivity type of the first ions is N-type.
The thickness of the first fin sidewall 191 on the sidewall of the first initial doping layer 181 is 2nm to 8nm.
In the process of forming the first initial doping layer 181, the first fin sidewall 191 limits a formation space of the first initial doping layer 181, and prevents the first initial doping layer 181 from protruding outward along the width direction of the first fin portion 111, thereby preventing a distance between edges of adjacent first initial doping layers 181 in the width direction of the first fin portion 111 from being excessively small. The material of the subsequent first plug and the first metal silicide layer are easy to fill in the region between the adjacent first doping layers in the width direction of the first fin portion 111.
Referring to fig. 13 and 14 in combination, fig. 13 is a schematic view on the basis of fig. 11, and fig. 14 is a schematic view on the basis of fig. 12, after the first initial doping layer 181 is formed, an underlying dielectric layer 211 is formed, wherein the underlying dielectric layer 211 is located on the semiconductor substrate 100, the first initial doping layer 181 and the second doping layer 182; forming a first dielectric opening 231 penetrating through the bottom dielectric layer 211 in the bottom dielectric layer 211, wherein the first dielectric opening 231 is located on the first initially doped layer 181; a second dielectric opening 232 is formed in the bottom dielectric layer 211 to penetrate through the bottom dielectric layer 211, and the second dielectric opening 232 is located on the second doped layer 182.
Specifically, after the first initial doping layer 181 is formed, a bottom dielectric layer 211 is formed, where the bottom dielectric layer 211 is located on the first region a isolation layer 103, the first fin sidewall 191, the first initial doping layer 181, and the sidewall of the first gate sidewall 191, and the bottom dielectric layer 211 is also located on the second region B isolation layer 103, the second fin sidewall 142, the second doping layer 182, and the sidewall of the second gate sidewall 141; removing the first gate protection layer 131 and the second gate protection layer 132 in the process of forming the bottom dielectric layer 211 to expose the top surface of the first gate structure 121 and the top surface of the second gate structure 122; after the bottom dielectric layer 211 is formed, removing the first gate structure 121, forming a first gate opening in the bottom dielectric layer 211 of the first region a, removing the second gate structure 122, and forming a second gate opening in the bottom dielectric layer 211 of the second region B; forming a first metal gate structure 221 in the first gate opening and a second metal gate structure 222 in the second gate opening; forming a top dielectric layer 212 on the first metal gate structure 221, the first gate sidewall 191, the second metal gate structure 222, the second gate sidewall 141 and the bottom dielectric layer 211, wherein the top dielectric layer 212 and the bottom dielectric layer 211 form an interlayer dielectric layer 210; forming a first dielectric opening 231 penetrating through the interlayer dielectric layer 210 in the interlayer dielectric layer 210 on two sides of the first metal gate structure 221, wherein the first initial doping layer 181 and the first fin sidewall 191 are located at the bottom of the first dielectric opening 231; a second dielectric opening 232 penetrating through the interlayer dielectric layer 210 is formed in the interlayer dielectric layer 210 on both sides of the second metal gate structure 222, and the second doping layer 182 and the second fin sidewall 142 are located at the bottom of the second dielectric opening 232.
After the first metal gate structure 221 is formed, the first initial doping layer 181 is respectively located in the first fin portion 111 at two sides of the first metal gate structure 221. After the second metal gate structure 222 is formed, the second doping layers 182 are respectively located in the second fins 112 at two sides of the second metal gate structure 122.
After the first dielectric opening 231 and the second dielectric opening 232 are formed, a groove treatment process is performed to form a first doping layer on the first initial doping layer 181, a groove is formed in the first doping layer, the groove is exposed on the top surface of the first doping layer, and the surfaces of the sidewalls of the groove on the two sides of the first fin portion 111 in the width direction are the surfaces of the first doping layer.
In this embodiment, after the first dielectric opening 231 and the second dielectric opening 232 are formed and before the recess process is performed, the sidewall of the second doped layer 182 has the second fin sidewall 142, and the second doped layer 182 and the second fin sidewall 142 have the second sidewall film 190 thereon.
During the recess treatment process, the second sidewall film 190 and the second fin sidewall 142 of the second region B may protect the second doped layer 182. The first dielectric opening 231 also exposes the isolation layer 103 of the first region a before the recess treatment process is performed.
The process of the recess treatment process will be described in detail with reference to fig. 15 to 18.
Referring to fig. 15, fig. 15 is a schematic view based on fig. 14, a portion of the first initial doping layer 181 is etched back to reduce the height of the first initial doping layer 181, so that the first initial doping layer 181 forms a first transition doping layer 184, a recess 240 located in the first fin portion 111 is formed on the first transition doping layer 184, and first fin sidewalls 191 are formed on sidewalls of the recess 240 on two sides of the first fin portion 111 in the width direction.
The depth of the etched-back portion of the first initially doped layer 181 is 3nm to 10nm. If the depth of etching the first initial doping layer 181 is too large, which results in the height of the first transition doping layer 184 being smaller, and the height of the sidewall of the first doping layer formed by the first transition doping layer 184 is smaller, the increase of the total area of the surface of the first doping layer is affected; if the depth of the first initial doping layer 181 is too small, the depth of the recess 240 is small, and the depth of the recess 240 determines the height of the subsequent mask sidewall, so that the height of the mask sidewall is too small, and the effect of the mask sidewall as a mask for etching the first transition doping layer 184 is reduced.
The process of etching back a portion of the first initial doping layer 181 to reduce the height of the first initial doping layer 181 is a dry etching process, and the parameters include: the gas used includes a fluorocarbon-based gas.
Referring to fig. 16, mask sidewall spacers 250 are formed on sidewalls of the recess 240, and the mask sidewall spacers 250 are in contact with the first fin sidewall 191.
The mask sidewall 250 is made of SiN, siCN, siBN, or SiON.
The thickness of the mask sidewall 250 is 2nm to 10nm. The thickness of the mask sidewall 250 refers to the dimension of the mask sidewall 250 in the width direction of the first fin portion 111. The significance of selecting this range for the thickness of the mask sidewall 250 is: if the thickness of the mask sidewall 250 is greater than 10nm, the distance between the mask sidewalls 250 at two sides of the recess 240 in the width direction of the first fin portion 111 is smaller, the area of the first transition doping layer 184 exposed by the mask sidewall 250 is smaller, a process window for subsequently etching the first transition doping layer 184 to form the first doping layer is smaller, and in the subsequent process of etching the first transition doping layer 184, etching gas hardly reaches an etching region, so that the depth of etching the first transition doping layer 184 is limited; if the thickness of the mask sidewall 250 is less than 2nm, the mask effect of the mask sidewall 250 is smaller in the subsequent etching process of the first transition doping layer 184.
The step of forming mask sidewall spacers 250 on the sidewalls of the recess 240 includes: forming a mask side wall material layer on the side wall and the bottom of the recess 240, the surface of the first fin side wall 191 and the semiconductor substrate 100; and etching back the mask side wall material layer until the top surface of the first transition doping layer 184 and the top surface of the first fin side wall 191 are exposed, and forming the mask side wall 250.
It should be noted that, in the process of forming the mask sidewall 250, materials of the mask sidewall 250 are further formed on the outer sidewall of the first fin sidewall 191, the sidewall of the first dielectric opening 231, and a part of the surface of the second sidewall film 190, and after the recess treatment process is performed, the corresponding materials of the mask sidewall 250 are removed.
Referring to fig. 17, the first transition doping layer 184 is etched by using the mask sidewall 250 and the first fin sidewall 191 as masks, so that the first transition doping layer 184 forms a first doping layer 183, a groove is formed in the first doping layer 183, the groove is exposed on the top surface of the first doping layer 183, and the surfaces of the sidewalls of the groove on both sides of the first fin portion 111 in the width direction are the surfaces of the first doping layer 183.
The process of etching the first transition doping layer 184 using the mask sidewall 250 and the first fin sidewall 191 as masks includes an anisotropic dry etching process, and the parameters include: the gas employed includes a fluorocarbon-based gas.
In one embodiment, the depth of the first transition doping layer 184 is etched by using the mask sidewall 250 and the first fin sidewall 191 as masks to occupy 20% to 100% of the thickness of the first transition doping layer 184, and the thickness of the first transition doping layer 184 is a dimension in a direction normal to the surface of the semiconductor substrate 100. The significance of selecting this range is: if the depth of etching the first transition doped layer 184 occupies less than 20% of the thickness of the first transition doped layer 184, the surface area of the first doped layer 183 is increased to a smaller extent relative to the surface area of the first transition doped layer 184, and the contact resistance between the first doped layer 183 and the subsequent first metal silicide layer is reduced to a smaller extent.
In this embodiment, the cross-sectional shape of the recess in the first doping layer 183 in the width direction of the first fin 111 is "U" shaped. In other implementations, the cross-sectional shape of the recess in the first doping layer in the width direction of the first fin is other shapes.
For the case where the top surface of the first doped layer protrudes outward, the increase in surface area of the first doped layer is limited by the growth rate of the first doped layer in the (100) plane normal direction. In this embodiment, the first doping layer 183 having the groove is formed by etching the first transition doping layer 184, so that the depth of the groove can be controlled by an etching process, the increase of the surface area of the first doping layer 183 is not limited by the growth rate of the first doping layer 183, the depth of the groove can be increased, and the increase of the surface area of the first doping layer 183 is facilitated.
In this embodiment, the first region a is used to form an N-type finfet, the second region B is used to form a P-type finfet, the first doping layer 183 is made of silicon doped with first ions, and the second doping layer 182 is made of silicon germanium doped with second ions. Accordingly, the grooves are formed only in the first doping layer 183, and the corresponding grooves are not formed in the second doping layer 183, so that stress loss of the second doping layer 183 to a channel in the P-type finfet is prevented, and reduction of mobility of carriers in the channel in the P-type finfet due to the stress loss is prevented.
Referring to fig. 18, after the first transition doping layer 184 is etched using the mask sidewall spacers 250 and the first fin sidewall 191 as masks, the mask sidewall spacers 250 are removed (refer to fig. 17).
The process of removing the mask sidewall 250 is a wet etching process or a dry etching process.
In this embodiment, the method further includes: after the first transition doping layer 184 is etched by using the mask side walls 250 and the first fin side walls 191 as masks, the first fin side walls 191 are removed. The first fin sidewall 191 and the mask sidewall 250 are removed to expose the top surface and the sidewall surface of the first doped layer 183.
In this embodiment, the method further includes: after the first transition doping layer 184 is etched by using the mask sidewall spacers 250 and the first fin sidewall spacers 191 as masks, the second fin sidewall spacers 142 at the bottom of the second dielectric opening 232 and the second sidewall film 190 of the second region B are removed to expose the top surface and the sidewall surface of the second doping layer 182, and the isolation layer 103 of the second region B is also exposed at the bottom of the second dielectric opening 232.
In this embodiment, the mask sidewall 250, the first fin sidewall 191, the second fin sidewall 142, and the second sidewall film 190 are removed in one etching process, which simplifies the process.
After the groove treatment process is performed, a first metal silicide layer is formed on the outer sidewall and the top surface of the first doping layer 183 and the inner wall of the groove, and a second metal silicide layer is formed on the top surface and the sidewall surface of the second doping layer 182. Specifically, after removing the first fin sidewall 191 and the mask sidewall 250, a first metal silicide layer is formed on the surface of the first doping layer 183; after removing the second fin sidewall spacers 142 on the sidewalls of the second doped layer 182, a second metal silicide layer is formed on the surface of the second doped layer 182.
A method of forming the first metal silicide layer and the second metal silicide layer is described below with reference to fig. 19 to 20.
Referring to fig. 19, a metal layer 260 is formed on the sidewalls and bottom of the first dielectric opening 231, the outer sidewalls and top surface of the first doping layer 183, and the inner wall surface of the groove, the sidewalls and bottom of the second dielectric opening 232, the sidewall surface and top surface of the second doping layer 182, and the top surface of the interlayer dielectric layer 210.
The metal layer 260 is made of Ti, co or Ni. In this embodiment, the material of the metal layer 260 is Ti. The process of forming the metal layer 260 is a deposition process, such as a sputtering process.
In this embodiment, the method further includes: a barrier layer 270 is formed on the surface of the metal layer 260. The material of the barrier layer 270 is titanium nitride or tantalum nitride. The process of forming the barrier layer 270 is a deposition process, such as a chemical vapor deposition process.
Referring to fig. 20, an annealing process is performed to react the outer sidewalls and the top surface of the first doping layer 183, and the metal layer 260 and the surface material of the first doping layer 183 on the inner wall of the groove to form a first metal silicide layer 281, and to react the metal layer 260 and the surface material of the second doping layer 182 on the sidewall surface and the top surface of the second doping layer 182 to form a second metal silicide layer 282.
In this embodiment, the barrier layer 270 is formed before the annealing process is performed, and in the annealing process, the barrier layer 270 can protect the metal layer 260 from being oxidized. In other embodiments, the barrier layer is formed after the annealing process.
In this embodiment, the method further includes: after the first metal silicide layer 281 and the second metal silicide layer 282 are formed, a first plug is formed in the first dielectric opening 231 and a second plug is formed in the second dielectric opening 232.
Referring to fig. 21, after forming the first metal silicide layer 281 and the second metal silicide layer 282, a plug material layer 290 is formed in the first dielectric opening 231 and the second dielectric opening 232 and on the interlayer dielectric layer 210.
The material of the plug material layer 290 is a metal, such as tungsten. The process of forming the plug material layer 290 is a deposition process. In this embodiment, the plug material layer 290 is located on the surface of the barrier layer 270.
Referring to fig. 22, the plug material layer 290, the barrier layer 270 and the metal layer 260 are planarized until the top surface of the interlayer dielectric layer 210 is exposed, such that the plug material layer 290 in the first dielectric opening 231 forms a first plug 291, and the plug material layer 290 in the second dielectric opening 232 forms a second plug 292.
Barrier layers 270 are provided between the first plug 291 and the first metal silicide layer 281, between the first plug 291 and the interlayer dielectric layer 210, and between the first plug 291 and the first region a isolation layer 103. The barrier layer 270 of the first region a serves to block diffusion of atoms of the first plug 291.
Barrier layers 270 are provided between the second plug 292 and the second metal silicide layer 282, between the second plug 292 and the interlayer dielectric layer 210, and between the second plug 292 and the second region B isolation layer 103. The barrier layer 270 of the second region B serves to block diffusion of atoms of the second plug 292.
Accordingly, the present embodiment further provides a semiconductor device formed by the above method, with reference to fig. 20, including: a semiconductor substrate 100, the semiconductor substrate 100 having a first fin portion 111 thereon; the first doping layer 183 is located in the first fin portion 111, a groove is formed in the first doping layer 183, the groove is exposed on the top surface of the first doping layer 183, and the surfaces of the side walls of the groove on the two sides in the width direction of the first fin portion 111 are the surfaces of the first doping layer 183; a first metal silicide layer 281 on the outer sidewall and top surface of the first doping layer 183 and the inner wall surface of the groove.
The cross-sectional shape of the recess in the first doping layer 183 in the width direction of the first fin 111 includes a "U" shape.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (17)

1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first fin part;
forming a first initial doping layer in the first fin portion;
performing a groove treatment process to enable the first initial doping layer to form a first doping layer, wherein a groove is formed in the first doping layer, the groove is exposed out of the top surface of the first doping layer, and the surfaces of the side walls of the groove in the width direction of the first fin portion are the surfaces of the first doping layer;
forming a first metal silicide layer on the outer side wall and the top surface of the first doping layer and the inner wall surface of the groove; before the groove processing technology is carried out, first fin side walls are formed, and the first fin side walls are located on the side walls of the first initial doping layer on the two sides of the first fin portion in the width direction and expose the top surface of the first initial doping layer;
the step of performing the groove treatment process includes: etching back part of the first initial doping layer to reduce the height of the first initial doping layer, so that the first initial doping layer forms a first transition doping layer, a recess located in the first fin part is formed in the first transition doping layer, and first fin side walls are arranged on two side walls of the recess in the width direction of the first fin part; forming a mask side wall on the side wall of the recess, wherein the mask side wall is in contact with the first fin side wall; etching the first transition doping layer by taking the mask side wall and the first fin side wall as masks, so that the first transition doping layer forms the first doping layer; removing the mask side wall after etching the first transition doping layer by taking the mask side wall and the first fin side wall as masks;
the method for forming the semiconductor device further comprises the following steps: removing the first fin side wall after etching the first transition doping layer by taking the mask side wall and the first fin side wall as masks; and after removing the first fin side wall and the mask side wall, forming the first metal silicide layer.
2. The method for forming a semiconductor device according to claim 1, further comprising: before forming the first initial doping layer, forming an isolation layer covering partial side walls of the first fin part on the semiconductor substrate, wherein the first fin part exposed by the isolation layer comprises a first replacement region;
the method for forming the first fin sidewall and the first initial doping layer comprises the following steps: forming a first fin side wall positioned on the surface of the isolation layer on the side wall of the first replacement region; etching to remove a first replacement region covered by the first fin side wall, forming a first initial replacement groove in the first fin part, wherein the side walls of two sides of the first initial replacement groove are respectively provided with the first fin side wall in the width direction of the first fin part; etching the first fin side wall on the inner wall of the first initial replacement groove to increase the size of the first initial replacement groove in the width direction of the first fin part to form a first replacement groove; forming the first preliminary doping layer in a first replacement trench.
3. The method of claim 1, wherein the first fin sidewall spacer is made of SiN, siCN, siBN, or SiON; the mask side wall is made of SiN, siCN, siBN or SiON.
4. The method for forming the semiconductor device according to claim 1, wherein the thickness of the mask sidewall is 2nm to 10nm.
5. The method of claim 1, wherein the first fin sidewall has a thickness of 2nm to 8nm.
6. The method of claim 1, wherein the step of forming the mask sidewall spacers on the sidewalls of the recess comprises: forming a mask side wall material layer on the side wall and the bottom of the recess, the surface of the first fin side wall and the semiconductor substrate; and etching the mask side wall material layer until the top surface of the first transition doping layer and the top surface of the first fin side wall are exposed to form the mask side wall.
7. The method of claim 1, wherein the etching the first transition doped layer using the mask sidewall and the first fin sidewall as masks comprises an anisotropic dry etching process.
8. The method for forming a semiconductor device according to claim 1, wherein the depth of etching the first transition doped layer using the mask sidewall and the first fin sidewall as masks occupies 20% to 100% of the thickness of the first transition doped layer.
9. The method for forming a semiconductor device according to claim 1, wherein the depth of the back-etched portion of the first preliminary doping layer is 3nm to 10nm.
10. The method of claim 1, wherein the first fin sidewall spacer is removed during the process of removing the mask sidewall spacer.
11. The method as claimed in claim 1, wherein a cross-sectional shape of the recess in a width direction of the first fin portion includes a "U" shape.
12. The method for forming a semiconductor device according to claim 1, further comprising: before the first initial doping layer is formed, forming a first grid electrode structure crossing the first fin portion on the semiconductor substrate, wherein the first grid electrode structure covers part of the top surface and part of the side wall surface of the first fin portion; the first initial doping layers are respectively positioned in the first fin parts at two sides of the first gate structure; after the first doping layer is formed, the first doping layer is respectively positioned in the first fin parts at two sides of the first gate structure.
13. The method of claim 1, wherein the semiconductor substrate comprises a first region and a second region, the first fin is located on the first region of the semiconductor substrate, and the second fin is located on the second region of the semiconductor substrate; the method for forming the semiconductor device further comprises the following steps: forming a second doped layer in the second fin portion before forming the first preliminary doped layer; and after the first doping layer is formed, forming a second metal silicide layer on the surface of the second doping layer.
14. The method as claimed in claim 13, wherein the semiconductor substrate has an isolation layer covering a portion of sidewalls of the second fin, and the second fin exposed by the isolation layer includes a second replacement region; the method for forming the semiconductor device further comprises the following steps: forming a second fin side wall positioned on the surface of the isolation layer on the side wall of the second replacement region of the second fin part; etching to remove a second replacement region covered by the second fin side wall, forming a second initial replacement groove in the second fin part, wherein the side walls of two sides of the second initial replacement groove are respectively provided with the second fin side wall in the width direction of the second fin part; etching the second fin side wall of the inner wall of the second initial replacement groove to increase the size of the second initial replacement groove in the width direction of the second fin part to form a second replacement groove; forming a second doping layer in the second replacement tank; and after removing the second fin side wall on the side wall of the second doping layer, forming the second metal silicide layer.
15. The method as claimed in claim 13, wherein the first region is used to form an N-type transistor and the second region is used to form a P-type transistor.
16. The method according to claim 13, wherein after the first preliminary doping layer is formed and before the recess treatment process is performed, a bottom dielectric layer is formed on the semiconductor substrate, the first preliminary doping layer, and the second doping layer; forming a first dielectric opening penetrating through the bottom dielectric layer in the bottom dielectric layer, wherein the first dielectric opening is positioned on the first initial doping layer; forming a second medium opening penetrating through the bottom medium layer in the bottom medium layer, wherein the second medium opening is positioned on the second doping layer; after a first medium opening and a second medium opening are formed, the groove processing technology is carried out; and after the groove processing technology is carried out, a first metal silicide layer is formed on the outer side wall and the top surface of the first doping layer and the inner wall of the groove, and a second metal silicide layer is formed on the top surface and the side wall surface of the second doping layer.
17. The method for forming a semiconductor device according to claim 16, further comprising: after the first metal silicide layer and the second metal silicide layer are formed, a first plug is formed in the first dielectric opening, and a second plug is formed in the second dielectric opening.
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