CN113113486B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN113113486B
CN113113486B CN202010032651.4A CN202010032651A CN113113486B CN 113113486 B CN113113486 B CN 113113486B CN 202010032651 A CN202010032651 A CN 202010032651A CN 113113486 B CN113113486 B CN 113113486B
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layer
fin
forming
gate structure
side wall
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CN113113486A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention provides a semiconductor device and a forming method thereof, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate is provided with a fin part structure, and the fin part structure comprises a plurality of first fin part layers and a second fin part layer positioned between the first fin part layers of two adjacent layers; forming a dummy gate structure crossing the fin structure on the substrate; etching the fin part structures on two sides of the pseudo gate structure, forming a groove in the fin part structure, and exposing the second fin part layer at the bottommost layer at the bottom of the groove; etching to remove part of the first fin part layer on the side wall of the groove to form a first correction fin part layer; forming an initial barrier layer on the side wall of the groove, the side wall of the first correction fin part layer and the side wall of the pseudo gate structure; removing the second fin portion layer at the bottommost layer, and forming a gap between the first fin portion layer at the bottommost layer and the first correction fin portion layer at the bottommost layer; the forming method can improve the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source-drain doped regions in the Fin portion located at both sides of the gate structure. Compared with a planar metal-oxide semiconductor field effect transistor, the fin type field effect transistor has stronger short channel inhibition capability and stronger working current.
As the size of integrated circuit devices becomes smaller and smaller with the further development of semiconductor technology, the conventional fin field effect transistor has a limitation in further increasing the operating current. Specifically, only the region near the top surface and the sidewall in the fin is used as a channel region, so that the volume of the fin used as the channel region is small, which limits the increase of the operating current of the finfet. Therefore, a gate-all-around (GAA) structure fin field effect transistor is proposed, so that the volume of the fin field effect transistor used as a channel region is increased, and the working current of the gate-all-around structure fin field effect transistor is further increased.
However, the performance of the finfet with a channel gate surrounding structure in the prior art needs to be improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which can improve the performance of the semiconductor device.
In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate is provided with a fin part structure, and the fin part structure comprises a plurality of first fin part layers and a second fin part layer positioned between the first fin part layers of two adjacent layers; forming a dummy gate structure crossing the fin structure on the substrate; etching the fin part structures on two sides of the pseudo gate structure, forming a groove in the fin part structure, and exposing the second fin part layer on the bottommost layer at the bottom of the groove; etching to remove part of the first fin part layer on the side wall of the groove to form a first correction fin part layer; forming an initial barrier layer on the side wall of the groove, the side wall of the first correction fin part layer and the side wall of the pseudo gate structure; and removing the second fin portion layer at the bottommost layer, and forming a gap between the first fin portion layer at the bottommost layer and the first correction fin portion layer at the bottommost layer.
Optionally, after forming the gap, the method further includes: forming isolation layers on the first fin portion layer at the bottommost layer on two sides of the gap, the bottom of the first correction fin portion layer at the bottommost layer, the bottom, the side wall and the top of the initial blocking layer, the bottom of the groove and the top of the dummy gate structure; forming an insulating layer on the isolation layer at the bottom of the groove, wherein the insulating layer covers part of the isolation layer on the side wall of the initial barrier layer; and etching and removing the isolation layer and part of the initial barrier layer which are not covered by the insulating layer until the top and the side wall of the pseudo gate structure and the side wall of the second fin portion layer are exposed, and forming a barrier layer on the side wall of the first correction fin portion layer.
Optionally, the barrier layer includes a first barrier layer and a second barrier layer, and a thickness of the second barrier layer is greater than a thickness of the first barrier layer.
Optionally, a source-drain doping layer is formed in the groove.
Optionally, after the source-drain doping layer is formed, the method further includes: forming a dielectric layer on the source drain doping layer and the dummy gate structure, wherein the dielectric layer covers the side wall of the dummy gate structure; removing the dummy gate structure and the first correction fin portion layer covered by the dummy gate structure, and forming a gate opening in the dielectric layer and between the adjacent second fin portion layers; and forming a gate structure in the gate opening, wherein the gate structure surrounds the second fin portion layer.
Optionally, the initial barrier layer is made of silicon nitride, silicon carbide, silicon oxynitride or silicon oxide.
Optionally, the process of forming the initial barrier layer includes a physical vapor deposition process or a chemical vapor deposition process.
Optionally, the material of the first fin portion layer and the material of the second fin portion layer are not the same; the first fin portion layer is made of monocrystalline silicon, and the second fin portion layer is made of monocrystalline silicon germanium; or the first fin portion layer is made of single crystal silicon germanium, and the second fin portion layer is made of single crystal silicon.
Optionally, the process of removing the second fin layer at the bottommost layer is a dry etching process or a wet etching process.
Optionally, etching the fin structure on both sides of the dummy gate structure, before forming the groove in the fin structure, further includes: and forming a side wall on the side wall of the pseudo gate structure.
Correspondingly, the invention also provides a semiconductor device, comprising: the structure comprises a substrate, wherein a fin part structure is arranged on the substrate and comprises a plurality of first fin part layers and a second fin part layer positioned between the first fin part layers of two adjacent layers; the grid structure is positioned on the substrate and covers part of the side wall and part of the top of the fin part structure, and the grid structure surrounds the second fin part layer; the grooves are positioned in the fin part structures on two sides of the grid electrode structure, and the first fin part layer at the bottommost layer is exposed at the bottom of the grooves; a gap between the first fin layer at the bottom layer and the bottom of the gate structure; and the blocking layer is positioned on the side wall of the grid structure between the second fin part layers of the two adjacent layers and positioned on the side wall of the grid structure between the gap and the second fin part layers.
Optionally, the blocking layer includes a first blocking layer and a second blocking layer, the first blocking layer is located on the sidewall of the gate structure between the two adjacent layers of the second fin layer, and the second blocking layer is located on the sidewall of the gate structure between the gap and the second fin layer.
Optionally, the thickness of the second barrier layer is greater than the thickness of the first barrier layer.
Optionally, the method further includes: the isolation layer is located on the first fin portion layer at the bottommost layer of the bottom of the groove, on the first fin portion layer at the bottommost layer of the two sides of the gap and on the bottom and the side wall of the second barrier layer.
Optionally, the insulating layer is located on the isolation layer at the bottom of the groove and on the isolation layer on the sidewall of the second blocking layer.
Optionally, the method further includes: and the source drain doping layer is positioned in the groove.
Optionally, the gate structure further includes a dielectric layer, the dielectric layer is located on the substrate and covers the source-drain doping layer, and a top surface of the dielectric layer is flush with a top surface of the gate structure.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the forming method, the gap is formed between the first fin part layer at the bottommost layer and the first correction fin part layer at the bottommost layer, so that the gap is formed between the substrate and the fin part and between the substrate and the dummy gate structure, a parasitic device is prevented from being formed on the substrate, and the problem of forming the parasitic device on the substrate is effectively solved; meanwhile, because a gap is formed between the dummy gate structure and the substrate, the distance between the dummy gate structure and the substrate is increased, so that when the dummy gate structure is removed to form the gate structure, the metal capacitance between the gate structure and the substrate is reduced, and the quality and the performance reliability of the formed semiconductor device are improved.
According to the semiconductor device, a gap is formed between the first fin layer on the bottommost layer and the grid electrode structure, so that the grid electrode structure is separated from the substrate, and no channel capable of forming a parasitic device is arranged at the bottom of the grid electrode structure, so that the parasitic device is prevented from being formed on the substrate, and the influence of the parasitic device on the performance of the semiconductor device is avoided; meanwhile, the distance between the bottom of the gate structure and the substrate is increased, so that the parasitic capacitance between the gate structure and the substrate is reduced, and the sensitivity of the semiconductor device is improved.
Drawings
Fig. 1 to 3 are schematic structural views illustrating a process of forming a semiconductor device according to an embodiment;
fig. 4 to 17 are schematic structural diagrams illustrating a process of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
The performance of the semiconductor device is poor, and the following description will be made with reference to the accompanying drawings.
Referring to fig. 1, a substrate 100 is provided, where the substrate 100 has a fin structure, and the fin structure includes a plurality of first fin layers 101 overlapped along a normal direction of the substrate surface, and a second fin layer 102 located between two adjacent first fin layers 101; forming a dummy gate structure 103 crossing the fin structure on the substrate 100, wherein the dummy gate structure 103 covers part of the sidewall and part of the top surface of the fin structure.
Referring to fig. 2, a groove 104 is formed in the fin structure at two sides of the dummy gate structure 103; removing a part of the first fin portion layer 101 on the side wall of the groove 104 to form a first modified fin portion layer 105, a first fin portion groove (not marked) and a second fin portion groove (not marked), wherein the first fin portion groove is located between the first modified fin portion layer 105 and the substrate 100 at the bottom layer, and the second fin portion groove is located between the second fin portion layers 102 at two adjacent layers; a first barrier layer 106 and a second barrier layer 108 located in the second fin recess are formed in the first fin recess.
Referring to fig. 3, a source-drain doped layer 107 is formed in the recess 104, and source-drain ions are contained in the source-drain doped layer 107.
The inventor finds that: the semiconductor device formed by the forming method is easy to form a parasitic device, and parasitic capacitance is easy to generate between the gate structure and the substrate, so that the performance reliability of the semiconductor device is poor.
The inventor researches and discovers that: the method comprises the steps of forming a fin portion structure on a substrate, wherein the fin portion structure is provided with a first fin portion layer and a second fin portion layer, after a pseudo grid electrode structure is formed, etching the fin portion structures on two sides of the pseudo grid electrode structure, the second fin portion layer at the bottommost layer is exposed at the bottom of the pseudo grid electrode structure, correcting the first fin portion layer on the side wall of a groove, forming a first correction fin portion layer, removing the second fin portion layer at the bottommost layer exposed at the bottom of the groove after an initial barrier layer is formed on the side wall of the first correction fin portion layer, the side wall of the groove and the side wall of the pseudo grid electrode structure, and forming a gap between the first fin portion layer at the bottommost layer and the first correction fin portion layer at the bottommost layer.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 17 are schematic structural diagrams illustrating a process of forming a semiconductor device according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, and the substrate 200 has a fin structure, where the fin structure includes a plurality of first fin layers 201 and a second fin layer 202 located between two adjacent first fin layers 201.
In this embodiment, the first fin layers 201 are overlapped along the normal direction of the surface of the substrate 200, and the second fin layers 202 are located between the adjacent first fin layers 201 along the normal direction of the surface of the substrate 200.
In this embodiment, the substrate 200 is made of monocrystalline silicon; in other embodiments, the material of the substrate 200 may also be single crystal silicon germanium.
The forming method of the fin structure comprises the following steps: forming a fin material film (not shown) on the substrate 200, wherein the fin material film comprises a plurality of layers of first fin films (not shown) overlapped along the surface normal direction of the substrate 200 and a second fin film (not shown) positioned in two adjacent layers of the first fin films; forming a patterned layer (not shown) on the fin material film; and etching the fin material film by using the patterned layer as a mask until the fin material film is exposed out of the top surface of the substrate to form the fin structure, wherein the fin structure comprises a plurality of first fin layers 201 overlapped along the normal direction of the surface of the substrate and a second fin layer 202 positioned between the two adjacent first fin layers 201.
The material of the first fin portion layer 201 is different from that of the second fin portion layer 202, and the purpose of the material is to remove the first fin portion layer 201 when a gate structure is formed subsequently, so that the material of the first fin portion layer 201 and the material of the second fin portion layer 202 which are made of different materials has a larger etching selection ratio, and the damage to the second fin portion layer 202 in the process of removing the first fin portion layer 201 is reduced.
In this embodiment, the material of the first fin layer 201 is monocrystalline silicon, and the material of the second fin layer 202 is monocrystalline silicon germanium; in other embodiments, the material of the first fin layer is single crystal silicon germanium, and the material of the second fin layer is single crystal silicon.
Referring to fig. 5, a dummy gate structure crossing the fin structure is formed on the substrate 200, and the dummy gate structure covers a portion of the sidewalls and a portion of the top surface of the fin structure.
The dummy gate structure includes: the semiconductor structure comprises a gate dielectric layer 203 positioned on the fin structure, a dummy gate layer 204 positioned on the gate dielectric layer 203, and a protective layer 205 positioned on the dummy gate layer 204.
In this embodiment, a sidewall 206 is formed on the sidewall of the dummy gate structure, that is, the sidewall 206 is formed on the sidewalls of the dummy gate layer 204 and the protection layer 205.
In other embodiments, the sidewall spacers 206 may not be formed on the sidewalls of the dummy gate structures.
In this embodiment, the material of the dummy gate layer 204 is polysilicon; in other embodiments, the material of the dummy gate layer 204 may also be amorphous silicon.
In this embodiment, the material of the protection layer 205 is silicon nitride; in other embodiments, the material of the protective layer may also use silicon oxide.
The method for forming the side wall 206 includes: forming a side wall material layer (not shown) on the top surface of the gate dielectric layer 203, the side wall of the dummy gate layer 204, the side wall of the protection layer 205 and the top surface; and etching back the side wall material layer until the protective layer 205 and the top surface of the gate dielectric layer 203 are exposed, so as to form the side wall 206.
The forming process of the side wall material layer is one or a combination of a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. The material of the sidewall spacers 206 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the sidewall spacers 206 are used to define the position of the subsequent source-drain doping layer.
Referring to fig. 6, the fin structure on both sides of the dummy gate structure is etched, a groove 207 is formed in the fin structure, and the second fin layer 202 at the bottom layer is exposed at the bottom of the groove 207.
In this embodiment, the groove 207 serves to provide a space for the source/drain doping layer to be formed subsequently.
The process for etching the fin structure comprises the following steps: an anisotropic dry etching process or an anisotropic wet etching process.
In this embodiment, the process for etching the fin structure is an anisotropic dry etching process, and the parameters of the dry etching process include: the adopted etching gas comprises HBr and Ar, wherein the flow rate of HBr is 10 sccm-1000sccm, and the flow rate of Ar is 10 sccm-1000 sccm.
Referring to fig. 7, a portion of the first fin layer 201 on the sidewall of the recess 207 is removed by etching, so as to form a first modified fin layer 208.
In this embodiment, the first fin layer 201 with a partial thickness at the bottom of the sidewall 206 is removed by etching to form the first modified fin layer 208, and fin grooves 209 are formed on two sides of the first modified fin layer 208.
In this embodiment, the fin recess 209 is used to provide space for the subsequent formation of a barrier layer.
In this embodiment, the process of removing the first fin portion layer 201 with a partial thickness is a wet etching process. The etching solution for wet etching has a good selection ratio to monocrystalline silicon and monocrystalline germanium-silicon, and can ensure that the morphology of the monocrystalline germanium-silicon is not influenced while the monocrystalline silicon is removed. The parameters of the wet etching process comprise: the etching solution is a tetramethylammonium hydroxide solution, the temperature is 20-80 ℃, and the volume percentage of the tetramethylammonium hydroxide solution is 10-80%.
Forming an initial blocking layer on the side wall of the groove, the side wall of the first modified fin portion layer and the side wall of the dummy gate structure, wherein the specific forming process refers to fig. 8 to 9.
Referring to fig. 8, an initial barrier material layer 210 is formed on the sidewalls and bottom of the recess 207, the sidewalls of the first modified fin layer 208, and the sidewalls and top surface of the dummy gate structure. In this embodiment, the initial barrier material layer 210 is formed on the sidewall of the recess 207, the fin recess 209 at two sides of the first modified fin layer 208, the sidewall of the sidewall 206, and the top of the protection layer 205.
In this embodiment, the material of the initial barrier material layer 210 is silicon nitride; in other embodiments, the material of the initial barrier material layer 210 may also be one or more of silicon nitride, silicon carbide, silicon oxynitride, or silicon oxide.
In this embodiment, the formation process of the initial barrier material layer 210 adopts a physical vapor deposition process; in other embodiments, the formation process of the initial barrier material layer 210 may also adopt a chemical vapor deposition process.
Referring to fig. 9, the initial barrier material layer 210 is etched back until the bottom surface of the recess 207 and the top surface of the protection layer 205 are exposed, forming an initial barrier layer 211.
The process of etching back the initial barrier material layer 210 includes an anisotropic dry etching process or an anisotropic wet etching process; in this embodiment, the process of etching back the initial barrier material layer 210 uses an anisotropic dry etching process, and parameters of the anisotropic dry etching process include: the etching gas comprises CF 4 And CH 2 F 2 Wherein CF 4 The flow rate of (C) is 50sccm to 500sccm 2 F 2 The flow rate of (2) is 30-100 sccm.
Referring to fig. 10, the second fin layer 202 at the bottom layer is removed, and a gap 212 is formed between the first fin layer 201 at the bottom layer and the first modified fin layer 208 at the bottom layer.
In this embodiment, the process of removing the second fin layer 202 at the bottommost layer is a wet etching process; in other embodiments, a dry etching process may be further used to remove the second fin layer 202 at the bottom layer.
In this embodiment, the step of removing the second fin layer 202 at the bottom layer is a selective wet etching process, and a wet etching solution has a good selectivity ratio of silicon to silicon germanium, so that the silicon germanium can be removed while the morphology of the silicon is not affected.
In this embodiment, the wet etching solution is: HCl gas with the temperature of 25-300 ℃ and the volume percentage of 20-90%.
In this embodiment, the substrate 200 and the dummy gate structure are isolated by using the gap 212, so that no channel can be formed at the bottom of the dummy gate structure, and thus, in a subsequent process, no redundant parasitic device is formed on the substrate 200, and the generation of the parasitic device is eliminated, thereby reducing the influence of the parasitic device on the performance of the semiconductor device and improving the performance reliability of the semiconductor device.
In this embodiment, due to the existence of the gap 212, the distance between the bottom of the dummy gate structure and the substrate 200 is increased, and when the first correction fin layer 208 is subsequently removed to form a gate structure surrounding the second fin layer 202, the distance between the gate structure and the substrate 200 is increased, so that the parasitic capacitance between the substrate 200 and the gate structure is reduced, the interference effect of the parasitic capacitance on the semiconductor device is reduced, the sensitivity of the performance of the semiconductor device is improved, and thus the performance of the semiconductor device is improved.
Referring to fig. 11, an isolation layer 213 is formed on the first fin layer 201 at the bottom layer on both sides of the gap 212, the bottom of the first modified fin layer 208 at the bottom layer, the bottom, the sidewall and the top of the initial barrier layer 211, the bottom of the recess 207 and the top of the dummy gate structure.
In this embodiment, the process of forming the isolation layer 213 is an atomic layer deposition process; in other implementations, the isolation layer 213 may be formed by a chemical vapor deposition process.
In this embodiment, the isolation layer 213 is made of silicon nitride; in other embodiments, the material of the isolation layer 213 may also be silicon oxide, silicon carbide, silicon oxynitride, or the like.
In this embodiment, the isolation layer 213 is formed by using an atomic layer deposition process, and the isolation layer 213 with better density and uniformity can be formed by using good step coverage capability of the atomic layer deposition process.
In this embodiment, the isolation layer 213 is formed to: the gap 212 between the subsequently formed gate structure and the substrate 200 can be ensured to be complete, so that isolation is effectively realized.
Referring to fig. 12, an insulating layer 214 is formed on the isolation layer 213 at the bottom of the recess 207, and the insulating layer 214 covers a portion of the isolation layer 213 at the sidewall of the initial barrier layer 211.
In this embodiment, the top surface of the insulating layer 214 is lower than the bottom surface of the first modified fin layer 208.
In this embodiment, the insulating layer 214 is made of silicon oxide; in other embodiments, the material of the insulating layer 214 may also be silicon nitride, silicon carbide, or the like.
In this embodiment, the top surface of the insulating layer 214 being lower than the bottom surface of the first modified fin layer 208 is for the purpose of: in order to subsequently etch the isolation layer 213 and the initial barrier layer 211 with a partial thickness, a first barrier layer and a second barrier layer with different thicknesses can be formed, so that the isolation effect between the source-drain doping layer and the gate structure is improved, the parasitic capacitance between the source-drain doping layer and the gate structure is reduced, and the performance of the finally formed semiconductor structure is improved.
In this embodiment, the process of forming the insulating layer 214 is a chemical vapor deposition process; in other embodiments, the process of forming the insulating layer 214 can also be an atomic layer deposition process or a physical vapor deposition process.
Referring to fig. 13, the isolation layer 213 and a portion of the initial barrier layer 211 not covered by the insulating layer 214 are removed by etching until the top and sidewalls of the dummy gate structure and the sidewalls of the second fin layer 202 are exposed.
In this embodiment, the etched initial blocking layer 211 includes a first blocking layer 2110 and a second blocking layer 2111, the first blocking layer 2110 is located on a sidewall of the first correction fin portion 208 between the adjacent second fin portion layers 202, the second blocking layer 2111 is located on a sidewall of the first correction fin portion layer 208 at the bottommost layer, the thickness of the second blocking layer 2111 is greater than that of the first blocking layer 2110, the thickness direction is perpendicular to the sidewall of the second blocking layer 2111, and in a subsequent process, the second blocking layer 2111 with an increased thickness can effectively improve an isolation effect between the source and drain doping layer and the formed gate structure, reduce a parasitic capacitance between the source and drain doping layer and the gate structure, and further improve performance of the finally formed semiconductor structure; meanwhile, the gap 212 can be completely formed between the insulating layer 214 and the isolation layer 213, and the gap 212 under the second barrier layer 2111 is protected.
In addition, the thickness of the first blocking layer 2110 is small, so that the influence on the growth of the subsequent source/drain doping layer when the thickness of the first blocking layer 2110 is large is avoided.
In this embodiment, the first blocking layer 2110 functions to increase a distance between the source/drain doping layer and the work function layer in the gate structure, and reduce a parasitic capacitance between the source/drain doping layer and the work function layer.
Referring to fig. 14, after the isolation layer 213 and the initial blocking layer 211 that are not covered by the insulation layer 214 are removed by etching, a source-drain doping layer 215 is formed in the groove 207, and source-drain ions are contained in the source-drain doping layer 215.
In this embodiment, the formation process of the source-drain doping layer 215 includes an epitaxial growth process; the process of doping the source and drain ions in the source and drain doping layer 215 includes an in-situ doping process.
When the semiconductor device is a P-type device, the material of the source-drain doping layer 215 includes: silicon, germanium, or silicon germanium; the source and drain ions are P-type ions and comprise boron ions and BF 2- Ions or indium ions; when the semiconductor device is an N-type device, the source-drain doping layer 215 is made of the following materials: silicon, gallium arsenideOr indium gallium arsenide; the source and drain ions are N-type ions and comprise phosphorus ions or arsenic ions.
In this embodiment, the semiconductor device is an N-type device, the source-drain doping layer 215 is made of silicon, and the source-drain ions are phosphorus ions.
Referring to fig. 15, a dielectric layer 216 is formed on the source-drain doping layer 215 and the dummy gate structure, and the dielectric layer 216 covers a sidewall of the dummy gate structure.
In this embodiment, the dielectric layer 216 covers the source-drain doping layer 215 and the sidewall of the dummy gate structure, and exposes the top surface of the dummy gate structure.
The forming method of the dielectric layer 216 includes: forming an initial dielectric layer (not shown) on the source-drain doping layer 215 and the dummy gate structure, where the initial dielectric layer covers a top surface and a sidewall surface of the dummy gate structure; the initial dielectric layer is planarized until the surface of the protection layer 205 on top of the dummy gate structure is exposed, forming the dielectric layer 216.
In this embodiment, the dielectric layer 216 is made of silicon oxide.
Referring to fig. 16, the dummy gate structure and the first modified fin layer 208 covered by the dummy gate structure are removed, and a gate opening 217 is formed in the dielectric layer 216 and between the adjacent second fin layers 202.
The method of removing the dummy gate structure and the first modified fin layer 208 covered by the dummy gate structure includes: removing the dummy gate layer 204, and forming an initial gate opening (not shown) in the dielectric layer 216; the first modified fin layer 208 exposed by the initial gate opening is removed, so that the gate opening 217 is formed by the initial gate opening.
Specifically, before removing the dummy gate layer 204, the method further includes removing the protective layer 205 on top of the dummy gate layer 204.
In this embodiment, the process of removing the first modified fin portion layer 208 adopts a wet etching process.
Referring to fig. 17, a gate structure 218 is formed within the gate opening 217, wherein the gate structure 218 surrounds the second fin layer 202.
The gate structure 202 includes a gate electrode layer and a work function layer.
The gate electrode layer is made of metal, and the metal material comprises one or more of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum.
In this embodiment, since the first blocking layer 2110 is formed between the gate structure 218 and the source doping layer 215, a distance between the gate structure 218 and the source doping layer 215 is increased, so that a parasitic capacitance between the gate structure 218 and the source doping layer 215 is reduced, and a performance and a quality of a finally formed semiconductor device are improved.
In this embodiment, the gap 212 is formed between the bottom of the gate structure 218 and the substrate 200, and a channel for forming a parasitic device is formed on the substrate 200, so that the parasitic device cannot be formed on the substrate 200, thereby eliminating the influence of the parasitic device on the formed semiconductor device.
In this embodiment, the gap 212 is formed between the gate structure 218 and the substrate 200, so that the distance between the gate structure 218 and the substrate 200 is increased, the parasitic capacitance between the substrate 200 and the gate structure 218 is reduced, the interference of the parasitic capacitance on the performance of the semiconductor device is reduced, and the quality and reliability of the semiconductor device are improved.
Accordingly, referring to fig. 17, the present invention further provides a semiconductor device, including: the structure comprises a substrate 200, wherein a fin structure is arranged on the substrate 200 and comprises a plurality of first fin layers 201 and a second fin layer 202 located between the first fin layers of two adjacent layers; a gate structure 218 located on the substrate 200 and covering a portion of sidewalls and a portion of a top of the fin structure, the gate structure 218 surrounding the second fin layer 202; the groove 207 is positioned in the fin portion structures on two sides of the gate structure, and the first fin portion layer 201 on the bottommost layer is exposed at the bottom; a gap 212 between the bottom-most first fin layer 201 and the bottom of the gate structure 218; and the barrier layers are positioned on the side wall of the grid electrode structure between the two adjacent layers of the second fin portion layers and on the side wall of the grid electrode structure between the gap and the second fin portion layers.
In this embodiment, the blocking layers include a first blocking layer 2110 and a second blocking layer 2111, the first blocking layer 2110 is located on sidewalls of the gate structure 218 between two adjacent layers of the second fin layer 202, and the second blocking layer 2111 is located on sidewalls of the gate structure 218 between the gap 212 and the second fin layer 202.
Further comprising: and the isolation layer 213 is located on the first fin layer 201 at the bottom layer of the bottom of the groove 207, on the first fin layer 201 at the bottom layer on both sides of the gap 212, and on the bottom and the sidewall of the second barrier layer 2111.
In this embodiment, the isolation layer 213 is formed to form the effective gap 212 between the gate structure and the substrate 200, so as to achieve isolation between the substrate 200 and the gate structure.
In this embodiment, the insulating layer 214 is located on the isolation layer 213 at the bottom of the groove 207 and on the isolation layer 213 at the sidewall of the second barrier layer 2111.
In this embodiment, the thickness of the second blocking layer 2111 is greater than that of the first blocking layer 2110, and the effect of the thickness of the second blocking layer 2111 greater than that of the first blocking layer 2110 is to increase the distance between the work function layer and the source/drain doping layer, so as to reduce the parasitic capacitance between the work function layer and the source/drain doping layer; meanwhile, the gap 212 can be completely formed between the insulating layer 214 and the isolation layer 213, and the gap 212 under the second barrier layer 2111 is protected.
In this embodiment, the method further includes: and the source drain doping layer 215 is positioned in the groove 207.
In this embodiment, the integrated circuit further includes a dielectric layer 216, where the dielectric layer 216 is located on the substrate and covers the source-drain doping layer 215, and a top surface of the dielectric layer is flush with a top surface of the gate structure.
In this embodiment, the gap 212 is formed between the first fin layer 201 at the bottommost layer and the first modified fin layer 208 at the bottommost layer, so that the substrate 200 is isolated from the fin structure at the bottom of the dummy gate structure, and the dummy gate structure is also isolated from the substrate 200, thereby eliminating the possibility of forming a parasitic device on the substrate 200, and on the other hand, reducing the parasitic capacitance between the gate structure and the substrate 200 in the subsequent process, improving the sensitivity of the finally formed semiconductor device, and enhancing the usability.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (17)

1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with a fin part structure, and the fin part structure comprises a plurality of layers of first fin part layers and a second fin part layer positioned between the first fin part layers of two adjacent layers;
forming a dummy gate structure crossing the fin structure on the substrate;
etching the fin part structures on two sides of the pseudo gate structure, forming a groove in the fin part structure, and exposing the second fin part layer at the bottommost layer at the bottom of the groove;
etching to remove part of the first fin part layer on the side wall of the groove to form a first correction fin part layer;
forming initial barrier layers on the side walls of the groove, the side wall of the first correction fin part layer and the side wall of the pseudo gate structure;
removing the second fin part layer at the bottommost layer, and forming a gap between the first fin part layer at the bottommost layer and the first correction fin part layer at the bottommost layer;
and removing the first corrected fin portion layer to form a grid electrode structure surrounding the second fin portion layer, wherein the substrate and the grid electrode structure are isolated by the gap.
2. The method of forming as claimed in claim 1, further comprising, after forming the gap:
forming isolation layers on the first fin portion layer at the bottommost layer on two sides of the gap, the bottom of the first correction fin portion layer at the bottommost layer, the bottom, the side wall and the top of the initial blocking layer, the bottom of the groove and the top of the dummy gate structure;
forming an insulating layer on the isolation layer at the bottom of the groove, wherein the insulating layer covers part of the isolation layer on the side wall of the initial barrier layer;
and etching and removing the isolation layer and part of the initial barrier layer which are not covered by the insulating layer until the top and the side wall of the pseudo gate structure and the side wall of the second fin portion layer are exposed, and forming a barrier layer on the side wall of the first correction fin portion layer.
3. The method of claim 2, wherein the barrier layer comprises a first barrier layer and a second barrier layer, a thickness of the second barrier layer is greater than a thickness of the first barrier layer, a direction of the thickness is perpendicular to a direction of sidewalls of the second barrier layer, the first barrier layer is located on sidewalls of the first modified fin layer between adjacent second fin layers, and the second barrier layer is located on sidewalls of the first modified fin layer between the gap and the second fin layers.
4. The method of forming as claimed in claim 2, further comprising: and forming a source-drain doped layer in the groove.
5. The method of forming in accordance with claim 4, further comprising, after forming said source drain doping layer:
forming a dielectric layer on the source drain doping layer and the dummy gate structure, wherein the dielectric layer covers the side wall of the dummy gate structure;
removing the dummy gate structure and the first correction fin portion layer covered by the dummy gate structure, and forming a gate opening in the dielectric layer and between the adjacent second fin portion layers;
and forming a grid structure in the grid opening, wherein the grid structure surrounds the second fin part layer.
6. The method of forming of claim 1, wherein the initial barrier layer is silicon nitride, silicon carbide, silicon oxynitride, or silicon oxide.
7. The method of claim 1, wherein the process of forming the initial barrier layer comprises a physical vapor deposition process or a chemical vapor deposition process.
8. The method of claim 1, wherein a material of the first fin layer and a material of the second fin layer are different; the first fin portion layer is made of monocrystalline silicon, and the second fin portion layer is made of monocrystalline silicon germanium; or the first fin portion layer is made of monocrystalline silicon germanium, and the second fin portion layer is made of monocrystalline silicon.
9. The method of claim 1, wherein a process of removing the second fin layer at the bottom layer is a dry etching process or a wet etching process.
10. The method of claim 1, wherein etching the fin structure on both sides of the dummy gate structure further comprises, before forming a recess in the fin structure: and forming a side wall on the side wall of the pseudo gate structure.
11. A semiconductor device, comprising:
the structure comprises a substrate, wherein a fin part structure is arranged on the substrate and comprises a plurality of first fin part layers and a second fin part layer positioned between the first fin part layers of two adjacent layers;
the grid structure is positioned on the substrate and covers part of the side wall and part of the top of the fin part structure, and the grid structure surrounds the second fin part layer;
the grooves are positioned in the fin part structures on two sides of the grid structure, and the first fin part layer at the bottommost layer is exposed at the bottom of the grooves;
a gap between the first fin layer at the bottom layer and the bottom of the gate structure;
and the barrier layers are positioned on the side wall of the grid electrode structure between the two adjacent layers of the second fin portion layers and on the side wall of the grid electrode structure between the gap and the second fin portion layers.
12. The semiconductor device of claim 11, wherein the barrier layer comprises a first barrier layer and a second barrier layer, the first barrier layer is located on sidewalls of the gate structure between two adjacent layers of the second fin layer, and the second barrier layer is located on sidewalls of the gate structure between the gap and the second fin layer.
13. The semiconductor device of claim 12, in which a thickness of the second barrier layer is greater than a thickness of the first barrier layer, a direction of the thickness being perpendicular to a direction of sidewalls of the second barrier layer.
14. The semiconductor device according to claim 12, further comprising: the isolation layer is located on the first fin portion layer at the bottommost layer of the bottom of the groove, on the first fin portion layer at the bottommost layer of the two sides of the gap, and on the bottom and the side wall of the second barrier layer.
15. The semiconductor device according to claim 14, further comprising: and the insulating layer is positioned on the isolating layer at the bottom of the groove and positioned on the isolating layer on the side wall of the second barrier layer.
16. The semiconductor device according to claim 11, further comprising: and the source drain doping layer is positioned in the groove.
17. The semiconductor device of claim 16, further comprising a dielectric layer on the substrate and covering the source-drain doping layer, a top surface of the dielectric layer being flush with a top surface of the gate structure.
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