CN113745111B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN113745111B CN113745111B CN202010469265.1A CN202010469265A CN113745111B CN 113745111 B CN113745111 B CN 113745111B CN 202010469265 A CN202010469265 A CN 202010469265A CN 113745111 B CN113745111 B CN 113745111B
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- 238000002955 isolation Methods 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 46
- 239000011229 interlayer Substances 0.000 claims description 30
- 239000002019 doping agent Substances 0.000 claims description 22
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- 238000011065 in-situ storage Methods 0.000 claims description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor device and a method of forming the same, the method of forming the same includes: providing a substrate, wherein the substrate comprises a first region, a first source doping layer is arranged on the first region, and first doping ions are arranged in the first source doping layer; forming a plurality of openings in the first source doping layer, wherein the bottoms of the openings expose the surface of the substrate of the first region; forming a channel pillar on a surface of the substrate in the exposed first region, the channel pillar including a second portion located within the opening and having sidewalls covered by the first source doping layer and a first portion located on the second portion; ion doping is carried out on the second part of the channel column to form a second source doped layer, second doped ions are arranged in the second source doped layer, the ion concentration of the second doped ions is smaller than that of the first doped ions, and the ion type of the second doped ions is the same as that of the first doped ions; the forming method of the invention improves the performance of the formed semiconductor device.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor device and a method of forming the same.
Background
Fin field effect transistors (Fin FETs) are an emerging type of multi-gate device that generally include a Fin protruding from a semiconductor substrate surface, a gate structure covering a portion of the top surface and sidewalls of the Fin, and source-drain doped regions in the Fin on either side of the gate structure. Compared with a planar metal-oxide semiconductor field effect transistor, the fin field effect transistor has stronger short channel inhibition capability and stronger working current.
With further development of semiconductor technology, the size of integrated circuit devices is smaller and smaller, and conventional fin field effect transistors have limitations in further increasing the operating current. In particular, since only the regions of the fin near the top surface and the sidewalls are used as the channel region, the volume of the fin used as the channel region is smaller, which limits the operating current of the fin field effect transistor. Therefore, a fin field effect transistor of a gate-all-around (GAA) structure is proposed, so that the volume for serving as a channel region is increased, and the operating current of the fin field effect transistor of the gate-around structure is further increased.
However, the performance of the fin field effect transistor with the channel gate surrounding structure in the prior art needs to be improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of a fin field effect transistor with a channel gate surrounding structure.
In order to solve the above technical problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate comprises a first region, a first source doping layer is arranged on the first region, and first doping ions are arranged in the first source doping layer; forming a plurality of openings in the first source doping layer, wherein the bottoms of the openings expose the surface of the substrate of the first region; forming a channel pillar on the exposed surface of the substrate of the first region, the channel pillar including a second portion located within the opening and having sidewalls covered by the first source doping layer and a first portion located on the second portion; and carrying out ion doping on the second part of the channel column to form a second source doped layer, wherein second doped ions are arranged in the second source doped layer, the ion concentration of the second doped ions is smaller than that of the first doped ions, and the ion type of the second doped ions is the same as that of the first doped ions.
Optionally, the second dopant ion has an ion concentration of 1.0E20 atoms/cm 3 ～8.0E21aotm/cm 3 。
Optionally, the doping process of the second doping ions includes in-situ doping.
Optionally, the substrate further includes a second region, the first region is adjacent to the second region, a third source doped layer is provided on the second region, and third doped ions are provided in the third source doped layer.
Optionally, the step of forming the opening in the first source doped layer includes: forming a plurality of discrete initial channel pillars on the first source doped layer and the third source doped layer; forming an initial isolation layer on the substrate, wherein the initial isolation layer covers the first source doping layer, the third source doping layer and the initial channel column; and removing the initial channel column of the first region and the first source doping layer at the bottom of the initial channel column until the surface of the substrate of the first region is exposed, and forming the opening in the first source doping layer.
Optionally, the initial channel pillar and the channel pillar are made of non-identical materials.
Optionally, the ion type of the third doping ion is opposite to the ion type of the first doping ion.
Optionally, after forming the second source doped layer, the method further includes: and removing part of the initial isolation layer to form an isolation layer covering the channel columns and part of the side walls of the initial channel columns, wherein the top surfaces of the isolation layer are lower than the top surfaces of the initial channel columns and the channel columns.
Optionally, after forming the isolation layer, the method further includes: a first gate structure is formed on a sidewall of the first portion of the channel pillar, the first gate structure including a first portion surrounding the sidewall of the channel pillar and a second portion located at the substrate surface of the first region on a side of the channel pillar.
Optionally, after forming the isolation layer, the method further includes: a second gate structure is formed on the sidewalls of the initial channel pillar, the second gate structure including a first portion surrounding the sidewalls of the initial channel pillar and a second portion on the substrate surface of the second region on one side of the initial channel pillar.
Optionally, an interlayer dielectric layer is formed on the first region and the second region of the substrate, a first conductive structure, a second conductive structure and a third conductive structure are formed in the interlayer dielectric layer of the first region, the first conductive structure is electrically connected with the first source doping layer, the second conductive structure is electrically connected with the top of the channel pillar, and the third conductive structure is electrically connected with the second portion of the first gate structure.
Optionally, a fourth conductive structure, a fifth conductive structure and a sixth conductive structure are formed in the interlayer dielectric layer of the second region, the fourth conductive structure is electrically connected with the third source doping layer, the fifth conductive structure is electrically connected with the top of the initial channel pillar, and the sixth conductive structure is electrically connected with the second portion of the second gate structure.
Optionally, before forming the initial isolation layer, the method further includes: and forming a third drain doping layer, wherein the third drain doping layer is positioned on the top of the initial channel column.
Optionally, the method further comprises: and forming a protective layer, wherein the protective layer is positioned on the third leakage doping layer.
Correspondingly, the invention also provides a semiconductor device, which comprises: a substrate comprising a first region; a first source doped layer on the substrate of the first region, the first source doped layer having first dopant ions therein; a channel pillar comprising a first portion and a second portion, the first portion being located on the first source doped layer, the second portion being located within the first source doping and sidewalls being covered by the first source doped layer; the second source doping layer is formed by ion doping of a second part of the channel column and is provided with second doping ions; wherein: the ion concentration of the second doping ions is smaller than that of the first doping ions, and the ion type of the second doping ions is the same as that of the first doping ions.
Optionally, the second dopant ion has an ion concentration of 1.0E20 atoms/cm 3 ～8.0E21atom/cm 3 。
Optionally, the substrate further includes a second region, the first region is adjacent to the second region, a third source doped layer is disposed on the second region, and third doped ions are disposed in the third source doped layer.
Optionally, the method further comprises: and an initial channel pillar located on the third source doping layer.
Optionally, the initial channel pillar and the channel pillar are made of non-identical materials.
Optionally, the ion type of the third doping ion is opposite to the ion type of the first doping ion.
Optionally, the method further comprises: and the isolating layer is positioned on the substrate and covers the channel columns and part of the side walls of the initial channel columns, and the top surfaces of the isolating layer are lower than the top surfaces of the initial channel columns and the channel columns.
Optionally, the method further comprises: a first gate structure on a sidewall of the channel pillar, the first gate structure including a first portion surrounding the sidewall of the channel pillar and a second portion on the substrate surface of the first region on a side of the channel pillar.
Optionally, the method further comprises: a second gate structure on a sidewall of the initial channel pillar, the second gate structure including a first portion surrounding the sidewall of the initial channel pillar and a second portion on the substrate surface of the second region on a side of the initial channel pillar.
Optionally, the method further comprises: and an interlayer dielectric layer which is positioned on the first region and the second region of the substrate and the top of which is higher than the top surfaces of the first gate structure and the second gate structure.
Optionally, the method further comprises: the first conductive structure, the second conductive structure and the third conductive structure are located in the interlayer dielectric layer of the first region, the first conductive structure is electrically connected with the first source doping layer, the second conductive structure is electrically connected with the top of the channel pillar, and the third conductive structure is electrically connected with the second part of the first gate structure.
Optionally, the method further comprises: the fourth conductive structure, the fifth conductive structure and the sixth conductive structure are located in the interlayer dielectric layer of the second region, the fourth conductive structure is electrically connected with the third source doping layer, the fifth conductive structure is electrically connected with the top of the initial channel column, and the sixth conductive structure is electrically connected with the second part of the second gate structure.
Optionally, the method further comprises: and the third drain doping layer is positioned at the top of the initial channel column, and the third doping ions are arranged in the third drain doping layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
forming a channel column on the substrate, wherein a first part of the channel column is located on the first source doping layer, a second part of the channel column is covered by the first source doping layer, and ion doping is carried out on the second part of the channel column, so that a second source doping layer is formed on the second part of the channel column, the concentration of second doping ions in the second source doping layer is smaller than that of first doping ions in the first source doping layer, and the ion types of the second doping ions are the same as those of the first doping ions. On the one hand, the concentration of the second doping ions in the second source doping layer is smaller than that of the first doping ions in the first source doping layer, on the other hand, the concentration of the second doping ions in the second source doping layer is lower than that of the first doping ions in the first source doping layer, so that the diffusion of the second doping ions into the channel column can be better controlled, the damage to the channel column is reduced, the quality of the channel column is improved, and because the concentration of the doping ions in the second source doping layer at the bottom of the channel column is low, ions which can be directly diffused into the channel column are fewer, and the first source doping layer is far away from the channel column, so that the damage to the channel column caused by the diffusion ions in the first source doping layer is less; meanwhile, the bottom of the channel column is provided with lower contact resistance due to the high concentration of the first doping ions in the first source doping layer on the substrate, because the contact is an ohmic contact, the resistance is related to the ion doping concentration, and the higher the ion doping concentration is, the lower the resistance is, so that the performance of the finally formed semiconductor device is enhanced.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment;
fig. 2 to 8 are schematic cross-sectional structures of a semiconductor device forming process in an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the fin field effect transistor with the conventional channel gate surrounding structure is to be improved. The analysis will now be described with reference to specific examples.
Fig. 1 is a schematic cross-sectional structure of a semiconductor device in an embodiment.
Referring to fig. 1, the method includes: a substrate 100, the substrate 100 comprising a first region 110 and a second region 120; a first source doped layer 111 located on the first region 110, the first source doped layer 111 having first doping ions therein; a second source doped layer 121 located in the second region, the second source doped layer 121 having second doped ions therein, the first doped ions having an ion type opposite to the ion type of the second doped ions; a first channel pillar 112 located on the first source doping layer 111; a second channel pillar 122 located on the second source doping layer 121, the material of the first channel pillar 112 being different from the material of the second channel pillar 122; an isolation layer 130 on the first and second source doping layers 111 and 121, the isolation layer 130 covering part of sidewalls of the first and second channel pillars 112 and 122; a first gate structure 113 located on a sidewall of the first channel pillar 112, the first gate structure 113 including a first portion 114 located on a sidewall of the first channel pillar 112, and a second portion 115 located on the substrate 100 on one side of the first channel pillar 112; a second gate structure 123 located on a sidewall of the second channel pillar 122, the second gate structure 123 including a first portion 124 located on a sidewall of the second channel pillar 122, the second portion 125 located on the substrate 100 on a side of the second channel pillar 122; a dielectric layer 140 on the substrate 100, the dielectric layer 140 covering the first gate structure 113 and the second gate structure 123, a top surface of the dielectric layer 140 being higher than a top surface of the first gate structure 113 and a top surface of the second gate structure 123; the conductive structures at the dielectric layer 140 include a first conductive structure 116 connected to the first source doped layer 111, a second conductive structure 117 connected to the top of the first channel pillar 112, a third conductive structure 118 connected to the second portion 115 of the first gate structure 113, a fourth conductive structure 126 connected to the second source doped layer 121, a fifth conductive structure 127 connected to the top of the second channel pillar 122, and a sixth conductive structure 128 connected to the second portion 125 of the second gate structure 123.
The semiconductor device with the structure is characterized in that a first channel column is formed on a first source doping layer, a second channel column is formed on a second source doping layer, materials of the first channel column and the second channel column are different, the second channel column is directly formed on the second source doping layer or the first channel column is directly formed on the first source doping layer, so that source doping layers with different concentrations are not formed at the bottoms and the peripheries of the first channel column or the second channel column, and short channel control and contact resistance control cannot be optimized to the greatest extent.
In order to solve the above problems, the technical scheme of the invention provides a semiconductor device and a forming method thereof,
and carrying out ion doping on a second part of the channel column covered by the first source doping layer to form a second source doping layer, wherein the first part of the channel column is positioned on the second source doping layer, the concentration of second doping ions in the second source doping layer is smaller than that of first doping ions in the first source doping layer, and the ion type of the second doping ions is the same as that of the first doping ions. In the subsequent use process, the first part of the channel column is used as a channel, the first part of the channel column is positioned on the second source doping layer, and as the concentration of second doping ions in the second source doping layer is smaller than that of first doping ions in the first source doping layer, the concentration of doping ions in the second source doping layer positioned at the bottom of the channel column is low, so that ions which can be directly diffused to the channel column are few, the first source doping layer is far away from the channel column, and the damage to the channel column caused by diffusion ions in the first source doping layer is less; meanwhile, the bottom of the channel column is provided with lower contact resistance due to the high concentration of the first doping ions in the first source doping layer on the substrate, because the contact is an ohmic contact, the resistance is related to the ion doping concentration, and the higher the ion doping concentration is, the lower the resistance is, so that the performance of the finally formed semiconductor device is enhanced.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Note that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 2 to 8 are schematic cross-sectional structures of a semiconductor device forming process in an embodiment of the present invention.
Referring to fig. 2, a substrate 200 is provided, the substrate 200 includes a first region 210, and a first source doped layer 211 is disposed on the first region 210, and first doped ions are disposed in the first source doped layer.
In this embodiment, the material of the substrate 200 is monocrystalline silicon; in other embodiments, the substrate may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, or silicon-on-insulator.
In this embodiment, the ion type of the first doped ion is P-type; the P-type ions include boron ions or indium ions.
In other embodiments, the ion type of the first doped ion may also be N-type; the N-type ions include phosphorus ions or arsenic ions.
In this embodiment, the first dopant ions are boron (B) ions, and the ion concentration of the first dopant ions is 3.0E20atom/cm 3 ～1.0E22atom/cm 3 。
In the present embodiment, the first source doping layer 211 is formed for the purpose of being used as a source later.
With continued reference to fig. 2, the substrate 200 further includes a second region 220, the first region 210 is adjacent to the second region 220, the second region 220 has a third source doped layer 221 thereon, and the third source doped layer 221 has third doped ions therein.
In this embodiment, the ion type of the first doping ion is opposite to the ion type of the third doping ion.
In this embodiment, the ion type of the third doped ion is N type; the N-type ions include phosphorus ions or arsenic ions.
In other embodiments, the ion type of the third doped ion may also be P-type; the P-type ions include boron ions or indium ions.
In the present embodiment, the third source doping layer 221 is formed for the purpose of being used as a source later.
In the present embodiment, the forming process of the first source doping layer 211 and the third source doping layer 221 includes an ion implantation process. In other embodiments, the forming process of the first source doping layer 211 and the third source doping layer 221 includes an in-situ doping process.
Referring to fig. 3, a plurality of discrete initial channel pillars 222 are formed on the first source doping layer 211 and the third source doping layer 221.
The method for forming the initial channel pillar 222 includes: forming an initial channel material layer (not shown) on the substrate 200; forming a patterned mask layer (not shown) on the surface of the initial channel material layer, wherein the patterned mask layer exposes a part of the surface of the initial channel material layer; and etching the initial channel material layer by taking the patterned mask layer as a mask until the surfaces of the first source doping layer 211 and the third source doping layer 221 are respectively exposed, and forming initial channel columns 222 on the first source doping layer 211 and the third source doping layer 221.
In this embodiment, the material of the initial channel pillars 222 comprises silicon. In other embodiments, the material of the initial channel pillars 222 comprises semiconductor material such as germanium, silicon germanium, gallium arsenide, or the like.
The process of etching the initial channel material layer comprises a dry etching process or a wet etching process; the process of forming the initial channel material layer includes a physical vapor deposition process, an epitaxial growth process, or an atomic layer deposition process.
In this embodiment, the process of etching the initial channel material layer includes a dry etching process, which can form the initial channel pillar 222 with good sidewall morphology; the process of forming the initial channel material layer includes a physical vapor deposition process capable of forming an initial channel material layer having a dense structure and a thicker thickness.
In this embodiment, the material of the patterned mask layer includes photoresist; the process of forming the patterned mask layer includes a spin-on process.
In other embodiments, the patterned mask layer includes a hard mask layer and a photoresist layer on the hard mask layer, and the material of the hard mask layer includes silicon oxide or silicon nitride.
In this embodiment, further comprising: a third drain doping layer 223 is formed on the top surface of the initial channel pillar 222, and the third drain doping layer 223 has the third doping ions therein.
In this embodiment, further comprising: a protective layer 224 is formed on the top surface of the third drain doping layer 223, and the protective layer is used to protect the top surface of the third drain doping layer 223 from being damaged in the subsequent process. The material of the protective layer 224 includes silicon nitride.
In other embodiments, the protective layer may not be formed.
After the initial channel pillars 222 are formed, the patterned masking layer is removed. In this embodiment, the process of removing the patterned mask layer includes an ashing process.
With continued reference to fig. 3, an initial isolation layer 300 is formed on the substrate 200, wherein the initial isolation layer 300 covers the first source doping layer 211, the third source doping layer 221, and the initial channel pillars 222.
In this embodiment, the initial isolation layer 300 is formed on the first source doping layer 211 and the third source doping layer 221, the initial isolation layer 300 covers the sidewalls of the initial channel pillars 222, and the top surface of the initial isolation layer 300 is higher than the top surface of the initial channel pillars 222.
In this embodiment, the material of the initial isolation layer 300 is silicon oxide; in other embodiments, the material of the initial isolation layer 300 may also be silicon nitride, silicon oxynitride, or silicon carbide nitride.
The process of forming the initial isolation layer 300 includes a flowable chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the process of forming the initial isolation layer 300 includes a flowable chemical vapor deposition process capable of forming an initial isolation layer having a dense structure and a thicker thickness.
In this embodiment, an initial isolation layer is formed on the first source doped layer and the third source doped layer, and the initial isolation layer 300 is formed by planarizing the material layer of the initial isolation layer until the top surface of the protection layer 224 is exposed.
Referring to fig. 4, a plurality of openings 212 are formed in the first source doped layer 211, and the bottoms of the openings 212 expose the surface of the substrate 200 of the first region 210.
The method of forming the opening 212 includes: the initial channel pillar 222 of the first region 210 and the first source doped layer 211 at the bottom of the initial channel pillar 222 are removed until the surface of the substrate 200 of the first region 210 is exposed, and the opening 212 is formed in the first source doped layer 211.
In this embodiment, the process of forming the opening 212 is a dry etching process; in other embodiments, the process of forming the opening 212 may also be a wet etching process.
In this embodiment, the process parameters for forming the opening 212 include: the gases used include: h 2 、O 2 、CH 3 F, wherein the H 2 Is 50sccm to 300sccm, O 2 The gas flow is 20sccm to 200sccm, CH 3 The flow rate of F gas is 40sccm to 1000sccm, and the reaction pressure is 20 mTorr to 200 mTorr.
In this embodiment, the purpose of removing the initial channel pillar 222 on the first source doped layer 211 on the first region 210 is to: channel pillars of a different material than the initial channel pillars 222 are subsequently formed on the first doped layer of the first region 210.
Referring to fig. 5, a channel pillar 213 is formed on the exposed surface of the substrate 200 of the first region 210, the channel pillar 213 including a second portion 215 located within the opening 212 and having sidewalls covered by the first source doped layer 211 and a first portion 214 located on the second portion 215.
The top surface of the channel pillar 213 is flush with the top surface of the initial isolation layer 300.
In this embodiment, the material of the channel pillar 213 is different from the material of the initial channel pillar 222.
In this embodiment, the material of the channel pillar 213 is silicon germanium; in other embodiments, the material of the channel pillar 213 may also be silicon or the like.
In this embodiment, the process of forming the channel pillar 213 is an epitaxial growth process.
In this embodiment, the process parameters for forming the channel pillar 213 include: the reaction gases used include: h 2 、HCl、SiCl 2 H 2 GeH 4 Wherein: h 2 Is 10sccm to 300sccm, HCl is 10sccm to 200sccm, siCl 2 H 2 Is 200sccm to 2000sccm, geH 4 The gas flow rate is 10sccm to 1500sccm, the temperature is 600 ℃ to 850 ℃, and the reaction pressure is 8 Torr to 300 Torr.
With continued reference to fig. 5, the second portion 215 of the channel pillar 213 is ion doped to form a second source doped layer 216, where the second source doped layer 216 has second doped ions therein, the second doped ions have a concentration less than that of the first doped ions, and the second doped ions have a same ion type as the first doped ions.
In this embodiment, during the operation of the semiconductor device, the first portion 214 of the channel pillar 213 serves as a channel, and since the concentration of the second doping ions in the second source doping layer 216 at the bottom of the channel is smaller than the concentration of the first doping ions in the first source doping layer 211 located around the second source doping layer, the ions that can diffuse into the first portion 214 of the channel pillar 213 in the second source doping layer 216 are reduced, and the ions that can diffuse into the first portion 214 in the first source doping layer around the second source doping layer are less due to the distance from the first portion 214, so that the damage of the diffused ions to the channel pillar 213 is reduced, and the quality of the first portion 214 used as a channel is improved, so as to improve the quality of the formed semiconductor device.
In the present embodiment, the concentration of the first doping ions in the first source doping layer 211 is higher and is larger than that of the second doping ions in the second source doping layer 216, so that the bottom of the channel pillar has lower contact resistance, because the contact is an ohmic contact, the resistance is related to the ion doping concentration, and the higher the ion doping concentration is, the lower the resistance is, so that the performance of the finally formed semiconductor device is enhanced.
The ions of the second doping ions are N-type ions or P-type ions.
In this embodiment, the ion type of the second doped ion is the same as that of the first doped ion, so the second doped ion is a P-type ion.
When the second doping ion is a P-type ion, the ion of the second doping ion is a boron ion or an indium ion.
In other embodiments, when the second dopant ion is an N-type ion, the ion of the second dopant ion is a phosphorus ion or an arsenic ion.
In this embodiment, the ions of the second doping ions are the same as those of the first doping ions, and boron (B) ions are used.
In this embodiment, the ions of the second doping ion are the same as those of the first doping ion, that is, boron (B) ions are used, and the same doping ion is selected to reduce the resistance of the formed device.
In other embodiments, the ions of the second dopant ions may also be different from the ions of the first dopant ions.
In the present embodiment, the ion concentration of the second dopant ion is 1.0E20 atoms/cm 3 ～～8.0E21atom/cm 3 . When the ion concentration of the second doping ion is less than 1.0E20atom/cm 3 The ion concentration of the second doping ions is low, and the formed resistance is too large; when the vertical ion concentration of the second doping ion is more than 8.0E21atom/cm 3 The higher the ion concentration of the second doping ion is, the more ions can be diffused into the channel column, and the more damage to the channel column is.
In this embodiment, the doping process of the second doping ion is an in-situ doping process, and the specific process doping includes: the reaction gases used include: siH (SiH) 2 Cl 2 、B 2 H 6 Mixed gas of GeH4, wherein the gas flow rate of the mixed gas is 1sccm to 1000sccm, and H is injected simultaneously 2 ，H 2 The volume size of the (C) is 0.1 SLM-50 SLM, the pressure is 50-300 Torr, and the temperature is 650-800 ℃.
Referring to fig. 6, after forming the second source doped layer 216, the method further includes: a portion of the initial isolation layer 300 is removed to form an isolation layer 310 covering the channel pillars 213 and a portion of the sidewalls of the initial channel pillars 222, the top surface of the isolation layer 310 being lower than the top surfaces of the initial channel pillars 222 and the channel pillars 213.
In this embodiment, the isolation layer 310 covers a portion of the sidewall of the first portion 214 of the channel pillar 213.
In this embodiment, the process of removing a portion of the thickness of the initial isolation layer 300 is a dry etching process.
In this embodiment, the isolation layer 310 is formed so that electrical isolation is formed between devices.
In this embodiment, further comprising: the protective layer 224 on the surface of the third drain doped layer 223 is removed.
Referring to fig. 7, after forming the isolation layer 310, the method further includes: a first gate structure 410 is formed on a sidewall of the first portion 214 of the channel pillar 213, the first gate structure 410 including a first portion surrounding the sidewall of the first portion 214 of the channel pillar 213 and a second portion located on the surface of the substrate 200 of the first region 210 on one side of the channel pillar 213.
With continued reference to fig. 7, a second gate structure 420 is formed on the sidewall of the initial channel pillar 222, the second gate structure 420 including a first portion surrounding the sidewall of the initial channel pillar 222 and a second portion on the surface of the substrate 200 in the second region 220 on one side of the initial channel pillar 222.
In this embodiment, the first gate structure 410 and the second gate structure 420 have the same structure, and each includes a gate dielectric layer 401, a work function layer 402, and a gate layer 403.
In this embodiment, the gate dielectric layer 401 of the first gate structure 410 is located on the sidewall of the first portion 214 of the channel pillar 213, the work function layer 402 is located on the surface of the gate dielectric layer 401, and the gate layer 403 is located on the surface of the work function layer 402.
In this embodiment, the gate dielectric layer 401 of the second gate structure 420 is located on the sidewall of the initial channel pillar 222, the work function layer 402 is located on the surface of the gate dielectric layer 401, and the gate layer 403 is located on the surface of the work function layer 402.
In this embodiment, the material of the gate dielectric layer 401 includes a high dielectric constant material, where the dielectric constant of the high dielectric constant material is greater than 3.9; the high dielectric constant material comprises hafnium oxide or aluminum oxide.
In other embodiments, the gate dielectric layer 401 comprises silicon oxide.
The material of the work function layer 402 includes titanium nitride, aluminum titanium, or tantalum nitride.
The material of the gate layer 403 includes polysilicon or metal. In this embodiment, the material of the gate layer includes a metal including tungsten.
In the present embodiment, the process of forming the work function material layer includes a chemical vapor deposition process or a physical vapor deposition process.
In this embodiment, the process of forming the gate material layer includes a physical vapor deposition process or an electroplating process.
In the present embodiment, the process of etching the gate material layer and the work function material layer includes a dry etching process.
In this embodiment, the first gate structure 410 is also located on the top surface of the first portion 214 of the channel pillar 213.
In this embodiment, the second gate structure 420 is further located on the top surface of the third drain doped layer 223.
Referring to fig. 8, an interlayer dielectric layer 400 is formed on the first region 210 and the second region 220 of the substrate 200.
The interlayer dielectric layer 400 is formed on the isolation layer 300, and the top surface of the interlayer dielectric layer 400 is higher than the top surfaces of the first gate structure 410 and the second gate structure 420.
In this embodiment, the material of the interlayer dielectric layer 400 includes silicon oxide; in other embodiments, the material of the interlayer dielectric layer 400 includes silicon nitride or silicon carbide nitride.
In this embodiment, the process of forming the interlayer dielectric layer 400 includes a chemical vapor deposition process. In other embodiments, the process of forming the interlayer dielectric layer 400 includes an atomic layer deposition process or a thermal oxidation process.
In this embodiment, the specific forming process of the interlayer dielectric layer 400 is divided into two steps, wherein a first interlayer dielectric layer (not shown in the figure) is formed on the isolation layer 310, and the first gate structure and the second gate structure are planarized after the first interlayer dielectric layer is formed, until the top surface of the first portion 214 of the channel pillar 213, a part of the sidewall of the first portion 214, and the top and sidewall surfaces of the third undoped layer 223 are exposed; a second interlayer dielectric layer (not shown) is then formed on the first interlayer dielectric layer, the top surface of the second interlayer dielectric layer being higher than the top surface of the third drain doped layer 223 and the top surface of the first portion 214 of the channel pillar 213.
With continued reference to fig. 8, a first conductive structure 501, a second conductive structure 502, and a third conductive structure 503 are formed in the interlayer dielectric layer 400 of the first region 210, wherein the first conductive structure 501 is electrically connected to the first source doped layer 211, the second conductive structure 502 is electrically connected to the top of the channel pillar 213, and the third conductive structure 503 is electrically connected to the second portion of the first gate structure 410.
A fourth conductive structure 504, a fifth conductive structure 505 and a sixth conductive structure 506 are formed in the interlayer dielectric layer 400 of the second region 220, the fourth conductive structure 504 is electrically connected to the third source doped layer 221, the fifth conductive structure 505 is electrically connected to the top of the initial channel pillar 222, i.e. to the third drain doped layer 223, and the sixth conductive structure 506 is electrically connected to the second portion of the second gate structure 420.
Accordingly, the present invention also provides a semiconductor device comprising a substrate 200, the substrate 200 comprising a first region 210 and a second region 220; a first source doped layer 211 on the substrate 200 of the first region 210, the first source doped layer 211 having first dopant ions therein; a channel pillar 213 comprising a first portion 214 and a second portion 215, the first portion 214 being located on the second portion 215, the second portion 215 being located within the first source doped layer 211 and sidewalls being covered by the first source doped layer 211; a second source doped layer 216, which is formed by ion doping the second portion 215 of the channel pillar 213 and has second doped ions; wherein: the ion concentration of the second doping ions is smaller than that of the first doping ions, and the ion type of the second doping ions is the same as that of the first doping ions.
In this embodiment, the first portion 214 of the channel pillar 213 is located on the second source doped layer 216, the ion concentration of the second doped ions is smaller than that of the first doped ions, the first portion 214 of the channel pillar 213 is used as a channel, so that the second source doped layer 216 at the bottom of the channel is used to have a smaller ion concentration, so that the ions that can diffuse into the first portion 214 of the channel pillar 213 in the second source doped layer 216 are reduced, and the first source doped layer 211 located around the second source doped layer 216 can diffuse into the first portion 214 less due to the distance from the first portion 214, thereby reducing the damage of the diffused ions to the channel pillar 213 and improving the quality of the first portion 214 used as a channel.
In this embodiment, at the same time, since the first doping ion concentration in the first source doping layer 211 on the substrate 200 is high, the bottom of the channel pillar has a lower contact resistance, because the contact is an ohmic contact, and the resistance is related to the ion doping concentration, the higher the ion doping concentration is, the smaller the resistance is, so that the performance of the finally formed semiconductor device is enhanced, and the performance of the formed semiconductor device is improved.
In this embodiment, the ion type of the first doped ion is P-type; in other embodiments, the ion type of the first doping ion may also be N-type.
When the first doping ions are P-type ions, the ions of the first doping ions are boron ions or indium ions;
when the first doping ion is an N-type ion, the ion of the first doping ion is a phosphorus ion or an arsenic ion.
In this embodiment. The ions of the second doping ions are the same as those of the first doping ions, and boron (B) ions are adopted.
In this example, 1.0E20atom/cm 3 ～～8.0E21atom/cm 3 . When the ion concentration of the second doping ion is less than 1.0E20atom/cm 3 The ion concentration of the second doping ions is low, and the formed resistance is too large; when the vertical ion concentration of the second doping ion is more than 8.0E21atom/cm 3 The higher the ion concentration of the second doping ion is, the more ions can be diffused into the channel column, and the more damage to the channel column is.
In this embodiment, the substrate 200 further includes a second region 220, where the first region 210 is adjacent to the second region 220, and a third source doped layer 221 is disposed on the second region 220, and third doped ions are disposed in the third source doped layer 221.
In this embodiment, further comprising: an initial channel pillar 222, the initial channel pillar 222 being located on the third source doped layer 221.
In this embodiment, the initial channel pillar 222 and the channel pillar 213 are made of non-identical materials.
In this embodiment, the ion type of the third doped ion is opposite to the ion type of the first doped ion, and the ion type of the third doped ion is N-type; the N-type ions include phosphorus ions or arsenic ions.
In other embodiments, the ion type of the third doped ion may also be P-type; the P-type ions include boron ions or indium ions.
In this embodiment, an isolation layer 310 is located on the substrate 200 and covers part of the sidewalls of the channel 213 and the initial channel pillar 222, and the top surface of the isolation layer 310 is lower than the top surfaces of the initial channel pillar 222 and the channel pillar 213.
In this embodiment, further comprising: a first gate structure 410 is located on a sidewall of the channel pillar 213, and includes a first portion surrounding the sidewall of the channel pillar 213 and a second portion located on the substrate surface of the first region on one side of the channel pillar 213.
In this embodiment, the first portion of the first gate structure surrounds the sidewall of the first portion 214 of the channel pillar 213.
In this embodiment, further comprising: a second gate structure 420 is located on a sidewall of the initial channel pillar, the second gate structure including a first portion surrounding the sidewall of the initial channel pillar 222 and a second portion located on the substrate surface of the second region on one side of the initial channel pillar 222.
In this embodiment, further comprising: an interlayer dielectric layer 400 is located on the first region 210 and the second region 220 of the substrate 200, and has a top higher than top surfaces of the first gate structure 410 and the second gate structure 420.
In this embodiment, further comprising: a first conductive structure 501, a second conductive structure 502 and a third conductive structure 503, wherein the first conductive structure 501, the second conductive structure 502 and the third conductive structure 503 are located in the interlayer dielectric layer 400 of the first region 210, the first conductive structure 501 is electrically connected with the first source doped layer 211, the second conductive structure 502 is electrically connected with the top of the channel pillar 213, and the third conductive structure 503 is electrically connected with the second portion of the first gate structure.
In this embodiment, further comprising: fourth conductive structure 504, fifth conductive structure 505 and sixth conductive structure 506, said fourth conductive structure 504, said fifth conductive structure 505 and said sixth conductive structure 506 being located within said interlayer dielectric layer 400 of the second region 220, said fourth conductive structure 504 being electrically connected to said third source doped layer 221, said fifth conductive structure 505 being electrically connected to the top of said initial channel pillar 222, said sixth conductive structure 506 being electrically connected to the second portion of said second gate structure.
In this embodiment, further comprising: and a third drain doping layer 223, wherein the third drain doping layer 223 is positioned at the top of the initial channel pillar 222, and the third drain doping layer 223 has the third doping ions therein.
In this embodiment, the fifth conductive structure 505 is electrically connected to the top of the third drain doped layer 223.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (27)
1. A method of forming a semiconductor device, comprising:
Providing a substrate, wherein the substrate comprises a first region, a first source doping layer is arranged on the first region, and first doping ions are arranged in the first source doping layer;
forming a plurality of openings in the first source doping layer, wherein the bottoms of the openings expose the surface of the substrate of the first region;
forming a channel pillar on the exposed surface of the substrate of the first region, the channel pillar including a second portion located within the opening and having sidewalls covered by the first source doping layer and a first portion located on the second portion;
ion doping the second portion of the channel pillar to form a second source doped layer, wherein second doped ions are arranged in the second source doped layer, the ion concentration of the second doped ions is smaller than that of the first doped ions, the ion type of the second doped ions is the same as that of the first doped ions, and the step of forming the opening comprises the following steps:
forming a plurality of discrete initial channel pillars on the first source doped layer;
forming an initial isolation layer on the substrate, wherein the initial isolation layer covers the first source doping layer and the initial channel column;
and removing the initial channel column of the first region and the first source doping layer at the bottom of the initial channel column until the surface of the substrate of the first region is exposed, and forming the opening in the first source doping layer.
2. The method of forming a semiconductor device according to claim 1, wherein an ion concentration of the second dopant ions is 1.0E20atom/cm 3 ～～8.0E21atom/cm 3 。
3. The method of forming a semiconductor device of claim 1, wherein the doping process of the second dopant ions comprises in-situ doping.
4. The method of forming a semiconductor device of claim 1, wherein the substrate further comprises a second region, the first region adjacent to the second region, the second region having a third source doped layer thereon, the third source doped layer having third dopant ions therein.
5. The method of forming a semiconductor device of claim 4, wherein forming the opening in the first source dopant layer further comprises:
forming a plurality of discrete initial channel pillars in the third source doped layer;
an initial isolation layer is formed on the substrate, and the initial isolation layer covers the third source doping layer.
6. The method of forming a semiconductor device of claim 5, wherein said initial channel pillar and said channel pillar are of non-identical materials.
7. The method of forming a semiconductor device of claim 4, wherein an ion type of the third dopant ion is opposite to an ion type of the first dopant ion.
8. The method of forming a semiconductor device according to claim 5, further comprising, after forming the second source doping layer: and removing part of the initial isolation layer to form an isolation layer covering the channel columns and part of the side walls of the initial channel columns, wherein the top surfaces of the isolation layer are lower than the top surfaces of the initial channel columns and the channel columns.
9. The method of forming a semiconductor device according to claim 8, further comprising, after forming the isolation layer: a first gate structure is formed on a sidewall of the first portion of the channel pillar, the first gate structure including a first portion surrounding the sidewall of the channel pillar and a second portion located at the substrate surface of the first region on a side of the channel pillar.
10. The method of forming a semiconductor device according to claim 9, further comprising, after forming the isolation layer: a second gate structure is formed on the sidewalls of the initial channel pillar, the second gate structure including a first portion surrounding the sidewalls of the initial channel pillar and a second portion on the substrate surface of the second region on one side of the initial channel pillar.
11. The method of forming a semiconductor device according to claim 10, further comprising: an interlayer dielectric layer is formed on the first region and the second region of the substrate, a first conductive structure, a second conductive structure and a third conductive structure are formed in the interlayer dielectric layer of the first region, the first conductive structure is electrically connected with the first source doping layer, the second conductive structure is electrically connected with the top of the channel column, and the third conductive structure is electrically connected with the second part of the first gate structure.
12. The method of forming a semiconductor device according to claim 11, further comprising: and forming a fourth conductive structure, a fifth conductive structure and a sixth conductive structure in the interlayer dielectric layer of the second region, wherein the fourth conductive structure is electrically connected with the third source doping layer, the fifth conductive structure is electrically connected with the top of the initial channel column, and the sixth conductive structure is electrically connected with the second part of the second gate structure.
13. The method of forming a semiconductor device of claim 5, further comprising, prior to forming the initial isolation layer: and forming a third drain doping layer, wherein the third drain doping layer is positioned on the top of the initial channel column.
14. The method of forming a semiconductor device according to claim 13, further comprising: and forming a protective layer, wherein the protective layer is positioned on the third leakage doping layer.
15. A semiconductor device formed by the method of forming a semiconductor device according to any one of claims 1 to 14, comprising:
a substrate comprising a first region;
a first source doped layer on the substrate of the first region, the first source doped layer having first dopant ions therein;
a channel pillar comprising a first portion and a second portion, the first portion being located on the first source doped layer, the second portion being located within the first source doped layer and sidewalls being covered by the first source doped layer;
the second source doping layer is formed by ion doping of a second part of the channel column and is provided with second doping ions; wherein: the ion concentration of the second doping ions is smaller than that of the first doping ions, and the ion type of the second doping ions is the same as that of the first doping ions.
16. The semiconductor device of claim 15, wherein the second dopant ions have an ion concentration of 1.0e20atom/cm 3 ～8.0E21atom/cm 3 。
17. The semiconductor device of claim 15, wherein the substrate further comprises a second region, the first region adjacent to the second region, the second region having a third source doped layer thereon, the third source doped layer having third dopant ions therein.
18. The semiconductor device according to claim 17, further comprising: and an initial channel pillar located on the third source doping layer.
19. The semiconductor device of claim 18, wherein the initial channel pillar and the channel pillar are of non-identical materials.
20. The semiconductor device of claim 17, wherein an ion type of the third dopant ion is opposite to an ion type of the first dopant ion.
21. The semiconductor device according to claim 18, further comprising: and the isolating layer is positioned on the substrate and covers the channel columns and part of the side walls of the initial channel columns, and the top surfaces of the isolating layer are lower than the top surfaces of the initial channel columns and the channel columns.
22. The semiconductor device according to claim 21, further comprising: a first gate structure on a sidewall of the channel pillar, the first gate structure including a first portion surrounding the sidewall of the channel pillar and a second portion on the substrate surface of the first region on a side of the channel pillar.
23. The semiconductor device according to claim 22, further comprising: a second gate structure on a sidewall of the initial channel pillar, the second gate structure including a first portion surrounding the sidewall of the initial channel pillar and a second portion on the substrate surface of the second region on a side of the initial channel pillar.
24. The semiconductor device according to claim 23, further comprising: and an interlayer dielectric layer which is positioned on the first region and the second region of the substrate and the top of which is higher than the top surfaces of the first gate structure and the second gate structure.
25. The semiconductor device according to claim 24, further comprising: the first conductive structure, the second conductive structure and the third conductive structure are located in the interlayer dielectric layer of the first region, the first conductive structure is electrically connected with the first source doping layer, the second conductive structure is electrically connected with the top of the channel pillar, and the third conductive structure is electrically connected with the second part of the first gate structure.
26. The semiconductor device according to claim 25, further comprising: the fourth conductive structure, the fifth conductive structure and the sixth conductive structure are located in the interlayer dielectric layer of the second region, the fourth conductive structure is electrically connected with the third source doping layer, the fifth conductive structure is electrically connected with the top of the initial channel column, and the sixth conductive structure is electrically connected with the second part of the second gate structure.
27. The semiconductor device according to claim 18, further comprising: and the third drain doping layer is positioned at the top of the initial channel column, and the third doping ions are arranged in the third drain doping layer.
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