CN109950152B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109950152B CN109950152B CN201711394366.1A CN201711394366A CN109950152B CN 109950152 B CN109950152 B CN 109950152B CN 201711394366 A CN201711394366 A CN 201711394366A CN 109950152 B CN109950152 B CN 109950152B
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate is provided with a sacrificial post; forming a support structure on the gate, the support structure exposing the top of the sacrificial post; after forming the support structure, removing the sacrificial post, forming a first opening in the first conductive structure, forming a second opening in the gate, and forming a third opening in the support structure; forming a first doping layer in the first opening, and doping first doping ions in the first doping layer through first in-situ doping; forming a channel layer in the second opening; and forming a second doping layer in the third opening, and doping second doping ions in the second doping layer through second in-situ doping. The forming method can improve the performance of the semiconductor structure.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
Metal-oxide-semiconductor field effect transistors (MOSFETs) are one of the most important components in modern integrated circuits. With the development of semiconductor technology, the conventional planar MOSFET has a weak ability to control channel current, resulting in a serious leakage current. A Fin field effect transistor (Fin FET) is an emerging multi-gate device that generally includes a Fin protruding from a surface of a semiconductor substrate, a gate covering a portion of a top surface and sidewalls of the Fin, and source-drain doped regions in the Fin on both sides of the gate. Compared with a planar MOSFET, the fin field effect transistor has stronger short channel inhibition capability and stronger working current.
However, the integration of either planar or finfet devices is still low. In order to further improve the integration of the semiconductor structure, a vertical Gate All Around (GAA) MOSFET is proposed.
However, the performance of the vertical all-around gate MOSFET of the prior art is to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a sacrificial post; forming a first conductive structure on the side wall surface of the sacrifice column part, wherein the top surface of the first conductive structure is lower than that of the sacrifice column; forming a gate on the top of the first conductive structure, wherein the gate is located on the side wall surface of the sacrifice column part, and the top surface of the gate is lower than that of the sacrifice column; forming a support structure on the top of the grid, wherein the support structure covers the side wall surface of the sacrificial column and exposes the top of the sacrificial column; after the support structure is formed, removing the sacrificial post, forming a first opening in the first conductive structure, forming a second opening in the gate, and forming a third opening in the support structure; forming a first doping layer in the first opening, and doping first doping ions in the first doping layer through first in-situ doping; forming a channel layer in the second opening; and forming a second doping layer in the third opening, and doping second doping ions in the second doping layer through second in-situ doping, wherein the second doping ions have the same or opposite conductivity type as the first doping ions.
Optionally, the sacrificial post includes: the mask layer is positioned on the fin part column; the step of forming the sacrificial post comprises: providing an initial substrate; forming a patterned mask layer on the initial substrate; and etching the initial substrate by taking the mask layer as a mask to form a substrate and a fin part column positioned on the substrate.
Optionally, the mask layer is made of silicon nitride or silicon oxynitride; the fin column is made of silicon, germanium, silicon carbide or monocrystal of III-V group element materials.
Optionally, the step of removing the sacrificial post includes: removing the mask layer; and removing the fin part column after removing the mask layer.
Optionally, the process for removing the mask layer includes: wet etching process; the process for removing the fin pillar comprises the following steps: one or a combination of the dry etching process and the wet etching process.
Optionally, the material of the first doping layer is silicon, germanium, silicon germanium or silicon carbide; the material of the second doping layer is silicon, germanium, silicon germanium or silicon carbide; the channel layer is made of silicon, germanium, silicon germanium or silicon carbide.
Optionally, the process for forming the first doping layer includes: chemical vapor deposition epitaxy process or solid phase epitaxy process; the process of forming the first doped layer includes: chemical vapor deposition epitaxy process or solid phase epitaxy process; the process of forming the first doped layer includes: a chemical vapor deposition epitaxy process or a solid phase epitaxy process.
Optionally, the concentration of the first doping ions in the first doping layer is greater than 1E21atoms/com3(ii) a The concentration of the second doping ions in the second doping layer is more than 1E21atoms/com3。
Optionally, the size of the first doping layer in the direction perpendicular to the surface of the substrate is 3nm to 7 nm; the size of the channel layer along the direction vertical to the surface of the substrate is 15 nm-25 nm; the size of the second doping layer along the direction vertical to the surface of the substrate is 3 nm-7 nm.
Optionally, before forming the gate, the method further includes: forming a first isolation layer on top of the first conductive structure, the first isolation layer having a top surface lower than the sacrificial post top surface; the gate is located on a top surface of the first isolation layer.
Optionally, after forming the second doping layer, the method further includes: removing part of the support structure to form a second isolation layer, wherein the top surface of the second isolation layer is lower than that of the second doping layer; and forming a second conductive structure on the top of the second isolation layer, wherein the second conductive structure is positioned on the surface of the side wall of the second doped layer.
Optionally, the support structure includes: a third isolation layer on the gate, a top surface of the third isolation layer being lower than a top surface of the sacrificial post; and the third conductive structure is positioned on the top of the third isolating layer and positioned on the side wall surface of the sacrificial column.
Optionally, before forming the gate, after forming the first conductive layer, the method further includes: forming a gate dielectric layer covering the surface of the side wall of the sacrificial column; the grid electrode covers the side wall of the grid medium layer.
Optionally, after removing the sacrificial post, the method further includes: and removing part of the gate dielectric layer to enable the top surface of the gate dielectric layer to be lower than the top surface of the support structure.
Optionally, before forming the second doping layer, removing a part of the gate dielectric layer; or after forming the second doping layer, the forming method further includes: removing part of the support structure to form a second isolation layer, wherein the second isolation layer exposes the side wall of the gate dielectric layer; and after the second isolation layer is formed, removing part of the gate dielectric layer to enable the top surface of the gate dielectric layer to be lower than the top surface of the second doping layer.
Optionally, the material of the gate dielectric layer includes one or a combination of silicon oxide and a high-k dielectric material; the thickness of the gate dielectric layer is 1 nm-2 nm.
Optionally, before removing the sacrificial post, after forming the gate, removing a part of the gate dielectric layer to make the top surface of the gate dielectric layer lower than the top surface of the sacrificial post; after removing part of the gate dielectric layer and before forming the support structure, the forming method further comprises the step of forming a first side wall on the surface of the side wall of the sacrificial column; after removing the sacrificial post, the method further comprises: and removing the first side wall.
Optionally, the first sidewall is made of silicon nitride or silicon oxynitride.
Optionally, the method further includes: doping a third dopant ion in the channel layer by a third in-situ doping; when the second doped ions are the same as the first doped ions in conductivity type, the third doped ions are opposite in conductivity type to the first doped ions; when the second doped ion and the first doped ion are opposite in conductivity type, the third doped ion and the first doped ion are the same in conductivity type, or the third doped ion and the second doped ion are the same in conductivity type.
The technical scheme of the invention also provides a semiconductor structure formed by the forming method.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming a semiconductor structure provided by the technical scheme of the invention, after the first opening, the second opening and the third opening are formed, first doping ions are doped into the first doping layer through first in-situ doping, and second doping ions are doped into the second doping layer through second in-situ doping. The first in-situ doping is beneficial to controlling the concentration of first doping ions in the first doping layer, and the concentration of the first doping ions in the first doping layer can be more uniform; the second in-situ doping is beneficial to controlling the concentration of the second doping ions in the second doping layer, and the concentration of the second doping ions in the second doping layer can be more uniform. Therefore, the forming method can improve the performance of the formed semiconductor structure. In addition, forming the first doping layer, the channel layer and the second doping layer after forming the first conductive structure and the gate electrode can prevent the second doping layer, the channel layer and the first doping layer from being lost during the process of forming the first conductive structure and the gate electrode, thereby improving the performance of the formed semiconductor structure.
Further, after the sacrificial column is removed, part of the gate dielectric layer is removed, and in the process of removing the sacrificial column, the gate dielectric layer can be used as a stop layer for removing the sacrificial column, so that the loss of the second isolation layer can be reduced.
Further, before the second doping layer is formed, after the third opening is formed, a part of the gate dielectric layer is removed, so that the dimension of the third opening in the direction parallel to the surface of the substrate can be increased, the dimension of the second doping layer in the direction parallel to the surface of the substrate can be increased, the area of the side wall surface of the second doping layer can be increased, the contact area between the second conductive structure and the second doping layer can be increased, and the contact resistance between the second conductive structure and the second doping layer can be reduced. Therefore, the forming method can improve the performance of the formed semiconductor structure.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 18 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The prior art semiconductor structures have a number of problems, such as: the performance of the resulting semiconductor structure is poor.
The reason for the poor performance of the conventional semiconductor structure is analyzed in combination with a semiconductor structure:
fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 having a fin pillar 101 thereon, the fin pillar 101 including a bottom region I; a channel region II located on the bottom region I; and a top region III located on the channel region II, wherein the fin pillar 201 has a mask layer 203 thereon.
Continuing to refer to fig. 1, forming a sidewall 111 covering the top region III and the channel region II of the fin pillar 101; and performing first ion implantation on the fin portion pillar 101 by using the sidewall 111 as a mask to form a first doped region 261 in the bottom region I of the fin portion pillar 101.
Referring to fig. 2, after the first ion implantation, a first conductive structure 131 is formed on the surface of the bottom region I of the fin pillar 101, and the first conductive structure 131 surrounds the bottom region I of the sacrificial pillar; after the first conductive structure 131 is formed, the sidewall 111 is removed (as shown in fig. 1); after removing the sidewall spacers 111, forming a first isolation layer 120 on the top of the first conductive structure 131; forming a gate structure 122 on top of the first isolation layer 120, wherein the gate structure 122 is located on the surface of the sidewall of the sacrificial post channel region II; a second isolation layer 143 is formed on top of the gate structure 122, and the second isolation layer 143 exposes sidewalls of the top region III of the fin pillar 101.
Referring to fig. 3, after forming the second isolation layer 143, a second ion implantation is performed on the fin pillar 101 to form a second doped region 162 in the top region III of the fin pillar 101.
And subsequently, forming a second conductive structure on the top of the second isolation layer 143, where the second conductive structure is located on the surface of the top region III of the fin pillar 101.
Forming a first doped region 161 in the bottom region I of the fin pillar 101 by first ion implantation; a second doped region 162 is formed in the top region III of the fin pillar 101 by a second ion implantation. The process of forming the first and second doping regions 161 and 162 by the ion implantation method is simple. However, since the first doped region 161 and the second doped region 262 are formed by performing an ion implantation process on the sidewall of the fin pillar 101, an implantation angle of the first ion implantation and the second ion implantation is greater than 0, and the implantation angle is an included angle between an ion implantation direction and a normal line of the surface of the substrate 100. Due to the projection effect of the adjacent fin pillars 101 on the first ion implantation and the second ion implantation, it is easy to cause that the doped ions hardly reach the bottoms of the fin pillars 101, so that the concentrations of the doped ions in the first doped region 161 and the second doped region 162 are not uniform, and the concentrations of the doped ions in the first doped region 161 and the second doped region 162 are difficult to control. Therefore, the performance of the semiconductor structure formed by the forming method is poor.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming a support structure on the gate, the support structure exposing the top of the sacrificial post; after forming the support structure, removing the sacrificial post, forming a first opening in the first conductive structure, and forming a third opening in the support structure; forming a first doping layer in the first opening, and doping first doping ions in the first doping layer through first in-situ doping; and forming a second doping layer in the third opening, and doping second doping ions in the second doping layer through second in-situ doping. The forming method can improve the performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 18 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
In this embodiment, the formed semiconductor structure is a MOS transistor. In other embodiments, the forming method of the invention can also be used for forming a tunneling field effect transistor.
Referring to fig. 4, a substrate 200 is provided, the substrate 200 having a sacrificial post thereon.
The sacrificial post includes: a bottom region C, a channel region B located on the bottom region C, and a top region A located on the channel region B.
The sacrificial column is in the shape of a cylinder. Specifically, the sacrificial column is in the shape of a cylinder or a square column.
In this embodiment, the sacrificial post includes: a fin pillar 201 and a mask layer 203 on the fin pillar 201. In other embodiments, the sacrificial post may comprise only the fin post.
In this embodiment, the step of forming the substrate 200 and the sacrificial post includes: providing an initial substrate; forming a patterned mask layer 203 on the initial substrate; and etching the initial substrate by taking the mask layer 203 as a mask to form a substrate 200 and a sacrificial column positioned on the substrate 200.
Before forming the mask layer 203, the step of forming the fin pillar further includes: an adhesion layer 202 is formed on the initial substrate.
The adhesion layer 202 serves to improve the adhesion of the interface between the mask layer 203 and the initial substrate.
In other embodiments, the sacrificial post comprises only the fin post. After etching the initial substrate, the step of forming the sacrificial post further comprises: and removing the mask layer and the adhesion layer.
In this embodiment, the starting substrate is a single crystal of silicon, germanium, silicon germanium or a group III-V material. The mask layer 203 is made of silicon nitride or silicon oxynitride. The material of the adhesion layer 202 is silicon oxide.
In this embodiment, the substrate 200 and the fin pillar 201 are made of silicon, germanium, silicon germanium, or silicon carbide. In other embodiments, the substrate and fin pillar material is a single crystal of a III-V material.
The process of etching the initial substrate comprises a dry etching process. The dry etching process has a good line width control effect, the size of the sacrificial post is easy to control, and the verticality between the formed sacrificial post and the surface of the substrate 200 is good. In other embodiments, the process of etching the initial substrate comprises wet etching.
In this embodiment, the bottom region C of the sacrificial post is used for forming a first opening in the subsequent step, so as to provide a space for forming a first doping layer in the subsequent step; the channel region C of the sacrificial column is used for forming a second opening subsequently, so that a space is provided for forming a channel layer subsequently; the top region A of the sacrificial post is used for forming a third opening subsequently, so that a space is provided for forming a second doping layer subsequently.
In this embodiment, the number of the sacrificial columns is two. In other embodiments, the number of the fin pillars may be one or more than two.
If the height of the sacrificial column is too small, the dimension of a first doping layer, a second doping layer or a channel layer formed subsequently along the direction vertical to the surface of the substrate 200 is easily too small, so that the performance of the formed semiconductor structure is affected; if the height of the sacrificial post is too large, the process difficulty is easily increased. Specifically, in this embodiment, the height of the sacrificial post is 6nm to 65 nm.
A first conductive structure is subsequently formed on the substrate 200, the first conductive structure covering the sidewall surface of the sacrificial post portion, and the surface of the first conductive structure being lower than the top surface of the sacrificial post.
In this embodiment, the top surface of the first conductive structure is flush with the top surface of the bottom region C.
Specifically, in this embodiment, the steps of forming the first conductive structure are as shown in fig. 5 to 9.
And subsequently forming a second side wall covering the side walls of the channel region B and the top region A of the sacrificial post.
In this embodiment, the step of forming the second sidewall is as shown in fig. 5 to 7.
Referring to fig. 5, a sacrificial layer 250 is formed on the substrate 200, wherein the surface of the sacrificial layer 250 is flush with the top surface of the bottom region C.
The sacrificial layer 250 is used to prevent a sidewall layer from being formed on the surface of the bottom region C, so that after the sacrificial layer 250 is removed, the surface of the sacrificial layer 250 has no sidewall layer.
In this embodiment, the material of the sacrificial layer 250 is silicon oxide. In other embodiments, the material of the sacrificial layer is silicon nitride or silicon oxynitride.
In this embodiment, the step of forming the sacrificial layer 250 includes: forming an initial sacrificial layer on the substrate 200, the initial sacrificial layer surface being higher than the sacrificial post bottom region C top surface; and etching the initial sacrificial layer to form a sacrificial layer 250, wherein the surface of the sacrificial layer 250 is flush with the top surface of the bottom area C.
In this embodiment, the initial sacrificial layer is made of silicon oxide, and the process of forming the initial sacrificial layer includes a fluid chemical vapor deposition process. The initial sacrificial layer formed by the fluid chemical vapor deposition process has good gap filling capacity and can fully fill gaps between adjacent sacrificial columns.
In other embodiments, the material of the initial sacrificial layer is an organic dielectric material, and the process of forming the initial sacrificial layer includes a spin coating process.
Referring to fig. 6, a sidewall layer 210 is formed to cover the surface of the sacrificial layer 250 and sidewalls of the channel region B and the top region a of the sacrificial post, and the sidewall layer 210 and the sacrificial layer 250 are made of different materials.
In this embodiment, the sidewall layer 210 is used for forming a second sidewall subsequently.
The material of the sidewall layer 210 is different from that of the sacrificial layer 250, so that the second sidewall is prevented from being removed in the subsequent process of removing the sacrificial layer 250.
In this embodiment, the sacrificial layer 250 is made of silicon oxide, and the sidewall layer 210 is made of silicon nitride. In other embodiments, the material of the sacrificial layer is silicon nitride, and the material of the sidewall layer is silicon oxide or silicon oxynitride.
The process of forming the sidewall layer 210 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The sidewall layer 210 is also located on the mask layer 203.
Referring to fig. 7, the sacrificial layer 250 and the sidewall layer 210 on the sacrificial layer 250 are removed to form a second sidewall 211.
The second side wall 211 is used for isolating the first metal layer from the channel region B of the sacrificial post in the process of subsequently forming the first metallization, so as to prevent the first metal layer from reacting with the channel region B, and further improve the performance of the formed semiconductor structure.
In this embodiment, the step of removing the sacrificial layer 250 and the sidewall layer 210 on the sacrificial layer 250 includes: and stripping the sacrificial layer 250 by wet etching, and removing the sacrificial layer 250 and the sidewall layer 210 on the sacrificial layer 250.
Specifically, in this embodiment, the process of stripping the sacrificial layer 250 includes a wet etching process. The wet etching has a good selectivity so that the sacrificial post channel region B and the sidewall layer 210 of the top region a are not easily lost.
The technological parameters of the wet etching comprise: the etching liquid is a mixed solution of hydrofluoric acid and ammonium fluoride, wherein the volume ratio of the ammonium fluoride to the hydrofluoric acid is 5-7.
After the sacrificial layer 250 is stripped, the sidewall layer 210 on the sacrificial layer 250 is also removed.
The stripping of the sacrificial layer 250 can remove the sidewall layer 210 on the sacrificial layer 250 during the process of removing the sacrificial layer 250, thereby simplifying the process flow.
In other embodiments, the step of removing the sacrificial layer and the sidewall layer on the sacrificial layer includes: performing anisotropic etching on the side wall layer, and removing the side wall layer on the sacrificial layer to form a second side wall; and removing the sacrificial layer after the anisotropic etching. The anisotropic etching process comprises an anisotropic dry etching process. The process for removing the sacrificial layer comprises one or two of a wet etching process and a dry etching process.
If the dimension of the second sidewall 211 in the direction perpendicular to the surface of the substrate 200 is too large, it is easy to cause the dimension of the subsequently formed first metallization in the direction perpendicular to the surface of the substrate 200 to be too small, so that the contact resistance between the first metallization and the first doped layer is easily increased; if the dimension of the second sidewall 211 in the direction perpendicular to the surface of the substrate 200 is too small, the dimension of the subsequently formed gate or the second metallization in the direction perpendicular to the surface of the substrate 200 is easily too small, thereby easily affecting the performance of the formed semiconductor structure. Specifically, in this embodiment, the dimension of the second sidewall 211 along the direction perpendicular to the surface of the substrate 200 is 6nm to 70 nm.
If the thickness of the second sidewall 211 is too small, it is not favorable for the subsequent isolation of the first metal layer 220 from the sacrificial post channel region B, which easily causes the atoms of the subsequent first metal layer material to penetrate through the second sidewall 211 to react with the sacrificial post 201, so as to form a first metallization between the gate and the sacrificial post, and is not favorable for improving the performance of the formed semiconductor structure; if the thickness of the second sidewall 211 is too large, the difficulty of the subsequent process of removing the second sidewall 211 is easily increased. Specifically, in this embodiment, the thickness of the second sidewall 211 is 2nm to 20 nm.
Forming a first conductive layer on the subsequent substrate 200, wherein the first conductive layer is located at the bottom region C of the sacrificial post and the sidewall surface of the second sidewall 211.
Referring to fig. 8, a first metallization 221 is formed on the surface of the bottom region C of the sacrificial post.
Specifically, in this embodiment, the first metallization 221 is located on the surface of the first doping layer 261. The first metallization 221 surrounds the sacrificial post bottom region C.
In this embodiment, the step of forming the first metallization 221 includes: forming a first metal layer 220 on the bottom region C of the sacrificial post and the sidewall surface of the second sidewall 211; the first metal layer 220 is subjected to a first annealing treatment, so that the first metal layer 220 reacts with the first doping layer 261 to form a first metallization 221.
The first metal layer 220 is used to react with the first doping layer 261 to form a first metallization 221.
The material of the first metal layer 220 is nickel, cobalt or titanium.
The process of forming the first metal layer 220 includes an electroplating process or a physical vapor deposition process.
In this embodiment, before the first annealing process, the first metal layer 220 is also located on the surface of the substrate 200 and the mask layer 203.
Since the sacrificial post bottom region C and the substrate 200 can react with the first metal layer 220 in the first annealing process, the first metallization 221 is located on the surface of the substrate 200 and the sacrificial post bottom region C. The second sidewalls 211 and the mask layer 203 do not react with the first metal layer 220, so that the first metal layer 220 remains on the second sidewalls 211 and the mask layer 203 after the first annealing process.
In other embodiments, after the first annealing process and before the subsequent formation of the initial plug, the step of forming the first conductive layer further comprises: and removing the residual metal layer.
With continued reference to fig. 8, an initial plug 230 is formed covering the first metallization 221 and the sidewalls of the second sidewall 211.
The initial plug 230 is used to electrically connect the first metallization 221 to an external circuit.
Specifically, in this embodiment, the initial plug 230 is located on the surface of the first metallization 221 and the surface of the first metal layer 220. In other embodiments, before forming the initial plug, the step of forming the first conductive layer further comprises: and removing the first metal layer, wherein the initial plug is positioned on the surfaces of the first metallization and the first side wall.
In this embodiment, the material of the initial plug 230 is tungsten.
The process of forming the initial plug 230 includes an organic metal chemical vapor deposition process or an electroplating process.
Referring to fig. 9, the initial plug 230 is etched to form a first plug 231, and a top surface of the first plug 231 is lower than or flush with a top surface of the channel region B.
The first plug 231 is used for electrically connecting the first doping layer formed later with an external circuit.
In this embodiment, after etching the first initial plug 230, the method further includes: the remaining first metal layer 220 is removed (as shown in fig. 8).
In this embodiment, after the etching of the initial plug 230, the remaining first metal layer 220 is removed. In other embodiments, the remaining first metal layer is removed after the first annealing process and before the initial plug is formed.
In this embodiment, the process of removing the first metal layer 220 includes a wet etching process. The process of etching the initial plug 230 includes a dry etching process or a wet etching process.
In this embodiment, the first conductive structure surrounds the sacrificial post bottom region C.
With continued reference to fig. 9, after forming the first conductive structure, the second sidewalls 211 are removed.
The second sidewalls 211 are removed to expose the sacrificial post channel region B, so that the subsequently formed gate contacts the surface of the sacrificial post channel region B.
In this embodiment, the process of removing the second sidewall 211 includes a wet etching process. In other embodiments, the process of removing the second sidewall spacers includes an isotropic dry etching process.
The process parameters for removing the second sidewall 211 include: the etching liquid comprises phosphoric acid; the etching temperature is 720-880 ℃.
Referring to fig. 10, a first isolation layer 222 is formed on the first conductive structure.
The first isolation layer 222 is used to electrically isolate the first conductive structure from a subsequently formed gate.
In this embodiment, the first isolation layer 222 is made of silicon oxide. Silicon oxide has good insulating properties. In other embodiments, the material of the first isolation layer may also be silicon nitride, silicon oxynitride, or a low-k (k less than 3.9) dielectric material, and the low-k dielectric material is a porous material.
The step of forming the first isolation layer 222 includes: forming a first initial isolation layer on the first conductive structure, the first initial isolation layer having a surface higher than the sacrificial post top surface; and etching the first initial isolation layer to form a first isolation layer 222, wherein the surface of the first isolation layer 222 is lower than the top surface of the channel region B.
The process of forming the first initial isolation layer comprises a fluid chemical vapor deposition process. The gap filling capability of the first initial isolation layer formed by the fluid chemical vapor deposition process is good.
The thickness of the first isolation layer 222 is a dimension of the first isolation layer 222 in a direction perpendicular to the surface of the substrate 200.
If the thickness of the first isolation layer 222 is too small, it is not favorable to achieve electrical isolation between the first conductive structure and the subsequently formed gate; if the thickness of the first isolation layer 222 is too large, the size of the gate or the second doped layer to be formed later is too small, which may affect the performance of the semiconductor structure to be formed. Specifically, in this embodiment, the thickness of the first isolation layer 222 is 2nm to 5 nm.
Referring to fig. 11, after the first conductive structure is formed, a gate dielectric layer covering the sidewalls and the top surface of the sacrificial post is formed.
In this embodiment, the gate dielectric layer is located on the first isolation layer 222.
The gate dielectric layer is made of one or two of silicon oxide and a high-k dielectric layer.
Specifically, in this embodiment, the gate dielectric layer includes: an oxide layer 240 covering the sidewalls of the sacrificial post; and a high-k dielectric layer 241 covering the surface of the sidewall of the oxide layer 240. In other embodiments, the gate dielectric layer may comprise only a high-k dielectric layer.
The oxide layer 240 is used to improve the interface state between the high-k dielectric layer 241 and the subsequently formed channel layer 262.
The material of the oxide layer 240 is silicon oxide.
The process of forming the oxide layer 240 includes: a thermal oxidation process or an in-situ steam generation process.
The material of the high-k dielectric layer 241 is a high-k (k is greater than 3.9) dielectric material, for example: HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3Or HfSiO4。
The process for forming the high-k dielectric layer 241 includes: an atomic layer deposition process or a chemical vapor deposition process.
If the thickness of the gate dielectric layer is too small, the electric isolation between the subsequently formed gate and the channel layer is not favorably realized, and the second initial isolation layer is not favorably protected in the subsequent sacrificial post removing process; if the thickness of the gate dielectric layer is too large, the difficulty of the subsequent process for removing the gate dielectric layer exposed by the gate is easily increased. Specifically, in this embodiment, the thickness of the gate dielectric layer is 1nm to 2 nm.
And forming a grid electrode on the first conductive structure, wherein the grid electrode covers the side wall surface of the part of the sacrificial post, the surface of the grid electrode is lower than the top surface of the sacrificial post, and the grid electrode covers the side wall of the grid medium layer.
In this embodiment, the step of forming the gate is as shown in fig. 12 and 13.
Referring to fig. 12, an initial gate 242 is formed on the first conductive structure, the initial gate 242 surface being higher than or flush with the sacrificial post top surface.
The material of the initial gate 242 is metal, such as: al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
The process of forming the initial gate 242 includes: an organic chemical vapor deposition process or an electroplating process.
Referring to fig. 13, a portion of the initial gate 242 (shown in fig. 12) is removed to form a gate 243, and a top surface of the gate 243 is lower than a top surface of the sacrificial post.
The gate 243 is used to control the electric field in the sacrificial column, thereby controlling the probability of electrons in the subsequent channel layer crossing the potential barrier between the first doped layer and the channel layer, or the potential barrier between the subsequently formed second doped layer and the channel layer, and thus controlling the on and off of the formed transistor.
In this embodiment, the surface of the gate 243 is flush with the top surface of the sacrificial post channel region B.
The process of removing a portion of the preliminary gate 242 includes: and (5) dry etching process. In other embodiments, the process of removing a portion of the initial gate includes a wet etch process.
The thickness of the gate 243 is the dimension of the gate 243 in the direction perpendicular to the surface of the substrate 200.
If the thickness of the gate 243 is too large, it is easy to cause the dimension of the second doping layer formed subsequently to be too small in the direction perpendicular to the surface of the substrate 200, thereby affecting the performance of the formed semiconductor structure; if the thickness of the gate 243 is too small, it is not favorable to increase the contact area between the gate 243 and the subsequently formed channel layer, and it is not favorable to increase the control effect of the gate 243 on the electric field in the channel layer. Specifically, in this embodiment, the thickness of the gate electrode 243 is 15nm to 25 nm.
Note that the gate 243 surrounds the sacrificial post channel region B. The gate 243 surrounds the channel region B of the sacrificial post, so that the gate 243 is in contact with each side surface of the channel region B of the sacrificial post, and the gate 243 can control the electric field in the sacrificial post from each side surface of the channel region B of the sacrificial post, thereby increasing the control effect of the gate 243 on electrons in the sacrificial post and improving the performance of the formed semiconductor structure.
Referring to fig. 14, a support structure 250 is formed on top of the gate 243, the support structure 250 covers the sidewall surface of the sacrificial post, and the support structure 250 exposes the top of the sacrificial post.
The support structure is used to subsequently enclose the sidewalls of the third opening 283.
In this embodiment, the top surface of the support structure 250 is flush with the top surface of the sacrificial post. In other embodiments, the support structure surface may be lower than the sacrificial post top surface.
In this embodiment, the material of the supporting structure 250 is silicon oxide. Silicon oxide has good insulating properties. In other embodiments, the material of the support structure may also be silicon nitride, silicon oxynitride, or a low-k (k less than 3.9) dielectric material, which is a porous material.
The process of forming the support structure 250 includes: a fluid chemical vapor deposition process. The gap filling capability of the support structure 250 formed by the fluid chemical vapor deposition process is good. In other embodiments, the material of the support structure is a low-k dielectric material, and the process of forming the support structure includes a spin-on process.
Referring to fig. 15, after the support structure 250 is formed, the sacrificial post is removed, a first opening 281 is formed in the first conductive structure, a second opening 282 is formed in the gate 243, and a third opening 283 is formed in the support structure 250.
The first opening 281 is used for receiving a first doping layer, the second opening 282 is used for receiving a channel layer, and the third opening 283 is used for receiving a second doping layer.
In this embodiment, the step of removing the sacrificial post includes: removing the mask layer 203; after removing the mask layer 203, the fin pillars 201 are removed.
After removing the mask layer 203, removing the adhesion layer 202 before removing the fin pillar 201.
In this embodiment, the process of removing the mask layer 203 includes: wet etching process; the process parameters for removing the mask layer 203 include that the etching solution comprises phosphoric acid.
The process of removing the fin pillar 201 includes: and (5) dry etching process.
Specifically, the process parameters for removing the fin portion pillar 201 include: the etching gas includes: CF (compact flash)4、CH3F、HBr、Cl2、Ar、N2Or O2One or more combinations of (a); the flow rate of the etching gas is 50sccm to 1000 sccm.
Referring to fig. 16, a first doping layer 261 is formed in the first opening 281 (as shown in fig. 15), and first doping ions are doped in the first doping layer 261 by first in-situ doping; forming a channel layer 262 in the second opening 282 (shown in fig. 15); a second doping layer 263 is formed in the third opening 283 (as shown in fig. 15), and second doping ions, which have the same or opposite conductivity type as the first doping ions, are doped in the second doping layer 263 by second in-situ doping.
In this embodiment, the first doping layer 261 serves as a source region of a transistor to be formed, and the second doping layer 263 serves as a drain region of the transistor to be formed; alternatively, the first doped layer 261 serves as a drain region of the formed transistor, and the second doped layer 263 serves as a source region of the formed transistor.
After the first, second, and third openings 281, 282, and 283 are formed, first dopant ions are doped in the first doping layer 261 by first in-situ doping, and second dopant ions are doped in the second doping layer 263 by second in-situ doping. The first in-situ doping is beneficial to controlling the concentration of the first doping ions in the first doping layer 261, and can make the concentration of the first doping ions in the first doping layer 261 more uniform; the second in-situ doping is beneficial to controlling the concentration of the second doping ions in the second doping layer 263 and can make the concentration of the second doping ions in the second doping layer 263 more uniform. Therefore, the forming method can improve the performance of the formed semiconductor structure.
In addition, after the first conductive structure and the gate 243 are formed, the first doping layer 261, the channel layer 262 and the second doping layer 263 are formed, so that the second doping layer 263, the channel layer 262 and the first doping layer 261 can be prevented from being damaged during the process of forming the first conductive structure and the gate 243, thereby improving the performance of the formed semiconductor structure.
When the semiconductor structure is a PMOS transistor, the material of the first doping layer 261 and the second doping layer 263 is silicon germanium or silicon. The material of the first doping layer 261 and the second doping layer 263 is silicon germanium, so that the first doping layer 261 and the second doping layer 263 can provide compressive stress for a channel of the PMOS transistor, and thus the migration rate of carriers in the channel of the formed PMOS transistor can be increased. The channel layer 262 is made of silicon or silicon germanium, which has high electron mobility and can improve the performance of the formed PMOS transistor.
When the formed semiconductor structure is an NMOS transistor, the material of the first doping layer 261 and the second doping layer 263 is silicon carbide or silicon. The material of the first doping layer 261 and the second doping layer 263 is silicon carbide, so that the first doping layer 261 and the second doping layer 263 can provide tensile stress for the channel of the NMOS transistor, and thus the migration rate of carriers in the channel of the formed NMOS transistor can be increased. The material of the channel layer 262 is silicon or silicon germanium.
When the formed semiconductor structure is a PMOS transistor, the first dopant ions are P-type ions, such as boron ions. When the formed semiconductor structure is an NMOS transistor, the first doping ions are N-type ions, such as phosphorous ions or arsenic ions.
In this embodiment, the first doping layer 261 is formed by first epitaxial growth; forming a channel layer 262 by second epitaxial growth; the second doping layer 263 is formed by third epitaxial growth.
The dimension of the first doping layer 261 in the direction perpendicular to the surface of the substrate 200 is the thickness of the first doping layer 261.
If the thickness of the first doping layer 261 is too large, the thickness of the second doping layer 263 or the channel layer 262 is easily made too small, thereby affecting the performance of the formed semiconductor structure; if the thickness of the first doping layer 261 is too small, the contact area between the first doping layer 261 and the first conductive structure is easily made small, resulting in too large contact resistance between the first doping layer 261 and the first conductive structure. Specifically, the thickness of the first doping layer 261 is 3nm to 7 nm.
If the concentration of the first doping ions in the first doping layer 261 is too small, the contact resistance between the first conductive structure and the first doping layer 261 is easily increased. Specifically, in this embodiment, the concentration of the first doping ions in the first doping layer 261 is greater than 1E21atoms/cm3。
In this embodiment, in the second epitaxial growth process, the channel layer 262 is subjected to third in-situ doping, and third dopant ions are doped into the channel layer 262; when the second doped ions are the same as the first doped ions in conductivity type, the third doped ions are opposite in conductivity type to the first doped ions; when the second doped ion and the first doped ion are opposite in conductivity type, the third doped ion and the first doped ion are the same in conductivity type, or the third doped ion and the second doped ion are the same in conductivity type.
In this embodiment, the formed semiconductor structure is an MOS transistor, the conductivity types of the first doped ions and the second doped ions are the same, the conductivity type of the third doped ions is opposite to that of the first doped ions, and the conductivity type of the third doped ions is opposite to that of the second doped ions. The third dopant ions can reduce the resistance of the channel layer 262.
In other embodiments, the formed semiconductor structure is a tunneling field effect transistor, the first dopant ion and the second dopant ion have opposite conductivity types, and the channel layer may not have the third dopant ion therein, or the third dopant ion and the first dopant ion have the same conductivity type, or the third dopant ion and the second dopant ion have the same conductivity type.
Specifically, when the formed semiconductor structure is an NMOS transistor, the third doping ions are P-type ions, such as boron ions. When the formed semiconductor structure is a PMOS transistor, the third dopant ions are N-type ions, such as phosphorous ions or arsenic ions.
If the thickness of the channel layer 262 is too large, the thickness of the second doping layer 263 or the first doping layer 261 is easily too small, thereby affecting the performance of the formed semiconductor structure; if the thickness of the channel layer 262 is too small, the contact area between the channel layer 262 and the gate 243 is easily made small, thereby causing the gate 243 to have a small control effect on carriers in the channel layer 262. Specifically, the thickness of the channel layer 261 is 15nm to 25 nm.
If the concentration of the third dopant ions in the channel layer 262 is too low, it is not favorable for reducing the resistance of the channel layer 262; if the concentration of the third dopant ions in the channel layer 262 is too high, the scattering effect of the third dopant ions on carriers is easily increased, and thus the migration rate of the carriers in the channel layer 262 is easily decreased. Therefore, in this embodiment, the concentration of the third dopant ions in the channel layer 262 is 1E16atoms/cm3～1E18atoms/cm3。
When the formed semiconductor structure is a PMOS transistor, the second dopant ions are P-type ions, such as boron ions. When the formed semiconductor structure is an NMOS transistor, the second doping ions are N-type ions, such as phosphorous ions or arsenic ions.
If the thickness of the second doping layer 263 is too large, the thickness of the first doping layer 261 or the channel layer 262 is easily made too small, thereby affecting the performance of the formed semiconductor structure; if the thickness of the second doped layer 263 is too small, the contact area between the second doped layer 263 and a subsequently formed second conductive structure is easily made small, so that the contact resistance between the second doped layer 263 and the second conductive structure is too large. Specifically, the thickness of the second doped layer 263 is 15nm to 25 nm.
If the concentration of the second doping ions in the second doping layer 263 is too low, the contact resistance between the subsequently formed second conductive structure and the second doping layer 263 is easily increased. Specifically, in this embodiment, the concentration of the second doping ions in the second doping layer 263 is greater than 1E21atoms/cm3。
It should be noted that, in the present embodiment, the formed semiconductor structure is a MOS transistor, and the conductivity types of the first doping ions and the second doping ions are the same. In other embodiments, the semiconductor structure is a tunneling field effect transistor, and the first doped ions and the second doped ions have opposite conductivity types.
In this embodiment, the materials of the first doping layer 261, the second doping layer 263 and the channel layer 262 are the same. The materials of the first doping layer 261, the second doping layer 263 and the channel layer 262 are the same, so that the process flow for forming the first doping layer 261, the channel layer 262 and the second doping layer 263 can be simplified. In other embodiments, the materials of the first doped layer, the second doped layer, and the channel layer may not be the same.
Specifically, in this embodiment, the formed semiconductor structure is a PMOS transistor, and the material of the first doped layer 261, the second doped layer 263 and the channel layer 262 is silicon germanium. In other embodiments, the semiconductor structure formed is an NMOS transistor, and the material of the first doped layer, the second doped layer, and the channel layer is silicon or silicon carbide.
In this embodiment, the first epitaxial growth, the second epitaxial growth, and the third epitaxial growth processes include a chemical vapor deposition epitaxial process. In a gas embodiment, the processes of the first epitaxial growth, the second epitaxial growth and the third epitaxial growth comprise a solid phase epitaxy process.
In this embodiment, the process parameters for forming the first doping layer 261 include: the reaction gases include a first silicon source gas, a first germanium source gas, and a first ion source gas, the first silicon source gas including SiH4Dichlorosilane and Si2H6One or more combinations thereof.
In this embodiment, the semiconductor structure is a PMOS transistor, and the first ion source gas comprises B2H6Or BCl3。
In other embodiments, when the semiconductor structure is an NMOS transistor, the first ion source gas comprises AsH3Or pH3。
In other embodiments, when the material of the first doped layer is silicon, the process parameters for forming the first doped layer include: the reactant gases include the first silicon source gas and the first ion source gas.
In this embodiment, the process parameters for forming the channel layer 262 include: the reaction gas comprises a second silicon source gas, a second germanium source gas and a second ion source gas, wherein the second silicon source gas comprises SiH4Dichlorosilane and Si2H6One or more combinations thereof. The second germanium source gas comprises GeH4。
In this embodiment, the semiconductor structure is a PMOS transistor, and the second ion source gas forming the channel layer 262 includes AsH3Or pH3. In other embodiments, when the semiconductor structure is an NMOS transistor, the second ion source gas comprises B2H6Or BCl3。
In other embodiments, when the material of the channel layer is silicon, the process parameters for forming the channel layer include: the reactant gases include the second ion source gas and the second silicon source gas.
In this embodiment, the process parameters for forming the second doped layer 263 include: the reactant gas comprises a third silicon source gas, a third germanium source gas and a third ion source gas, wherein the third silicon source gas comprises SiH4Dichlorosilane and Si2H6The third germanium source gas comprises GeH4。
In this embodiment, the third ion source gas comprises B for a PMOS transistor of the semiconductor structure being formed2H6Or BCl3. In other embodiments, the third ion source gas comprises AsH when forming an NMOS transistor of the semiconductor structure3Or pH3。
In other embodiments, when the material of the second doped layer is silicon, the process parameters for forming the second doped layer include: the reactant gases include the third silicon source gas and a third ion source gas.
In this embodiment, the materials of the first silicon source gas, the second silicon source gas and the third silicon source gas are the same, and the flow rates of the first silicon source gas, the second silicon source gas and the third silicon source gas are the same. The first germanium source gas, the second germanium source gas and the third germanium source gas are made of the same material, and the first germanium source gas, the second germanium source gas and the third germanium source gas are made of the same flow rate. Specifically, the step of forming the first doping layer 261, the channel layer 262 and the third doping layer 263 includes: introducing a first silicon source gas and a first germanium source gas into the first opening 281, the second opening 282 and the third opening 283, and introducing a first ion source gas into the first opening 281; after the first doping layer 261 is formed, the introduction of the first ion source gas is stopped, and a second ion source gas is introduced into the second opening 282; after the channel layer 262 is formed, the introduction of the second ion source gas is stopped, and a third ion source gas is introduced into the third opening 283.
In this embodiment, the flow rate of the first silicon source gas introduced into the first opening 281, the second opening 282, and the third opening 283 is 1sccm to 2000sccm, and the flow rate of the first germanium source gas is 1sccm to 2000 sccm; the flow rate of the first ion source gas is 1 sccm-2000 sccm; the flow rate of the second ion source gas is 0.5 sccm-1000 sccm; the flow rate of the third ion source gas is 1 sccm-2000 sccm.
Referring to fig. 17, after the second doped layer 263 is formed, a portion of the support structure 250 is removed (as shown in fig. 16), and a second isolation layer 251 is formed, wherein a top surface of the second isolation layer 251 is lower than a top surface of the second doped layer 263.
Removing a portion of the support structure 250 serves to expose sidewalls of the gate dielectric layer, thereby facilitating subsequent removal of a portion of the gate dielectric layer.
The process of removing a portion of the support structure 250 includes a dry etching process or a wet etching process.
The thickness of the second isolation layer 251 is a dimension of the second isolation layer 251 in a direction perpendicular to the surface of the substrate 200.
If the thickness of the second isolation layer 251 is too small, it is not favorable to achieve electrical isolation between the subsequently formed second conductive structure and the gate 243; if the thickness of the second isolation layer 251 is too large, the size of the second conductive structure to be formed later is too small, which may affect the performance of the semiconductor structure to be formed. Specifically, in this embodiment, the thickness of the second isolation layer 251 is 2nm to 5 nm.
In this embodiment, after the sacrificial post is removed, part of the gate dielectric layer is removed, and in the process of removing the sacrificial post, the gate dielectric layer can serve as a stop layer for removing the sacrificial post, so that the loss of the second isolation layer 251 can be reduced.
With reference to fig. 17, after the second isolation layer 251 is formed, a portion of the gate dielectric layer is removed, so that the top surface of the gate dielectric layer is lower than the top surface of the second doped layer 263.
Removing part of the gate dielectric layer is used to expose the sidewalls of the second doped layer, so that the subsequently formed second conductive layer can be electrically connected to the second doped layer 263.
In this embodiment, the step of removing a portion of the gate dielectric layer includes: and etching the gate dielectric layer by using the second isolation layer 251 as a mask, and removing the gate dielectric layer exposed by the second isolation layer 251.
The process for etching the gate dielectric layer comprises an isotropic dry etching process or a wet etching process.
In this embodiment, after the second isolation layer is formed, a portion of the gate dielectric layer is removed. In other embodiments, after removing the sacrificial post and before forming the second doped layer, a portion of the gate dielectric layer may be removed to reduce the height of the top surface of the gate dielectric layer. Before the second doping layer is formed, after the third opening is formed, part of the gate dielectric layer is removed, the size of the third opening in the direction parallel to the surface of the substrate can be increased, the size of the second doping layer in the direction parallel to the surface of the substrate can be increased, the area of the side wall of the second doping layer can be increased, the contact area between the second conductive structure and the second doping layer is increased, the contact resistance between the second conductive structure and the second doping layer is reduced, and the performance of the formed semiconductor structure is improved.
In another embodiment, before removing the sacrificial post, removing a part of the gate dielectric layer to make the top surface of the gate dielectric layer lower than the top surface of the sacrificial post; after the gate dielectric layer and the grid electrode are formed, forming a first side wall on the surface of the side wall of the sacrificial column; after removing the sacrificial post, the method further comprises: and removing the first side wall. The first side wall is made of silicon nitride or silicon oxynitride. And removing the first side wall before forming the second doped layer, or removing the first side wall after forming the second isolation layer and before subsequently forming the second conductive structure.
Referring to fig. 18, a second conductive structure is formed on the second isolation layer 251, and the second conductive structure covers the sidewall surface of the second doped layer 263.
The second conductive structure surrounds the second doped layer 263.
The second conductive structure includes: a second metallization 270 at the surface of the sacrificial post top region a; a second plug 271 covering the second metallization 270. Specifically, the second metallization 270 is located on the sidewall and the top surface of the second doped layer 263.
In this embodiment, the step of forming the second conductive structure includes: forming a second metallization 270 on the sidewalls and top surface of the second doped layer 263; a second plug 271 is formed on the second isolation layer 251, and the second plug 271 covers the second metallization 270.
The step of forming the second metallization 270 comprises: forming a second metal layer on the top and sidewall surfaces of the second doped layer 263 and the second isolation layer 251; and performing second annealing treatment on the second metal layer to enable the second metal layer 270 to react with the second doping layer 263 to form a second metallization 271.
In this embodiment, before forming the second plug 271 and after the second annealing, the step of forming the second conductive structure further includes: the second metal layer on the second isolation layer 251 is removed. Removing the second metal layer can reduce the influence of the second metal layer on the isolation performance of the second isolation layer 251. In other embodiments, the remaining second metal layer may not be removed.
The second metal layer is made of nickel or cobalt.
The process for forming the second metal layer includes an electroplating process or a physical vapor deposition process.
The material of the second plug 271 is tungsten.
The process of forming the second plug 271 includes: an electroplating process or an organometallic vapor chemical deposition process.
It should be noted that, in this embodiment, the supporting structure 250 is formed before the second conductive structure is formed; before forming the second conductive structure, a portion of the support structure is removed to form the second isolation layer 251. Since the material of the support structure 250 is a non-metallic material. During the process of forming the first doping layer 261, the channel layer 262 and the second doping layer 263, the material atoms of the support structure 250 are not easily diffused, so that the conductive properties of the first doping layer 261, the channel layer 262 and the second doping layer 263 are not easily affected.
In other embodiments, the support structure comprises: a third isolation layer on the gate, a top surface of the third isolation layer being lower than a top surface of the sacrificial post; and the third conductive structure is positioned on the top of the third isolating layer and positioned on the side wall surface of the sacrificial column.
It should be further noted that, in this embodiment, after the second doping layer is formed, a second conductive structure is formed. Because the sacrificial post comprises the mask layer, and the top surface of the supporting structure is flush with the top surface of the sacrificial post, the supporting structure covers the side wall of the mask layer. And after removing the sacrificial post, forming a third opening, wherein part of the third opening is overlapped with the space occupied by the mask layer. And part of the second doping layer occupies the space of the mask layer, and after the second metallization is formed, the second metallization is positioned on the surface of the second doping layer, so that after the second doping layer is formed, the contact area between the second conductive structure and the second doping layer can be increased by forming the second conductive structure, and the contact resistance between the second conductive structure and the second doping layer is further reduced.
With continued reference to fig. 18, an embodiment of the invention further provides a semiconductor structure formed by the forming method of the previous embodiment.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a sacrificial post;
forming a first conductive structure on the side wall surface of the sacrifice column part, wherein the top surface of the first conductive structure is lower than that of the sacrifice column;
forming a gate on the top of the first conductive structure, wherein the gate is located on the side wall surface of the sacrifice column part, and the top surface of the gate is lower than that of the sacrifice column;
forming a support structure on the top of the grid, wherein the support structure covers the side wall surface of the sacrificial column and exposes the top of the sacrificial column;
after forming bearing structure, remove sacrificial post forms the opening, the opening includes from top to bottom in proper order: a first opening formed in the first conductive structure, a second opening formed in the gate, and a third opening formed in the support structure; the first opening is flush with the first conductive structure; the second opening is flush with the grid electrode, and the third opening is flush with the support structure;
forming a first doping layer in the first opening, and doping first doping ions in the first doping layer through first in-situ doping;
forming a channel layer in the second opening;
and forming a second doping layer in the third opening, and doping second doping ions in the second doping layer through second in-situ doping, wherein the second doping ions have the same or opposite conductivity type as the first doping ions.
2. The method of forming a semiconductor structure of claim 1, wherein the sacrificial post comprises: the mask layer is positioned on the fin part column;
the step of forming the sacrificial post comprises: providing an initial substrate; forming a patterned mask layer on the initial substrate; and etching the initial substrate by taking the mask layer as a mask to form a substrate and a fin part column positioned on the substrate.
3. The method of claim 2, wherein the mask layer is made of silicon nitride or silicon oxynitride; the fin column is made of silicon, germanium, silicon carbide or monocrystal of III-V group element materials.
4. The method of forming a semiconductor structure of claim 2, wherein the step of removing the sacrificial post comprises: removing the mask layer; and removing the fin part column after removing the mask layer.
5. The method of claim 4, wherein the process of removing the mask layer comprises: wet etching process; the process for removing the fin pillar comprises the following steps: one or a combination of the dry etching process and the wet etching process.
6. The method of forming a semiconductor structure according to claim 1, wherein a material of the first doping layer is silicon, germanium, silicon germanium, or silicon carbide; the material of the second doping layer is silicon, germanium, silicon germanium or silicon carbide; the channel layer is made of silicon, germanium, silicon germanium or silicon carbide.
7. The method of claim 1, wherein the process of forming the first doped layer comprises: chemical vapor deposition epitaxy process or solid phase epitaxy process; the process of forming the second doped layer includes: chemical vapor deposition epitaxy process or solid phase epitaxy process; the process of forming the channel layer includes: a chemical vapor deposition epitaxy process or a solid phase epitaxy process.
8. The method for forming a semiconductor structure according to claim 1, wherein a concentration of first dopant ions in the first doped layer is greater than 1E21atoms/com3(ii) a The concentration of the second doping ions in the second doping layer is more than 1E21atoms/com3。
9. The method according to claim 1, wherein a dimension of the first doping layer in a direction perpendicular to the surface of the substrate is 3nm to 7 nm; the size of the channel layer along the direction vertical to the surface of the substrate is 15 nm-25 nm; the size of the second doping layer along the direction vertical to the surface of the substrate is 3 nm-7 nm.
10. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the gate electrode: forming a first isolation layer on top of the first conductive structure, the first isolation layer having a top surface lower than the sacrificial post top surface; the gate is located on a top surface of the first isolation layer.
11. The method of forming a semiconductor structure of claim 1, further comprising, after forming the second doped layer: removing part of the support structure to form a second isolation layer, wherein the top surface of the second isolation layer is lower than that of the second doping layer; and forming a second conductive structure on the top of the second isolation layer, wherein the second conductive structure is positioned on the surface of the side wall of the second doped layer.
12. The method of forming a semiconductor structure of claim 1, wherein the support structure comprises: a third isolation layer on the gate, a top surface of the third isolation layer being lower than a top surface of the sacrificial post; and the third conductive structure is positioned on the top of the third isolating layer and positioned on the side wall surface of the sacrificial column.
13. The method of forming a semiconductor structure of claim 1, wherein before forming the gate electrode, after forming the first conductive layer, further comprising: forming a gate dielectric layer covering the surface of the side wall of the sacrificial column; the grid electrode covers the side wall of the grid medium layer.
14. The method of forming a semiconductor structure of claim 13, wherein after removing the sacrificial post, further comprising: and removing part of the gate dielectric layer to enable the top surface of the gate dielectric layer to be lower than the top surface of the support structure.
15. The method of claim 14, wherein a portion of the gate dielectric layer is removed prior to forming the second doped layer;
or after forming the second doping layer, the forming method further includes: removing part of the support structure to form a second isolation layer, wherein the second isolation layer exposes the side wall of the gate dielectric layer; and after the second isolation layer is formed, removing part of the gate dielectric layer to enable the top surface of the gate dielectric layer to be lower than the top surface of the second doping layer.
16. The method of claim 15, wherein the gate dielectric layer comprises one or a combination of silicon oxide and a high-k dielectric material; the thickness of the gate dielectric layer is 1 nm-2 nm.
17. The method for forming a semiconductor structure of claim 13, wherein before removing the sacrificial post and after forming the gate, removing a portion of the gate dielectric layer such that a top surface of the gate dielectric layer is lower than a top surface of the sacrificial post;
after removing part of the gate dielectric layer and before forming the support structure, the forming method further comprises the step of forming a first side wall on the surface of the side wall of the sacrificial column;
after removing the sacrificial post, the method further comprises: and removing the first side wall.
18. The method for forming a semiconductor structure according to claim 17, wherein the first sidewall spacers are made of silicon nitride or silicon oxynitride.
19. The method of forming a semiconductor structure of claim 1, further comprising: doping a third dopant ion in the channel layer by a third in-situ doping; when the second doped ions are the same as the first doped ions in conductivity type, the third doped ions are opposite in conductivity type to the first doped ions; when the second doped ion and the first doped ion are opposite in conductivity type, the third doped ion and the first doped ion are the same in conductivity type, or the third doped ion and the second doped ion are the same in conductivity type.
20. A semiconductor structure formed by the method of forming of any one of claims 1 through 19.
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| WO2013158692A1 (en) * | 2012-04-17 | 2013-10-24 | International Business Machines Corporation | Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures |
| CN105702738A (en) * | 2016-02-05 | 2016-06-22 | 中国科学院微电子研究所 | Negative capacitor-equipped FinFET, manufacture method therefor and electronic device |
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