CN108122761B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108122761B CN108122761B CN201611085957.6A CN201611085957A CN108122761B CN 108122761 B CN108122761 B CN 108122761B CN 201611085957 A CN201611085957 A CN 201611085957A CN 108122761 B CN108122761 B CN 108122761B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a base, wherein the base comprises a substrate and a fin part positioned on the substrate; forming a grid structure; forming a source drain doped region; forming a precursor side wall on the side wall of the grid structure facing the source drain doped region; forming a pseudo side wall on the side wall of the precursor side wall; forming a dielectric layer; thinning the precursor side wall to expose partial side wall of the grid structure, wherein the rest precursor side wall is used for forming a corner side wall; and removing the pseudo side wall, and forming a vacuum side wall between the grid structure and the dielectric layer. The technical scheme of the invention is beneficial to improving the degradation problem of the on-resistance and on-current performance of the transistor and improving the performance of the formed semiconductor structure.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration of semiconductor devices increase, the size of transistors also becomes smaller and smaller. The performance of transistors is degraded by the short channel effect and gate leakage problems at small dimensions, and thus improving performance by reducing the physical dimensions of conventional transistors faces a series of difficulties.
Group iii-v semiconductor materials (e.g., InGaAs) are currently the focus of research due to their excellent electron transport properties. In order to solve the difficulty that the physical size of the conventional semiconductor device is difficult to further reduce, the prior art proposes a technical scheme for forming a transistor channel by using a iii-v group semiconductor material to improve the performance of the transistor.
However, in the prior art, the performance of the semiconductor structure of the III-V semiconductor material as the channel material still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a fin part positioned on the substrate; forming a grid electrode structure on the fin part, wherein the grid electrode structure stretches across the fin part and covers the partial top of the fin part and the surface of partial side wall of the fin part; forming source-drain doped regions in the fin parts on the two sides of the grid structure; forming a precursor side wall on the side wall of the grid structure facing the source drain doped region; forming a pseudo side wall on the side wall of the precursor side wall; forming a dielectric layer on the substrate exposed by the gate structure, the precursor side wall and the pseudo side wall, wherein the dielectric layer exposes the gate structure, the precursor side wall and the pseudo side wall; thinning the precursor side wall to expose partial side wall of the grid structure, wherein the rest precursor side wall is used for forming a corner side wall; and removing the pseudo side wall, and forming a vacuum side wall between the grid structure and the dielectric layer.
Optionally, in the step of forming the precursor side wall, the material of the precursor side wall is one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
Optionally, the step of forming the precursor side wall includes: forming a side wall material layer on the grid structure and the substrate; and removing the side wall material layer on the grid structure and the substrate to form a precursor side wall positioned on the side wall of the grid structure.
Optionally, the step of removing the gate structure and the substrate sidewall material layer includes: performing first plasma treatment on the gate structure and the substrate side wall material layer; and removing part of the material subjected to plasma treatment in a wet method mode to form the precursor side wall.
Optionally, after the forming of the precursor side wall and before the forming of the pseudo side wall, the forming method further includes: performing second plasma treatment on the part of the precursor side wall far away from the substrate; the step of thinning the precursor side wall comprises the following steps: and removing part of the material subjected to the plasma treatment by a wet method.
Optionally, in the step of forming the precursor side wall, the material of the precursor side wall is silicon nitride; one or both of the steps of the first plasma processing and the second plasma processing include: plasma treatment was performed using H2 or He plasma.
Optionally, using H2Or in the step of carrying out plasma treatment by He plasma, the process parameters comprise: the process gas pressure is in the range of 2mTorr to 100mTorr, H2Or He flow rate in the range of 50sccm to 500sccm and process temperature in the range of 0 ℃ to 100 ℃.
Optionally, in the step of forming the precursor side wall, the material of the precursor side wall is silicon nitride; the step of removing the plasma-treated portion of the material by a wet process includes: and removing part of the material subjected to the plasma treatment by adopting hydrofluoric acid.
Optionally, in the step of forming the vacuum sidewall, a ratio of a size of the vacuum sidewall to a size of the corner sidewall is in a range from 5:4 to 5:1 in a direction perpendicular to the substrate surface.
Optionally, in the step of forming the source and drain doped regions, along the extending direction of the fin portion, a distance between the source and drain doped regions is greater than a size of the gate structure; the step of forming the precursor side wall comprises the following steps: and forming the precursor side wall on the fin part between the source drain doping area and the grid structure.
Optionally, in the step of forming the pseudo side wall, the pseudo side wall is made of polycrystalline silicon.
Optionally, the step of removing the pseudo side wall includes: and removing the pseudo side wall in a chemical diffusion etching mode.
Optionally, the step of removing the pseudo side wall by chemical diffusion etching includes: by NH3And removing the pseudo side wall.
Optionally, in the step of providing the substrate, a material of the fin portion is a iii-v semiconductor material.
Optionally, in the step of providing the substrate, the fin portion is made of InGaAs.
Accordingly, the present invention also provides a semiconductor structure comprising:
the substrate comprises a substrate and a fin part positioned on the substrate; a dielectric layer on the substrate; the grid electrode structure is positioned on the fin part in the dielectric layer, stretches across the fin part and covers the partial top of the fin part and the surface of partial side wall; the source-drain doped regions are positioned in the fin parts on two sides of the grid structure; the corner side wall is positioned on the side wall of the grid structure facing the source drain doped region; and the vacuum side wall is positioned between the grid structure and the dielectric layer.
Optionally, the corner sidewall is made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
Optionally, in a direction perpendicular to the substrate surface, a ratio of the size of the vacuum sidewall to the size of the corner sidewall is in a range from 5:4 to 5: 1.
Optionally, the fin portion is made of a III-V semiconductor material.
Optionally, the distance between the source and drain doped regions is greater than the size of the gate structure; the corner side wall is positioned on the fin part between the source drain doping area and the grid electrode structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme, the corner side wall is formed on the side wall of the grid structure facing the source drain doped region, and the dielectric constant of the material of the corner side wall is larger than that of vacuum, so that the average dielectric constant of the corner side wall and the average dielectric constant of the vacuum side wall can be effectively increased due to the arrangement of the corner side wall, the smaller edge capacitance can be maintained, the problem of degradation of the on-resistance and on-current performance of a transistor can be improved, and the performance of the formed semiconductor structure can be improved.
Drawings
Fig. 1 to 13 are schematic structural diagrams corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention.
Detailed Description
As known from the background art, the semiconductor structure using III-V semiconductor material as channel material in the prior art has the problem of poor performance. The reason for the poor performance of the III-V semiconductor material is analyzed by combining the characteristics of the III-V semiconductor material:
the channel formed by the III-V semiconductor material has more remarkable quantum confinement effect and subband splitting phenomenon. Therefore, with the reduction of the channel length, the semiconductor structure with the III-V group semiconductor material as the channel material is easy to have the problems that the electric isolation performance of a gate dielectric layer is degraded, and the tunneling current of a gate is increased.
In order to suppress gate leakage, a gate dielectric layer with a larger thickness is required to be arranged in a semiconductor structure with III-V semiconductor materials as channel materials. In order to improve the influence of the increase of the thickness of the gate dielectric layer on the performance of the device, a vacuum spacer structure is introduced into the semiconductor structure, namely, the gate structure and the dielectric layer are electrically insulated by air.
But because the dielectric constant of air is small (K)vacuum1), the arrangement of the vacuum sidewall reduces the fringe Capacitance (fringe Capacitance) of the device, but at the same time, the on-resistance and on-current performance of the transistor are degraded, which affects the performance of the formed semiconductor structure.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including:
providing a base, wherein the base comprises a substrate and a fin part positioned on the substrate; forming a grid electrode structure on the fin part, wherein the grid electrode structure stretches across the fin part and covers the partial top of the fin part and the surface of partial side wall of the fin part; forming source-drain doped regions in the fin parts on the two sides of the grid structure; forming a precursor side wall on the side wall of the grid structure facing the source drain doped region; forming a pseudo side wall on the side wall of the precursor side wall; forming a dielectric layer on the substrate exposed by the gate structure, the precursor side wall and the pseudo side wall, wherein the dielectric layer exposes the gate structure, the precursor side wall and the pseudo side wall; thinning the precursor side wall to expose partial side wall of the grid structure, wherein the rest precursor side wall is used for forming a corner side wall; and removing the pseudo side wall, and forming a vacuum side wall between the grid structure and the dielectric layer.
According to the technical scheme, the corner side wall is formed on the side wall of the grid structure facing the source drain doped region, and the dielectric constant of the material of the corner side wall is larger than that of vacuum, so that the average dielectric constant of the corner side wall and the average dielectric constant of the vacuum side wall can be effectively increased due to the arrangement of the corner side wall, the smaller edge capacitance can be maintained, the problem of degradation of the on-resistance and on-current performance of a transistor can be improved, and the performance of the formed semiconductor structure can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1 to 13, schematic structural diagrams corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention are shown.
As shown in fig. 1 to 3, a base is provided, and the base includes a substrate 100 and a fin 130 on the substrate 100.
Wherein FIG. 1 is a schematic three-dimensional structure of the substrate, and FIG. 2 is a schematic cross-sectional structure along line AA in FIG. 1; fig. 3 is a schematic cross-sectional view taken along line BB in fig. 1.
The substrate 100 is used to provide a process platform.
In this embodiment, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the substrate may also be a polysilicon substrate, an amorphous silicon substrate or a silicon germanium substrate, a carbon silicon substrate, a silicon on insulator substrate, a germanium on insulator substrate, a glass substrate or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate. The material of the substrate may be chosen to be suitable for process requirements or easy to integrate.
Fin 130 is used to provide a channel for the finfet.
In the present embodiment, the fin 130 is made of a iii-v semiconductor material. Specifically, the material of the fin 130 is InGaAs. In other embodiments of the present invention, the fin may be made of other iii-v semiconductor materials. The III-V group semiconductor material becomes an ideal channel material of the transistor by higher low field electron mobility, which is beneficial to reducing the channel length of the transistor and improving the integration level of the semiconductor structure.
The steps of forming the substrate 100 and the fin 130 include: providing a substrate 100; forming a fin material layer on the substrate 100; forming a patterned fin part mask layer on the fin part material layer; and etching the fin material layer by using the fin mask layer as a mask to form a fin 130.
The fin material layer is used for etching to form the fin 130.
In this embodiment, the fin 130 is made of InGaAs. Therefore, the material of the fin material layer is also InGaAs, and may be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition.
It should be noted that, in this embodiment, the base further includes an oxide layer 110 located between the substrate 100 and the fin 130. The oxide layer 110 is used to provide a good interface foundation for the fin material layer to improve the quality of the formed fin material layer. Therefore, after providing the substrate 100 and before forming the fin material layer, the forming method further includes: an oxide layer is formed on the substrate 100.
The fin mask layer is used to define the size and location of the fin 130.
The step of forming the fin mask layer includes: forming a mask material layer on the fin material layer; forming a pattern layer on the mask material layer; and etching the mask material layer by taking the pattern layer as a mask to expose the fin part material layer so as to form the fin part mask layer.
The pattern layer is used for patterning the mask material layer so as to define the size and the position of the fin portion.
In this embodiment, the pattern layer is a patterned photoresist layer and may be formed through a coating process and a photolithography process. In other embodiments of the present invention, the patterned layer may also be a mask formed by a multi-patterning mask process, so as to reduce the feature size of the fin portion and the distance between adjacent fin portions, and improve the integration level of the formed semiconductor structure. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
With continued reference to fig. 1-3, a gate structure on the fin 130 is formed, the gate structure crossing the fin 130 and covering a portion of the top and a portion of the sidewall of the fin 130.
In this embodiment, the gate structure is a dummy gate structure 121 for occupying a space for a metal gate structure to be formed subsequently. In other embodiments of the present invention, the gate structure may also be a gate structure of the formed semiconductor structure.
In this embodiment, the dummy gate structure 121 may be a stacked structure, and includes a dummy oxide layer on the substrate and a dummy gate on the dummy oxide layer. The dummy gate is made of polysilicon, and the dummy oxide layer is made of silicon oxide and silicon oxynitride.
In other embodiments of the present invention, the dummy gate may be made of other materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. In other embodiments of the present invention, the dummy gate structure may also be a single-layer structure, and the material may be one or more selected from polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, amorphous carbon, and other materials.
The step of forming the dummy gate structure 121 includes: forming a dummy gate material layer on the substrate; and forming a dummy gate mask layer on the dummy gate material layer, and etching the dummy gate material layer by using the dummy gate mask layer as a mask to form the dummy gate structure 121.
With continued reference to fig. 1 to 3, source-drain doped regions 131 are formed in the fins 130 on both sides of the gate structure.
Specifically, in this embodiment, the gate structure is a dummy gate structure 121. The step of forming the source and drain doped regions 131 includes: and forming source-drain doped regions 131 in the fin portions 130 on two sides of the dummy gate structure 121.
In this embodiment, the semiconductor structure is an NMOS transistor, so the doped ions of the source/drain doped region 131 are N-type ions, such as P, As or Sb. In other embodiments of the present invention, the semiconductor structure may also be a PMOS transistor, so that the doped ions In the source/drain doped region are P-type ions, such as B, Ga or In.
In this embodiment, along the extending direction of the fin 130, the distance between the source/drain doped regions 131 is greater than the size of the dummy gate structure 121, that is, the semiconductor structure has a structure in which a source/drain region (gate-to-source/drain) is exposed at the bottom. The structure is beneficial to reducing the fringe capacitance of the drain terminal in the formed semiconductor structure, thereby improving the performance of the formed semiconductor structure. Therefore, a portion of the fin 130 between the source and drain doped regions 131 for forming a channel is not covered by the dummy gate structure 121, that is, the dummy gate structure 121 exposes a portion of the fin 130 between the source and drain doped regions 131 for forming a channel.
In this embodiment, the step of forming the source/drain doped region 131 includes: the source/drain doped regions 131 are formed by performing ion implantation on the fin portions 130 on both sides of the dummy gate structure 121. However, in other embodiments of the present invention, the source/drain doped region may also be formed in the fin portion by epitaxial growth.
Referring to fig. 4 to fig. 7, a precursor sidewall spacer 144 is formed on the sidewall of the gate structure facing the source/drain doped region 131.
Wherein fig. 4 and 6 are schematic cross-sectional views corresponding to fig. 2; fig. 5 and 7 are schematic cross-sectional views corresponding to fig. 3.
In this embodiment, the gate structure is a dummy gate structure 121. The step of forming the precursor sidewall spacers 144 therefore includes: and forming a precursor side wall 144 on the side wall of the dummy gate structure 121 facing the source-drain doped region 131.
The precursor side walls 144 are used to occupy space for the formation of subsequent vacuum side walls and are also used to form corner side walls by etching. In addition, in this embodiment, the gate structure is a dummy gate structure 121, so the precursor sidewall 144 is also used to define the size and position of a subsequently formed gate structure.
In this embodiment, the distance between the source-drain doped regions 131 is greater than the size of the gate structure. The step of forming the precursor side walls 144 includes: and forming the precursor side walls 144 on the fin 130 between the source-drain doped region 131 and the gate structure.
The material of the precursor side walls 144 is silicon nitride. In other embodiments of the present invention, the material of the precursor sidewall may also be one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride
The step of forming the precursor side walls 144 includes: forming a side wall material layer 143 on the gate structure and the substrate; and removing the side wall material layers on the gate structure and the substrate to form a precursor side wall 144 positioned on the side wall of the gate structure.
In this embodiment, the step of forming the precursor side wall 144 includes: as shown in fig. 4, a sidewall material layer 143 is formed on the dummy gate structure 121 and the substrate; as shown in fig. 5, the sidewall material layers on the dummy gate structure 121 and the substrate are removed, and a precursor sidewall 144 located on the sidewall of the dummy gate structure 121 is formed.
The step of removing the sidewall material layer 143 on the gate structure and on the substrate includes: performing first plasma treatment 210 on the gate structure and the substrate sidewall material layer 143; a portion of the material subjected to the first plasma treatment 210 is removed by a wet process to form the precursor side walls 144.
Specifically, the step of removing the sidewall material layer 143 on the dummy gate structure 121 and on the substrate includes: performing first plasma treatment 210 on the dummy gate structure 121 and the substrate sidewall material layer 143; and removing part of the material subjected to the first plasma treatment by a wet method to form the precursor side walls 144.
In this embodiment, the material of the precursor sidewall is silicon nitride. Therefore, in the step of the first plasma treatment 210, H is used2Or He plasma to carry out plasma treatment, and the process parameters comprise: the process gas pressure is in the range of 2mTorr to 100mTorr, H2Or the flow rate of the He gas is within the range of 50sccm to 500sccm, the flow rate of the Ar gas is within the range of 0sccm to 200sccm, and the process temperature is within the range of 0 ℃ to 100 ℃; the step of removing the part of the material processed by the plasma by means of wet etching comprises the following steps: and removing part of the material subjected to the plasma treatment by using hydrofluoric acid, wherein the hydrofluoric acid is dilute hydrofluoric acid, namely the concentration of the hydrofluoric acid ranges from 1/2000 to 1/100 in percentage by volume.
The method of combining plasma treatment and wet etching has a high etching selection ratio for the side wall material layer 143, so that the influence of the process steps for forming the precursor side wall 144 on other semiconductor structures on the substrate can be effectively reduced, the yield can be improved, and the performance of the formed semiconductor structure can be improved.
With combined reference to fig. 8 and 9, a dummy sidewall spacer 145 is formed on the sidewall of the precursor sidewall spacer 144.
Fig. 8 is a schematic cross-sectional structure diagram corresponding to fig. 6, and fig. 9 is a schematic cross-sectional structure diagram corresponding to fig. 7.
The dummy sidewall 145 is used to occupy space for the formation of the subsequent vacuum sidewall.
Specifically, in this embodiment, the material of the pseudo sidewall spacers 145 is polysilicon. The step of forming the dummy spacers 145 includes: forming a pseudo side wall material layer on the substrate, the pseudo gate structure 121 (as shown in fig. 6) and the surfaces of the precursor side walls 144; and removing the substrate, the pseudo gate structure 121 and the pseudo side wall material layer on the precursor side wall 144, wherein the remaining pseudo side wall material layer on the side wall of the precursor side wall 144 is used for forming the pseudo side wall 145.
It should be noted that, as shown in fig. 7, after the precursor side walls 144 are formed and before the dummy side walls 145 are formed, the forming method further includes: a second plasma treatment 220 is performed on portions of the precursor side walls 144 remote from the substrate 100.
The second plasma treatment 220 is used to provide a process foundation for the subsequent formation of the corner sidewall spacers, thereby reducing the effect of the formation of the corner sidewall spacers on other semiconductor structures on the substrate.
Specifically, in the step of the second plasma treatment 220, H is used2Or He plasma to carry out plasma treatment, and the process parameters comprise: the process gas pressure is in the range of 2mTorr to 100mTorr, H2Or the flow rate of the He gas is in the range of 50sccm to 500sccm, the flow rate of the Ar gas is in the range of 0sccm to 200sccm, and the process temperature is in the range of 0 ℃ to 100 ℃.
In this embodiment, the first plasma processing 210 and the second plasma processing 220 are processed in the same manner. This is merely an example, and in other embodiments of the present invention, the first plasma processing step and the second plasma processing step are processed in different manners.
With continued reference to fig. 8 and 9, a dielectric layer 150 is formed on the substrate where the gate structure, the precursor sidewall spacers 144, and the dummy sidewall spacers 145 are exposed, and the dielectric layer 150 exposes the gate structure, the precursor sidewall spacers 144, and the dummy sidewall spacers 145.
The dielectric layer 150 is used for realizing electrical isolation between adjacent semiconductor structures and also for defining the size and position of a subsequently formed vacuum sidewall.
In this embodiment, the dielectric layer 150 is an interlayer dielectric layer made of silicon oxide. In other embodiments of the present invention, the material of the dielectric layer may also be selected from other dielectric materials such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, and the like.
The step of forming the dielectric layer 150 includes: forming a dielectric material layer on the substrate exposed by the dummy gate structure 121, the precursor side walls 144 and the dummy side walls 145 by chemical vapor deposition (for example, fluid chemical vapor deposition) or the like, wherein the dielectric material layer covers the dummy gate structure 121; and removing the dielectric material layer higher than the dummy gate structure 121 to expose the dummy gate structure 121, the precursor side walls 144 and the dummy side walls 145.
It should be noted that in this embodiment, the gate structure is a dummy gate structure 121, so with reference to fig. 8 and 9, after the dielectric layer 150 is formed, the dummy gate structure 121 (as shown in fig. 6) is removed to form an opening, and a metal gate structure 120 is formed in the opening.
In this embodiment, the semiconductor structure has a "high-K metal gate" structure; the step of removing the dummy gate structure 121 is used to form a metal gate structure.
The dummy gate structure 121 crosses over the fin 130 and covers part of the top and the sidewall of the fin 130, so that the bottom of the opening formed by removing the dummy gate structure 121 exposes part of the top and the sidewall of the fin 130. The metal gate structure 120 formed in the opening also crosses over the fin 130 and covers a portion of the surface of the top and sidewalls of the fin 130.
The metal gate structure 120 includes a gate dielectric layer (not shown) disposed on the substrate and a gate electrode (not shown) disposed on the gate dielectric layer.
The gate dielectric layer is used for realizing the electric isolation between the formed gate structure and the channel in the substrate. The gate dielectric layer is made of a high-K dielectric material. The high-K dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the gate dielectric layer is made of HfO2. In other embodiments of the present invention, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3And the like.
The gate electrode layer serves as an electrode to realize electrical connection with an external circuit. In this embodiment, the material of the gate electrode layer is W. In other embodiments of the present invention, the gate electrode layer may be made of Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.
It should be noted that, since the material of the fin portion 130 is InGaAs, compared with the technical solution in which the material of the fin portion is other semiconductor materials, in this embodiment, the Thickness of the gate dielectric layer is larger, so that the gate dielectric layer has a larger Thickness of an Equivalent Oxide layer (Equivalent Oxide Thickness) to suppress the gate leakage current. Specifically, in this embodiment, the thickness of the gate dielectric layer is within
To
Within the range.
Referring to fig. 10 and 11, the precursor side walls 144 (as shown in fig. 8 and 9) are thinned to expose a part of the side walls of the gate structure, and the remaining precursor side walls 144 are used to form corner side walls 141.
In this embodiment, the gate structure is a metal gate structure 120, so the step of performing thinning processing includes: and thinning the precursor side walls 144 to expose part of the side walls of the metal gate structure 120 to form corner side walls 141.
Wherein, fig. 10 is a schematic cross-sectional structure diagram corresponding to fig. 8; fig. 11 is a schematic cross-sectional view of fig. 9.
The corner sidewall 141 is used for realizing electrical isolation between the gate structure and other semiconductor structures together with a vacuum sidewall formed subsequently.
The dielectric constant of the material of the corner sidewall 141 is greater than that of vacuum, so the arrangement of the corner sidewall 141 is beneficial to improving the problem of the degradation of the on-resistance and on-current performance of the transistor, reducing the delay phenomenon, and improving the performance of the formed semiconductor structure.
The material of the precursor side walls 144 (shown in fig. 8 and 9) is silicon nitride, that is, the material of the corner side walls 141 is silicon nitride. The dielectric constant of the silicon nitride is 7.5, so the formation of the corner sidewall 141 of the silicon nitride material is beneficial to improving the problem of the performance degradation of the on-resistance and the on-current of the transistor.
In this embodiment, a part of the material of the precursor sidewall 144 away from the substrate 100 is subjected to a second plasma treatment 220 (as shown in fig. 6 and 7), so the step of thinning the precursor sidewall 144 includes: and removing part of the material subjected to the plasma treatment by a wet method.
The step of removing the plasma treated portion of material comprises: hydrofluoric acid is used to remove portions of the material that has undergone the second plasma treatment 220. Specifically, in the step of removing a portion of the material with hydrofluoric acid, the concentration of hydrofluoric acid is in a range from 1/2000 to 1/100 by volume percent. It should be noted that the volume percentage refers to the volume percentage of HF to water.
In this embodiment, the step of removing the first plasma-processed portion and the step of removing the second plasma-processed portion are performed in the same manner. In other embodiments of the present invention, the step of removing the first plasma-treated portion of the material and the step of removing the second plasma-treated portion of the material may be performed in different manners.
After the plasma treatment, the wet etching method has a high etching rate on the precursor side walls 144, so that the plasma treatment and the wet etching are combined to remove part of the material of the precursor side walls 144, the influence of the thinning process on other semiconductor structures on the substrate can be effectively reduced, the yield can be improved, and the performance of the formed semiconductor structure can be improved.
It should be noted that, as shown in fig. 11, in this embodiment, the precursor sidewall spacers 144 (shown in fig. 10) are located between the source-drain doped region 131 and the gate structure 120, so that the corner sidewall spacers 141 are also located between the source-drain doped region 131 and the gate structure 120. This is advantageous in optimizing the performance of the on-resistance and capacitance of the resulting semiconductor structure, thereby improving the delay problem.
Referring to fig. 12 and 13, the dummy spacers 145 are removed, and vacuum spacers 142 are formed between the gate structure and the dielectric layer 150.
The vacuum side wall 142 is used for improving the problem of reduction of conduction current in the formed semiconductor structure and improving the influence of a gate dielectric layer with larger thickness on the formed semiconductor structure. The dielectric constant of the vacuum sidewall 142 is low, which is beneficial to reducing the fringe Capacitance (Fringing Capacitance) of the formed semiconductor structure.
The step of removing the dummy spacers 145 includes: and removing the pseudo side walls 145 by means of chemical diffusion etching. After removing the pseudo-sidewall spacers 145, gaps are formed among the metal gate structure 120, the corner sidewall spacers 141, and the dielectric layer 150, and the gaps are used for forming the vacuum sidewall spacers 142.
In this embodiment, the step of removing the dummy spacers 145 by chemical diffusion etching includes: by NH3And removing the pseudo side walls 145. Specifically, a Frontier machine is adopted, and NH is adopted3And removing the pseudo side walls 145 by means of chemical diffusion etching. Because the material of the pseudo-side wall 145 is polysilicon, the etching rate of the polysilicon material is higher in the etching method in such a way, so that the influence of the process for forming the vacuum side wall 142 on other semiconductor structures can be effectively reduced by removing the pseudo-side wall 145 in such a way, which is beneficial to the improvement of yield and the performance of devices.
It should be noted that, in a direction perpendicular to the substrate surface, a ratio of a size of the vacuum sidewall 142 to a size of the corner sidewall 141 is not preferably too large or too small.
In the direction perpendicular to the substrate surface, if the ratio of the size of the vacuum sidewall 142 to the size of the corner sidewall 141 is too large, that is, the size of the vacuum sidewall 142 is too large, and the size of the corner sidewall 141 is too small, the average dielectric constants of the vacuum sidewall 142 and the corner sidewall 141 are small, which may affect the function of improving the performance degradation problem of the on-resistance and the on-current; if the ratio of the size of the vacuum sidewall 142 to the size of the corner sidewall 141 is too small, that is, the size of the vacuum sidewall 142 is too small, and the size of the corner sidewall 141 is too large, the average dielectric constants of the vacuum sidewall 142 and the corner sidewall 141 are large, which may also affect the function of improving the performance degradation problem of the on-resistance and the on-current. Specifically, in the step of forming the vacuum sidewall 142, the ratio of the size of the vacuum sidewall 142 to the size of the corner sidewall 141 along the direction perpendicular to the substrate surface is in the range of 5:4 to 5: 1.
Accordingly, the present invention also provides a semiconductor structure, as shown in fig. 13, including:
a base including a substrate 100 and a fin 130 on the substrate 100; a dielectric layer 150 on the substrate; a gate structure located on the fin 130 in the dielectric layer 150, the gate structure crossing over the fin 130 and covering a portion of the top and a portion of the sidewall of the fin; source-drain doped regions 131 located in the fin portions 130 on both sides of the gate structure; the corner side wall 141 is positioned on the side wall of the gate structure facing the source drain doped region 131; and the vacuum side wall 142 is positioned between the gate structure and the dielectric layer 150.
The substrate 100 is used to provide a process platform.
In this embodiment, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the substrate may also be a polysilicon substrate, an amorphous silicon substrate or a silicon germanium substrate, a carbon silicon substrate, a silicon on insulator substrate, a germanium on insulator substrate, a glass substrate or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate. The material of the substrate may be chosen to be suitable for process requirements or easy to integrate.
In the present embodiment, the fin 130 is made of a iii-v semiconductor material. Specifically, the material of the fin 130 is InGaAs. In other embodiments of the present invention, the fin may be made of other iii-v semiconductor materials. The III-V group semiconductor material becomes an ideal channel material of the transistor by higher low field electron mobility, which is beneficial to reducing the channel length of the transistor and improving the integration level of the semiconductor structure.
It should be noted that, in this embodiment, the base further includes an oxide layer 110 located between the substrate 100 and the fin 130. The oxide layer 110 is used to provide an interface foundation for the formation of the fin material to improve the quality of the fin 130.
The dielectric layer 150 is used for realizing electrical isolation between adjacent semiconductor structures and also for defining the size and position of a subsequently formed vacuum sidewall.
In this embodiment, the dielectric layer 150 is an interlayer dielectric layer made of silicon oxide. In other embodiments of the present invention, the material of the dielectric layer may also be selected from other dielectric materials such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, and the like.
The gate structure is used for controlling the conduction and the cut-off of a channel in the semiconductor structure.
In this embodiment, the semiconductor structure has a "high-K metal gate" structure, so the gate structure is a metal gate structure 120. The metal gate structure 120 includes a gate dielectric layer (not shown) disposed on the substrate and a gate electrode (not shown) disposed on the gate dielectric layer.
The gate dielectric layer is used for realizing the electric isolation between the formed gate structure and the channel in the substrate. The gate dielectric layer is made of a high-K dielectric material. The high-K dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the gate dielectric layer is made of HfO2. In other embodiments of the present invention, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3And the like.
The gate electrode layer serves as an electrode to realize electrical connection with an external circuit. In this embodiment, the material of the gate electrode layer is W. In other embodiments of the present invention, the gate electrode layer may be made of Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.
It should be noted that, since the material of the fin portion 130 is InGaAs, compared with the technical solution in which the material of the fin portion is other semiconductor materials, in this embodiment, the Thickness of the gate dielectric layer is larger, so that the gate dielectric layer has a larger Thickness of an Equivalent Oxide layer (Equivalent Oxide Thickness) to suppress the gate leakage current. Specifically, in this embodiment, the thickness of the gate dielectric layer is within
To
Within the range.
The source-drain doped region 131 is used for forming a source region or a drain region of the semiconductor structure.
In this embodiment, the semiconductor structure is an NMOS transistor, so the doped ions in the source/drain doped region 131 are N-type ions, such as P, As or Sb. In other embodiments of the present invention, the semiconductor structure may also be a PMOS transistor, so that the doped ions In the source/drain doped region are P-type ions, such as B, Ga or In.
In this embodiment, along the extending direction of the fin 130, the distance between the source/drain doped regions 131 is greater than the size of the dummy gate structure 121, that is, the semiconductor structure has a structure in which a source/drain region (gate-to-source/drain) is exposed at the bottom. The structure is beneficial to reducing the fringe capacitance of the drain terminal in the formed semiconductor structure, thereby improving the performance of the formed semiconductor structure. Therefore, a portion of the fin 130 between the source and drain doped regions 131 for forming a channel is not covered by the metal gate structure 120, that is, the metal gate structure 120 exposes a portion of the fin 130 between the source and drain doped regions 131 for forming a channel.
The corner side walls 141 are used for realizing electrical isolation between the gate structure and other semiconductor structures together with the vacuum side walls 142.
The dielectric constant of the material of the corner sidewall 141 is greater than that of vacuum, so the arrangement of the corner sidewall 141 is beneficial to improving the problem of the degradation of the on-resistance and on-current performance of the transistor, reducing the delay phenomenon, and improving the performance of the formed semiconductor structure.
In this embodiment, the corner sidewall 141 is made of silicon nitride. The dielectric constant of silicon nitride is 7.5, so the corner sidewall 141 of silicon nitride material is beneficial to improving the problem of the performance degradation of the on-resistance and the on-current of the transistor.
In other embodiments of the present invention, the corner sidewall may also be made of one or more materials selected from silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride
In this embodiment, the distance between the source-drain doped regions 131 is greater than the size of the gate structure, so the corner sidewall 141 is located on the fin 130 between the source-drain doped regions 131 and the gate structure.
The vacuum side wall 142 is used for improving the problem of reduction of conduction current in the formed semiconductor structure and improving the influence of a gate dielectric layer with larger thickness on the formed semiconductor structure. The dielectric constant of the vacuum sidewall 142 is low, which is beneficial to reducing the fringe Capacitance (Fringing Capacitance) of the formed semiconductor structure.
It should be noted that, in a direction perpendicular to the substrate surface, a ratio of a size of the vacuum sidewall 142 to a size of the corner sidewall 141 is not preferably too large or too small.
In the direction perpendicular to the substrate surface, if the ratio of the size of the vacuum sidewall 142 to the size of the corner sidewall 141 is too large, that is, the size of the vacuum sidewall 142 is too large, and the size of the corner sidewall 141 is too small, the average dielectric constants of the vacuum sidewall 142 and the corner sidewall 141 are small, which may affect the function of improving the performance degradation problem of the on-resistance and the on-current; if the ratio of the size of the vacuum sidewall 142 to the size of the corner sidewall 141 is too small, that is, the size of the vacuum sidewall 142 is too small, and the size of the corner sidewall 141 is too large, the average dielectric constants of the vacuum sidewall 142 and the corner sidewall 141 are large, which may also affect the function of improving the performance degradation problem of the on-resistance and the on-current. Specifically, in the step of forming the vacuum sidewall 142, the ratio of the size of the vacuum sidewall 142 to the size of the corner sidewall 141 along the direction perpendicular to the substrate surface is in the range of 5:4 to 5: 1.
In summary, according to the technical scheme of the invention, the corner side wall is formed on the side wall of the gate structure facing the source-drain doped region, and the dielectric constant of the material of the corner side wall is greater than that of vacuum, so that the average dielectric constant of the corner side wall and the average dielectric constant of the vacuum side wall can be effectively increased by the arrangement of the corner side wall, thereby being beneficial to maintaining smaller edge capacitance, improving the degradation problem of the on-resistance and on-current performance of the transistor, and being beneficial to improving the performance of the formed semiconductor structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a fin part positioned on the substrate;
forming a grid electrode structure on the fin part, wherein the grid electrode structure stretches across the fin part and covers the partial top of the fin part and the surface of partial side wall of the fin part;
forming source-drain doped regions in the fin parts on the two sides of the grid structure;
forming a precursor side wall on the side wall of the grid structure facing the source drain doped region;
forming a pseudo side wall on the side wall of the precursor side wall;
forming a dielectric layer on the substrate exposed by the gate structure, the precursor side wall and the pseudo side wall, wherein the dielectric layer exposes the gate structure, the precursor side wall and the pseudo side wall;
thinning the precursor side wall to expose partial side wall of the grid structure, wherein the rest precursor side wall is used for forming a corner side wall;
and removing the pseudo side wall, and forming a vacuum side wall between the grid structure and the dielectric layer.
2. The method of claim 1, wherein in the step of forming the precursor sidewall spacers, the material of the precursor sidewall spacers is one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
3. The method of forming of claim 1, wherein forming the precursor sidewall spacers comprises:
forming a side wall material layer on the grid structure and the substrate;
and removing the side wall material layer on the grid structure and the substrate to form a precursor side wall positioned on the side wall of the grid structure.
4. The method of claim 3, wherein the step of removing the layer of spacer material on the gate structure and on the substrate comprises:
performing first plasma treatment on the gate structure and the substrate side wall material layer;
and removing part of the material subjected to plasma treatment in a wet method mode to form the precursor side wall.
5. The method of forming of claim 1, wherein after forming the precursor sidewall spacers and before forming the dummy sidewall spacers, the method further comprises: performing second plasma treatment on the part of the precursor side wall far away from the substrate;
the step of thinning the precursor side wall comprises the following steps: and removing part of the material subjected to the plasma treatment by a wet method.
6. The method of claim 4, wherein in the step of forming the precursor side wall, the precursor side wall is made of silicon nitride;
after the precursor side wall is formed and before the pseudo side wall is formed, the forming method further comprises the following steps: performing second plasma treatment on the part of the precursor side wall far away from the substrate;
one or both of the steps of the first plasma processing and the second plasma processing include: by means of H2Or He plasma.
7. The forming method of claim 6, wherein H is used2Or in the step of carrying out plasma treatment by He plasma, the process parameters comprise: the process gas pressure is in the range of 2mTorr to 100mTorr, H2Or He flow rate in the range of 50sccm to 500sccm and process temperature in the range of 0 ℃ to 100 ℃.
8. The forming method of claim 4 or 5, wherein in the step of forming the precursor side wall, the material of the precursor side wall is silicon nitride;
the step of removing the plasma-treated portion of the material by a wet process includes: and removing part of the material subjected to the plasma treatment by adopting hydrofluoric acid.
9. The method according to claim 1, wherein in the step of forming the vacuum sidewall, a ratio of a size of the vacuum sidewall to a size of the corner sidewall in a direction perpendicular to the substrate surface is in a range from 5:4 to 5: 1.
10. The method of claim 1, wherein in the step of forming source and drain doped regions, a distance between the source and drain doped regions along the fin extension direction is greater than a dimension of the gate structure;
the step of forming the precursor side wall comprises the following steps: and forming the precursor side wall on the fin part between the source drain doping area and the grid structure.
11. The method according to claim 1, wherein in the step of forming the dummy side walls, the dummy side walls are made of polysilicon.
12. The method according to claim 1 or 11, wherein the step of removing the dummy spacers comprises: and removing the pseudo side wall in a chemical diffusion etching mode.
13. The method of claim 12, wherein the step of removing the dummy spacers by chemical diffusion etching comprises: by NH3And removing the pseudo side wall.
14. The method of claim 1, wherein the fin is formed of a group iii-v semiconductor material in the step of providing the substrate.
15. The method of claim 1 or 14, wherein the step of providing the substrate comprises forming the fin from InGaAs.
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