CN106847695A - The forming method of fin field effect pipe - Google Patents

The forming method of fin field effect pipe Download PDF

Info

Publication number
CN106847695A
CN106847695A CN201510894258.5A CN201510894258A CN106847695A CN 106847695 A CN106847695 A CN 106847695A CN 201510894258 A CN201510894258 A CN 201510894258A CN 106847695 A CN106847695 A CN 106847695A
Authority
CN
China
Prior art keywords
fin
field effect
forming method
layer
fin field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510894258.5A
Other languages
Chinese (zh)
Inventor
赵海
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201510894258.5A priority Critical patent/CN106847695A/en
Publication of CN106847695A publication Critical patent/CN106847695A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A kind of forming method of fin field effect pipe, including:Substrate is provided, the substrate surface is formed with some discrete fins, and the substrate surface is also formed with covering the separation layer on fin partial sidewall surface, and separation layer top less than fin top;Treatment is doped to the fin;After the doping treatment is carried out, prosthetic treatment is carried out to fin top and side wall using gas cluster ion beam technique, repair layer is formed in the fin top surface and sidewall surfaces;Remove the repair layer;After the repair layer is removed, the grid structure of the fin, the atop part surface of the grid structure covering fin and sidewall surfaces are developed across.The present invention improves the electric property of the fin field effect pipe to be formed.

Description

The forming method of fin field effect pipe
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of formation side of fin field effect pipe Method.
Background technology
With continuing to develop for semiconductor process technique, semiconductor technology node follows the development of Moore's Law Trend constantly reduces.In order to adapt to the reduction of process node, it has to constantly shorten MOSFET field-effects The channel length of pipe.The shortening of channel length has the tube core density for increasing chip, increases MOSFET The benefits such as the switching speed of effect pipe.
However, with the shortening of device channel length, the distance between device source electrode and drain electrode also shortens therewith, So grid is deteriorated to the control ability of raceway groove, the difficulty of grid voltage pinch off (pinch off) raceway groove Also it is increasing so that sub-threshold leakage (subthreshold leakage) phenomenon, i.e., so-called short channel Effect (SCE:Short-channel effects) it is easier generation.
Therefore, the requirement scaled in order to preferably adapt to device size, semiconductor technology is gradually opened Begin from planar MOSFET transistor to the transistor transient of the three-dimensional with more high effect, such as fin Formula FET (FinFET).In FinFET, grid can at least enter from both sides to ultra-thin body (fin) Row control, with the grid more much better than than planar MOSFET devices to the control ability of raceway groove, can be fine Suppression short-channel effect;And FinFET is relative to other devices, with more preferable existing integrated circuit The compatibility of manufacturing technology.
However, the electric property of the fin field effect pipe of prior art formation has much room for improvement.
The content of the invention
The problem that the present invention is solved is to provide a kind of forming method of fin field effect pipe, improves the fin for being formed The electric property of formula FET.
To solve the above problems, the present invention provides a kind of forming method of fin field effect pipe, including:Carry For substrate, the substrate surface is formed with some discrete fins, and the substrate surface is also formed with covering The separation layer on fin partial sidewall surface, and separation layer top is less than fin top;To the fin It is doped treatment;After the doping treatment is carried out, using gas cluster ion beam technique to described Fin top and side wall carry out prosthetic treatment, are formed in the fin top surface and sidewall surfaces and repaired Layer;Remove the repair layer;After the repair layer is removed, the grid knot of the fin is developed across Structure, the atop part surface of the grid structure covering fin and sidewall surfaces.
Optionally, the prosthetic treatment is suitable to improve the surface roughness of fin top and side wall.
Optionally, the gas that the prosthetic treatment is used includes oxygen-containing gas.
Optionally, the oxygen-containing gas is O2、O3Or H2O。
Optionally, the gas that the prosthetic treatment is used also includes Ar, N2Or He.
Optionally, the technological parameter of the gas cluster ion beam technique includes:Etching gas and O are provided2, Ar, N are also provided2Or one or more gas in He, etching gas be halogen, carbon, One or more chemical compound gas of composition in protium or nitrogen, etching gas air pressure is more than or equal to 1 Individual standard atmospheric pressure, etching gas form the ion beam of cluster gas by ionization, wherein, ion beam adds Fast electric-field intensity is less than or equal to 100kv, and ion beam energy is less than or equal to 100kev, ion beam dose Less than or equal to 1E17cluster/cm2
Optionally, the material of the fin is silicon;The material of the repair layer is silica.
Optionally, the thickness of the repair layer is 0.5 nanometer to 1 nanometer.
Optionally, using wet-etching technology, the repair layer is removed.
Optionally, the etch liquids that the wet-etching technology is used are the hydrofluoric acid solution of dilution, dilution Hydrofluoric acid solution in the volume ratio of deionized water and hydrofluoric acid be 200:1 to 500:1.
Optionally, before treatment is doped to the fin, in the fin top surface and side wall Surface forms screen layer;Before the prosthetic treatment is carried out, removal is located at fin top surface and side The screen layer of wall surface.
Optionally, the screen layer is formed using atom layer deposition process.
Optionally, the material of the screen layer is silica or silicon oxynitride.
Optionally, the doping treatment is carried out using ion implantation technology;The doping of the doping treatment from Son is N-type ion or p-type ion.
Optionally, after the removal repair layer, before the formation grid structure, also including step: Cleaning treatment is carried out to the fin top surface and sidewall surfaces.
Optionally, the grid structure includes gate dielectric layer and the gate electrode layer positioned at gate dielectric layer surface.
Optionally, the processing step for forming the grid structure includes:In the fin top surface and side Wall surface and insulation surface form gate dielectric film;Gate electrode film is formed on the gate dielectric film surface; The graphical gate electrode film and gate dielectric film, form the grid structure.
Optionally, the substrate includes first area and second area, wherein, first area is NMOS Region or PMOS area, second area are NMOS area or PMOS area.
Compared with prior art, technical scheme has advantages below:
In the technical scheme of the forming method of the fin field effect pipe that the present invention is provided, mixed to fin Live together reason after, formed grid structure before, using gas cluster ion beam technique to fin top and side Wall carries out prosthetic treatment, and repair layer is formed in the fin top surface and sidewall surfaces by lattice damage, After the repair layer is removed, the lattice defect of fin top surface and sidewall surfaces is removed, and fin The flatness of portion top and sidewall surfaces is improved so that between the grid structure and fin that are subsequently formed Interface performance be improved, contacted between the grid structure and fin closely, so as to improve formation The electric property of fin field effect pipe.
Further, the gas that the prosthetic treatment is used includes oxygen-containing gas so that gas-cluster ion There is oxonium ion, the oxonium ion can not only carry out physical bombardment to fin top and side wall, also in beam Can will fin top and sidewall surfaces oxidation, so as to be effectively improved removal repair layer after fin top and Sidewall surfaces flatness.
Further, the gas that the prosthetic treatment is used also includes Ar, N2Or He so that gas group In ion beam have Ar ions, N ions or He ions, the Ar ions, N ions or He from Son can carry out physical bombardment to fin top and side wall, so as to further improve fin top and side wall table Face flatness.
Brief description of the drawings
The cross-section structure of the fin field effect pipe forming process that Fig. 1 to Figure 10 is provided for one embodiment of the invention Schematic diagram.
Specific embodiment
From background technology, the electric property of the fin field effect pipe that prior art is formed has much room for improvement.
It has been investigated that, the interface performance between gate dielectric layer and fin in grid structure is poor, is to cause One of major reason for electric property difference in fin field effect pipe.
Therefore, the present invention provides a kind of forming method of fin field effect pipe, there is provided substrate, the substrate Surface is formed with some discrete fins, and the substrate surface is also formed with covering fin partial sidewall surface Separation layer, and the separation layer top less than fin top;Treatment is doped to the fin; Carry out after the doping treatment, fin top and side wall are entered using gas cluster ion beam technique The treatment of row prosthetic, repair layer is formed in the fin top surface and sidewall surfaces;Remove the reparation Layer;After the repair layer is removed, the grid structure of the fin, the grid structure are developed across Cover atop part surface and the sidewall surfaces of fin.The present invention formed grid structure before, using gas Body cluster ions beam technique carries out prosthetic treatment to fin top and side wall, forms repair layer, described to repair Renaturation process can improve fin top and sidewall surfaces roughness, described after repair layer is removed Fin has surface flatness higher, and the lattice that fin portion surface sustains damage is removed so that formed Grid structure and fin between there is good interface performance, the grid structure contacts closely with fin, So as to improve the electric property of the fin field effect pipe of formation.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings Specific embodiment of the invention is described in detail.
The cross-section structure of the fin field effect pipe forming process that Fig. 1 to Figure 10 is provided for one embodiment of the invention Schematic diagram.
With reference to Fig. 1, there is provided substrate 200 and some discrete fin 201 positioned at the surface of substrate 200.
The substrate 200 can be silicon substrate or be the silicon substrate on insulator, and the substrate 200 is also It can be the silicon substrate on germanium substrate, silicon-Germanium substrate, gallium arsenide substrate or insulator.The substrate 200 include first area I and second area II, first area I be NMOS area or PMOS area, Second area II is NMOS area or PMOS area.The present embodiment is with the fin field effect pipe for being formed As a example by cmos device, wherein, first area I is PMOS area, and second area II is nmos area Domain, the surface of first area I substrates 200 is formed with discrete fin 201, the second area II The surface of substrate 200 is formed with discrete fin 201.
The material of the fin 201 includes silicon, germanium, SiGe, carborundum or GaAs.The present embodiment In, the material of the fin 201 is identical with the material of substrate 200.
In one embodiment, forming the substrate 200 and the processing step of fin 201 includes:Carry For initial substrate;Patterned hard mask layer is formed in the initial substrate surface;With described patterned Hard mask layer is initial substrate described in mask etching, and the initial substrate after etching is used as substrate 200, substrate 200 surfaces are formed with some discrete fins 201.
The formation process of the patterned hard mask layer includes:Self-alignment duplex pattern (SADP, Self-aligned Double Patterned) triple graphical (the Self-aligned Triple of technique, autoregistration Patterned) technique or autoregistration quadruple are graphical (Self-aligned Double Double Patterned) Technique.The Dual graphing technique includes LELE (Litho-Etch-Litho-Etch) techniques or LLE (Litho-Litho-Etch) technique.
In the present embodiment, the processing step for forming the substrate 200 and fin 201 includes:There is provided just Beginning substrate;Some discrete sacrifice layers are formed in the initial substrate surface;Formation is covered in described initial The side wall film of substrate surface and sacrificial layer surface;The side wall film is etched back to, etching removal is located at sacrifices The side wall film of layer top surface and part initial substrate surface, forms the side wall layer of adjacent sacrifice layer side wall; Remove the sacrifice layer;Initial substrate described in the side wall layer as mask etching, forms some discrete Fin 201, the initial substrate after etching is used as substrate 200;Remove the side wall layer.
In the present embodiment, the bottom size of the fin 201 is more than top dimension, and the fin 201 has Inclined sidewall surfaces.In other embodiments, the fin sidewall surfaces are mutually perpendicular to substrate surface, The fin bottom size is identical with top dimension.
With continued reference to Fig. 1, the surface of substrate 200 between the adjacent fin 201 forms separation layer 202, The covering of the separation layer 202 fin 201 partial sidewall surface, and the separation layer 202 top surface Less than the top surface of fin 201.
The separation layer 202 is used for the follow-up isolation structure as fin field effect pipe, isolates adjacent area Fin 201, prevent that unnecessary electrical connection occurs between adjacent fin 201;The separation layer 202 Material is silica or silicon oxynitride.
Used as one embodiment, the processing step for forming the separation layer 202 includes:In the substrate 200 Surface and the surface of fin 201 form barrier film, and the top surface of the barrier film is higher than fin 201 Top surface;It is etched back to the barrier film and forms separation layer 202, and the top surface of separation layer 202 is less than fin The top surface of portion 201.
In the present embodiment, using mobility chemical vapor deposition method (FCVD, Flowable Chemical Vapor Deposition) form the barrier film so that and the separation layer 202 of formation is in substrate 200 and fin The filling effect of the corner between portion 201 is good.
With reference to Fig. 2, screen layer 203 is formed in the top surface of the fin 201 and sidewall surfaces.
In the present embodiment, the screen layer 203 is also located at the surface of separation layer 202.
The effect of the screen layer 203 includes:Play a part of to protect fin 201, prevent fin 201 Sustained damage during hard mask layer is subsequently formed, keep the characteristic size of fin 201 constant, from And improve the electric property of the fin field effect pipe for being formed.Also, subsequently carried out to part fin 201 During ion implantation technology, the screen layer 203 can also play a part of ion implanting cushion, it is to avoid Ion implantation technology causes implant damage to fin 201.Meanwhile, it is follow-up to include using cineration technics or wet Method degumming process removes the processing step of Other substrate materials, and the screen layer 203 can prevent fin 201 In cineration technics meeting wet method degumming process environment, it is to avoid fin 201 sustains damage.
Because rear extended meeting removes the screen layer 203, it is desirable to remove the technique of screen layer 203 to fin 201 Have no adverse effects, therefore the material of the screen layer 203 should be to be easy to removed material, and removal The technique of screen layer 203 has larger etching selection ratio to screen layer 203 and fin 201.Therefore, In the present embodiment, the material of the screen layer 203 is silica.
In order that the technique for forming screen layer 203 has no adverse effects or influences on the characteristic size of fin 201 It is small, it is to avoid or reduction forms the consumption that the technique of screen layer 203 is caused to the material of fin 201, using heavy Product technique forms the screen layer 203, and depositing operation provides the gas containing the material atom of fin 201 and makees It is main source gas, can greatly reduces the amount that oxygen source gas aoxidize the material of fin 201, reduces fin 201 The consumption of material.
In the present embodiment, the material of the fin 201 is silicon, then the main source gas that depositing operation is provided is Silicon source gas, the silicon source gas includes SiH4Or SiH2Cl2
The screen layer 203, the shielding are formed using chemical vapor deposition method or atom layer deposition process The thickness of layer 203 is 2 nanometers to 10 nanometers.
With reference to Fig. 3, the first doping treatment is carried out to the second area II fins 201.
First doping treatment is used for the electric property of the device for improving second area II formation, with first Doping treatment is that as a example by well region adulterates, the Doped ions of first doping treatment are N-type ion or p-type Ion.
First doping treatment is carried out using ion implantation technology.In the present embodiment, the second area II is NMOS area, and the Doped ions of first doping treatment are p-type ion, wherein, N-type from Son is B, Ga or In.
The processing step for carrying out first doping treatment includes:Form the fin of the covering first area I Top surface and first photoresist layer 204 on sidewall surfaces and the surface of separation layer 202;With first light Photoresist layer 204 is mask, and ion implanting is carried out to the second area II fins 202;Remove described One photoresist layer 204.In a specific embodiment, first doping is carried out using ion implantation technology The technological parameter for the treatment of includes:0~20 degree of implant angle scope, ion implantation concentration scope is 1E13atom/cm3~1E18/atom/cm3, Implantation Energy scope is 2Kev~20Kev.
With reference to Fig. 4, the second doping treatment is carried out to the first area I fins 201.
Second doping treatment is used for the electric property of the device for improving first area I formation, is mixed with second As a example by miscellaneous treatment is for well region doping, the Doped ions of second doping treatment for N-type ion or p-type from Son.
Second doping treatment is carried out using ion implantation technology.In the present embodiment, the first area I It is PMOS area, the Doped ions of first doping treatment are N-type ion, wherein, N-type ion It is P, As or Sb.
The processing step for carrying out second doping treatment includes:Form the fin of the covering second area II Portion's top surface and second photoresist layer 205 on sidewall surfaces and the surface of separation layer 202;With described second Photoresist layer 205 is mask, and ion implanting is carried out to the second area II fins 202;Removal is described Second photoresist layer 205.In a specific embodiment, described second is carried out using ion implantation technology to mix The technological parameter for living together reason includes:0~20 degree of implant angle scope, ion implantation concentration scope is 1E13atom/cm3~1E18/atom/cm3, Implantation Energy scope is 2Kev~20Kev.
With reference to Fig. 5, annealing 206 is carried out to the fin 201.
The effect of the treatment treatment 206 includes:On the one hand, the annealing 206 can be certain The lattice damage that abovementioned dopant treatment is caused to fin 201 is repaired in degree;On the other hand, the annealing Treatment 206 can also activate the Doped ions in fin 201 so that Doped ions enter in fin 201 Row concentration is redistributed.
Using laser annealing, Millisecond annealing or rapid thermal anneal process, the annealing 206 is carried out.
With reference to Fig. 6, the screen layer 203 (referring to Fig. 5) is removed.
The technique removal being combined using dry etching, wet etching or dry etching and wet etching is described Screen layer 203.
Used as one embodiment, the etch liquids of the wet-etching technology are hydrofluoric acid solution (DHF: Dilute HF), wherein, the volume ratio of hydrofluoric acid reclaimed water and hydrofluoric acid is 50:1 to 1000:1.
As another embodiment, using the dry etch process etching removal screen layer 203, pass through SiCoNi etching systems perform the dry etch process, and the etching gas of dry etch process include NH3 And HF, in certain embodiments, etching gas are removed includes NH3Outside HF, can also include lazy Property gas, such as N2, He or Ar.
Used as other embodiment, the technique being combined using dry etching and wet etching removes the shielding Layer 203, for example, first carrying out dry etch process then carries out wet-etching technology, to etch removal shielding Layer 203.
The wet-etching technology or dry etch process are very big to the etch rate of silica, and hardly Etching can be caused to silicon, therefore, the technique for removing screen layer 203 will not cause bad shadow to fin 201 Ring, after the screen layer 203 is removed, fin 201 still maintains good characteristic size.
Although the screen layer 203 being previously formed makes fin 201 be processed by abovementioned dopant to a certain extent Harmful effect reduce, but the top surface of the fin 201 and sidewall surfaces still have lattice damage, So that the top surface of fin 201 and sidewall surfaces performance are still poor, the top surface of fin 201 and side wall table Face is coarse, if follow-up directly form grid structure, the grid structure and fin on the surface of fin 201 Interface performance between 201 is poor.Therefore, the present embodiment is follow-up also being repaiied to the top of fin 201 and side wall Renaturation process, improve the top surface of fin 201 and sidewall surfaces performance.
With reference to Fig. 7, using gas cluster ion beam (GCIB, gas cluster ion beam) technique to institute Stating the top of fin 201 and side wall carries out prosthetic treatment, in the top surface of the fin 201 and side wall table Face forms repair layer 207.
The prosthetic treatment is suitable to improve the surface roughness of fin top and side wall.In the present embodiment, During carrying out prosthetic treatment using gas cluster ion beam technique, not only to the top of fin 201 and Sidewall surfaces carry out chemically (chemical) treatment, also carry out thing to the top of fin 201 and sidewall surfaces Rationality (physical) treatment, it is described chemically to process main including the top of fin 201 and sidewall surfaces Oxidation, the lattice defect at the top of fin 201 and sidewall surfaces is aoxidized, the physical treatment master To include carrying out physical bombardment (sputter) to the top of fin 201 and sidewall surfaces, especially to fin 201 The part of top and side wall protrusion carries out physical bombardment, so that convex in removing the top of fin 201 and side wall Go out part.By way of chemically processing and being combined with physical treatment, reach removal fin 201 in By the purpose that the surface of lattice damage removes, and the surface oxidation of fin 201 is formed into repair layer 207, made The surface roughness of fin 201 after repair layer 207 must be formed to be improved.
In the present embodiment, the gas that the prosthetic treatment is used includes oxygen-containing gas so that the gas of formation Contain oxonium ion in body cluster ions beam, on the one hand the oxonium ion can aoxidize the top surface of fin 201 And sidewall surfaces, on the other hand the oxonium ion can also carry out thing to the top of fin 201 and sidewall surfaces Reason bombardment.The oxygen-containing gas is O2、O3Or H2O。
The gas that the prosthetic treatment is used also includes Ar, N2Or He so that the cluster gas of formation Contain Ar ions, N ions or He ions, the Ar ions, N ions or He ions in ion beam Physical bombardment is carried out to the top surface of fin 201 and sidewall surfaces, the direction of the ion beam bombardment is vertical In the surface of substrate 200, so that the lattice that further bombardment removal fin 201 surface sustains damage, enters one Step improves the top of fin 201 and sidewall surfaces flatness.
In the present embodiment, the material of the fin 201 is silicon, and the material of the repair layer 207 is oxidation Silicon.The technological parameter for carrying out prosthetic treatment using gas cluster ion beam technique includes:Etching gas is provided Body and O2, Ar, N are also provided2Or one or more gas in He, etching gas be halogen, One or more chemical compound gas of composition in carbon, protium or nitrogen, etching gas air pressure More than or equal to 1 standard atmospheric pressure, etching gas form the ion beam of cluster gas by ionization, wherein, Ion beam accelerating field intensity is less than or equal to 100kv, and ion beam energy is less than or equal to 100kev, from Beamlet dosage is less than or equal to 1E17cluster/cm2
Wherein, etching gas are CH3F、CH3Cl、CH3Br、CHF3、CHClF2、CHBrF2、CH2F2、 CH2ClF、CH2BrF、CHCl2F、CHBrCl2、CHBr3In one in or it is various.
In the present embodiment, the thickness of the repair layer 207 is 0.5 nanometer to 1 nanometer so that fin 201 The defect that surface sustains damage is oxidized, and avoids the oxidized degree of fin 201 excessive.
With reference to Fig. 8, the repair layer 207 (referring to Fig. 7) is removed.
In order to avoid the technique for removing repair layer 207 causes to damage to the top surface of fin 201 and sidewall surfaces Wound, using the wet-etching technology etching removal repair layer 207.
In the present embodiment, the etch liquids that wet-etching technology is used are the hydrofluoric acid solution of dilution, dilution Hydrofluoric acid solution in the volume ratio of deionized water and hydrofluoric acid be 200:1 to 500:1, the etch liquids In hydrofluoric acid concentration it is relatively low so that wet-etching technology is small to the etch rate of separation layer 202, Separation layer 202 is avoided to be subject to unnecessary damage.
It is described to repair when carrying out prosthetic treatment using gas cluster ion beam technique in due to the present embodiment The environment of renaturation process is more gentle, and gas cluster ion beam will not even to the damage very little of fin 201 The surface of fin 201 is caused to damage so that after the repair layer 207 is removed, the surface of fin 201 With lattice quality and surface flatness higher higher.This embodiment avoids plasma to fin The lattice damage that portion causes.
After the repair layer 207 is removed, also including step:To the top surface of the fin 201 and Sidewall surfaces carry out cleaning treatment, further provide good interface basis to be subsequently formed grid structure.
It is follow-up also to include step:The grid structure of the fin 201 is developed across, the grid structure covers The atop part and sidewall surfaces of lid fin 201.Specifically, the formation process of the grid structure includes Following steps:Formed in the top surface of the fin 201 and sidewall surfaces and the surface of separation layer 202 Gate dielectric film;Gate electrode film is formed on the gate dielectric film surface;The graphical gate electrode film and grid Deielectric-coating, forms the grid structure.The forming step of grid structure is carried out in detail below with reference to accompanying drawing Describe in detail bright.
With reference to Fig. 9, in the top surface of the fin 201 and sidewall surfaces and the surface shape of separation layer 202 Into gate dielectric film 208.
The gate dielectric film 208 provides Process ba- sis for the gate dielectric layer being subsequently formed in grid structure.By Repaired in the lattice damage of the top surface of fin 201 and sidewall surfaces, the top of the fin 201 and Sidewall surfaces roughness is improved, therefore, gate dielectric film 208 and fin 201 that the present embodiment is formed Between interface performance it is good, the gate dielectric film 208 is contacted closely with fin 201.
The material of the gate dielectric film 208 is silica, silicon nitride or high-k gate dielectric material, k grid high Dielectric material refers to material of the relative dielectric constant more than silica relative dielectric constant, high-k gate dielectric Material include LaO, AlO, BaZrO, HfZrO, HfZrON, HfLaO, HfSiO, HfSiON, LaSiO、AlSiO、HfTaO、HfTiO、Al2O3Or Si3N4
In the present embodiment, the material of the gate dielectric film 208 is Al2O3, using physical gas-phase deposition Form the gate dielectric film 208.
With continued reference to Fig. 9, gate electrode film 209 is formed on the surface of the gate dielectric film 208.
The gate electrode film 209 provides Process ba- sis to be subsequently formed gate electrode layer.
The material of the gate electrode film 209 include polysilicon, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN or WSi.
In the present embodiment, the material of the gate electrode film 209 is Al.
With reference to Figure 10, the graphical gate electrode film 209 (referring to Fig. 9) forms gate electrode layer 219;Figure Gate dielectric film 208 (referring to Fig. 9) described in shape forms gate dielectric layer 218.
Specifically, forming graph layer on the surface of the gate electrode film 209;With the graph layer as mask, Etching removal is positioned at the surface of part separation layer 202 and the gate electrode film 209 on the surface of part fin 201 And gate dielectric film 208;Remove the graph layer.
Wherein, gate dielectric layer 218 and the gate electrode layer 219 positioned at gate dielectric layer 218 top surface Laminated construction constitutes grid structure, and the grid structure also covers across the fin 201, the grid structure The atop part surface of lid fin 201 and sidewall surfaces.
It is follow-up also to include step:Fin 201 to the grid structure both sides is doped treatment, in grid Source region is formed in the fin 201 of pole structure side, leakage is formed in the fin 201 of grid structure opposite side Area.
Because before grid structure is formed, the top surface of the fin 201 and sidewall surfaces are with higher Flatness, the roughness of the top of the fin 201 and side wall improved so that in grid structure Interface performance between gate dielectric layer 218 and fin 201 is good, and the grid structure connects with fin 201 Touch tight, so that the electric property of the fin field effect pipe for being formed is improved.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore guarantor of the invention Shield scope should be defined by claim limited range.

Claims (18)

1. a kind of forming method of fin field effect pipe, it is characterised in that including:
Substrate is provided, the substrate surface is formed with some discrete fins, and the substrate surface is also formed There are the separation layer on covering fin partial sidewall surface, and separation layer top less than fin top;
Treatment is doped to the fin;
After the doping treatment is carried out, using gas cluster ion beam technique to the fin top and Side wall carries out prosthetic treatment, and repair layer is formed in the fin top surface and sidewall surfaces;
Remove the repair layer;
After the repair layer is removed, the grid structure of the fin, the grid structure are developed across Cover atop part surface and the sidewall surfaces of fin.
2. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that at the prosthetic Reason is suitable to improve the surface roughness of fin top and side wall.
3. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that at the prosthetic Managing the gas for using includes oxygen-containing gas.
4. the forming method of fin field effect pipe as claimed in claim 3, it is characterised in that the oxygen-containing gas It is O2、O3Or H2O。
5. the forming method of fin field effect pipe as claimed in claim 3, it is characterised in that at the prosthetic Managing the gas for using also includes Ar, N2Or He.
6. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the cluster gas The technological parameter of ion beam technology includes:Etching gas and O are provided2, Ar, N are also provided2Or He In one or more gas, etching gas be halogen, carbon, protium or nitrogen in One or more composition chemical compound gas, etching gas air pressure be more than or equal to 1 standard atmospheric pressure, Etching gas form the ion beam of cluster gas by ionization, wherein, ion beam accelerating field intensity is small In or equal to 100kv, ion beam energy is less than or equal to 100kev, and ion beam dose is less than or equal to 1E17cluster/cm2
7. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the material of the fin Expect to be silicon;The material of the repair layer is silica.
8. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the repair layer Thickness is 0.5 nanometer to 1 nanometer.
9. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that use wet etching Technique, removes the repair layer.
10. the forming method of fin field effect pipe as claimed in claim 9, it is characterised in that the wet etching The etch liquids that technique is used are the hydrofluoric acid solution of dilution, deionized water in the hydrofluoric acid solution of dilution It is 200 with the volume ratio of hydrofluoric acid:1 to 500:1.
The forming method of 11. fin field effect pipes as claimed in claim 1, it is characterised in that to the fin Before being doped treatment, screen layer is formed in the fin top surface and sidewall surfaces;Carry out Before the prosthetic treatment, removal is positioned at fin top surface and the screen layer of sidewall surfaces.
The forming method of 12. fin field effect pipes as claimed in claim 11, it is characterised in that use atomic layer deposition Product technique forms the screen layer.
The forming method of 13. fin field effect pipes as claimed in claim 11, it is characterised in that the screen layer Material is silica or silicon oxynitride.
The forming method of 14. fin field effect pipes as claimed in claim 1, it is characterised in that use ion implanting Technique carries out the doping treatment;The Doped ions of the doping treatment are N-type ion or p-type ion.
The forming method of 15. fin field effect pipes as claimed in claim 1, it is characterised in that repaiied described in removal After cladding, before the formation grid structure, also including step:To the fin top surface and Sidewall surfaces carry out cleaning treatment.
The forming method of 16. fin field effect pipes as claimed in claim 1, it is characterised in that the grid structure Including gate dielectric layer and the gate electrode layer positioned at gate dielectric layer surface.
The forming method of 17. fin field effect pipes as claimed in claim 16, it is characterised in that form the grid The processing step of structure includes:In the fin top surface and sidewall surfaces and insulation surface Form gate dielectric film;Gate electrode film is formed on the gate dielectric film surface;The graphical gate electrode film And gate dielectric film, form the grid structure.
The forming method of 18. fin field effect pipes as claimed in claim 1, it is characterised in that the substrate includes First area and second area, wherein, first area is NMOS area or PMOS area, second Region is NMOS area or PMOS area.
CN201510894258.5A 2015-12-07 2015-12-07 The forming method of fin field effect pipe Pending CN106847695A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510894258.5A CN106847695A (en) 2015-12-07 2015-12-07 The forming method of fin field effect pipe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510894258.5A CN106847695A (en) 2015-12-07 2015-12-07 The forming method of fin field effect pipe

Publications (1)

Publication Number Publication Date
CN106847695A true CN106847695A (en) 2017-06-13

Family

ID=59151398

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510894258.5A Pending CN106847695A (en) 2015-12-07 2015-12-07 The forming method of fin field effect pipe

Country Status (1)

Country Link
CN (1) CN106847695A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216198A (en) * 2017-06-30 2019-01-15 台湾积体电路制造股份有限公司 Gate stack structure and forming method thereof
CN110890279A (en) * 2018-09-11 2020-03-17 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN112802736A (en) * 2019-11-14 2021-05-14 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020014407A1 (en) * 2000-07-10 2002-02-07 Allen Lisa P. System and method for improving thin films by gas cluster ion beam processing
CN102104069A (en) * 2009-12-16 2011-06-22 中国科学院微电子研究所 Fin type transistor structure and manufacturing method thereof
CN104752222A (en) * 2013-12-31 2015-07-01 中芯国际集成电路制造(上海)有限公司 Forming method of fin type field effect transistor
CN105097533A (en) * 2014-05-12 2015-11-25 中芯国际集成电路制造(上海)有限公司 Forming method of semiconductor structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020014407A1 (en) * 2000-07-10 2002-02-07 Allen Lisa P. System and method for improving thin films by gas cluster ion beam processing
CN102104069A (en) * 2009-12-16 2011-06-22 中国科学院微电子研究所 Fin type transistor structure and manufacturing method thereof
CN104752222A (en) * 2013-12-31 2015-07-01 中芯国际集成电路制造(上海)有限公司 Forming method of fin type field effect transistor
CN105097533A (en) * 2014-05-12 2015-11-25 中芯国际集成电路制造(上海)有限公司 Forming method of semiconductor structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216198A (en) * 2017-06-30 2019-01-15 台湾积体电路制造股份有限公司 Gate stack structure and forming method thereof
CN109216198B (en) * 2017-06-30 2022-03-29 台湾积体电路制造股份有限公司 Gate stack structure and forming method thereof
CN110890279A (en) * 2018-09-11 2020-03-17 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN110890279B (en) * 2018-09-11 2023-09-15 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN112802736A (en) * 2019-11-14 2021-05-14 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Similar Documents

Publication Publication Date Title
US10269927B2 (en) Semiconductor structures and fabrication methods thereof
TWI415263B (en) Semiconductor device and method for fabricating thereof
CN103855093B (en) Semiconductor device and method for manufacturing the same
CN107785422B (en) Semiconductor structure and manufacturing method thereof
US11387149B2 (en) Semiconductor device and method for forming gate structure thereof
WO2014082334A1 (en) Method for manufacturing semiconductor device
US20190259671A1 (en) Fin field-effect transistor
CN108010884A (en) Semiconductor structure and forming method thereof
CN106847683A (en) The method for improving fin field effect pipe performance
CN107346783A (en) Semiconductor structure and its manufacture method
CN106952908A (en) Semiconductor structure and its manufacture method
CN105226023A (en) The formation method of semiconductor device
CN108630548B (en) Fin type field effect transistor and forming method thereof
WO2014082342A1 (en) P-type mosfet and manufacturing method thereof
WO2014082337A1 (en) Semiconductor device and manufacturing method thereof
CN103855008A (en) N-type MOSFET and manufacturing method thereof
US10269972B2 (en) Fin-FET devices and fabrication methods thereof
CN106847695A (en) The forming method of fin field effect pipe
CN109087887B (en) Semiconductor structure and forming method thereof
CN106653692A (en) Method for manufacturing semiconductor device
CN106847874A (en) The forming method of the semiconductor devices with different threshold voltages
CN106876335A (en) The manufacture method of semiconductor structure
CN107481932B (en) Method for manufacturing semiconductor structure
CN107293489A (en) Improve the method for fin field effect pipe performance
WO2014082331A1 (en) Method for manufacturing p-type mosfet

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20170613