CN107293489A - Improve the method for fin field effect pipe performance - Google Patents
Improve the method for fin field effect pipe performance Download PDFInfo
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- CN107293489A CN107293489A CN201610208067.3A CN201610208067A CN107293489A CN 107293489 A CN107293489 A CN 107293489A CN 201610208067 A CN201610208067 A CN 201610208067A CN 107293489 A CN107293489 A CN 107293489A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
A kind of method of improvement fin field effect pipe performance, including：Covering substrate surface and the separation layer of fin sidewall surfaces are formed, the separation layer exposes the fin of first thickness；Fin higher than separation layer is made annealing treatment, the annealing is suitable to the round and smooth degree for improving the fin top corner, wherein, the annealing is containing H2Atmosphere under carry out；After the annealing is carried out, the separation layer formation isolation structure of second thickness is removed；After the isolation structure is formed, oxidation processes are carried out to the fin higher than isolation structure, at the top of fin and sidewall surfaces formation oxide layer.The present invention improves the round and smooth degree in fin top corner region by making annealing treatment, so that the oxidated layer thickness uniformity formed is improved, the width dimensions of fin bottom are also avoided to become big simultaneously, therefore the reliability and electric property of the fin field effect pipe formed are improved.
Description
Technical field
It is more particularly to a kind of to improve fin field effect pipe performance the present invention relates to technical field of manufacturing semiconductors
Method.
Background technology
With continuing to develop for semiconductor process technique, semiconductor technology node follows the development of Moore's Law
Trend constantly reduces.In order to adapt to the reduction of process node, it has to constantly shorten MOSFET field-effects
The channel length of pipe.Tube core density of the shortening with increase chip of channel length, increases MOSFET
The benefits such as the switching speed of effect pipe.
However, with the shortening of device channel length, the distance between device source electrode and drain electrode also shortens therewith,
So grid is deteriorated to the control ability of raceway groove so that sub-threshold leakage (subthreshold leakage)
Phenomenon, i.e., so-called short-channel effect (SCE：Short-channel effects) it is easier to occur.
Therefore, in order to preferably adapt to the requirement that device size is scaled, semiconductor technology is gradually opened
The transistor transient begun from planar MOSFET transistor to the three-dimensional with more high effect, such as fin
Formula FET (FinFET).In FinFET, grid at least can be from both sides to ultra-thin body (fin)
It is controlled, can be very with the grid more much better than than planar MOSFET devices to the control ability of raceway groove
Good suppression short-channel effect；And FinFET is relative to other devices, with more preferable existing integrated electricity
The compatibility of road manufacturing technology.
However, the electric property of the fin field effect pipe of prior art formation has much room for improvement.
The content of the invention
The problem of present invention is solved is to provide a kind of method of improvement fin field effect pipe performance, improves fin
Top corner round and smooth degree, so as to improve the performance of the fin field effect pipe of formation.
To solve the above problems, the present invention provides a kind of method of improvement fin field effect pipe performance, including：
Substrate is provided, the substrate surface is formed with discrete fin；Form the covering substrate surface and fin
Less than at the top of fin at the top of the separation layer of portion's sidewall surfaces, the separation layer, the separation layer exposes the
The fin of one thickness；The fin higher than separation layer is made annealing treatment, the annealing is suitable to
The round and smooth degree of the fin top corner is improved, wherein, the annealing is containing H2Atmosphere under enter
OK；After the annealing is carried out, the separation layer formation isolation structure of second thickness is removed；In shape
Into after the isolation structure, oxidation processes are carried out to the fin higher than isolation structure, in fin
Top and sidewall surfaces formation oxide layer.
Optionally, the annealing temperature of the annealing is 300 DEG C~500 DEG C.
Optionally, in the technique made annealing treatment, H2Flow is 1sccm~1000sccm.
Optionally, the first thickness is 0.5nm~5nm.
Optionally, the second thickness is 5nm~50nm.
Optionally, before the separation layer is formed, the fin top surface is formed with hard mask layer.
Optionally, forming the processing step of the separation layer includes：Form the covering substrate surface, fin
It is higher than hard mask layer top at the top of portion's sidewall surfaces and the barrier film on hard mask layer surface, the barrier film
Portion；Remove higher than the barrier film at the top of the hard mask layer；Then, the hard mask layer is removed；Remove
The barrier film of segment thickness forms the separation layer.
Optionally, the formation process of the barrier film includes：Using mobility chemical vapor deposition method shape
Into forerunner's barrier film；Annealing curing process is carried out to forerunner's barrier film, forerunner's barrier film is converted into
Barrier film.
Optionally, before the barrier film is formed, in the substrate surface and fin sidewall surfaces shape
Linear oxide layer；While the barrier film of segment thickness is removed, also remove linear higher than separation layer
Oxide layer.
Optionally, the material of the liner oxidation layer is silica.
Optionally, the oxidation processes are dry-oxygen oxidation, steam oxidation or wet-oxygen oxidation.
Optionally, the oxidation processes are carried out using steam in situ generation oxidation technology, technological parameter includes：
Reacting gas includes O2、H2And H2O, wherein, O2Flow is 0.1slm to 20slm, H2Flow is
0.1slm to 20slm, H2O flows are 0.1slm to 50slm, and reaction chamber temperature is 650 degree to 1000
Degree, reaction chamber pressure be 0.1 support to 760 supports, a length of 5 seconds to 10 points during reaction.
Optionally, the material of the oxide layer is silica.
Optionally, in addition to step：In the oxidation layer surface formation high-k gate dielectric layer；In the high k
Gate dielectric layer surface forms gate electrode layer.
Optionally, the substrate includes core device region and input and output device area, wherein, core devices
Area's substrate surface is formed with fin, and input and output device area substrate surface is formed with fin；It is described being formed
After oxide layer, in addition to step：Remove the oxide layer of the core device region；In the core devices
The fin portion surface in area forms pseudo- oxide layer, and the thickness of the pseudo- oxide layer is less than the thickness of oxide layer；Institute
State oxidation layer surface and pseudo- oxidation layer surface forms pseudo- gate layer；The shape in the fin of the pseudo- gate layer both sides
Into source-drain electrode；Interlayer dielectric layer is formed on the source-drain electrode surface, the interlayer dielectric layer also covers pseudo- grid
Layer sidewall surfaces；Etching removes the pseudo- gate layer；Etching removes the pseudo- oxide layer, exposes core device
Part area fin portion surface；In core device region fin portion surface formation boundary layer, the interfacial layer thickness is small
In oxidated layer thickness.
Optionally, in addition to：In the interface layer surfaces and oxidation layer surface formation gate electrode layer.
Optionally, in addition to：In the interface layer surfaces and oxidation layer surface formation high-k gate dielectric layer；
In high-k gate dielectric layer surface formation gate electrode layer.
Compared with prior art, technical scheme has advantages below：
In the technical scheme for the improvement fin field effect pipe performance that the present invention is provided, in substrate surface and fin
Side wall formation separation layer, the separation layer exposes the fin of first thickness；Then, to higher than separation layer
Fin made annealing treatment, the annealing is carried out under the atmosphere containing H2, and at the annealing
Reason is suitable to the round and smooth degree for improving fin top corner so that subsequently at the top of fin with the oxidation of side wall formation
Layer thickness homogeneity is improved；Then remove second thickness separation layer formation isolation structure, to higher than
The fin of isolation structure carries out oxidation processes, because fin top corner round and smooth degree is improved so that fin
Portion's top corner no longer has region of stress concentration, therefore oxidation of the oxidation processes to fin top and side wall
Speed is identical or close, and the thickness evenness for the oxide layer being correspondingly formed is improved, and improves the fin formed
The reliability and electric property of formula FET.
Further, the first thickness for the fin that the separation layer exposes is 0.5nm~5nm, is only exposed
Need to carry out at the top of the fin of round and smoothization, and the fin side wall of most of thickness is isolated layer covering, therefore
Annealing will not be undergone by being isolated the fin of layer covering, so that being isolated the width of the fin of layer covering
Spend characteristic size and keep constant.
Brief description of the drawings
The cross-section structure for the fin field effect pipe forming process that Fig. 1 to Figure 10 provides for one embodiment of the invention
Schematic diagram.
Embodiment
From background technology, the electric property of the fin field effect pipe of prior art formation has much room for improvement.
The gate dielectric layer of fin field effect pipe includes the oxide layer of covering fin top surface and sidewall surfaces,
The quality of the oxide layer has important influence to the performance of fin field effect pipe.It has been investigated that, fin
There is corner region (corner), the corner region is fin top surface and sidewall surfaces at the top of portion
There is certain stress (stress) in juncture area, the corner region.It is common, using oxidation technology pair
Fin top surface and sidewall surfaces carry out oxidation processes, form the oxide layer.However, due to by
The influence of the corner region stress, oxidation processes are smaller to the fin oxidation rate of the corner region,
So as to cause the thinner thickness of the oxide layer of corner region formation.
Because the oxidated layer thickness of corner region formation is relatively thin, the reliability of fin field effect pipe is proposed compared with
Big challenge, for example, Gate Oxide Integrity (GOI, Gate Oxide Integrity), dielectric and when
Between related breakdown performance (TDDB, Time Dependent Dielectric Breakdown), positive temperature-no
Stability characteristic (quality) (PBTI, Positive Bias Temperature Instability) or negative temperature-unstable characteristic
One or more in (NBTI, Negative Bias Temperature Instability) have undesirable effect.
This problem is more notable for input and output (IO, Input or Output) device.
To solve the above problems, the present invention provides a kind of method of improvement fin field effect pipe performance, including：
Substrate is provided, the substrate surface is formed with discrete fin；Form the covering substrate surface and fin
Less than at the top of fin at the top of the separation layer of portion's sidewall surfaces, the separation layer, the separation layer exposes the
The fin of one thickness；The fin higher than separation layer is made annealing treatment, the annealing is suitable to
The round and smooth degree of the fin top corner is improved, wherein, the annealing is containing H2Atmosphere under enter
OK；After the annealing is carried out, the separation layer formation isolation structure of second thickness is removed；In shape
Into after the isolation structure, oxidation processes are carried out to the fin higher than isolation structure, in fin
Top and sidewall surfaces formation oxide layer.The method that the present invention is provided, to being made annealing treatment at the top of fin
Make fin top corner round and smoothization, improve the round and smooth degree of fin top corner, therefore at the top of the fin
It can be improved with the thickness evenness of the oxide layer of sidewall surfaces formation, so as to improve the fin of formation
The performance of FET.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
The cross-section structure signal for the fin field effect pipe forming process that Fig. 1 to Figure 10 provides for an embodiment
Figure.
With reference to Fig. 1 there is provided substrate 101, the surface of substrate 101 is formed with discrete fin 102.
In the present embodiment, input and output device and core devices (Core are included with the fin field effect pipe of formation
Device exemplified by).The substrate 101 includes core device region I and input and output device area II, wherein,
Core device region I provides technique platform to be subsequently formed core devices, and input and output device area II is follow-up
Form input and output device and technique platform is provided, wherein, input and output device is entering apparatus or follower
One or both of part.In the present embodiment, the core device region I and input and output device area II phases
Neighbour, in other embodiments, the core device region can also be separated by with input and output device area.
The material of the substrate 101 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium, institute
It can also be the silicon substrate on insulator or the germanium substrate on insulator to state substrate 101；The fin 102
Material include silicon, germanium, SiGe, carborundum, GaAs or gallium indium.It is described in the present embodiment
Substrate 101 is silicon substrate, and the material of the fin 102 is silicon.
In the present embodiment, forming the substrate 101, the processing step of fin 102 includes：Initial lining is provided
Bottom；Patterned hard mask layer 103 is formed in the initial substrate surface；It is with the hard mask layer 103
Initial substrate after initial substrate described in mask etching, etching is as substrate 101, positioned at the surface of substrate 101
Projection be used as fin 102.
In one embodiment, forming the processing step of the hard mask layer 103 includes：It is initially formed just
Begin hard mask；Patterned photoresist layer is formed in the initial hard mask surface；With described patterned
Photoresist layer is initial hard mask described in mask etching, in initial substrate surface formation hard mask layer 103；Go
Except the patterned photoresist layer.In other embodiments, the formation process of the hard mask layer can also
Enough include：Self-alignment duplex pattern (SADP, Self-aligned Double Patterned) technique, from
Alignment triple graphical (Self-aligned Triple Patterned) techniques or autoregistration quadruple are graphical
(Self-aligned Double Double Patterned) technique.The Dual graphing technique includes LELE
(Litho-Etch-Litho-Etch) technique or LLE (Litho-Litho-Etch) technique.
In the present embodiment, after the fin 102 is formed, retain positioned at the top surface of fin 102
Hard mask layer 103.The material of the hard mask layer 103 is silicon nitride, subsequently when carrying out flatening process,
The top surface of hard mask layer 103 can as flatening process stop position, play protection fin
The effect at 102 tops.
In the present embodiment, the top dimension of the fin 102 is less than bottom size.In other embodiments,
The side wall of the fin can also be perpendicular with substrate surface, i.e., the top dimension of fin is equal to bottom size.
The round and smooth degree in the top corner region of fin 102 is poor, in one embodiment, the fin 102
Top corner is in close to 90 degree so that the stress of the corner region is more concentrated.
With reference to Fig. 2, oxidation processes are carried out to the surface of fin 102, in the surface of substrate 100 and fin
The sidewall surfaces formation liner oxidation layer of portion 102 104.
Because fin 102 is to be formed by etching after initial substrate, the fin 102 generally has protrusion
Corner angle and surface has defect.The present embodiment carries out oxidation processes formation liner oxidation layer to fin 102
104, in oxidation processes, because the specific surface area of the faceted portions of the protrusion of fin 102 is bigger, more
It is oxidized easily, after subsequently removing liner oxidation layer 104, the not only defect on the surface of fin 102
Layer is removed, and protrusion faceted portions are also removed, and make that the surface of fin 102 is smooth, lattice quality is obtained
To improvement, it is to avoid the point discharge problem of fin 102.Also, the liner oxidation layer 104 formed is also favourable
Interface performance between the separation layer and fin 102 that raising is subsequently formed.
The oxidation processes can be using the mixed of oxygen plasma oxidation technology or sulfuric acid and hydrogen peroxide
Close solution oxide technique.The oxidation processes can also be aoxidized to the surface of substrate 101 so that formation
Liner oxidation layer 104 is also located at the surface of substrate 101.
In the present embodiment, using ISSG (steam in situ is generated, In-situ Stream Generation) oxidation
Technique carries out oxidation processes to fin 102, the liner oxidation layer 104 is formed, due to the material of fin 102
The material for expecting the liner oxidation layer 104 for silicon, being correspondingly formed is silica.
The oxidation processes are the processing of turning sphering, however, after the oxidation processes are carried out, it is described
The corner region of fin 102 still has certain stress.
With reference to Fig. 3, the covering surface of substrate 101, the sidewall surfaces of fin 102 and hard mask are formed
The barrier film 105 on 103 surface of layer, the top of barrier film 105 is higher than the top of hard mask layer 103；Then,
The barrier film 105 higher than the top of hard mask layer 103 is removed, makes the top of barrier film 105 with covering firmly
The top of film layer 103 is flushed.
In the present embodiment, also barrier film 105 is formed on 104 surface of liner oxidation layer.
The barrier film 105 provides Process ba- sis to be subsequently formed isolation structure；The barrier film 105
Material is insulating materials, for example, silica, silicon nitride or silicon oxynitride.In the present embodiment, it is described every
Material from film 105 is silica.
In order to improve filling perforation (gap-filling) ability to form the technique of barrier film 105, using mobility
Vapour deposition (FCVD, Flowable CVD) or high vertical width are learned than chemical vapor deposition method (HARP
CVD), the barrier film 105 is formed.In a specific embodiment, the formation of the barrier film 105
Technique includes：Using mobility chemical vapor deposition method formation forerunner's barrier film；The forerunner is isolated
Film carries out annealing curing process, and forerunner's barrier film is converted into barrier film 105.
In the present embodiment, using chemical mechanical milling tech, grinding is removed higher than the top of hard mask layer 103
Barrier film 105, until the top of remaining barrier film 105 at the top of hard mask layer 103 with flushing.
With reference to Fig. 4, the hard mask layer 103 (referring to Fig. 3) is removed.
Using wet-etching technology, etching removes the hard mask layer 103.
In the present embodiment, the material of the hard mask layer 103 is silicon nitride, and etching removes hard mask layer 103
The etch liquids used is phosphoric acid solutions.
With reference to Fig. 5, the barrier film 105 (referring to Fig. 4) of segment thickness is removed, the covering substrate is formed
101 surfaces and the separation layer 106 of the sidewall surfaces of fin 102, the top of separation layer 106 are less than fin
102 tops, the separation layer 106 exposes the fin 102 of first thickness.
The effect of the separation layer 106 includes：On the one hand, it subsequently may proceed to etching and remove segment thickness
Separation layer 106 is to form isolation structure；On the other hand, the covering of separation layer 106 fin 102 is big
Partial sidewall surface, only the fin 102 of first thickness is exposed, therefore is isolated layer 106 and covers
The influence that is produced from follow-up annealing of the side wall of fin 102, so as to ensure the width of fin 102
Characteristic size will not become big.
The first thickness is unsuitable excessive, otherwise subsequently exposed to the fin 102 made annealing treatment in environment
Thickness is excessive, causes while 102 top corner round and smooth degree of fin is improved, to also result in thicker fin
102 width characteristics become large-sized, and influence the performance of fin field effect pipe.Therefore, in the present embodiment, institute
First thickness is stated for 0.5nm~5nm.
Mutually tied with wet-etching technology using dry etch process, wet-etching technology or dry etch process
The technique of conjunction, etching removes the barrier film 105 of segment thickness.
In the present embodiment, the barrier film 105 for removing segment thickness is etched using wet-etching technology, wet method is carved
The etch liquids that etching technique is used is hydrofluoric acid solutions.
During the barrier film 105 of segment thickness is removed, also etching removes partial linear oxide layer 104,
Remove the liner oxidation layer 104 higher than separation layer 106.
With reference to Fig. 6, annealing 107 is carried out to the fin 102 higher than separation layer 106, it is described to move back
Fire processing 107 is suitable to the round and smooth degree for improving the top corner of fin 102, wherein, the annealing
Containing H2Atmosphere carry out.
During the annealing 107, the silicon atom positioned at the top corner region of fin 102 occurs
Migrate, the general trend that migratory direction occurs for the silicon atom positioned at the top corner region of fin 102 is
Moved to the surface direction of substrate 101.Therefore, the annealing 107 can improve the top of fin 102
The round and smooth degree at turning, the effect to top corner round and smoothization (corner rounding) of fin 102 is good.
In H2Atmosphere under carry out annealing and 107 can improve the round and smooth degree of the top corner of fin 102,
Its mechanism of action is complex.As one kind explanation, masterpiece is answered due to the top corner region of fin 102
With larger so that the silicon atom dangling bonds in the top corner region of fin 102 are more, therefore, carried in the external world
When supplying the enough energy of silicon atom in fin 102 top corner region, silicon atom can shake off Si-Si bond
Constraint, as free silicon atom, free silicon atom is under self gravitation effect to the surface of substrate 101
Move in direction.
If the annealing temperature of the annealing 107 is too low, the silicon in the top corner region of fin 102 is former
The energy that son is obtained is relatively low, and silicon atom, which is difficult to obtain, can shake off the energy of chemical bond constraint；At the annealing
Also unsuitable too high, the otherwise migration of the silicon atom in the top corner region of fin 102 of the annealing temperature of reason 107
Distance will increase, and cause the width characteristics of fin 102 to become large-sized.Therefore, in the present embodiment, it is described
The annealing temperature of annealing 107 is 300 DEG C~500 DEG C.
In a specific embodiment, the technological parameter of the annealing 107 includes：H2Flow is
1sccm~1000sccm, annealing temperature is 300 DEG C~500 DEG C.
During annealing 107, covered because the side wall of most of fin 102 is isolated layer 106,
So that be isolated layer 106 covering fin 102 be not exposed to annealing 107 environment in so that by every
Silicon atom in the fin 102 that absciss layer 106 is covered will not be migrated, so as to avoid the bottom of fin 102
Width characteristics become large-sized.
With reference to Fig. 7, after the annealing is carried out, (the reference of separation layer 106 of second thickness is removed
Fig. 6) form isolation structure 108.
The isolation structure 108 plays a part of electric isolation.In the present embodiment, the second thickness is
5nm~50nm.
Mutually tied using wet-etching technology, dry etch process or wet-etching technology or dry etch process
The etching technics of conjunction, etching removes the separation layer 106 of second thickness.
In the present embodiment, using wet-etching technology, etching removes the separation layer 106 of second thickness, described
The etch liquids of wet-etching technology are hydrofluoric acid solution.
With reference to Fig. 8, after the isolation structure 108 is formed, to the fin higher than isolation structure 108
Portion 102 carries out oxidation processes, at the top of fin 102 and sidewall surfaces formation oxide layer 109.
The oxidation processes are dry-oxygen oxidation, steam oxidation or wet-oxygen oxidation.In the present embodiment, using original
Position steam generation oxidation technology carries out the oxidation processes, and technological parameter includes：Reacting gas includes O2、
H2And H2O, wherein, O2Flow is 0.1slm to 20slm, H2Flow is 0.1slm to 20slm, H2O
Flow is 0.1slm to 50slm, and reaction chamber temperature is 650 degree to 1000 degree, and reaction chamber pressure is
0.1 support is to 760 supports, a length of 5 seconds to 10 points during reaction.
Because foregoing annealing causes the round and smooth degree of the top corner of fin 102 to be improved, therefore fin
The stress of the top corner of portion 102 reduces so that oxidation processes are to the top of fin 102 and the oxygen of side wall
Change speed is identical or differs very little, so that the thickness evenness of the oxide layer 109 formed is good, it is to avoid
The problem of in the prior art fin corner region oxidated layer thickness is thin, and then it is complete to improve grid oxic horizon
Property, improve TDDB effects, NBTI effects or PBTI effects, improve the fin field effect pipe that is formed
Reliability and electric property.
In the present embodiment, the material of the oxide layer 109 is silica, the thickness of the oxide layer 109
For 10 angstroms to 30 angstroms.
In the present embodiment, the fin field effect pipe of formation includes input and output device and core devices, described
Oxide layer 109 is used as a part for gate dielectric layer in input and output device, rear extended meeting removal core device region I
Oxide layer 109, retain input and output device area II oxide layer 109, the I shapes again in core device region
Into the thin boundary layer of thickness ratio oxide layer 109.
With reference to Fig. 9, etching removes the oxide layer 109 positioned at core device region I；Then, in the core
The device region I surface of fin 102 forms pseudo- oxide layer 110.
In the present embodiment, the oxide layer removed positioned at core device region I is etched using SiCoNi etching systems
109。
The material of the pseudo- oxide layer 110 is silica, during subsequent etching removes pseudo- gate layer,
The pseudo- oxide layer 110 plays a part of protecting core device region I fins 102.In the present embodiment, use
Oxidation technology forms the pseudo- oxide layer 110.
With reference to Figure 10, on the surface of oxide layer 109 and core device region of the input and output device area II
The I surface of pseudo- oxide layer 110 forms pseudo- grid film；Second graph layer is formed on the pseudo- grid film surface (not scheme
Show)；With second graph layer for mask, the graphical pseudo- grid film forms pseudo- gate layer 112.
In the present embodiment, formed after and gate electrode layer (high k last metal are formed after high-k gate dielectric layer
Gate last) technique.The material of the pseudo- gate layer 112 is polysilicon, amorphous carbon or non-crystalline silicon；It is described
Pseudo- gate layer 112 takes up space position for the actual gate structure of fin field effect pipe.
In the present embodiment, the material of the pseudo- gate layer 112 is polysilicon.
Follow-up processing step includes：Processing is doped to the fin 102 of the pseudo- both sides of gate layer 112,
Source-drain electrode is formed in the fin 102；Interlayer dielectric layer, the layer are formed on the source-drain electrode surface
Between the pseudo- sidewall surfaces of gate layer 112 of dielectric layer covering；Etching removes the pseudo- gate layer 112；Etching removes described
Pseudo- oxide layer 110；Boundary layer, the boundary layer are formed on the surface of fin 102 of the core device region I
Thickness be less than oxide layer 109 thickness；Form the covering interface layer surfaces and the table of oxide layer 109
The high-k gate dielectric layer in face；In high-k gate dielectric layer surface formation gate electrode layer.In another embodiment
In, additionally it is possible to directly in interface layer surfaces and oxidation layer surface formation gate electrode layer.
Wherein, the gate dielectric layer of the core devices of formation includes boundary layer and the high k positioned at interface layer surfaces
Gate dielectric layer, the gate dielectric layer of the input and output device of formation includes oxide layer 109 and positioned at oxide layer
The high-k gate dielectric layer on 109 surfaces.The oxide layer 109 formed in Such analysis, the present embodiment has
Having has round and smooth turning shape between higher thickness evenness, and the oxide layer 109 and fin 102
Looks interface, so that the gate dielectric layer thickness evenness of the input and output device formed is good, it is to avoid turning
The sharp and point discharge problem that causes, improve GOI problems, TDDB problems, NBTI problems and
PBTI problems, improve the reliability and electric property of input and output device, and then improve the fin formed
The reliability and electric property of effect pipe.
In other embodiments, additionally it is possible to using the work for being initially formed formation gate electrode layer after high-k gate dielectric layer
Skill (high k first metal gate last), i.e. in boundary layer and oxide layer before pseudo- grid film is formed
Surface forms high-k gate dielectric layer；Or use is initially formed the work that high-k gate dielectric layer is initially formed gate electrode layer
The technique of skill (high k first metal gate first), i.e. pseudo- grid film is not necessarily formed, directly in boundary layer
And oxidation layer surface formation high-k gate dielectric layer, then in high-k gate dielectric layer surface formation gate electrode layer,
Then the graphical gate electrode layer and high-k gate dielectric layer, form grid structure.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (17)
1. a kind of improve the method for fin field effect pipe performance, it is characterised in that
Substrate is provided, the substrate surface is formed with discrete fin；
Form low at the top of the covering substrate surface and the separation layer of fin sidewall surfaces, the separation layer
At the top of fin, the separation layer exposes the fin of first thickness；
The fin higher than separation layer is made annealing treatment, the annealing is suitable to improve the fin
The round and smooth degree of portion's top corner, wherein, the annealing is containing H2Atmosphere under carry out；
After the annealing is carried out, the separation layer formation isolation structure of second thickness is removed；
After the isolation structure is formed, oxidation processes are carried out to the fin higher than the isolation structure,
At the top of fin and sidewall surfaces formation oxide layer.
2. improve the method for fin field effect pipe performance as claimed in claim 1, it is characterised in that the annealing
The annealing temperature of processing is 300 DEG C~500 DEG C.
3. improve the method for fin field effect pipe performance as claimed in claim 1, it is characterised in that moved back
In the technique of fire processing, H2Flow is 1sccm~1000sccm.
4. improve the method for fin field effect pipe performance as claimed in claim 1, it is characterised in that described first
Thickness is 0.5nm~5nm.
5. improve the method for fin field effect pipe performance as claimed in claim 1, it is characterised in that described second
Thickness is 5nm~50nm.
6. improve the method for fin field effect pipe performance as claimed in claim 1, it is characterised in that forming institute
State before separation layer, the fin top surface is formed with hard mask layer.
7. improve the method for fin field effect pipe performance as claimed in claim 6, it is characterised in that form described
The processing step of separation layer includes：Form the covering substrate surface, fin sidewall surfaces and hard
Higher than at the top of hard mask layer at the top of the barrier film of mask layer surface, the barrier film；Remove higher than described
Barrier film at the top of hard mask layer；Then, the hard mask layer is removed；Remove the isolation of segment thickness
Film forms the separation layer.
8. improve the method for fin field effect pipe performance as claimed in claim 7, it is characterised in that the isolation
The formation process of film includes：Using mobility chemical vapor deposition method formation forerunner's barrier film；To institute
State forerunner's barrier film and carry out annealing curing process, forerunner's barrier film is converted into barrier film.
9. improve the method for fin field effect pipe performance as claimed in claim 7, it is characterised in that forming institute
State before barrier film, liner oxidation layer is formed in the substrate surface and fin sidewall surfaces；Going
Except segment thickness barrier film while, also remove higher than separation layer liner oxidation layer.
10. improve the method for fin field effect pipe performance as claimed in claim 9, it is characterised in that described linear
The material of oxide layer is silica.
11. improve the method for fin field effect pipe performance as claimed in claim 1, it is characterised in that the oxidation
It is processed as dry-oxygen oxidation, steam oxidation or wet-oxygen oxidation.
12. improve the method for fin field effect pipe performance as claimed in claim 1, it is characterised in that using in situ
Steam generation oxidation technology carries out the oxidation processes, and technological parameter includes：Reacting gas includes O2、
H2And H2O, wherein, O2Flow is 0.1slm to 20slm, H2Flow be 0.1slm to 20slm,
H2O flows are 0.1slm to 50slm, and reaction chamber temperature is 650 degree to 1000 degree, reaction chamber
Pressure be 0.1 support to 760 supports, a length of 5 seconds to 10 points during reaction.
13. improve the method for fin field effect pipe performance as claimed in claim 1, it is characterised in that the oxidation
The material of layer is silica.
14. improve the method for fin field effect pipe performance as claimed in claim 1, it is characterised in that also including step
Suddenly：In the oxidation layer surface formation high-k gate dielectric layer；Formed in the high-k gate dielectric layer surface
Gate electrode layer.
15. improve the method for fin field effect pipe performance as claimed in claim 1, it is characterised in that the substrate
Including core device region and input and output device area, wherein, core device region substrate surface is formed with fin
Portion, input and output device area substrate surface is formed with fin；After the oxide layer is formed, also wrap
Include step：Remove the oxide layer of the core device region；Fin portion surface shape in the core device region
Into pseudo- oxide layer, the thickness of the pseudo- oxide layer is less than the thickness of oxide layer；In the oxidation layer surface
And pseudo- oxidation layer surface forms pseudo- gate layer；Source-drain electrode is formed in the fin of the pseudo- gate layer both sides；
Interlayer dielectric layer is formed on the source-drain electrode surface, the interlayer dielectric layer also covers pseudo- gate layer side wall table
Face；Etching removes the pseudo- gate layer；Etching removes the pseudo- oxide layer, exposes core device region fin
Portion surface；In core device region fin portion surface formation boundary layer, the interfacial layer thickness is less than oxygen
Change thickness degree.
16. improve the method for fin field effect pipe performance as claimed in claim 15, it is characterised in that also include：
In the interface layer surfaces and oxidation layer surface formation gate electrode layer.
17. improve the method for fin field effect pipe performance as claimed in claim 15, it is characterised in that also include：
In the interface layer surfaces and oxidation layer surface formation high-k gate dielectric layer；In the high-k gate dielectric
Layer surface formation gate electrode layer.
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