CN107591362B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN107591362B CN107591362B CN201610527753.7A CN201610527753A CN107591362B CN 107591362 B CN107591362 B CN 107591362B CN 201610527753 A CN201610527753 A CN 201610527753A CN 107591362 B CN107591362 B CN 107591362B
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Abstract
A method of forming a semiconductor structure, comprising: providing a substrate and a fin part protruding out of the substrate; forming an isolation structure on a substrate, wherein a fin part exposed out of the isolation structure is used as a first region of a fin part, and an unexposed fin part is used as a second region of the fin part; forming a protective layer on the side wall of the first region of the fin part; annealing the second region of the fin part to form an oxide layer on the side wall of the second region of the fin part; removing the protective layer; forming a pseudo gate structure which crosses the first region of the fin part and covers the partial top and the surface of the side wall of the first region of the fin part; forming a dielectric layer on the substrate between the fin parts; and removing the pseudo gate structure. After a protective layer is formed on the side wall of the first region of the fin portion, annealing treatment is carried out on the second region of the fin portion, so that the width size of the second region of the fin portion is reduced; the subsequent process for removing the pseudo gate structure also causes loss to the isolation structure, and exposes a part of the second region of the fin part, thereby avoiding widening of a channel region of the device.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following moore's law is continuously reduced. To accommodate the reduction in process nodes, the channel length of MOSFET fets has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip, increasing the switching speed of the MOSFET field effect transistor and the like.
However, as the length of the channel of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, and the sub-threshold leakage (SCE) phenomenon, so-called short-channel effects, is more likely to occur.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar MOSFET transistors to three-dimensional transistors with higher performance, such as fin field effect transistors (finfets). In the FinFET, the grid electrode can control the ultrathin body (fin part) at least from two sides, the control capability of the grid electrode on a channel is much stronger than that of a planar MOSFET device, and the short channel effect can be well inhibited; and compared with other devices, the FinFET has better compatibility of the existing integrated circuit manufacturing technology.
However, the electrical properties of the semiconductor devices formed by the prior art need to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can optimize the electrical performance of a semiconductor device.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate; forming an isolation structure on the substrate between the fin parts, wherein the fin parts exposed out of the isolation structure are used as first regions of the fin parts, and the fin parts not exposed out are used as second regions of the fin parts; forming a protective layer on the side wall of the first region of the fin part; annealing the second region of the fin part, and forming an oxide layer on the side wall of the second region of the fin part; removing the protective layer; forming a pseudo gate structure which crosses the first region of the fin part and covers the partial top surface and the side wall surface of the first region of the fin part, wherein the pseudo gate structure comprises a pseudo gate oxide layer and a pseudo gate electrode layer positioned on the surface of the pseudo gate oxide layer; forming a dielectric layer on the substrate between the fin parts, wherein the dielectric layer exposes out of the pseudo gate structure; removing the pseudo gate structure, and forming an opening exposing the fin part in the dielectric layer; and forming a metal gate structure in the opening.
Optionally, the protective layer is made of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
Optionally, the thickness of the protective layer is
To
Optionally, the step of forming the protective layer includes: forming a protective film which conformally covers the first region of the fin part, wherein the protective film also covers the surface of the isolation structure; the step of forming the protective layer includes: and forming a protective film which conformally covers the first region of the fin part, wherein the protective film also covers the surface of the isolation structure.
Optionally, the protective film is formed by an atomic layer deposition process.
Optionally, the material of the protective film is silicon nitride, and the process parameters of the atomic layer deposition process include: the precursor introduced into the atomic layer deposition chamber is a precursor containing silicon and nitrogen, the process temperature is 400-600 ℃, the pressure is 1-10 mTorr, the gas flow of the precursor is 1500-4000 sccm, and the deposition times are 15-50 times.
Optionally, annealing the second region of the fin portion by using water vapor annealing.
Optionally, the annealing treatment is water vapor annealing treatment; the technological parameters of the water vapor annealing treatment comprise: the reaction gases are hydrogen and oxygen, the annealing temperature is 400-800 ℃, the gas flow of the hydrogen is 1-20 slm, the gas flow of the oxygen is 1-20 slm, and the pressure is one standard atmosphere.
Optionally, the thickness of the oxide layer is
To
Optionally, the protective layer is removed by a wet etching process.
Optionally, the protective layer is made of silicon nitride, and the solution adopted in the wet etching is a phosphoric acid solution.
Optionally, the material of the dummy gate oxide layer is silicon oxide.
Optionally, the process for forming the pseudo gate oxide layer is an in-situ steam generation oxidation process.
OptionalThe process parameters of the in-situ steam generation oxidation process comprise: providing O2And H2，O2The flow rate is 10sccm to 40sccm, H2The flow rate is 0.2sccm to 2sccm, the chamber temperature is 900 ℃ to 1100 ℃, the chamber pressure is 4Torr to 10Torr, and the process time is 5S to 30S.
Optionally, after the annealing treatment is performed on the second region of the fin portion, the width value of the second region of the fin portion is 8nm to 16nm, and after the pseudo gate structure is formed, the width value of the first region of the fin portion is 6nm to 14 nm.
Optionally, the substrate includes a peripheral region and a core region, a fin portion protruding from the substrate in the peripheral region is a first fin portion, and a fin portion protruding from the substrate in the core region is a second fin portion; in the step of forming the isolation structure on the substrate between the fin portions, the first fin portions exposed out of the isolation structure are used as first fin portion first areas, and the first fin portions not exposed out are used as first fin portion second areas; the first fin parts exposed out of the isolation structure are used as first fin part first areas, and the first fin parts not exposed out of the isolation structure are used as first fin part second areas; the step of forming a protective layer on the sidewall of the first region of the fin portion includes: forming the protective layer in the first region of the first fin portion and the first region of the second fin portion; the step of forming a dummy gate structure which crosses the first region of the fin and covers part of the top surface and the side wall surface of the first region of the fin comprises the following steps: forming a first pseudo gate structure which stretches across the first region of the first fin part and covers the partial top surface and the side wall surface of the first region of the first fin part, and forming a second pseudo gate structure which stretches across the first region of the second fin part and covers the partial top surface and the side wall surface of the first region of the second fin part, wherein the first pseudo gate structure comprises a gate oxide layer and a first pseudo gate electrode layer positioned on the surface of the gate oxide layer, and the second pseudo gate structure comprises a gate pseudo gate oxide layer and a second pseudo gate electrode layer positioned on the surface of the pseudo gate oxide layer; the step of removing the dummy gate structure comprises: removing the first dummy gate electrode layer and the second dummy gate electrode layer, and forming openings in the dielectric layers of the peripheral region and the core region; forming a filling layer filling the opening of the peripheral area; forming a photoresist layer on the filling layer, wherein the photoresist layer also covers the dielectric layer in the peripheral area; and removing the pseudo gate oxide layer at the bottom of the opening of the core region by taking the photoresist layer as a mask.
Accordingly, the present invention also provides a semiconductor structure comprising: the substrate comprises a substrate and a fin part protruding out of the substrate; the isolation structure is positioned on the substrate between the fin parts; the oxide layer is positioned between the fin part and the isolation structure; the metal gate structure stretches across the fin part and covers the top surface and the side wall surface of the fin part; and the dielectric layer is positioned on the substrate between the fin parts and exposes out of the metal grid structure.
Optionally, the thickness of the oxide layer is
To
Optionally, the fin portion exposed out of the isolation structure is used as a fin portion first region, and the fin portion not exposed out is used as a fin portion second region; the oxide layer is positioned between the second region of the fin part and the isolation structure; the metal gate structure crosses over the first region of the fin and covers a portion of the top surface and the sidewall surface of the first region of the fin.
Optionally, the width value of the second region of the fin portion is 8nm to 16nm, and the width value of the first region of the fin portion is 6nm to 14 nm.
Compared with the prior art, the technical scheme of the invention has the following advantages:
after an isolation structure is formed on a substrate between fin parts, firstly forming a protective layer on the side wall of a first region of the fin part, then annealing a second region of the fin part, and forming an oxide layer on the side wall of the second region of the fin part; the annealing treatment is used for oxidizing partial materials of the second region of the fin portion, so that the width size of the second region of the fin portion is reduced, and the first region of the fin portion is not affected under the protection effect of the protection layer; when the dummy gate structure is formed on the first region of the fin portion, partial materials of the first region of the fin portion can be oxidized by an oxidation process for forming the dummy gate oxide layer, so that the width size of the first region of the fin portion is reduced. Compared with the scheme of directly forming the pseudo-gate structure on the first region of the fin part, the method can avoid the problem of overlarge width size of the second region of the fin part so as to reduce the difference value between the width size of the first region of the fin part and the width size of the second region of the fin part; the subsequent process for removing the pseudo-gate structure also causes loss to the isolation structure, and exposes a part of the second region of the fin part, so that the problem of widening of a device channel region can be avoided, the short channel effect caused by widening of the device channel region is avoided, and the electrical performance of the semiconductor device is improved.
The invention provides a semiconductor structure, which comprises an oxide layer positioned between a fin part and an isolation structure; through the formation process of the oxide layer, the problem of widening of a channel region of a device can be avoided, so that a short channel effect caused by widening of the channel region of the device can be avoided, and the electrical performance of the semiconductor device is improved.
Drawings
FIGS. 1-3 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 4to 16 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is known from the background art, the electrical properties of the semiconductor devices formed by the prior art need to be improved. The reason is analyzed in conjunction with a method of forming a semiconductor structure. Referring to fig. 1 to 9, schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure are shown. The forming method of the semiconductor structure comprises the following steps:
referring to fig. 1, a base is provided, and the base includes a substrate 100 and a fin portion protruding from the substrate 100.
Specifically, the substrate 100 includes a peripheral region i and a core region ii, a fin portion protruding from the substrate 100 in the peripheral region i is a first fin portion 110, and a fin portion protruding from the substrate 100 in the core region ii is a second fin portion 120.
A hard mask layer 200 is also formed on the top of the fin portion, and the hard mask layer 200 is used as an etching mask for forming the substrate 100 and the fin portion.
Referring to fig. 2, an isolation structure 102 is formed on the substrate 100 between adjacent fins, wherein the isolation structure 102 covers part of the sidewall surface of the fin.
Specifically, the first fin portion 110 exposed out of the isolation structure 102 is used as a first fin portion first region 111, and the unexposed first fin portion 110 is used as a first fin portion second region 112; the second fin 120 exposed by the isolation structure 102 serves as a second fin first region 121, and the unexposed second fin 120 serves as a second fin second region 122.
The isolation structure 102 is made of silicon oxide. It should be noted that, after the isolation structure 102 is formed, the hard mask layer 200 is removed.
Referring to fig. 3, an in-situ steam generation oxidation process is adopted to form a gate oxide layer 131 covering the first fin portion 110, and form a dummy gate oxide layer 132 covering the second fin portion 120, where the gate oxide layer 131 and the dummy gate oxide layer 132 are made of silicon oxide. .
The oxidation process oxidizes a part of the material of the first fin first region 111 and the second fin first region 121, thereby causing the width dimensions of the first fin first region 111 and the second fin first region 121 to become smaller. Therefore, the width dimension of the second fin second region 122 is larger than the width dimension of the second fin first region 121.
After the gate oxide layer 131 and the dummy gate oxide layer 132 are formed, the following steps further include: forming a first dummy gate electrode layer on the gate oxide layer 131, and forming a second dummy gate electrode layer on the dummy gate oxide layer 132; forming a dielectric layer on the substrate 100, wherein the top of the dielectric layer is flush with the tops of the first dummy gate electrode layer and the second dummy gate electrode layer; removing the first dummy gate electrode layer, forming a first opening exposing the gate oxide layer 131 in the dielectric layer, removing the second dummy gate electrode layer, and forming a second opening exposing the dummy gate oxide layer 132 in the dielectric layer; removing the pseudo gate oxide layer 132 at the bottom of the second opening; and forming a metal gate structure in the first opening and the second opening.
However, the process of removing the dummy gate oxide layer 132 at the bottom of the second opening easily loses the core region ii isolation structure 102 with a partial thickness, thereby exposing a portion of the second fin portion second region 122; the width of the second fin second region 122 is greater than the width of the second fin first region 121, that is, the width of the first fin 110 exposed out of the isolation structure 102 is increased, so that a channel region of the formed semiconductor device is widened, and a short channel effect is easily caused by the widened channel region, thereby easily causing a decrease in electrical performance of the semiconductor device.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate; forming an isolation structure on the substrate between the fin parts, wherein the fin parts exposed out of the isolation structure are used as first regions of the fin parts, and the fin parts not exposed out are used as second regions of the fin parts; forming a protective layer on the side wall of the first region of the fin part; annealing the second region of the fin part, and forming an oxide layer on the side wall of the second region of the fin part; removing the protective layer; forming a pseudo gate structure which crosses the first region of the fin part and covers the partial top surface and the side wall surface of the first region of the fin part, wherein the pseudo gate structure comprises a pseudo gate oxide layer and a pseudo gate electrode layer positioned on the surface of the pseudo gate oxide layer; forming a dielectric layer on the substrate between the fin parts, wherein the dielectric layer exposes out of the pseudo gate structure; removing the pseudo gate structure, and forming an opening exposing the fin part in the dielectric layer; and forming a metal gate structure in the opening.
After an isolation structure is formed on a substrate between fin parts, firstly forming a protective layer on the side wall of a first region of the fin part, then annealing a second region of the fin part, and forming an oxide layer on the side wall of the second region of the fin part; the annealing treatment is used for oxidizing partial materials of the second region of the fin portion, so that the width size of the second region of the fin portion is reduced, and the first region of the fin portion is not affected under the protection effect of the protection layer; when the dummy gate structure is formed on the first region of the fin portion, partial materials of the first region of the fin portion can be oxidized by an oxidation process for forming the dummy gate oxide layer, so that the width size of the first region of the fin portion is reduced. Compared with the scheme of directly forming the pseudo-gate structure on the first region of the fin part, the method can avoid the problem of overlarge width size of the second region of the fin part so as to reduce the difference value between the width size of the first region of the fin part and the width size of the second region of the fin part; the subsequent process for removing the pseudo-gate structure also causes loss to the isolation structure, and exposes a part of the second region of the fin part, so that the problem of widening of a device channel region can be avoided, the short channel effect caused by widening of the device channel region is avoided, and the electrical performance of the semiconductor device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4to 16 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 4 and 5 in combination, fig. 4 is a perspective view (only two fins are shown) of the semiconductor structure, and fig. 5 is a schematic view of a cross-sectional structure along the direction AA1 in fig. 4, wherein a base is provided, and the base includes a substrate 300 and a fin (not labeled) protruding from the substrate 300.
The substrate 300 provides a process platform for the subsequent formation of semiconductor devices. In this embodiment, the substrate 300 includes a peripheral region i (shown in fig. 5) and a core region ii (shown in fig. 5); correspondingly, the fin portion protruding from the substrate 300 in the peripheral region i is a first fin portion 310, and the fin portion protruding from the substrate 300 in the core region ii is a second fin portion 310.
In this embodiment, the substrate 300 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The material of the fin is the same as the material of the substrate 300. In this embodiment, the fin portion is made of silicon; correspondingly, the material of the first fin portion 310 and the second fin portion 310 is silicon. In other embodiments, the material of the fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; correspondingly, the material of the first fin part and the second fin part can also be germanium, silicon carbide, gallium arsenide or indium gallium arsenide.
Specifically, the process steps for forming the substrate 300 and the fin portion include: providing an initial substrate; forming a patterned hard mask layer 400 on the initial substrate surface (as shown in fig. 5); and etching the initial substrate by taking the hard mask layer 400 as a mask, wherein the etched initial substrate is taken as the substrate 300, and the protrusion on the surface of the substrate 300 is taken as a fin part.
In this embodiment, after the substrate 300 and the fin portion are formed, the hard mask layer 400 on the top of the fin portion is remained. The hard mask layer 400 is made of silicon nitride, and when a planarization process is performed subsequently, the top surface of the hard mask layer 400 is used for defining a stop position of the planarization process, so that the top of the fin portion is protected.
In this embodiment, the sidewalls of the fin are perpendicular to the surface of the substrate 300, i.e., the top dimension of the fin is equal to the bottom dimension. In other embodiments, the top dimension of the fin may be smaller than the bottom dimension.
In this embodiment, the width of each fin is equal along a direction parallel to the substrate 300.
With reference to fig. 6, it should be noted that after the substrate 300 and the fin portion are formed, the forming method further includes: a liner oxide layer 301 is formed on the surface of the fin 300 for repairing the first fin 310 and the second fin 320.
In this embodiment, the process of forming the pad oxide layer 301 is an oxidation process.
Since the first and second fins 310 and 320 are formed by etching an initial substrate, the first and second fins 310 and 320 generally have a convex corner and a surface defect. In the oxidation treatment process, because the convex edge portions of the first fin portion 310 and the second fin portion 320 have larger specific surface and are easier to be oxidized, after the liner oxide layer 301 is removed, not only are the defect layers on the surfaces of the first fin portion 310 and the second fin portion 320 removed, but also the convex edge portions are removed, so that the surfaces of the first fin portion 310 and the second fin portion 320 are smooth, the lattice quality is improved, the problem of tip discharge at the top corners of the first fin portion 310 and the second fin portion 320 is avoided, and the improvement of the performance of the fin field effect transistor is facilitated.
The oxidation treatment may employ an oxygen plasma oxidation process, or a mixed solution oxidation process of sulfuric acid and hydrogen peroxide. The oxidation process also oxidizes the surface of the substrate 300, so that the formed pad oxide layer 301 is also located on the surface of the substrate 300.
In this embodiment, the liner oxide layer 301 is formed by performing an oxidation process on the substrate 300 and the fin portion by using an ISSG (In-situ steam Generation) oxidation process, wherein the thickness of the liner oxide layer 301 is
To
Since the material of the substrate 300 and the fin portion is silicon, the material of the correspondingly formed pad oxide layer 301 is silicon oxide.
Referring to fig. 7, isolation structures 302 are formed on the substrate 300 between the fins (not shown), the fins exposed to the isolation structures 302 serve as first fin regions (not shown), and the unexposed fins serve as second fin regions (not shown).
In this embodiment, the fins include a first fin 310 protruding from the substrate 300 in the peripheral region i and a second fin 320 protruding from the substrate 300 in the core region ii. Correspondingly, the first fin portion 310 exposed out of the isolation structure 302 is a first fin portion first region 311, and the unexposed first fin portion 310 is a first fin portion second region 312; the second fin portion 320 exposed by the isolation structure 302 is a second fin portion first region 321, and the unexposed second fin portion 320 is a second fin portion second region 322.
The isolation structure 302 serves as an isolation structure of a semiconductor structure for isolating adjacent devices. In this embodiment, the isolation structure 302 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
It should be noted that, in the present embodiment, the isolation structure 302 is a shallow trench isolation layer.
Specifically, the step of forming the isolation structure 302 includes: forming a precursor isolation film on the pad oxide layer 301, wherein the top of the precursor isolation film is higher than the top of the hard mask layer 400; carrying out first annealing treatment on the precursor isolation film, and converting the precursor isolation film into an isolation film; grinding to remove the isolation film higher than the top of the hard mask layer 400; a portion of the thickness of the isolation film is removed to form isolation structures 302.
In order to improve the gap-filling capability of the process for forming the isolation film, in this embodiment, a Flowable Chemical Vapor Deposition (FCVD) process is used to form the precursor isolation film. In another embodiment, the precursor isolation film may also be formed using a high aspect ratio chemical vapor deposition process (HARP CVD).
It should be noted that, after the isolation structure 302 is formed, the hard mask layer 400 on the top of the fin portion is retained, and the hard mask layer 400 is used for protecting the fin portion in the subsequent annealing process to prevent the top of the fin portion from being oxidized.
It should be further noted that, while removing the isolation film with a partial thickness, the liner oxide layer 301 on the first fin portion first region 311 and the second fin portion first region 321 is also removed.
It should be further noted that, in this embodiment, the top dimension of the fin portion is equal to the bottom dimension, and the width dimension of each fin portion is equal along the direction parallel to the substrate 300; that is, the widths of the first fin first region 311, the first fin second region 312, the second fin first region 321, and the second fin second region 322 are equal along a direction parallel to the substrate 300.
Referring to fig. 8, a protection layer 500 is formed on the sidewalls of the first region (not labeled) of the fin.
The protection layer 500 is used to protect the first region of the fin portion from being oxidized during the subsequent annealing process.
In this embodiment, the material of the protection layer 500 is silicon nitride. In other embodiments, the material of the protective layer may also be silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
It should be noted that the thickness of the protective layer 500 is not too thin, nor too thick. If the thickness of the protection layer 500 is too thin, the protection effect on the first region of the fin portion is not obvious in the subsequent annealing treatment, which easily causes the first region of the fin portion to be oxidized; since the distance between the fins is small, that is, the process window for forming the protection layer 500 is small, in order to enable the protection layer 500 to be formed between the fins well and the protection layer 500 has no hole defect between the fins, the thickness of the protection layer 500 is not too thick. For this purpose, in this embodiment, the thickness of the protection layer 500 is
To
Specifically, the step of forming the protective layer 500 includes: forming a protective film conformally covering the first region (not labeled) of the fin portion, wherein the protective film also covers the surface of the isolation structure 302; and removing the protective film on the top of the first region of the fin portion and the isolation structure 302 by using a maskless etching process, and forming a protective layer 500 on the sidewall of the first region of the fin portion.
It should be noted that the fin portion includes a first fin portion 310 and a second fin portion 320; accordingly, the protection layer 500 is located on sidewalls of the first and second fin first regions 311 and 321.
It should be further noted that a hard mask layer 400 is formed on the top of the first fin portion 310 and the second fin portion 320; correspondingly, in the step of forming the protective film, the protective film also conformally covers the hard mask layer 400; in the maskless etching process, the top of the hard mask layer 400 and the protective film on the isolation structure 302 are removed, and a protective layer 500 is formed on the sidewall of the first region of the fin portion and the sidewall of the hard mask layer 400.
In this embodiment, the protective film is formed by an atomic layer deposition process. Specifically, the process parameters of the atomic layer deposition process include: and introducing the precursor into the atomic layer deposition chamber, wherein the precursor is a precursor containing silicon and nitrogen.
It should be noted that the process temperature of the atomic layer deposition process is not too low and not too high. When the process temperature is too low, the deposition speed of each deposition process is easily too low, so that the thickness of the protective film is thin, or the process time needs to be increased to reach a target thickness value, so that the formation efficiency of the protective film is reduced; when the process temperature is too high, thermal decomposition of the precursor is easily caused, so that a phenomenon similar to chemical vapor deposition is introduced, the purity and the step coverage of the protective film are affected, and the formation quality of the protective film is finally reduced. For this reason, in the present embodiment, the process temperature is 400 to 600 degrees celsius.
And setting the gas flow, the chamber pressure and the deposition times of the precursor within reasonable range values based on the set process temperature, so that the high purity and the good step coverage of the protective film are ensured, and the thickness of the protective film meets the process requirements. Therefore, in the present embodiment, the pressure is 1 mtorr to 10 mtorr, the gas flow rate of the precursor is 1500sccm to 4000sccm, and the deposition times are 15 to 50 times.
In other embodiments, the protective film may be formed by a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 9, an annealing process 510 is performed on the second region of the fin (not labeled) to form an oxide layer 361 on the sidewalls of the second region of the fin.
The annealing process 510 is used to oxidize the first fin second region 312 and the second fin second region 322, so that the material of part of the first fin second region 312 and the second fin second region 322 is converted from silicon to silicon oxide; thus, the width dimensions of the first and second fin second regions 312, 322 decrease in a direction parallel to the substrate 300.
It should be noted that, in this embodiment, the oxide layer 361 includes the liner oxide layer 301 and a silicon oxide layer converted from a portion of the first fin second region 312 and the second fin second region 322.
It should be noted that after the annealing process 510 is performed, the width of the second region of the fin portion is not too large or too small. The subsequent process of removing the dummy gate oxide layer on the second fin first region 321 also causes loss to the isolation structure 302, so that a part of the second fin second region 322 is exposed, and if the width value of the fin second region is too large, a device channel region is easily widened, thereby causing a short channel effect; if the width of the second region of the fin portion is too small, the electrical performance of the semiconductor device is easily deviated. Therefore, in the present embodiment, the width of the second region of the fin portion is 8nm to 16nm, that is, the widths of the first and second regions 312 and 322 of the fin portion are 8nm to 16 nm.
It should be further noted that the oxidation degree of the annealing process 510 on the second region of the fin portion affects the width dimension of the second region of the fin portion; accordingly, the thickness of the oxide layer 361 affects the width of the second region of the fin. In this embodiment, the thickness of the oxide layer 361 is set as
To
In this embodiment, the second region of the fin portion is annealed 510 using a water vapor anneal. Specifically, the process parameters of the water vapor annealing treatment include: the reaction gases are hydrogen and oxygen, and the pressure is one standard atmosphere.
It should be noted that the gas flow rate of the reaction gas is not too small, nor too large. If the gas flow of the reaction gas is too low, the second region of the fin portion is easily oxidized to a lower degree, so that the effect of reducing the width dimension of the second region of the fin portion in a direction parallel to the surface of the substrate 300 is not obvious; if the gas flow rate of the reaction gas is too high, too much second region of the fin portion is easily oxidized, and the width of the second region of the fin portion is too small in a direction parallel to the surface of the substrate 300. For this reason, in the present embodiment, the gas flow rate of hydrogen is 1slm to 20slm, and the gas flow rate of oxygen is 1slm to 20 slm.
It should be noted that the annealing temperature is not too low nor too high. When the annealing temperature is too low, the oxidation speed of the second region of the fin portion is too slow, so that the effect of reducing the width dimension of the second region of the fin portion in a direction parallel to the surface of the substrate 300 is not obvious easily; when the annealing temperature is too high, the oxidation speed of the second region of the fin portion is too high, which easily causes too many second regions of the fin portion to be oxidized, and thus the width of the second regions of the fin portion is too small in a direction parallel to the surface of the substrate 300. For this reason, in the present embodiment, the annealing temperature is 400 ℃ to 800 ℃.
It should be further noted that, because the hard mask layer 400 is formed on the tops of the first fin portion first region 311 and the second fin portion first region 321, and the protective layer 500 is formed on the sidewalls of the first fin portion first region 311 and the second fin portion first region 321, the hard mask layer 400 and the protective layer 500 protect the first fin portion first region 311 and the second fin portion first region 321 in the annealing process 510, so as to prevent the first fin portion first region 311 and the second fin portion first region 321 from being oxidized; therefore, the width dimensions of the first and second fin first regions 311 and 321 do not change along a direction parallel to the substrate 300.
Referring to fig. 10, the protective layer 500 is removed (as shown in fig. 9).
In this embodiment, the protective layer 500 is removed by a wet etching process. Specifically, the material of the protection layer 500 is silicon nitride, and the solution adopted in the wet etching is a phosphoric acid solution.
In other embodiments, the protective layer may be removed by a dry etching process or a combination of a dry etching process and a wet etching process.
It should be noted that the hard mask layer 400 (as shown in fig. 9) is made of silicon nitride, and in the step of removing the protection layer 500, the hard mask layer 400 on the top of the first fin portion 310 and the second fin portion 320 is also removed.
Referring to fig. 11 and 12 in combination, fig. 12 is a schematic cross-sectional structure diagram of fig. 11 along an extending direction of the fin portion (as shown in a direction of BB1 in fig. 4), and a dummy gate structure (not shown) is formed to cross the first region (not shown) of the fin portion and cover a portion of a top surface and a sidewall surface of the first region of the fin portion, where the dummy gate structure includes a dummy gate oxide layer 332 (shown in fig. 11) and a dummy gate electrode (not shown) located on a surface of the dummy gate oxide layer 332.
The dummy gate structure occupies a space for a metal gate structure to be carried out subsequently.
In this embodiment, the dummy gate structure includes a first dummy gate structure that spans the first fin first region 311 and covers a portion of the top surface and the sidewall surface of the first fin first region 311, and a second dummy gate structure that spans the second fin first region 321 and covers a portion of the top surface and the sidewall surface of the second fin first region 321.
In this embodiment, the substrate 300 includes a peripheral region i and a core region ii; correspondingly, the first dummy gate structure includes a gate oxide layer 331 (shown in fig. 11) and a first dummy gate electrode layer 341 (shown in fig. 12) on the surface of the gate oxide layer 331, and the second dummy gate structure includes a dummy gate oxide layer 332 and a second dummy gate electrode layer 342 on the surface of the dummy gate oxide layer 332.
The gate oxide layer 331 and the dummy gate oxide layer 332 are made of silicon oxide. The material of the first dummy gate electrode layer 341 and the second dummy gate electrode layer 342 may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. In this embodiment, the material of the first dummy gate electrode layer 341 and the second dummy gate electrode layer 342 is polysilicon.
In this embodiment, the gate oxide layer 331 and the dummy gate oxide layer 332 are formed using an In-situ steam Generation (ISSG) oxidation process. Specifically, the process parameters of the in-situ steam generation oxidation process include: providing O2And H2，O2The flow rate is 10sccm to 40sccm, H2The flow rate is 0.2sccm to 2sccm, the chamber temperature is 900 ℃ to 1100 ℃, the chamber pressure is 4Torr to 10Torr, and the process time is 5S to 30S.
It should be noted that, the oxidation process oxidizes a part of the thickness of the first region of the fin portion to form the gate oxide layer 331 and the dummy gate oxide layer 332; therefore, after the gate oxide layer 331 and the dummy gate oxide layer 332 are formed, the width dimensions of the first fin portion first region 311 and the second fin portion first region 321 become smaller along the direction parallel to the substrate 300. In this embodiment, after the gate oxide layer 331 and the dummy gate oxide layer 332 are formed, the width value of the first fin region is 6nm to 14nm, that is, the width values of the first fin region 311 and the second fin region 321 are 6nm to 14 nm.
It should be noted that, in this embodiment, the width of the first region of the fin portion is equal to the width of the second region of the fin portion, so that the influence of the width of the second region of the fin portion protruding from the isolation structure 302 on the electrical performance of the semiconductor device can be avoided.
It should be further noted that, after the first dummy gate structure and the second dummy gate structure are formed, the forming method further includes: forming a side wall 303 on the side wall of the first pseudo gate structure and the second pseudo gate structure; a first source-drain doped region 351 is formed in the first fin portion 310 on two sides of the sidewall 303, and a second source-drain doped region 352 is formed in the second fin portion 320 on two sides of the sidewall 303.
With continued reference to fig. 12, a dielectric layer 304 is formed on the substrate between the fins, wherein the dielectric layer 304 exposes the dummy gate structure.
In this embodiment, the dielectric layer 304 is flush with the first dummy gate structure and the second dummy gate structure, and the tops of the first dummy gate electrode layer 341 and the second dummy gate electrode layer 342 are exposed.
The dielectric layer 304 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the dielectric layer 304 is made of silicon oxide.
Referring to fig. 13-15 in combination, fig. 15 is a schematic cross-sectional view taken along a direction perpendicular to an extending direction of the fin portion (as shown in the direction of AA1 in fig. 4) in fig. 14, where the dummy gate structure is removed, and an opening 314 exposing the fin portion is formed in the dielectric layer 304.
The opening 314 provides a spatial location for the subsequent formation of a metal gate structure.
In this embodiment, the first dummy gate structure and the second dummy gate structure are removed, and the opening 314 is formed in the dielectric layer 304 in the peripheral region i and the core region ii.
It should be noted that the substrate 300 includes a peripheral region i and a core region ii, the substrate 300 in the peripheral region i is used to form a peripheral device (for example, an input/output device), the substrate 300 in the core region ii is used to form a core device, an operating voltage of the core device is lower than an operating voltage of the peripheral device, and in order to prevent problems such as electrical breakdown, when an operating voltage of the device is higher, a thickness of a gate dielectric layer of the device is required to be thicker, that is, a thickness of a gate dielectric layer of the subsequently formed core region ii is smaller than a thickness of a gate dielectric layer in the peripheral region i. For this reason, in this embodiment, before forming the gate dielectric layer in the core region ii, the dummy gate oxide layer 332 is removed (as shown in fig. 13), so that the thickness of the gate dielectric layer (not shown) of the peripheral device formed subsequently is greater than the thickness of the gate dielectric layer (not shown) of the core device.
Specifically, the step of removing the dummy gate structure includes: removing the first dummy gate electrode layer 341 (shown in fig. 12) and the second dummy gate electrode layer 342 (shown in fig. 12), and forming an opening 314 (shown in fig. 13) in the dielectric layers 304 in the peripheral region i and the core region ii; forming a filling layer (not shown) filling the openings 314 in the peripheral region i; forming a photoresist layer (not shown) on the filling layer, wherein the photoresist layer also covers the dielectric layer 304 in the peripheral region i; and removing the dummy gate oxide layer 332 at the bottom of the opening 314 of the core region ii by using the photoresist layer as a mask (as shown in fig. 13).
In this embodiment, the fill layer is made of OD L (Organic Dielectric L eye) material, and is formed by spin-on Coating, and the top of the fill layer is flush with the top of the Dielectric layer 304. in other embodiments, the fill layer can also be a BARC (Bottom Anti-Reflective Coating) material or a DUO (deep UV L light Absorbing Oxide) material3-SiOXSi-OH, or SiOH3And the like.
In this embodiment, the first dummy gate structure and the second dummy gate structure are removed by using a dry etching process. In other embodiments, a wet etching process or a process combining a wet etching process and a dry etching process may be further adopted to remove the first dummy gate structure and the second dummy gate structure.
It should be noted that, in the process of removing the dummy gate oxide layer 332, the isolation structure 302 in the core region ii is easily damaged, so that a portion of the second fin second region 322 is exposed.
Referring to fig. 16, fig. 16 is a schematic view of the structure of fig. 14, and a metal gate structure 324 is formed in the opening 314 (shown in fig. 14).
The metal gate structure 324 includes a gate dielectric layer (not shown) on the bottom and sidewalls of the opening 314, and a metal layer (not shown) filling the opening 314.
The gate dielectric layer is made of a high-k gate dielectric material, wherein the high-k gate dielectric materialBy material is meant a gate dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the gate dielectric layer is made of HfO2. In other embodiments, the gate dielectric layer may also be made of HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2Or Al2O3。
In this embodiment, the metal layer is made of W. In other embodiments, the material of the metal layer may also be Al, Cu, Ag, Au, Pt, Ni, or Ti.
It should be noted that, in this embodiment, the process of removing the dummy gate oxide layer 132 easily loses the core region ii isolation structure 102 with a partial thickness, so that a part of the second fin portion second region 122 is exposed; since the width of the second fin portion 122 in the direction parallel to the surface of the substrate 300 is reduced under the influence of the annealing process 510 (as shown in fig. 9), the problem of widening of the channel region of the device can be avoided, so that the short channel effect can be avoided, and the electrical performance of the semiconductor device can be improved.
With continued reference to fig. 16, the present invention also provides a semiconductor structure comprising:
a base including a substrate 300 and a fin (not labeled) protruding from the substrate 300;
an isolation structure 302 on the substrate 300 between the fins;
an oxide layer 361 (shown in fig. 15) between the fin and the isolation structure 302;
a metal gate structure 324 spanning the fin and covering a portion of the top surface and sidewall surfaces of the fin;
a dielectric layer 304 on the substrate between the fins, the dielectric layer 304 exposing the metal gate structure 324.
In this embodiment, the substrate 300 includes a peripheral region i and a core region ii; correspondingly, the fin portion protruding from the substrate 300 in the peripheral region i is a first fin portion 310, and the fin portion protruding from the substrate 300 in the core region ii is a second fin portion 310.
In this embodiment, the substrate 300 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The material of the fin is the same as the material of the substrate 300. In this embodiment, the fin portion is made of silicon; correspondingly, the material of the first fin portion 310 and the second fin portion 310 is silicon. In other embodiments, the material of the fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; correspondingly, the material of the first fin part and the second fin part can also be germanium, silicon carbide, gallium arsenide or indium gallium arsenide.
The isolation structure 302 serves as an isolation structure of a semiconductor structure for isolating adjacent devices. In this embodiment, the isolation structure 302 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride. It should be noted that, in the present embodiment, the isolation structure 302 is a shallow trench isolation layer.
In this embodiment, the fin exposed out of the isolation structure 302 serves as a first region of the fin (not shown), and the fin not exposed out serves as a second region of the fin (not shown). Accordingly, the oxide layer 301' is located between the second region of the fin portion and the isolation structure 302.
In this embodiment, the width of the second region of the fin portion is 8nm to 16nm, and the width of the first region of the fin portion is 6nm to 14 nm.
It should be noted that the fins include a first fin 310 protruding from the substrate 300 in the peripheral region i and a second fin 320 protruding from the substrate 300 in the core region ii. Correspondingly, the first fin portion 310 exposed out of the isolation structure 302 is a first fin portion first region 311, and the unexposed first fin portion 310 is a first fin portion second region 312; the second fin portion 320 exposed by the isolation structure 302 is a second fin portion first region 321, and the unexposed second fin portion 320 is a second fin portion second region 322.
It should be further noted that the semiconductor structure further includes: is located on the linerA liner oxide layer 301 (shown in fig. 15) between the bottom 300 and the isolation structures 302. In this embodiment, the material of the pad oxide layer 301 is silicon oxide, and the thickness of the pad oxide layer 301 is
To
In this embodiment, the oxide layer 361 includes the liner oxide layer 301 and a silicon oxide layer converted from a portion of the second region of the fin portion. Correspondingly, the liner oxide layer 301 is also located between the fin second region and the isolation structure 302.
It should be noted that the thickness of the oxide layer 361 should not be too thin, nor too thick. Because a part of the oxide layer 361 is formed by converting a part of the second region of the fin portion, if the thickness of the oxide layer 361 is too thin, the width value of the first region of the fin portion close to the top of the isolation structure 302 is easily too large, so that the channel region of the device is easily widened, and a short channel effect is further caused; if the thickness of the oxide layer 361 is too thick, the width of the first region of the fin near the top of the isolation structure 302 is too small, which may easily cause the electrical performance of the semiconductor device to shift. For this reason, in this embodiment, the thickness of the oxide layer 361 is set as
To
In the present embodiment, the metal gate structure 324 crosses over the first region of the fin and covers a portion of the top surface and the sidewall surface of the first region of the fin. The metal gate structure 324 includes a gate dielectric layer (not shown), and a metal layer (not shown) on the gate dielectric layer.
The gate dielectric layer is made of a high-k gate dielectric material, wherein the high-k gate dielectric materialBy material is meant a gate dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. In this embodiment, the gate dielectric layer is made of HfO2. In other embodiments, the gate dielectric layer may also be made of HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2Or Al2O3。
In this embodiment, the metal layer is made of W. In other embodiments, the material of the metal layer may also be Al, Cu, Ag, Au, Pt, Ni, or Ti.
The semiconductor structure includes an oxide layer 361 between the fin and the isolation structure 302; through the formation process of the oxide layer 361, the problem of widening of a channel region of a device can be avoided, so that a short channel effect caused by widening of the channel region of the device can be avoided, and further, the electrical performance of the semiconductor device is improved.
The semiconductor structure of the present invention is formed by the method for forming the semiconductor structure of the present invention, but is not limited to the method for forming.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate;
forming an isolation structure on the substrate between the fin parts, wherein the fin parts exposed out of the isolation structure are used as first regions of the fin parts, and the fin parts not exposed out are used as second regions of the fin parts;
forming a protective layer on the side wall of the first region of the fin part;
annealing the second region of the fin part, and forming an oxide layer on the side wall of the second region of the fin part to oxidize partial materials of the second region of the fin part so as to reduce the width dimension of the second region of the fin part;
removing the protective layer;
forming a dummy gate structure which stretches across the first region of the fin part and covers the partial top surface and the side wall surface of the first region of the fin part, wherein the dummy gate structure comprises a dummy gate oxide layer and a dummy gate electrode layer positioned on the surface of the dummy gate oxide layer, and the oxidation process for forming the dummy gate oxide layer can oxidize partial materials of the first region of the fin part to reduce the width size of the first region of the fin part so as to reduce the difference value between the width size of the first region of the fin part and the width size of the second region of the fin part;
forming a dielectric layer on the substrate between the fin parts, wherein the dielectric layer exposes out of the pseudo gate structure;
removing the pseudo gate structure, and forming an opening exposing the fin part in the dielectric layer, wherein the process of removing the pseudo gate structure causes loss to the isolation structure, and a part of the second region of the fin part is exposed;
and forming a metal gate structure in the opening.
2. The method of forming a semiconductor structure according to claim 1, wherein a material of the protective layer is silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
3. The method of forming a semiconductor structure of claim 1, wherein the protective layer has a thickness of
To
4. The method of forming a semiconductor structure of claim 1, wherein forming the protective layer comprises: forming a protective film which conformally covers the first region of the fin part, wherein the protective film also covers the surface of the isolation structure;
and removing the protective film on the top of the first region of the fin part and the isolation structure by adopting a maskless etching process, and forming a protective layer on the side wall of the first region of the fin part.
5. The method of forming a semiconductor structure according to claim 4, wherein the protective film is formed using an atomic layer deposition process.
6. The method of claim 5, wherein the material of the protective film is silicon nitride, and the atomic layer deposition process comprises the following process parameters: the precursor introduced into the atomic layer deposition chamber is a precursor containing silicon and nitrogen, the process temperature is 400-600 ℃, the pressure is 1-10 mTorr, the gas flow of the precursor is 1500-4000 sccm, and the deposition times are 15-50 times.
7. The method of claim 1, wherein the annealing the second region of the fin is performed using a water vapor anneal.
8. The method of forming a semiconductor structure of claim 1, wherein the annealing process is a water vapor annealing process;
the technological parameters of the water vapor annealing treatment comprise: the reaction gases are hydrogen and oxygen, the annealing temperature is 400-800 ℃, the gas flow of the hydrogen is 1-20 slm, the gas flow of the oxygen is 1-20 slm, and the pressure is one standard atmosphere.
9. The method of forming a semiconductor structure of claim 1, wherein said oxide layer has a thickness of about
To
10. The method of forming a semiconductor structure of claim 1, wherein the protective layer is removed using a wet etch process.
11. The method for forming a semiconductor structure according to claim 10, wherein the protective layer is made of silicon nitride, and the solution used in the wet etching is a phosphoric acid solution.
12. The method of forming a semiconductor structure of claim 1, wherein a material of the dummy gate oxide layer is silicon oxide.
13. The method of forming a semiconductor structure of claim 12, wherein the process of forming said dummy gate oxide layer is an in-situ steam-generated oxidation process.
14. The method of forming a semiconductor structure of claim 13, wherein the process parameters of the in-situ steam-generated oxidation process comprise: providing O2And H2，O2The flow rate is 10sccm to 40sccm, H2The flow rate is 0.2sccm to 2sccm, the chamber temperature is 900 ℃ to 1100 ℃, the chamber pressure is 4Torr to 10Torr, and the process time is 5S to 30S.
15. The method of claim 1, wherein a width of the second region of the fin is 8nm to 16nm after the annealing, and wherein a width of the first region of the fin is 6nm to 14nm after the forming of the dummy gate structure.
16. The method of claim 1, wherein the substrate comprises a peripheral region and a core region, wherein the fin protruding from the substrate in the peripheral region is a first fin, and the fin protruding from the substrate in the core region is a second fin;
in the step of forming the isolation structure on the substrate between the fin portions, the first fin portions exposed out of the isolation structure are used as first fin portion first areas, and the first fin portions not exposed out are used as first fin portion second areas; the first fin parts exposed out of the isolation structure are used as first fin part first areas, and the first fin parts not exposed out of the isolation structure are used as first fin part second areas;
the step of forming a protective layer on the sidewall of the first region of the fin portion includes: forming the protective layer in the first region of the first fin portion and the first region of the second fin portion;
the step of forming a dummy gate structure which crosses the first region of the fin and covers part of the top surface and the side wall surface of the first region of the fin comprises the following steps: forming a first pseudo gate structure which stretches across the first region of the first fin part and covers the partial top surface and the side wall surface of the first region of the first fin part, and forming a second pseudo gate structure which stretches across the first region of the second fin part and covers the partial top surface and the side wall surface of the first region of the second fin part, wherein the first pseudo gate structure comprises a gate oxide layer and a first pseudo gate electrode layer positioned on the surface of the gate oxide layer, and the second pseudo gate structure comprises a gate pseudo gate oxide layer and a second pseudo gate electrode layer positioned on the surface of the pseudo gate oxide layer;
the step of removing the dummy gate structure comprises: removing the first dummy gate electrode layer and the second dummy gate electrode layer, and forming openings in the dielectric layers of the peripheral region and the core region; forming a filling layer filling the opening of the peripheral area; forming a photoresist layer on the filling layer, wherein the photoresist layer also covers the dielectric layer in the peripheral area; and removing the pseudo gate oxide layer at the bottom of the opening of the core region by taking the photoresist layer as a mask.
17. A semiconductor structure formed by the method of forming of any of claims 1-16, comprising:
the substrate comprises a substrate and a fin part protruding out of the substrate;
the isolation structure is positioned on the substrate between the fin parts;
the oxide layer is positioned between the fin part and the isolation structure;
the metal gate structure stretches across the fin part and covers the top surface and the side wall surface of the fin part;
and the dielectric layer is positioned on the substrate between the fin parts and exposes out of the metal grid structure.
18. The semiconductor structure of claim 17, wherein the oxide layer has a thickness value of
To
19. The semiconductor structure of claim 17, wherein the fin exposed to the isolation structure serves as a first region of a fin and the unexposed fin serves as a second region of a fin;
the oxide layer is positioned between the second region of the fin part and the isolation structure;
the metal gate structure crosses over the first region of the fin and covers a portion of the top surface and the sidewall surface of the first region of the fin.
20. The semiconductor structure of claim 19, wherein the width of the second region of the fin is between 8nm and 16nm and the width of the first region of the fin is between 6nm and 14 nm.
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| CN107919284B (en) * | 2016-10-10 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN110473832B (en) * | 2018-05-11 | 2021-11-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof, static random access memory and forming method thereof |
| CN110890279B (en) * | 2018-09-11 | 2023-09-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111162043B (en) * | 2018-11-07 | 2022-12-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111863609B (en) * | 2019-04-30 | 2023-03-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112117191A (en) * | 2019-06-19 | 2020-12-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112670180B (en) * | 2019-10-16 | 2024-08-23 | 长鑫存储技术有限公司 | Memory, semiconductor device and manufacturing method thereof |
| CN111029258A (en) * | 2019-12-03 | 2020-04-17 | 中国科学院微电子研究所 | Fin-shaped structure, semiconductor device and preparation method of semiconductor device |
| CN113497034B (en) * | 2020-03-19 | 2024-07-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112038291A (en) * | 2020-07-24 | 2020-12-04 | 中国科学院微电子研究所 | Manufacturing method of semiconductor device, semiconductor device and electronic equipment |
| CN113948396B (en) * | 2021-09-18 | 2024-09-10 | 上海华力集成电路制造有限公司 | Manufacturing method of fin field effect transistor |
| CN117673083A (en) * | 2022-09-01 | 2024-03-08 | 华为技术有限公司 | Semiconductor device, manufacturing method thereof, chip and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1653608A (en) * | 2002-06-03 | 2005-08-10 | 国际商业机器公司 | Fin FET devices from bulk semiconductor and method for forming |
| CN105097533A (en) * | 2014-05-12 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN105448730A (en) * | 2014-08-30 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method of forming same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103632945B (en) * | 2012-08-29 | 2016-05-25 | 中芯国际集成电路制造(上海)有限公司 | The formation method of fin formula field effect transistor |
| CN105448717A (en) * | 2014-06-26 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
-
2016
- 2016-07-06 CN CN201610527753.7A patent/CN107591362B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1653608A (en) * | 2002-06-03 | 2005-08-10 | 国际商业机器公司 | Fin FET devices from bulk semiconductor and method for forming |
| CN105097533A (en) * | 2014-05-12 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN105448730A (en) * | 2014-08-30 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method of forming same |
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