CN107591362A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN107591362A CN107591362A CN201610527753.7A CN201610527753A CN107591362A CN 107591362 A CN107591362 A CN 107591362A CN 201610527753 A CN201610527753 A CN 201610527753A CN 107591362 A CN107591362 A CN 107591362A
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Abstract
A kind of forming method of semiconductor structure, including：Substrate is provided and protrudes from the fin of substrate；Isolation structure is formed on substrate, is exposed to the fin of isolation structure as fin first area, the fin not exposed is as fin second area；In fin first area, side wall forms protective layer；Fin second area is made annealing treatment, oxide layer is formed in fin second area side wall；Remove protective layer；It is developed across fin first area and covers the pseudo- grid structure of fin first area atop part and sidewall surfaces；Dielectric layer is formed on substrate between fin；Remove pseudo- grid structure.The present invention makes annealing treatment to fin second area after fin first area side wall forms protective layer, reduces the width dimensions of fin second area；The technique for subsequently removing pseudo- grid structure also causes to be lost to isolation structure, part fin second area is exposed, so as to avoid device channel region from broadening.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
With the continuous development of semiconductor process technique, semiconductor technology node follows the development of Moore's Law
Trend constantly reduces.In order to adapt to the reduction of process node, it has to constantly shorten MOSFET field-effects
The channel length of pipe.Tube core density of the shortening of channel length with increase chip, increase MOSFET fields
The benefits such as the switching speed of effect pipe.
However, with the shortening of device channel length, the distance between device source electrode and drain electrode also shortens therewith,
So grid is deteriorated to the control ability of raceway groove so that sub-threshold leakage (subthreshold leakage)
Phenomenon, i.e., so-called short-channel effect (SCE：Short-channel effects) it is easier to occur.
Therefore, in order to preferably adapt to the scaled requirement of device size, semiconductor technology is gradually opened
Begin from planar MOSFET transistor to the transistor transient of the three-dimensional with more high effect, such as fin
Formula FET (FinFET).In FinFET, grid at least can be from both sides to ultra-thin body (fin)
It is controlled, there are the grid more much better than than planar MOSFET devices to the control ability of raceway groove, can be very
Good suppression short-channel effect；And FinFET has more preferable existing integrated electricity relative to other devices
The compatibility of road manufacturing technology.
But the electric property of the semiconductor devices of prior art formation has much room for improvement.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of semiconductor structure and forming method thereof, optimization semiconductor device
The electric property of part.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：There is provided
Substrate, the substrate include substrate and protrude from the fin of the substrate；Lining between the fin
Isolation structure is formed on bottom, the fin of the isolation structure is exposed to as fin first area, does not expose
Fin as fin second area；In the fin first area, side wall forms protective layer；To the fin
Portion's second area is made annealing treatment, and oxide layer is formed in the fin second area side wall；Remove institute
State protective layer；It is developed across the fin first area and the covering fin first area atop part table
Face and the pseudo- grid structure of sidewall surfaces, dummy gate structure include pseudo- gate oxide and positioned at the pseudo- grid
Aoxidize the pseudo- gate electrode layer of layer surface；Dielectric layer, the medium are formed in substrate between the fin
Layer exposes dummy gate structure；Dummy gate structure is removed, is formed in the dielectric layer and exposes the fin
The opening in portion；Metal gate structure is formed in said opening.
Optionally, the material of the protective layer be silicon nitride, carborundum, carbonitride of silicium, carbon silicon oxynitride,
Silicon oxynitride, boron nitride or boron carbonitrides.
Optionally, the thickness of the protective layer isExtremely
Optionally, the step of forming the protective layer includes：Form the conformal covering fin first area
Diaphragm, the diaphragm also covers the isolation structure surface；The step of forming the protective layer is wrapped
Include：The diaphragm of the conformal covering fin first area is formed, the diaphragm also covers the isolation
Body structure surface.
Optionally, the diaphragm is formed using atom layer deposition process.
Optionally, the material of the diaphragm is silicon nitride, the technological parameter of the atom layer deposition process
Including：The presoma being passed through into ald room is the siliceous and presoma of nitrogen, technological temperature 400
Degree Celsius to 600 degrees Celsius, pressure is 1 millitorr to 10 millitorrs, and the gas flow of presoma is 1500sccm
To 4000sccm, frequency of depositing is 15 times to 50 times.
Optionally, the fin second area is made annealing treatment using steam annealing.
Optionally, the annealing makes annealing treatment for steam；The technological parameter of the steam annealing
Including：Reacting gas is hydrogen and oxygen, and annealing temperature is 400 DEG C to 800 DEG C, the gas flow of hydrogen
For 1slm to 20slm, the gas flow of oxygen is 1slm to 20slm, and pressure is a standard atmospheric pressure.
Optionally, the thickness value of the oxide layer isExtremely
Optionally, the protective layer is removed using wet-etching technology.
Optionally, the material of the protective layer is silicon nitride, and the solution that the wet etching uses is phosphoric acid
Solution.
Optionally, the material of the pseudo- gate oxide is silica.
Optionally, the technique for forming the pseudo- gate oxide generates oxidation technology for situ steam.
Optionally, the technological parameter of the situ steam generation oxidation technology includes：O is provided2And H2,
O2Flow is 10sccm to 40sccm, H2Flow is 0.2sccm to 2sccm, and chamber temp is 900 DEG C
To 1100 DEG C, chamber pressure is 4Torr to 10Torr, and the process time is 5S to 30S.
Optionally, after being made annealing treatment to the fin second area, the width of the fin second area
Angle value is 8nm to 16nm, and after forming pseudo- grid structure, the width value of the fin first area is 6nm
To 14nm.
Optionally, the substrate includes peripheral region and core space, protrudes from the fin of the peripheral region substrate
For the first fin, the fin for protruding from the core space substrate is the second fin；Between the fin
In the step of isolation structure is formed on substrate, the first fin of the isolation structure is exposed to as the first fin
Portion first area, the first fin not exposed is as the first fin second area；It is exposed to the isolation junction
First fin of structure is as the first fin first area, and the first fin not exposed is as the first fin second
Region；Include in the fin first area the step of side wall formation protective layer：In first fin
One region and the second fin first area form the protective layer；Be developed across the fin first area and
The step of pseudo- grid structure for covering the fin first area atop part surface and sidewall surfaces, includes：Shape
Into across the first fin first area and covering the first fin first area atop part surface and
First pseudo- grid structure of sidewall surfaces, it is developed across the second fin first area and covering described second
Fin first area atop part surface and the second pseudo- grid structure of sidewall surfaces, the first pseudo- grid structure
The first pseudo- gate electrode layer including gate oxide and positioned at the gate oxide surface, the second pseudo- grid
Structure includes pseudo- gate oxide and the second pseudo- gate electrode layer positioned at the pseudo- gate oxide surface；Remove
The step of dummy gate structure, includes：The described first pseudo- gate electrode layer and the second pseudo- gate electrode layer are removed,
Opening is formed in the dielectric layer of the peripheral region and core space；Form filling out for the full peripheral region opening of filling
Fill layer；Photoresist layer is formed on the packed layer, the photoresist layer also covers Jie of the peripheral region
Matter layer；Using the photoresist layer as mask, the pseudo- gate oxide of the core space open bottom is removed.
Accordingly, the present invention also provides a kind of semiconductor structure, including：Substrate, the substrate include lining
Bottom and the fin for protruding from the substrate；Isolation structure, on the substrate between the fin；Oxygen
Change layer, between the fin and isolation structure；Metal gate structure, across the fin and covering
The fin atop part surface and sidewall surfaces；Dielectric layer, in the substrate between the fin,
The dielectric layer exposes the metal gate structure.
Optionally, the thickness value of the oxide layer isExtremely
Optionally, the fin of the isolation structure is exposed to as fin first area, the fin not exposed
As fin second area；The oxide layer is between the fin second area and isolation structure；Institute
State atop part of the metal gate structure across the fin first area and the covering fin first area
Surface and sidewall surfaces.
Optionally, the width value of the fin second area is 8nm to 16nm, the fin first area
Width value be 6nm to 14nm.
Compared with prior art, technical scheme has advantages below：
After the present invention forms isolation structure on the substrate between the fin, first in fin first area side
Wall forms protective layer, then the fin second area is made annealing treatment, in the area of fin second
Oxide layer is formed in the side wall of domain；The portion of material made annealing treatment for aoxidizing the fin second area,
The width dimensions of the fin second area are made to diminish, and the fin first area is in the protection of protective layer
It is uninfluenced under effect；When forming pseudo- grid structure on fin first area, the oxygen of pseudo- gate oxide is formed
Chemical industry skill can aoxidize the portion of material of the fin first area, make the broad-ruler of the fin first area
It is very little to diminish.Compared to the scheme that pseudo- grid structure is directly formed on fin first area, the present invention can avoid
The problem of fin second area width dimensions are excessive, to reduce fin first area width dimensions
With the difference of fin second area width dimensions；The follow-up technique for removing dummy gate structure also to it is described every
Cause to be lost from structure, expose part fin second area, therefore device channel region can be avoided to broaden
The problem of, so as to avoid the short-channel effect caused by device channel region broadens, and then improve semiconductor device
The electric property of part.
The present invention provides a kind of semiconductor structure, and the semiconductor structure includes being located at fin and isolation structure
Between oxide layer；By the formation process of the oxide layer, it can avoid what device channel region broadened from asking
Topic, so as to avoid the short-channel effect caused by device channel region broadens, and then improve semiconductor device
The electric property of part.
Brief description of the drawings
Fig. 1 to Fig. 3 is each step counter structure schematic diagram in a kind of forming method of semiconductor structure；
Fig. 4 to Figure 16 be semiconductor structure of the present invention the embodiment of forming method one in each step counter structure
Schematic diagram.
Embodiment
From background technology, the electric property for the semiconductor devices that prior art is formed has much room for improvement.Knot
The forming method of unification kind semiconductor structure analyzes its reason.Referring to figs. 1 to Fig. 9, show that one kind is partly led
Structural representation corresponding to each step in the manufacture method of body structure.The forming method of the semiconductor structure
Comprise the following steps：
With reference to figure 1, there is provided substrate, the substrate include substrate 100 and protrude from the substrate 100
Fin.
Specifically, the substrate 100 includes peripheral region I and core space II, protrudes from the peripheral region I
The fin of substrate 100 is the first fin 110, and the fin for protruding from the substrate 100 of core space II is second
Fin 120.
Hard mask layer 200 is also formed with the top of the fin, the hard mask layer 200 is used as and forms the lining
Bottom 100 and the etch mask of fin.
With reference to figure 2, on the substrate 100 between the adjacent fin formed isolation structure 102, it is described every
From the partial sidewall surface that structure 102 covers the fin.
Specifically, the first fin 110 for being exposed to the isolation structure 102 is used as first the firstth area of fin
Domain 111, the first fin 110 not exposed are used as the first fin second area 112；It is exposed to the isolation
Second fin 120 of structure 102 is used as the second fin first area 121, the second fin 120 not exposed
As the second fin second area 122.
The material of the isolation structure 102 is silica.It should be noted that form the isolation structure
After 102, the hard mask layer 200 is removed.
With reference to figure 3, oxidation technology is generated using situ steam, forms the grid for covering first fin 110
Oxide layer 131, and form the pseudo- gate oxide 132 for covering second fin 120, the gate oxide
131 and the material of pseudo- gate oxide 132 be silica..
The oxidation technology can aoxidize the fin first area 121 of the first fin first area 111 and second
Portion of material, so as to cause the fin first area 121 of the first fin first area 111 and second
Width dimensions diminish.Therefore, the width dimensions of the second fin second area 122 are more than described the
The width dimensions of two fin first areas 121.
It should be noted that after forming the gate oxide 131 and pseudo- gate oxide 132, follow-up step
Suddenly also include：The first pseudo- gate electrode layer is formed on the gate oxide 131, in the pseudo- gate oxide
The second pseudo- gate electrode layer is formed on 132；Dielectric layer, the dielectric layer top are formed on the substrate 100
Flushed with the top of the described first pseudo- gate electrode layer and the second pseudo- gate electrode layer；Remove the described first pseudo- grid electricity
Pole layer, the first opening for exposing the gate oxide 131 is formed in the dielectric layer, and described in removal
Second pseudo- gate electrode layer, the second opening for exposing the pseudo- gate oxide 132 is formed in the dielectric layer；
Remove the pseudo- gate oxide 132 of second open bottom；Formed in the described first opening and the second opening
Metal gate structure.
But the technique of the pseudo- gate oxide 132 of second open bottom is removed, part is easily lost
The isolation structure 102 of core space II of thickness, so as to expose part the second fin second area 122；And institute
The width dimensions for stating the second fin second area 122 are more than the width of the second fin first area 121
Size, also just say, be exposed to the width dimensions increase of the first fin 110 of the isolation structure 102,
So as to which the channel region of the semiconductor devices resulted in broadens, channel region broaden easily caused by short channel effect
Should, and then easily cause the electric property of semiconductor devices to decline.
In order to solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided, the substrate includes substrate and protrudes from the fin of the substrate；Between the fin
Substrate on form isolation structure, be exposed to the fin of the isolation structure as fin first area, not
The fin exposed is as fin second area；In the fin first area, side wall forms protective layer；To institute
State fin second area to be made annealing treatment, oxide layer is formed in the fin second area side wall；Go
Except the protective layer；It is developed across the fin first area and covering fin first area part top
Portion surface and the pseudo- grid structure of sidewall surfaces, dummy gate structure include pseudo- gate oxide and positioned at described
The pseudo- gate electrode layer on pseudo- gate oxide surface；Dielectric layer is formed in substrate between the fin, it is described
Dielectric layer exposes dummy gate structure；Dummy gate structure is removed, is formed in the dielectric layer and exposes institute
State the opening of fin；Metal gate structure is formed in said opening.
After the present invention forms isolation structure on the substrate between the fin, first in fin first area side
Wall forms protective layer, then the fin second area is made annealing treatment, in the area of fin second
Oxide layer is formed in the side wall of domain；The portion of material made annealing treatment for aoxidizing the fin second area,
The width dimensions of the fin second area are made to diminish, and the fin first area is in the protection of protective layer
It is uninfluenced under effect；When forming pseudo- grid structure on fin first area, the oxygen of pseudo- gate oxide is formed
Chemical industry skill can aoxidize the portion of material of the fin first area, make the broad-ruler of the fin first area
It is very little to diminish.Compared to the scheme that pseudo- grid structure is directly formed on fin first area, the present invention can avoid
The problem of fin second area width dimensions are excessive, to reduce fin first area width dimensions
With the difference of fin second area width dimensions；The follow-up technique for removing dummy gate structure also to it is described every
Cause to be lost from structure, expose part fin second area, therefore device channel region can be avoided to broaden
The problem of, so as to avoid the short-channel effect caused by device channel region broadens, and then improve semiconductor device
The electric property of part.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Fig. 4 to Figure 16 be semiconductor structure of the present invention the embodiment of forming method one in each step counter structure
Schematic diagram.
With reference to reference to the stereogram (only illustrating two fins) that figure 4 and Fig. 5, Fig. 4 are semiconductor structure,
Fig. 5 is cross-sectional views of the Fig. 4 along AA1 directions, there is provided substrate, the substrate include substrate 300
And protrude from the fin (not indicating) of the substrate 300.
The substrate 300 provides technique platform to be subsequently formed semiconductor devices.It is described in the present embodiment
Substrate 300 includes peripheral region I (as shown in Figure 5) and core space II (as shown in Figure 5)；Accordingly,
The fin for protruding from the substrate 300 of peripheral region I is the first fin 310, protrudes from the core space II and serves as a contrast
The fin at bottom 300 is the second fin 310.
In the present embodiment, the substrate 300 is silicon substrate.In other embodiments, the material of the substrate
Material can also be germanium, SiGe, carborundum, GaAs or gallium indium, and the substrate can also be insulation
The germanium substrate on silicon substrate or insulator on body.
The material of the fin is identical with the material of the substrate 300.In the present embodiment, the fin
Material is silicon；Accordingly, the material of the fin 310 of the first fin 310 and second is silicon.Other realities
Apply in example, the material of the fin can also be germanium, SiGe, carborundum, GaAs or gallium indium；
Accordingly, the material of first fin and the second fin can also be germanium, SiGe, carborundum, arsenic
Change gallium or gallium indium.
Specifically, forming the processing step of the substrate 300 and fin includes：Initial substrate is provided；
The initial substrate surface forms patterned hard mask layer 400 (as shown in Figure 5)；With the hard mask
Layer 400 is initial substrate described in mask etching, and the initial substrate after etching is as substrate 300, positioned at substrate
The projection on 300 surfaces is as fin.
In the present embodiment, after forming the substrate 300 and fin, retain the hard mask at the top of fin
Layer 400.The material of the hard mask layer 400 is silicon nitride, subsequently when carrying out planarization process technique,
The top surface of hard mask layer 400 is used for the stop position for defining planarization process technique, plays protection
Effect at the top of fin.
In the present embodiment, the side wall of the fin and the perpendicular of substrate 300, the i.e. top of fin
Portion's size is equal to bottom size.In other embodiments, the top dimension of the fin is also less than bottom
Portion's size.
It is equal along the direction parallel to the substrate 300, the width dimensions of each fin in the present embodiment.
With reference to reference to figure 6, it is necessary to explanation, formed after the substrate 300 and fin, the formation
Method also includes：Cushion oxide layer 301 is formed on the surface of fin 300, for repairing first fin
The fin 320 of portion 310 and second.
In the present embodiment, the technique for forming the cushion oxide layer 301 is oxidation processing technique.
Because the fin 320 of the first fin 310 and second is the institute by being formed after etching initial substrate
The corner angle and surface of the first fin 310 and the second fin 320 generally with protrusion are stated with defect.In oxygen
Change in processing procedure, due to the ratio of the faceted portions of the fin 320 of the first fin 310 and second protrusion
Surface is bigger, it is easier to it is oxidized, after subsequently removing the cushion oxide layer 301, and not only described the
The defects of one fin 310 and the second 320 surface of fin, layer was removed, and protruded faceted portions and be also removed,
So as to so that the surface of the fin 320 of first fin 310 and second is smooth, lattice quality is changed
It is kind, the first fin 310 and the drift angle point discharge problem of the second fin 320 are avoided, is advantageous to improve fin
The performance of FET.
The oxidation processes can use the mixed of oxygen plasma oxidation technology or sulfuric acid and hydrogen peroxide
Close solution oxide technique.It should be noted that the oxidation processes can also be entered to the surface of substrate 300
Row oxidation so that the cushion oxide layer 301 of formation is also located at the surface of substrate 300.
In the present embodiment, using ISSG (situ steam generates, In-situ Stream Generation) oxidation
Technique carries out oxidation processes to the substrate 300 and fin, forms the cushion oxide layer 301, the lining
The thickness of pad oxide 301 isExtremelyBecause the material of the substrate 300 and fin is silicon,
The material for the cushion oxide layer 301 being correspondingly formed is silica.
With reference to figure 7, isolation structure 302 is formed on the substrate 300 between the fin (not indicating),
The fin for being exposed to the isolation structure 302 (does not indicate) as fin first area, the fin not exposed
(do not indicated) as fin second area.
In the present embodiment, the fin includes the first fin protruded from the substrate 300 of peripheral region I
310, and the second fin 320 protruded from the substrate 300 of core space II.Accordingly, it is exposed to
First fin 310 of the isolation structure 302 is the first fin first area 311, the first fin not exposed
Portion 310 is used as the first fin second area 312；It is exposed to the second fin 320 of the isolation structure 302
For the second fin first area 321, the second fin 320 not exposed is used as the second fin second area 322.
Isolation structure of the isolation structure 302 as semiconductor structure, for adjacent devices are played every
From effect.In the present embodiment, the material of the isolation structure 302 is silica.In other embodiments,
The material of the isolation structure can also be silicon nitride or silicon oxynitride.
It should be noted that in the present embodiment, the isolation structure 302 is shallow groove isolation layer.
Specifically, the step of forming isolation structure 302 includes：In the cushion oxide layer 301
Forerunner's barrier film is formed, the top of forerunner's barrier film is higher than the top of hard mask layer 400；To institute
State forerunner's barrier film and carry out the first annealing, forerunner's barrier film is converted into barrier film；Grinding is gone
Except the barrier film higher than the top of hard mask layer 400；The barrier film for removing segment thickness is isolated with being formed
Structure 302.
In order to improve the filling perforation for the technique to form the barrier film (gap-filling) ability, in the present embodiment,
Forerunner's barrier film is formed using mobility chemical vapor deposition method (FCVD, Flowable CVD).
In another embodiment, can also use high vertical wide than chemical vapor deposition method (HARP CVD) formation institute
State forerunner's barrier film.
It should be noted that after forming the isolation structure 302, retain the hard mask at the top of the fin
Layer 400, the hard mask layer 400, for protecting the fin, avoids institute in follow-up annealing
State and be oxidized at the top of fin.
It should also be noted that, while the barrier film of segment thickness is removed, first fin is also removed
Cushion oxide layer 301 on the fin first area 321 of portion first area 311 and second.
It should also be noted that, in the present embodiment, the top dimension of the fin is equal to bottom size, and
Along parallel on the direction of the substrate 300, the width dimensions of each fin are equal；That is, along flat
Row is on the direction of the substrate 300, the first fin first area 311, the first fin second area
312nd, the width of the second fin first area 321 and the second fin second area 322 is equal.
With reference to figure 8, (do not indicate) side wall in the fin first area and form protective layer 500.
The protective layer 500, for protecting the fin first area, is kept away in follow-up annealing
Exempt from the fin first area to be oxidized.
In the present embodiment, the material of the protective layer 500 is silicon nitride.In other embodiments, it is described
The material of protective layer can also be carborundum, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride
Or boron carbonitrides.
It should be noted that the thickness of the protective layer 500 is unsuitable excessively thin, it is also unsuitable blocked up.If institute
State that the thickness of protective layer 500 is excessively thin, in follow-up annealing, to the guarantor of the fin first area
DeGrain is protected, easily causes the fin first area to be oxidized；Due between the fin away from
From smaller, that is to say, that it is smaller to form the process window of the protective layer 500, in order that the protection
Layer 500 is preferably formed between the fin, and the protective layer 500 is non-porous between the fin
Hole defect, the thickness of the protective layer 500 are unsuitable blocked up.Therefore, in the present embodiment, the protective layer
500 thickness isExtremely
Specifically, the step of forming protective layer 500 includes：Form the conformal covering fin first
The diaphragm in region (not indicating), the diaphragm also cover the surface of isolation structure 302；Using
Without mask etching technique, the diaphragm at the top of the fin first area and on isolation structure 302 is removed,
Protective layer 500 is formed in the side wall of the fin first area.
It should be noted that the fin includes the first fin 310 and the second fin 320；Accordingly, institute
State the side that protective layer 500 is located at the fin first area 321 of the first fin first area 311 and second
On wall.
It should also be noted that, the top of 310 and second fin of the first fin 320 is formed with hard mask
Layer 400；Accordingly, in the step of forming the diaphragm, the also conformal covering of the diaphragm is described to be covered firmly
Film layer 400；In the no mask etching technical process, remove the top of the hard mask layer 400 and every
From the diaphragm in structure 302, in the side wall of the fin first area and the side wall of hard mask layer 400
Upper formation protective layer 500.
In the present embodiment, the diaphragm is formed using atom layer deposition process.Specifically, the atom
The technological parameter of layer depositing operation includes：The presoma being passed through into ald room is siliceous and nitrogen
Presoma.
It should be noted that the technological temperature of the atom layer deposition process is unsuitable too low, it is also unsuitable too high.
When technological temperature is too low, easily cause the deposition velocity of each depositing operation excessively slow, it is described so as to cause
The thinner thickness of diaphragm, or need to increase the process time to reach target thickness value, so as to reduce
State the formation efficiency of diaphragm；When the technological temperature is too high, easily cause the heat point of the presoma
Solution, so as to introduce the phenomenon of similar chemical vapor deposition, and then influence the purity and step of the diaphragm
Spreadability, finally reduce the formation quality of the diaphragm.Therefore, in the present embodiment, technological temperature is
400 degrees Celsius to 600 degrees Celsius.
Based on the technological temperature of the setting, by the gas flow of presoma, chamber pressure and frequency of depositing
It is set in zone of reasonableness value, so as to ensure the high-purity of the diaphragm and good step spreadability, and
The thickness of the diaphragm is set to meet process requirements.Therefore, in this implementation, pressure is 1 millitorr to 10 millis
Support, the gas flow of presoma is 1500sccm to 4000sccm, and frequency of depositing is 15 times to 50 times.
In other embodiments, chemical vapor deposition method or physical gas-phase deposition can also be used,
Form the diaphragm.
With reference to figure 9, annealing 510 is carried out to the fin second area (not indicating), in the fin
Oxide layer 361 is formed in portion's second area side wall.
The annealing 510 is used for the first fin second area 312 and second the secondth area of fin
Domain 322 is aoxidized, and makes part the first fin second area 312 and the second fin second area 322
Material changes into silica by silicon；Therefore, on the direction parallel to the substrate 300, described first
The width dimensions of the fin second area 322 of fin second area 312 and second reduce.
It should be noted that in the present embodiment, the oxide layer 361 includes the cushion oxide layer 301,
And be transformed by the part fin second area 322 of the first fin second area 312 and second
Silicon oxide layer.
It should also be noted that, after carrying out the annealing 510, the width of the fin second area
Value is unsuitable excessive, also unsuitable too small.Subsequently remove the pseudo- grid oxygen on the second fin first area 321
The technique for changing layer, also causes to be lost to the isolation structure 302, so as to expose the fin of part second the
Two regions 322, if the width value of the fin second area is excessive, easily device channel region is caused to broaden,
And then cause short-channel effect；If the width value of the fin second area is too small, easily cause partly to lead
The electric property of body device shifts.Therefore, in the present embodiment, the width of the fin second area
It is worth for 8nm to 16nm, i.e., described first fin second area 312 and the second fin second area 322
Width value be 8nm to 16nm.
It should also be noted that, the degree of oxidation shadow of 510 pairs of fin second areas of the annealing
Ring the width dimensions of the fin second area；Accordingly, described in the thickness effect of the oxide layer 361
The width dimensions of fin second area.In the present embodiment, the thickness value of the oxide layer 361 isExtremely
In the present embodiment, annealing 510 is carried out to the fin second area using steam annealing.Specifically
Ground, the technological parameter of the steam annealing include：Reacting gas is hydrogen and oxygen, pressure one
Individual standard atmospheric pressure.
It should be noted that the gas flow of reacting gas is unsuitable very few, it is also unsuitable excessive.It is if described
The gas flow of reacting gas is very few, easily causes the oxidized degree of the fin second area relatively low,
So as to cause on the direction parallel to the surface of substrate 300, the fin second area width dimensions
The DeGrain of reduction；If the gas flow of the reacting gas is excessive, easily cause excessive fin
Portion's second area is oxidized, and then is caused on the direction parallel to the surface of substrate 300, the fin
Portion's second area width dimensions are too small.Therefore, in the present embodiment, the gas flow of hydrogen for 1slm extremely
20slm, the gas flow of oxygen is 1slm to 20slm.
It should also be noted that, annealing temperature is unsuitable too low, it is also unsuitable too high.The annealing temperature is too low
When, it is excessively slow to the oxidation rate of the fin second area, so as to easily cause parallel to the substrate
On the direction on 300 surfaces, the DeGrain of the fin second area width dimensions reduction；The annealing
It is too fast to the oxidation rate of the fin second area when temperature is too high, easily cause excessive fin
Two regions are oxidized, so as to cause on the direction parallel to the surface of substrate 300, the fin
Two peak widths are undersized.Therefore, in the present embodiment, annealing temperature is 400 DEG C to 800 DEG C.
It should also be noted that, due to the fin first area of the first fin first area 311 and second
Hard mask layer 400, firstth area of fin of the first fin first area 311 and second are formed on 321 top
Matcoveredn 500 is formed in the side wall in domain 321, the hard mask layer 400 and protective layer 500 move back described
The fin first area 321 of the first fin first area 311 and second is protected in fire processing 510, is avoided
The fin first area 321 of first fin first area 311 and second is oxidized；Therefore, along parallel
In on the direction of the substrate 300, the fin first area of the first fin first area 311 and second
321 width dimensions do not change.
With reference to figure 10, the protective layer 500 (as shown in Figure 9) is removed.
In the present embodiment, the protective layer 500 is removed using wet-etching technology.Specifically, the protection
The material of layer 500 is silicon nitride, and the solution that the wet etching uses is phosphoric acid solution.
In other embodiments, dry etch process, or dry etch process and wet method can also be used to carve
The technique that etching technique is combined removes the protective layer.
It should be noted that the material of the hard mask layer 400 (as shown in Figure 9) is silicon nitride, going
Except in the step of protective layer 500, also removing the top of 310 and second fin of the first fin 320
Hard mask layer 400.
With reference to being Figure 11 along fin bearing of trend (BB1 in such as Fig. 4 with reference to figure 11 and Figure 12, Figure 12
Shown in direction) cross-sectional view, be developed across the fin first area (not indicating) and cover
Cover the pseudo- grid structure (not indicating) of the fin first area atop part surface and sidewall surfaces, the puppet
Grid structure includes pseudo- gate oxide 332 (as shown in figure 11) and positioned at the pseudo- table of gate oxide 332
The pseudo- gate electrode (not indicating) in face.
Dummy gate structure takes up space position for the follow-up metal gate structure that carries out.
In the present embodiment, dummy gate structure includes the first pseudo- grid structure, the first pseudo- grid structure across
The first fin first area 311 and the covering atop part surface of the first fin first area 311
And sidewall surfaces, in addition to the second pseudo- grid structure, the second pseudo- grid structure is across second fin
One region 321 and the covering atop part surface of the second fin first area 321 and sidewall surfaces.
In the present embodiment, the substrate 300 includes peripheral region I and core space II；Accordingly, described
One pseudo- grid structure includes gate oxide 331 (as shown in figure 11) and positioned at the table of gate oxide 331
The first pseudo- gate electrode layer 341 (as shown in figure 12) in face, the second pseudo- grid structure include pseudo- gate oxide
332 and the second pseudo- gate electrode layer 342 positioned at the pseudo- surface of gate oxide 332.
The material of the gate oxide 331 and pseudo- gate oxide 332 is silica.The first pseudo- grid electricity
The material of 341 and second pseudo- gate electrode layer 342 of pole layer can be polysilicon, silica, silicon nitride, nitrogen
Silica, carborundum, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.In the present embodiment, described first
The material of pseudo- 341 and second pseudo- gate electrode layer 342 of gate electrode layer is polysilicon.
In the present embodiment, (In-situ Stream Generation, ISSG) oxidation is generated using situ steam
Technique forms the gate oxide 331 and pseudo- gate oxide 332.Specifically, the situ steam generation oxygen
The technological parameter of chemical industry skill includes：O is provided2And H2, O2Flow is 10sccm to 40sccm, H2Stream
Measure as 0.2sccm to 2sccm, chamber temp is 900 DEG C to 1100 DEG C, chamber pressure be 4Torr extremely
10Torr, process time are 5S to 30S.
It should be noted that the fin first area of the oxidation technology by oxidized portion thickness,
To form the gate oxide 331 and pseudo- gate oxide 332；Therefore, the He of gate oxide 331 is formed
After pseudo- gate oxide 332, along parallel on the direction of the substrate 300, the area of the first fin first
The width dimensions of the fin first area 321 of domain 311 and second diminish.In the present embodiment, the grid are formed
After oxide layer 331 and pseudo- gate oxide 332, the width value of the fin first area is 6nm to 14nm,
The width value of the i.e. described fin first area 321 of first fin first area 311 and second be 6nm extremely
14nm。
It should be noted that in the present embodiment, the width value of the fin first area is equal to the fin
The width value of second area, so as to avoid protruding from the fin second area of the isolation structure 302
Influence of the width dimensions to semiconductor devices electric property.
It should also be noted that, after forming the described first pseudo- grid structure and the second pseudo- grid structure, the formation
Method also includes：Side wall 303 is formed in the side wall of the described first pseudo- grid structure and the second pseudo- grid structure；Institute
State in the first fin 310 of the both sides of side wall 303 and form the first source and drain doping area 351, in the side wall 303
The second source and drain doping area 352 is formed in second fin 320 of both sides.
With continued reference to Figure 12, dielectric layer 304, the dielectric layer are formed in the substrate between the fin
304 expose dummy gate structure.
In the present embodiment, the dielectric layer 304 flushes with the described first pseudo- grid structure and the second pseudo- grid structure,
And expose the described first pseudo- pseudo- top of gate electrode layer 342 of gate electrode layer 341 and second.
The material of the dielectric layer 304 is insulating materials, for example, silica, silicon nitride, silicon oxynitride,
Silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.In the present embodiment, the material of the dielectric layer 304 is
Silica.
With reference to reference to figures 13 to Figure 15, Figure 15 is Figure 14 along perpendicular to fin bearing of trend (in such as Fig. 4
Shown in AA1 directions) cross-sectional view, remove dummy gate structure, in the dielectric layer 304
It is interior to form the opening 314 for exposing the fin.
The opening 314 provides locus to be subsequently formed metal gate structure.
In the present embodiment, the first pseudo- grid structure and the second pseudo- grid structure are removed, in the peripheral region I
With the opening 314 of formation in the dielectric layer 304 of core space II.
It should be noted that the substrate 300 includes peripheral region I and core space II, the peripheral region I
Substrate 300 be used for formed peripheral devices (such as：Input/output device), the substrate 300 of core space II
For forming core devices, the operating voltage of core devices is smaller than the operating voltage of peripheral devices, to prevent
The problems such as electrical breakdown, when the operating voltage of device is bigger, it is desirable to the thickness of the gate dielectric layer of device is thicker,
That is, the thickness of the gate dielectric layer for the core space II being subsequently formed is less than the gate dielectric layer of peripheral region I
Thickness.Therefore, in the present embodiment, before the gate dielectric layer of core space II is formed, first described in removal
Pseudo- gate oxide 332 (as shown in figure 13), so that the peripheral devices gate dielectric layer being subsequently formed (is not marked
Show) thickness be more than core devices gate dielectric layer (not indicating) thickness.
Specifically, the step of removing dummy gate structure includes：Remove the described first pseudo- gate electrode layer 341
(as shown in figure 12) and the second pseudo- gate electrode layer 342 (as shown in figure 12), in the He of peripheral region I
314 (as shown in figure 13) of opening are formed in the dielectric layer 304 of core space II；Form the full periphery of filling
The packed layer (not shown) of the opening of area I 314；Photoresist layer (not shown) is formed on the packed layer,
The photoresist layer also covers the dielectric layer 304 of the peripheral region I；Using the photoresist layer as mask, go
Except the pseudo- gate oxide 332 (as shown in figure 13) of 314 bottoms of the core space II opening.
In the present embodiment, the material of the packed layer is ODL (Organic Dielectric Layer) material,
The packed layer is formed using spin coating process, and pushed up at the top of the packed layer with the dielectric layer 304
Portion flushes.In other embodiments, the material of the packed layer can also be BARC (Bottom
Anti-Reflective Coating) material or DUO (Deep UV Light Absorbing Oxide) material.
Wherein, the DUO materials are a kind of siloxane polymer materials, including CH3-SiOX, Si-OH or
SiOH3Deng.
In the present embodiment, the first pseudo- grid structure and the second pseudo- grid structure are removed using dry etch process.
In other embodiments, wet-etching technology or wet-etching technology and dry etching work can also be used
The technique that skill is combined, remove the first pseudo- grid structure and the second pseudo- grid structure.
It should be noted that during the pseudo- gate oxide 332 is removed, easily to the core
The isolation structure 302 in area II causes to be lost, so as to the second fin second area 322 described in exposed portion.
With reference to figure 16, Figure 16 is the structural representation based on Figure 14, in 314 (such as Figure 14 of the opening
It is shown) in formed metal gate structure 324.
The metal gate structure 324 includes the gate dielectric layer on 314 bottoms of the opening and side wall
(not indicating), and the metal level (not indicating) of the full opening 314 of filling.
The material of the gate dielectric layer is high-k gate dielectric material, wherein, high-k gate dielectric material refers to
Relative dielectric constant is more than the gate dielectric material of silica relative dielectric constant.In the present embodiment, the grid
The material of dielectric layer is HfO2.In other embodiments, the material of the gate dielectric layer can also be
HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3。
In the present embodiment, the material of the metal level is W.In other embodiments, the metal level
Material can also be Al, Cu, Ag, Au, Pt, Ni or Ti.
It should be noted that in the present embodiment, the technique of the removal pseudo- gate oxide 132, easily damage
The isolation structure 102 of core space II of segment thickness is consumed, causes to expose part the second fin second area 122；
Because the second fin second area 122 is under the influence of 510 (as shown in Figure 9) are made annealing treatment, edge
Reduce parallel to the width dimensions in the direction on the surface of substrate 300, therefore device channel region can be avoided
The problem of broadening, so as to avoid short-channel effect, and then improve the electric property of semiconductor devices.
With continued reference to Figure 16, the present invention also provides a kind of semiconductor structure, including：
Substrate, the substrate include substrate 300 and protrude from the fin (not indicating) of the substrate 300；
Isolation structure 302, on the substrate 300 between the fin；
Oxide layer 361 (as shown in figure 15), between the fin and isolation structure 302；
Metal gate structure 324, across the fin and the covering fin atop part surface and side wall table
Face；
Dielectric layer 304, in the substrate between the fin, the dielectric layer 304 exposes the metal
Grid structure 324.
In the present embodiment, the substrate 300 includes peripheral region I and core space II；Accordingly, protrude from
The fin of the substrate 300 of peripheral region I is the first fin 310, protrudes from the substrate 300 of core space II
Fin be the second fin 310.
In the present embodiment, the substrate 300 is silicon substrate.In other embodiments, the material of the substrate
Material can also be germanium, SiGe, carborundum, GaAs or gallium indium, and the substrate can also be insulation
The germanium substrate on silicon substrate or insulator on body.
The material of the fin is identical with the material of the substrate 300.In the present embodiment, the fin
Material is silicon；Accordingly, the material of the fin 310 of the first fin 310 and second is silicon.Other realities
Apply in example, the material of the fin can also be germanium, SiGe, carborundum, GaAs or gallium indium；
Accordingly, the material of first fin and the second fin can also be germanium, SiGe, carborundum, arsenic
Change gallium or gallium indium.
Isolation structure of the isolation structure 302 as semiconductor structure, for adjacent devices are played every
From effect.In the present embodiment, the material of the isolation structure 302 is silica.In other embodiments,
The material of the isolation structure can also be silicon nitride or silicon oxynitride.It should be noted that the present embodiment
In, the isolation structure 302 is shallow groove isolation layer.
In the present embodiment, the fin for being exposed to the isolation structure 302 (is not marked as fin first area
Show), the fin not exposed (does not indicate) as fin second area.Accordingly, the oxide layer 301 '
Between the fin second area and isolation structure 302.
In the present embodiment, the width value of the fin second area is 8nm to 16nm, the fin first
The width value in region is 6nm to 14nm.
It should be noted that the fin includes the first fin protruded from the substrate 300 of peripheral region I
Portion 310, and the second fin 320 protruded from the substrate 300 of core space II.Accordingly, expose
In the first fin 310 of the isolation structure 302 be the first fin first area 311, first not exposed
Fin 310 is used as the first fin second area 312；It is exposed to the second fin of the isolation structure 302
320 be the second fin first area 321, and the second fin 320 not exposed is used as the second fin second area
322。
It should also be noted that, the semiconductor structure also includes：Positioned at the substrate 300 and isolation junction
Cushion oxide layer 301 (as shown in figure 15) between structure 302.In the present embodiment, the cushion oxide layer
301 material is silica, and the thickness of the cushion oxide layer 301 isExtremely
It should be noted that in the present embodiment, the oxide layer 361 includes the cushion oxide layer 301,
And the silicon oxide layer being transformed by the part fin second area.Accordingly, the liner oxidation
Layer 301 is also located between the fin second area and isolation structure 302.
It should be noted that the thickness of the oxide layer 361 is unsuitable excessively thin, it is also unsuitable blocked up.Due to portion
The oxide layer 361 is divided to be transformed by the part fin second area, if the oxide layer 361
Thickness it is excessively thin, easily cause the width value close to the fin first area at the top of the isolation structure 302
It is excessive, so as to easily cause device channel region to broaden, and then cause short-channel effect；If the oxidation
The thickness of layer 361 is blocked up, easily causes close to the fin first area at the top of isolation structure 302
Width value is too small, easily causes the electric property of semiconductor devices to shift.Therefore, in the present embodiment,
The thickness value of the oxide layer 361 isExtremely
In the present embodiment, the metal gate structure 324 is across described in the fin first area and covering
The atop part surface of fin first area and sidewall surfaces.The metal gate structure 324 is situated between including grid
Matter layer (does not indicate), and the metal level (not indicating) on the gate dielectric layer.
The material of the gate dielectric layer is high-k gate dielectric material, wherein, high-k gate dielectric material refers to
Relative dielectric constant is more than the gate dielectric material of silica relative dielectric constant.In the present embodiment, the grid
The material of dielectric layer is HfO2.In other embodiments, the material of the gate dielectric layer can also be
HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3。
In the present embodiment, the material of the metal level is W.In other embodiments, the metal level
Material can also be Al, Cu, Ag, Au, Pt, Ni or Ti.
The semiconductor structure includes the oxide layer 361 between fin and isolation structure 302；Pass through institute
The formation process of oxide layer 361 is stated, the problem of device channel region being avoided to broaden, so as to avoid
The short-channel effect caused by device channel region broadens, and then improve the electric property of semiconductor devices.
It should be noted that semiconductor structure of the present invention is formed by the forming method of semiconductor structure of the present invention,
But it is not limited to the forming method.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including：Substrate is provided, the substrate includes substrate and protrudes from the fin of the substrate；Isolation structure is formed on substrate between the fin, the fin for being exposed to the isolation structure is made For fin first area, the fin not exposed is as fin second area；In the fin first area, side wall forms protective layer；The fin second area is made annealing treatment, oxygen is formed in the fin second area side wall Change layer；Remove the protective layer；It is developed across the fin first area and the covering fin first area atop part surface and side The pseudo- grid structure of wall surface, dummy gate structure include pseudo- gate oxide and positioned at the pseudo- gate oxides The pseudo- gate electrode layer on surface；Dielectric layer is formed in substrate between the fin, the dielectric layer exposes dummy gate structure；Dummy gate structure is removed, the opening for exposing the fin is formed in the dielectric layer；Metal gate structure is formed in said opening.
- 2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the protective layer Material is silicon nitride, carborundum, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or carbon Boron nitride.
- 3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the protective layer Thickness isExtremely
- 4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that form the protection The step of layer, includes：The diaphragm of the conformal covering fin first area is formed, the diaphragm is also Cover the isolation structure surface；Using without mask etching technique, the guarantor at the top of the fin first area and on isolation structure is removed Cuticula, protective layer is formed in the side wall of the fin first area.
- 5. the forming method of semiconductor structure as claimed in claim 4, it is characterised in that using atomic layer deposition Product technique forms the diaphragm.
- 6. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that the diaphragm Material is silicon nitride, and the technological parameter of the atom layer deposition process includes：Into ald room The presoma being passed through is the siliceous and presoma of nitrogen, and technological temperature is 400 degrees Celsius to 600 degrees Celsius, Pressure is 1 millitorr to 10 millitorrs, and the gas flow of presoma is 1500sccm to 4000sccm, is sunk Product number is 15 times to 50 times.
- 7. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that annealed using steam The fin second area is made annealing treatment.
- 8. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the annealing Made annealing treatment for steam；The technological parameter of the steam annealing includes：Reacting gas is hydrogen and oxygen, annealing temperature For 400 DEG C to 800 DEG C, the gas flow of hydrogen is 1slm to 20slm, and the gas flow of oxygen is 1slm To 20slm, pressure is a standard atmospheric pressure.
- 9. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the oxide layer Thickness value isExtremely
- 10. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that using wet etching Technique removes the protective layer.
- 11. the forming method of semiconductor structure as claimed in claim 10, it is characterised in that the protective layer Material is silicon nitride, and the solution that the wet etching uses is phosphoric acid solution.
- 12. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the pseudo- gate oxidation The material of layer is silica.
- 13. the forming method of semiconductor structure as claimed in claim 12, it is characterised in that form the pseudo- grid The technique of oxide layer is that situ steam generates oxidation technology.
- 14. the forming method of semiconductor structure as claimed in claim 13, it is characterised in that the situ steam The technological parameter of generation oxidation technology includes：O is provided2And H2, O2Flow is 10sccm to 40sccm, H2Flow is 0.2sccm to 2sccm, and chamber temp is 900 DEG C to 1100 DEG C, chamber pressure 4Torr To 10Torr, the process time is 5S to 30S.
- 15. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that to the fin After two regions are made annealing treatment, the width value of the fin second area is 8nm to 16nm, shape Into after pseudo- grid structure, the width value of the fin first area is 6nm to 14nm.
- 16. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the substrate includes Peripheral region and core space, the fin for protruding from the peripheral region substrate is the first fin, is protruded from described The fin of core space substrate is the second fin；In the step of isolation structure is formed on substrate between the fin, the isolation structure is exposed to The first fin as the first fin first area, the first fin not exposed is as first the secondth area of fin Domain；The first fin of the isolation structure is exposed to as the first fin first area, first not exposed Fin is as the first fin second area；.Include in the fin first area the step of side wall formation protective layer：In first fin first Region and the second fin first area form the protective layer；It is developed across the fin first area and the covering fin first area atop part surface and side The step of pseudo- grid structure of wall surface, includes：It is developed across described in the first fin first area and covering First fin first area atop part surface and the first pseudo- grid structure of sidewall surfaces, it is developed across described Second fin first area and covering the second fin first area atop part surface and sidewall surfaces Second pseudo- grid structure, the first pseudo- grid structure include gate oxide and positioned at the gate oxide surfaces The first pseudo- gate electrode layer, the second pseudo- grid structure includes pseudo- gate oxide and positioned at the pseudo- grid oxygen Change the second pseudo- gate electrode layer of layer surface；The step of removing dummy gate structure includes：Remove the described first pseudo- gate electrode layer and the second pseudo- grid electricity Pole layer, opening is formed in the dielectric layer of the peripheral region and core space；Form the full peripheral region of filling The packed layer of opening；Photoresist layer is formed on the packed layer, the photoresist layer also covers the week The dielectric layer in border area；Using the photoresist layer as mask, the pseudo- grid oxygen of the core space open bottom is removed Change layer.
- A kind of 17. semiconductor structure, it is characterised in that including：Substrate, the substrate include substrate and protrude from the fin of the substrate；Isolation structure, on the substrate between the fin；Oxide layer, between the fin and isolation structure；Metal gate structure, across the fin and the covering fin atop part surface and sidewall surfaces；Dielectric layer, in the substrate between the fin, the dielectric layer exposes the metal gates knot Structure.
- 18. semiconductor structure as claimed in claim 17, it is characterised in that the thickness value of the oxide layer isExtremely
- 19. semiconductor structure as claimed in claim 17, it is characterised in that be exposed to the fin of the isolation structure Portion is as fin first area, and the fin not exposed is as fin second area；The oxide layer is between the fin second area and isolation structure；The metal gate structure is across the fin first area and the portion of the covering fin first area Divide top surface and sidewall surfaces.
- 20. semiconductor structure as claimed in claim 19, it is characterised in that the width of the fin second area It is worth for 8nm to 16nm, the width value of the fin first area is 6nm to 14nm.
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