CN107275213A - The manufacture method of semiconductor structure - Google Patents
The manufacture method of semiconductor structure Download PDFInfo
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- CN107275213A CN107275213A CN201610216872.0A CN201610216872A CN107275213A CN 107275213 A CN107275213 A CN 107275213A CN 201610216872 A CN201610216872 A CN 201610216872A CN 107275213 A CN107275213 A CN 107275213A
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- 238000000034 method Methods 0.000 title claims abstract description 90
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 239000000463 material Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 230000003667 anti-reflective effect Effects 0.000 claims abstract description 33
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 25
- 238000011049 filling Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 52
- 239000007789 gas Substances 0.000 claims description 50
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 230000008569 process Effects 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- 238000001039 wet etching Methods 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 230000008859 change Effects 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 claims 1
- 238000001312 dry etching Methods 0.000 claims 1
- 230000009931 harmful effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 391
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 230000000694 effects Effects 0.000 description 14
- 230000003647 oxidation Effects 0.000 description 14
- 238000007254 oxidation reaction Methods 0.000 description 14
- 230000002093 peripheral effect Effects 0.000 description 13
- 230000004888 barrier function Effects 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 238000000926 separation method Methods 0.000 description 7
- 238000010276 construction Methods 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 229910052582 BN Inorganic materials 0.000 description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 229910010038 TiAl Inorganic materials 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- PPWPWBNSKBDSPK-UHFFFAOYSA-N [B].[C] Chemical compound [B].[C] PPWPWBNSKBDSPK-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000005416 organic matter Substances 0.000 description 2
- 230000001936 parietal effect Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910015345 MOn Inorganic materials 0.000 description 1
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011538 cleaning material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of manufacture method of semiconductor structure, including：Offer includes the substrate and the fin on substrate of first area and second area；The pseudo- grid structure of fin portion surface formation first in first area, including the first pseudo- gate electrode layer, and in the pseudo- grid structure of fin portion surface formation second of second area, including the second pseudo- gate electrode layer；Dielectric layer is formed on substrate；The first pseudo- gate electrode layer and the second pseudo- gate electrode layer are removed, the first opening and the second opening is formed in dielectric layer respectively；In the second opening sidewalls formation sacrifice layer；The filling anti-reflective film in the first opening and the second opening；The anti-reflective film in the second opening is removed, patterned anti-reflecting layer is formed.The present invention is before filling anti-reflective film; in the second opening sidewalls formation sacrifice layer; sacrifice layer can protect the material layer of the second opening sidewalls; the technique for avoiding the formation of patterned anti-reflecting layer produces harmful effect to the quality of the material layer of the second opening sidewalls, and then improves the electric property of semiconductor devices.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of manufacture method of semiconductor structure.
Background technology
In semiconductor fabrication, with the development trend of super large-scale integration, integrated circuit feature chi
Very little lasting reduction.For the reduction of meeting market's demand size, the channel lengths of MOSFET FETs also phase
Should constantly it shorten.However, with the shortening of device channel length, the distance between device source electrode and drain electrode
Shorten therewith, therefore grid is deteriorated therewith to the control ability of raceway groove, grid voltage pinch off (pinch off)
The difficulty of raceway groove is also increasing so that sub-threshold leakage (subthreshold leakage) phenomenon, i.e. institute
Short-channel effect (the SCE of meaning：Short-channel effects) it is easier to occur.
Therefore, for the reduction of more preferable meeting market's demand size, semiconductor technology gradually starts from plane
Mosfet transistor is to the transistor transient of the three-dimensional with more high effect, such as fin field effect
Manage (FinFET).In FinFET, grid can be at least controlled from both sides to ultra-thin body (fin),
With control ability of the grid more much better than than planar MOSFET devices to raceway groove, it can be good at suppressing short
Channelling effect；And FinFET is relative to other devices, with more preferable existing production of integrated circuits technology
Compatibility.
Fin field effect pipe is broadly divided into core (Core) device and periphery (I/O) device according to function distinguishing
Part (or being input/output device).Distinguished according to the conductivity type of fin field effect pipe, core devices can
It is divided into core nmos device and core PMOS device, peripheral devices can be divided into periphery nmos device
With periphery P MOS device.
Under normal circumstances, much bigger than the operating voltage of core devices of the operating voltage of peripheral devices.It is anti-
Only the problems such as electrical breakdown, when the operating voltage of device is bigger, it is desirable to which the thickness of the gate dielectric layer of device is got over
Thickness, therefore, the thickness of the gate dielectric layer of peripheral devices are typically larger than the thickness of the gate dielectric layer of core devices.
But, the electric property of the semiconductor devices of prior art formation has much room for improvement.
The content of the invention
The problem of present invention is solved is to provide a kind of manufacture method of semiconductor structure, improves semiconductor devices
Electric property.
To solve the above problems, the present invention provides a kind of manufacture method of semiconductor structure.Including following step
Suddenly：Semiconductor base is provided, the semiconductor base includes substrate and the fin on the substrate,
The substrate includes first area and second area；Fin portion surface formation first in the first area is pseudo-
Grid structure simultaneously forms the second pseudo- grid structure in the fin portion surface of the second area, wherein, described first is pseudo-
Grid structure includes gate oxide and the first pseudo- gate electrode layer, and the described second pseudo- grid structure includes pseudo- gate oxide
With the second pseudo- gate electrode layer；Dielectric layer, the dielectric layer and the described first pseudo- grid are formed over the substrate
Structure and the second pseudo- grid structure flush and expose the described first pseudo- gate electrode layer and the second pseudo- gate electrode layer；Go
Except the described first pseudo- gate electrode layer, the first opening is formed in the dielectric layer, the described second pseudo- grid are removed
Electrode layer, forms the second opening in the dielectric layer；In second opening sidewalls formation sacrifice layer；
Formed after the sacrifice layer, the filling anti-reflective film in the described first opening and the second opening；Remove described
Anti-reflective film in second opening, forms patterned anti-reflecting layer；Using the anti-reflecting layer as mask,
Remove the sacrifice layer of second opening sidewalls and the pseudo- gate oxide of the second open bottom；Remove described
After the pseudo- gate oxide of two open bottoms, the anti-reflecting layer in first opening is removed；In the grid oxygen
Change and form gate dielectric layer on layer surface, the bottom of the first opening sidewalls and the second opening and side wall；Institute
State in the first opening and the second opening and fill metal level.
Compared with prior art, technical scheme has advantages below：
The present invention is opened after the described first pseudo- gate electrode layer and the second pseudo- gate electrode layer is removed described first
In mouth and the second opening before filling anti-reflective film, sacrifice layer is formed in second opening sidewalls, it is described
Sacrifice layer can be protected to the material layer of second opening sidewalls, it is to avoid form patterned anti-reflective
The technique for penetrating layer produces harmful effect to the quality of the material layer of second opening sidewalls, it is also possible that
The second grid structure formed in the second opening has higher width uniformity, and second grid structure
Sidewall profile is good, and then improves the electric property of semiconductor devices.
In alternative, the sacrifice layer is also formed into first opening sidewalls, and hence it is also possible to
During removing the anti-reflecting layer in first opening, the material layer to first opening sidewalls rises
To protective effect, the electric property of semiconductor devices is further improved.
Brief description of the drawings
Fig. 1 to Fig. 4 is the corresponding structural representation of each step of manufacture method of prior art semiconductor structure；
Fig. 5 to Figure 21 be semiconductor structure of the present invention the embodiment of manufacture method one in each step counter structure
Schematic diagram.
Embodiment
The electrical property of the semiconductor devices of prior art is poor, and it is analyzed with reference to semiconductor structure manufacture method
Reason.Referring to figs. 1 to Fig. 4, show that each step of manufacture method of prior art semiconductor structure is corresponding
Structural representation.The manufacture method of the semiconductor structure comprises the following steps：
With reference to Fig. 1, semiconductor base is formed, the semiconductor base includes substrate 100 and positioned at described
Fin on substrate 100；The substrate 100 includes first area I and second area II, positioned at described
Fin on the substrate 100 of first area I is the first fin 110, positioned at the substrate 100 of second area II
On fin be the second fin 120.The first area I is used to form peripheral devices, the second area
II is used to form core devices.
Specifically, the semiconductor base is also including being located at the first pseudo- grid structure of the first area I (not
Sign), the second pseudo- grid structure (not indicating) positioned at the second area II, positioned at the described first pseudo- grid
The first area source region of structure both sides or drain region 113, and second positioned at the described second pseudo- grid structure both sides
Region source region or drain region 123.Wherein, the described first pseudo- grid structure includes being located at the table of the first fin 110
The gate oxide 111 in face and the first pseudo- gate electrode layer 112 positioned at the surface of gate oxide 111, it is described
Second pseudo- grid structure is included positioned at the pseudo- gate oxide 121 on the surface of the second fin 120 and positioned at described
The pseudo- gate electrode layer 122 of the second of the pseudo- surface of gate oxide 121.It is described that the semiconductor base also includes covering
The dielectric layer 130 of first pseudo- grid structure and the second pseudo- grid structure.
With reference to Fig. 2, etching removes the described first pseudo- gate electrode layer 112 (as shown in Figure 1), is being given an account of
The first opening 200 is formed in matter layer 130；The described second pseudo- gate electrode layer 122 (as shown in Figure 1) is removed,
The second opening 210 is formed in the dielectric layer 130.
With reference to Fig. 3, in the described first 200 (as shown in Figure 2) of opening and second 210 (such as Fig. 2 of opening
It is shown) in filling anti-reflective film 300, the anti-reflective film 300 also covers the surface of dielectric layer 130；
Graph layer (not shown) is formed on the surface of anti-reflective film 300.
With reference to Fig. 4, using the graph layer as mask, the graphical anti-reflective film 300, described first
Region I forms anti-reflecting layer 301.
The operating voltage of core devices is smaller than the operating voltage of peripheral devices, the problems such as to prevent electrical breakdown,
When the operating voltage of device is bigger, it is desirable to which the thickness of the gate dielectric layer of device is thicker.Therefore, being formed
It is first mask with the graph layer and anti-reflecting layer 301 before the gate dielectric layer of second area II, etching
The pseudo- gate oxide 121 of 210 bottoms of the second opening is removed, so that the peripheral devices grid being subsequently formed
The thickness of dielectric layer (not indicating) is more than the thickness of core devices gate dielectric layer (not indicating).
But, after the graphical anti-reflective film 300 (as shown in Figure 3) is to form anti-reflecting layer 301,
Second opening, 210 contents tend to have anti-reflecting layer residue 311, and the anti-reflecting layer residue 311
It is difficult to remove；In addition, the anti-reflecting layer residue 311 can also influence follow-up to the pseudo- gate oxide
121 etching technics, causes to be difficult to by the pseudo- gate oxide 121 that the anti-reflecting layer residue 311 is covered
Remove, so as to influence the formation quality of follow-up second grid structure.
It has been investigated that, formed after the anti-reflecting layer 301, can be to the described second opening 210 (as schemed
Shown in 2) cleaning processing is carried out, to remove the anti-reflecting layer residue 311, still, at the cleaning
Material layer of the reason easily to the described second 210 side walls of opening has undesirable effect, so as to cause semiconductor device
The decline of the electrical property of part.
In order to solve the technical problem, the present invention provides a kind of manufacture method of semiconductor devices, including：
Semiconductor base is provided, the semiconductor base includes substrate and the fin on the substrate, institute
Stating substrate includes first area and second area；The pseudo- grid of fin portion surface formation first in the first area
Structure simultaneously forms the second pseudo- grid structure in the fin portion surface of the second area, wherein, the described first pseudo- grid
Structure includes gate oxide and the first pseudo- gate electrode layer, the described second pseudo- grid structure include pseudo- gate oxide and
Second pseudo- gate electrode layer；Dielectric layer, the dielectric layer and the described first pseudo- grid knot are formed over the substrate
Structure and the second pseudo- grid structure flush and expose the described first pseudo- gate electrode layer and the second pseudo- gate electrode layer；Remove
Described first pseudo- gate electrode layer, forms the first opening in the dielectric layer, removes the described second pseudo- grid electricity
Pole layer, forms the second opening in the dielectric layer；In second opening sidewalls formation sacrifice layer；Shape
Into after the sacrifice layer, the filling anti-reflective film in the described first opening and the second opening；Remove described
Anti-reflective film in two openings, forms patterned anti-reflecting layer；Using the anti-reflecting layer as mask, go
Except the sacrifice layer and the pseudo- gate oxide of the second open bottom of second opening sidewalls；Remove described second
After the pseudo- gate oxide of open bottom, the anti-reflecting layer in first opening is removed；In the gate oxidation
Gate dielectric layer is formed on layer surface, the bottom of the first opening sidewalls and the second opening and side wall；Described
Metal level is filled in first opening and the second opening.
The present invention is opened after the described first pseudo- gate electrode layer and the second pseudo- gate electrode layer is removed described first
In mouth and the second opening before filling anti-reflective film, sacrifice layer is formed in second opening sidewalls, it is described
Sacrifice layer can be protected to the material layer of second opening sidewalls, it is to avoid form patterned anti-reflective
The technique for penetrating layer produces harmful effect to the quality of the material layer of second opening sidewalls, it is also possible that
The second grid structure formed in the second opening has higher width uniformity, and second grid structure
Sidewall profile is good, and then improves the electric property of semiconductor devices.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Fig. 5 to Figure 21 be semiconductor structure of the present invention the embodiment of manufacture method one in each step counter structure
Schematic diagram.
With reference to reference to Fig. 5 and Fig. 6, Fig. 6 be cross-sectional views of the Fig. 5 along AA1 directions there is provided
Semiconductor base, the semiconductor base includes substrate 400 and the fin on the substrate 400,
The substrate 400 includes first area I (as shown in Figure 6) and second area II (as shown in Figure 6).
In the present embodiment, the fin on the substrate 400 of first area I is the first fin 410, position
In the fin on the substrate 400 of second area II be the second fin 420.
In the present embodiment, the first area I is used to form peripheral devices (for example：Input/output device),
The second area II is used to form core devices.The first area I can be N-type region or p type island region,
The second area II can be N-type region or p type island region, the first area I and the type of second area II
It is identical.
The material of the substrate 400 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium, institute
It can also be the silicon substrate on insulator or the germanium substrate on insulator to state substrate 400；First fin
The material of the fin 420 of portion 410 and second includes silicon, germanium, SiGe, carborundum, GaAs or gallium
Indium.In the present embodiment, the substrate 400 is silicon substrate, the fin 420 of the first fin 410 and second
Material be silicon.
Specifically there is provided include the step of the semiconductor base：Initial substrate is provided, described initial
Patterned hard mask layer 500 is formed in substrate；It is mask with the hard mask layer 500, etches described first
Primordium bottom, forms some discrete projections；The projection is that the initial substrate after fin, etching is used as lining
Bottom 400, the substrate 400 includes first area I and second area II, positioned at the first area I
Fin is the first fin 410, is the second fin 420 positioned at the fin of the second area II.
In the present embodiment, the material of the hard mask layer 500 is silicon nitride, is subsequently carrying out flat chemical industry
During skill, the surface of hard mask layer 500 can as flatening process stop position, and described cover firmly
Film layer 500 can also play a part of the protection top of the first fin 410 and the top of the second fin 420.
With reference to reference Fig. 7, it is necessary to which what is illustrated is to provide after the semiconductor base, the manufacture method
Also include：Liner oxidation layer 401 is formed on the surface of 410 and second fin of the first fin 420, is used for
Repair the fin 420 of the first fin 410 and second.
In oxidation processes, the corner angle protruded due to the fin 420 of the first fin 410 and second
Partial ratio surface is bigger, it is easier to be oxidized, after subsequently removing liner oxidation layer 401, no
The defect layer on the only described surface of first fin, 410 and second fin 420 is removed, and protrusion faceted portions
Also it is removed, makes that the surface of the fin 420 of the first fin 410 and second is smooth, lattice quality is obtained
Improve, it is to avoid the drift angle point discharge problem of 410 and second fin of the first fin 420, be conducive to changing
The performance of kind fin field effect pipe.
In the present embodiment, the liner oxidation layer 401 is also located at the surface of substrate 400, described linear
The material of oxide layer 401 is silica.
With reference to reference Fig. 8, it is necessary to which explanation, is formed after the liner oxidation layer 401, the manufacture
Method also includes：Separation layer 402 is formed on the surface of substrate 400.
The separation layer 402 as semiconductor structure isolation structure, for being played between adjacent devices
Buffer action, the material of the separation layer 402 can be silica, silicon nitride or silicon oxynitride.This reality
Apply in example, the material of the separation layer 402 is silica.
It should be noted that in the present embodiment, the separation layer 402 is shallow groove isolation layer, but is not limited
In shallow groove isolation layer.
Specifically, the step of forming separation layer 402 includes：On 401 surface of liner oxidation layer
Form barrier film, the top top (as shown in Figure 7) higher than the hard mask layer 500 of the barrier film；
Grinding removes the barrier film higher than the top of hard mask layer 500；The barrier film of segment thickness is removed with shape
Into separation layer 402；Remove the hard mask layer 500.
It should be noted that also removing part fin portion surface during the barrier film of segment thickness is removed
Liner oxidation layer 401.
With reference to Fig. 9, Fig. 9 is the cross-sectional view along BB1 (as shown in Figure 5) direction, described
The fin portion surface of first area I forms the first pseudo- grid structure (not indicating) and in the second area II
The pseudo- grid structure (not indicating) of fin portion surface formation second, wherein, the described first pseudo- grid structure includes gate oxidation
The pseudo- gate electrode layer 413 of layer 411 and first, the described second pseudo- grid structure includes pseudo- gate oxide 421 and second
Pseudo- gate electrode layer 423.
The first pseudo- grid structure and the second pseudo- grid structure is are subsequently formed first grid structure and second grid
Structure takes up space position.
In the present embodiment, the fin positioned at the substrate 400 of first area I is the first fin 410, is located at
The fin of the substrate 400 of second area II is the second fin 420.Accordingly, the described first pseudo- grid are formed
In the step of structure and the second pseudo- grid structure, the first pseudo- grid structure is formed on the surface of the first fin 410
(not indicating) and the second pseudo- grid structure (not indicating) is formed on the surface of the second fin 420.
In the present embodiment, the described first pseudo- grid structure is across the surface of the first fin 410 and covering is described
The atop part surface of first fin 410 and sidewall surfaces, including gate oxide 411, and the gate oxidation
The first pseudo- gate electrode layer 413 on 411 surface of layer；Described second pseudo- grid structure is across second fin 420
Surface and the covering atop part surface of the second fin 420 and sidewall surfaces, including pseudo- gate oxide 421,
And the second pseudo- gate electrode layer 423 on the surface of pseudo- gate oxide 421.
The material of the gate oxide 411 and pseudo- gate oxide 421 is silica, the described first pseudo- grid electricity
The material of the pseudo- gate electrode layer 423 of pole layer 413 and second is polysilicon, silica, silicon nitride, nitrogen oxidation
Silicon, carborundum, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.In the present embodiment, the described first pseudo- grid
The material of the pseudo- gate electrode layer 423 of electrode layer 413 and second is polysilicon.
Specifically, the step of forming described first pseudo- grid structure and the second pseudo- grid structure includes：Form covering
The pseudo- gate oxidation films of the fin 420 of first fin 410 and second；In the pseudo- gate oxidation films surface shape
Into pseudo- gate electrode film；Planarization process is carried out to the pseudo- gate electrode film；On the pseudo- gate electrode film surface
Form the first graph layer 510；It is mask with first graph layer 510, the graphical pseudo- gate electrode film
With pseudo- gate oxidation films, gate oxide 411 is formed on the surface of the first fin 410, in the gate oxide
411 surfaces form the first pseudo- gate electrode layer 413, and pseudo- gate oxide is formed on the surface of the second fin 420
421, the second pseudo- gate electrode layer 423 is formed on the pseudo- surface of gate oxide 421；Remove first figure
Shape layer 510.
In the present embodiment, first graph layer 510 is hard mask layer, first graph layer 510
Material is silicon nitride.
With reference to reference Figure 10, it is necessary to which explanation, forms the described first pseudo- grid structure and the second pseudo- grid structure
Afterwards, the manufacture method also includes：In the described first pseudo- grid structure side wall formation side of first area first
Parietal layer 414, in the described second pseudo- grid structure side wall formation second area the first side wall layer 424.
The material of first area the first side wall layer 414 and second area the first side wall layer 424 can be
Silica, silicon nitride, carborundum, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or carbon
Boron nitride, the first area the first side wall layer 414 and second area the first side wall layer 424 can be single
Rotating fields or laminated construction.In the present embodiment, the first area the first side wall layer 414 and second area
The first side wall layer 424 is single layer structure, the first area the first side wall layer 414 and second area first
The material of side wall layer 424 is silicon nitride.
With reference to Figure 11 is referred to, the manufacture method also includes：In first area the first side wall layer 414
Surface forms first area second sidewall layer 415, is formed on 424 surface of second area the first side wall layer
Second area second sidewall layer 425；The is formed in the first fin 410 of the described first pseudo- grid structure both sides
One regional stress layer 416, second area is formed in the second fin 420 of the described second pseudo- grid structure both sides
Stressor layers 426；First area source region or drain region (not shown) are formed in the first area stressor layers 416,
Second area source region or drain region (not shown) are formed in the second area stressor layers 426.
The first area second sidewall layer 415 and the material of second area second sidewall layer 425 can be
Silica, silicon nitride, carborundum, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or carbon
Boron nitride, the first area second sidewall layer 415 and second area second sidewall layer 425 can be single
Rotating fields or laminated construction.In the present embodiment, the first area second sidewall layer 415 and second area
Second sidewall layer 425 is single layer structure, the first area second sidewall layer 415 and second area second
The material of side wall layer 425 is silicon nitride.
With reference to Figure 12, on the substrate 400 formed dielectric layer 460, the dielectric layer 460 with it is described
First pseudo- grid structure and the second pseudo- grid structure flush and expose the described first pseudo- puppet of gate electrode layer 413 and second
Gate electrode layer 423.
The material of the dielectric layer 460 be insulating materials, for example, silica, silicon nitride, silicon oxynitride,
Silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.In the present embodiment, the material of the dielectric layer 460 is
Silica.
In the present embodiment, the dielectric layer 460 is laminated construction, including on the substrate 400
First medium layer 440, and the second dielectric layer 450 positioned at 440 surface of first medium layer.Wherein,
The consistency of the second dielectric layer 450 is more than the consistency of first medium layer 440, so that flat
The surface flatness of the second dielectric layer 450 is improved in smooth chemical industry skill.
It should be noted that before the dielectric layer 460 is formed, the manufacture method also includes：
Etching barrier layer 430 is formed on the substrate 400, it is pseudo- that the etching barrier layer 430 also covers described first
Grid body structure surface and the second pseudo- grid body structure surface.
The etching barrier layer 430 is used for as the etching stop layer in the etching technics of subsequent touch hole, and
It is used as the stop position of subsequent planarization technique.In the present embodiment, the material of the etching barrier layer 430
For silicon nitride.
Specifically, the step of forming dielectric layer 460 includes：Formed after the etching barrier layer 430,
Full first medium film is filled on substrate 400 between the fin and fin, the first medium film is also
Cover the described first pseudo- grid structure and the second pseudo- grid structure, and higher than described the at the top of the first medium film
The one pseudo- top of gate electrode layer 413 and the second pseudo- top of gate electrode layer 423；Planarize the first medium film
Until exposing the top surface of etching barrier layer 430；It is etched back to remove the first medium film of segment thickness
To form first medium layer 440；Second medium film, described the are formed on 440 surface of first medium layer
Second medium film also covers the described first pseudo- grid structure and the second pseudo- grid body structure surface, and the second medium film
Top is higher than the described first pseudo- top of gate electrode layer 413 and the second pseudo- top of gate electrode layer 423；Planarization
The second medium film is until expose the described first pseudo- top surface of gate electrode layer 413 and the second pseudo- gate electrode
423 top surface of layer, to form second dielectric layer 450.
It should be noted that while the second medium film is planarized, also removing and being located at described first
The pseudo- top of gate electrode layer 413 and the etching barrier layer 430 at the second pseudo- top of gate electrode layer 423, make what is formed
The top of second dielectric layer 450 and the described first pseudo- pseudo- gate electrode layer 423 of gate electrode layer 413 and second
Top is flushed.
With reference to Figure 13, the described first pseudo- gate electrode layer 413 (as shown in figure 12) is removed, in the medium
The first opening 600 is formed in layer 460, the described second pseudo- gate electrode layer 423 (as shown in figure 12) is removed,
The second opening 610 is formed in the dielectric layer 460.
In the present embodiment, in the processing step with along with, etching removes the described first pseudo- gate electrode layer 412
With the second pseudo- gate electrode layer 422.
In the present embodiment, using dry etch process, wet etching or dry etch process and wet etching
The technique being combined, etching removes the described first pseudo- pseudo- gate electrode layer 423 of gate electrode layer 413 and second.Its
In, because the etching technics has to the described first pseudo- pseudo- gate electrode layer 423 of gate electrode layer 413 and second
There is higher etching selection ratio, that is to say, that the etching technics is to the described first pseudo- He of gate electrode layer 413
The etch rate of second pseudo- gate electrode layer 423 is more than the etch rate to the dielectric layer 460, so that
When etching removes the described first pseudo- puppet of gate electrode layer 413 and second gate electrode layer 423, it can reduce to institute
State the loss of dielectric layer 460.
With reference to Figure 14, in the side wall formation sacrifice layer 620 of the described second opening 610.
The sacrifice layer 620 is used for the material layer that second opening, 610 side walls are protected in subsequent technique,
Protect the second area the first side wall layer 424, it is to avoid follow-up technique is to the side of second area first
Parietal layer 424 has undesirable effect.
In the present embodiment, the sacrifice layer 620 is also formed into the side wall of first opening 600.
In the present embodiment, the material of the sacrifice layer 620 is silica, forms the sacrifice layer 620
Technique is atom layer deposition process.
Specifically, the technological parameter of the atom layer deposition process includes：It is passed through into ald room
Presoma be siliceous presoma, technological temperature be 100 degrees Celsius to 500 degrees Celsius, pressure is 5
Millitorr is to 20 supports, and frequency of depositing is 5 times to 40 times.
Wherein, when technological temperature is less than 100 degrees Celsius, it is easily caused the deposition speed of each depositing operation
Spend it is slow, so as to cause the thinner thickness of the sacrifice layer 620, or need the increase process time with up to
To target thickness value, so as to reduce the formation efficiency of the sacrifice layer 620；When the technological temperature is higher than
At 500 degrees Celsius, the thermal decomposition of the presoma is easily caused, so as to introduce similar chemical vapor deposition
Phenomenon, and then the purity and step coverage of the sacrifice layer 620 are influenceed, finally reduce the sacrifice layer
620 formation quality.
Based on the technological temperature of the setting, chamber pressure, gas flow and frequency of depositing are set in conjunction
Manage in value range, it is to avoid the phenomenon of similar chemical vapor deposition occurs, so as to ensure the sacrifice layer 620
High-purity and good step spreadability, and then improve the formation quality of the sacrifice layer 620.
It should be noted that the thickness of the sacrifice layer 620 is unsuitable blocked up, it is also unsuitable excessively thin.If institute
The thickness for stating sacrifice layer 620 is excessively thin, is easily removed in subsequent technique, so as to be difficult to play protection institute
State the effect of second area the first side wall layer 424；Further, since first opening 600 and second is opened
The opening size of mouth 610 is limited, that is to say, that the process window for forming the sacrifice layer 620 is limited,
If the thickness of the sacrifice layer 620 is blocked up, the sacrifice layer 620 is in the described first opening 600 and the
Taken up space in two openings 610 excessive, be easily caused and be subsequently difficult to be formed in the described first opening 600
Anti-reflective film, and cause the waste of manufacturing cost.Therefore, in the present embodiment, the sacrifice layer 620
Thickness isExtremely
It should be noted that by the atom layer deposition process, the also conformal covering of the sacrifice layer 620
The surface of pseudo- gate oxide 421, the first 600 bottoms of opening, and the sacrifice layer 620 also covers institute
State the surface of dielectric layer 460.
With reference to Figure 15, in the described first 600 (as shown in figure 14) of opening and the second opening 610 (as schemed
Shown in 14) interior filling anti-reflective film 520.
The anti-reflective film 520 is used to reduce standing wave effect, to improve photoetching quality.In the present embodiment,
The anti-reflective film 520 also covers the surface of dielectric layer 460.
The anti-reflective film 520 is organic material.In the present embodiment, using chemical vapor deposition method shape
Into the anti-reflective film 520.
It should be noted that the manufacture method also includes：Formed and schemed on the surface of anti-reflective film 520
Shape layer 530.
The graph layer 530 is used as the etch mask of the subsequent patterning anti-reflective film 520, also conduct
The etching for subsequently removing the pseudo- gate oxide 421 of described second opening, 610 (as shown in figure 13) bottoms is covered
Film.
In the present embodiment, the material of the graph layer 530 is photoresist.
With reference to Figure 16 and Figure 17 is referred to, the anti-reflective film 520 in second opening 610 is removed (as schemed
Shown in 15), form patterned anti-reflecting layer 521.
Specifically, be mask with the graph layer 530, etching remove it is described second opening 610 in and
The anti-reflective film 520 on the surface of dielectric layer 460 of the second area II, forms patterned anti-reflecting layer
521。
It should be noted that formed by the etching technics after the patterned anti-reflecting layer 521,
Second opening, 610 contents tend to have anti-reflecting layer residue 522.
Accordingly, the step of forming patterned anti-reflecting layer 521 includes：Remove second opening 610
Interior anti-reflective film 520 (as shown in figure 15), forms patterned anti-reflecting layer 521, wherein, it is described
There is anti-reflecting layer residue 522 (as shown in figure 15) in second opening 610；It is open to described second
610 carry out cleaning processing, remove the anti-reflecting layer residue 522 in second opening 610.
In the present embodiment, using plasma dry etch process, remove it is described second opening 610 in
And the anti-reflective film 520 on the surface of dielectric layer 460 of the second area II.
In the present embodiment, the material of the anti-reflecting layer 521 is organic matter, accordingly, the antireflection
The material of layer residue 522 is organic matter.
In the present embodiment, the technique for carrying out clearing up processing to the described second opening 610 is cineration technics.
Specifically, the processing step of the cineration technics includes：Reacting gas is passed through, the reaction is utilized
Gas removes the anti-reflecting layer residue 522 in second opening 610, and the reacting gas is O2、
N2And H2Mixed gas.
It should be noted that the gas flow of the mixed gas is unsuitable too high, it is also unsuitable too low.If
Gas flow is too low, be easily caused remove the anti-reflecting layer residue 522 speed it is excessively slow so that meeting
Reduce manufacture efficiency；If gas flow is too high, process costs can be wasted on the contrary.Therefore, the present embodiment
In, the gas flow of the mixed gas is 500sccm to 8000sccm.
Based on the gas flow of the setting, pressure, temperature and process time are set in zone of reasonableness value
It is interior, to improve removal effect and removal efficiency to the anti-reflecting layer residue 522.In the present embodiment,
The pressure is 1 standard atmospheric pressure, and temperature is 150 DEG C to 350 DEG C, and the process time is 100 seconds to 1000
Second.
It should be noted that second opening, 610 side walls are formed with sacrifice layer 620, the sacrifice layer
620 during the anti-reflecting layer residue 522 in second opening 610 is removed, to described second
The material layer of 610 side walls of being open plays a protective role, that is, protects the second area the first side wall layer 424,
The technique is avoided to have undesirable effect the quality of second area the first side wall layer 424, can be with
So that the width dimensions of the follow-up second grid structure formed in the second opening meet the requirements, and second grid
Structure side wall has good pattern.
It should also be noted that, the follow-up pseudo- gate oxide that 610 bottoms of the second opening are removed in etching
During 421, the pseudo- gate oxide 421 covered by the anti-reflecting layer residue 522 is difficult to be removed,
So as to cause pseudo- gate oxide 421 to have part residual, and then influence second gate in follow-up second opening 610
The formation quality of pole structure.Therefore, by removing the anti-reflecting layer residue in second opening 610
522, the formation quality of second grid structure in follow-up second opening 610 can be improved.
It is mask with the anti-reflecting layer 521 with reference to Figure 18, removes second opening, 610 side walls
The pseudo- gate oxide 421 (as shown in figure 17) of 610 bottoms of the opening of sacrifice layer 620 and second.
The first area I is used to form peripheral devices (for example：Input/output device), secondth area
Domain II is used to form core devices, and the operating voltage of core devices is smaller than the operating voltage of peripheral devices, is
The problems such as preventing electrical breakdown, when the operating voltage of device is bigger, it is desirable to the thickness of the gate dielectric layer of device
It is thicker, that is to say, that the thickness of the gate dielectric layer for the second area II being subsequently formed is less than first area I
Gate dielectric layer thickness.Therefore, in the present embodiment, before the gate dielectric layer of second area II is formed,
The pseudo- gate oxide 421 is first removed, so that the peripheral devices gate dielectric layer (not indicating) being subsequently formed
Thickness be more than core devices gate dielectric layer (not indicating) thickness.
It should be noted that the surface of anti-reflecting layer 521 is formed with graph layer 530, described second is removed
Be open 610 side walls sacrifice layer 620 and second be open 610 bottoms pseudo- gate oxide 421 the step of in,
It is mask with the graph layer 530 and anti-reflecting layer 521.
It should be noted that the surface of pseudo- gate oxide 421 and the dielectric layer of the second area II
460 surfaces are formed with sacrifice layer 620, therefore, remove the sacrifice layer 620 of second opening, 610 side walls
With second opening 610 bottoms pseudo- gate oxide 421 the step of in, also remove the pseudo- gate oxide 421
Surface and the sacrifice layer 620 on the surface of II dielectric layer of second area 460.
It should also be noted that, the material of the sacrifice layer 620 is silica, the pseudo- gate oxide 421
Material be silica, therefore, it can remove the sacrifice layer 620 and puppet in the etching technics with along with
Gate oxide 421.
In the present embodiment, the sacrifice layer 620 and puppet of the second area II are removed using dry etch process
Gate oxide 421, the dry etch process is SiCoNi etching technics.
The SiCoNi etching technics is big to the etch rate of the sacrifice layer 620 and pseudo- gate oxide 421
In the etch rate to the dielectric layer 460, therefore, the sacrifice layer 620 and pseudo- grid are removed in etching
The loss to the dielectric layer 460 can be reduced while oxide layer 421；And SiCoNi etching technics has
Beneficial to load effect of the etching technics to graphics intensive area and figure rarefaction is improved, so as to improve each region
To the homogeneity of the sacrifice layer 620 and the etch rate of pseudo- gate oxide 421.
Specifically, the step of SiCoNi etching technics includes：With NF3And NH3It is used as reacting gas
To generate etching gas；The sacrifice layer 620 and puppet of the second area II are etched by the etching gas
Gate oxide 421.
It should be noted that the gas flow influence of the etching gas is to the sacrifice layer 620 and pseudo- grid
The etch rate and etching effect of oxide layer 421, therefore, the gas flow of the etching gas should not mistake
Height, it is also unsuitable too low.In the present embodiment, NF3Gas flow be 20sccm to 200sccm, NH3
Gas flow be 20sccm to 500sccm.
Based on the gas flow of the setting, pressure and process time are set in zone of reasonableness value, with
Improve etching effect and the etching efficiency to the sacrifice layer 620 and pseudo- gate oxide 421.The present embodiment
In, chamber pressure is 1Torr to 100Torr, and the process time is 10S to 200S.
With reference to Figure 19, the anti-reflecting layer 521 (as shown in figure 18) in first opening 600 is removed.
In the present embodiment, the manufacture method also includes：Remove before the anti-reflecting layer 521, remove institute
State graph layer 530 (as shown in figure 18).In addition, removing the anti-reflecting layer in first opening 600
While 521, the anti-reflecting layer 521 on the surface of I dielectric layer of first area 460 is also removed.
The technique for removing the anti-reflecting layer 521 can be wet-etching technology or dry etch process.This
In embodiment, the anti-reflecting layer 521 is removed using dry plasma etch technique.
Specifically, the technological parameter of the plasma dry etch process includes：Etching gas are CH4、
H2And N2Mixed gas.
It should be noted that the gas flow of the etching gas is unsuitable excessive, it is also unsuitable too small.If
The gas flow of the etching gas is too small, and it is excessively slow to be easily caused etch rate, so that when can increase technique
Between, reduce manufacture efficiency；If the gas flow of the etching gas is excessive, etching is easily reduced stable
Property.Therefore, in the present embodiment, CH4Gas flow be 10sccm to 100sccm, N2Gas stream
Measure as 10sccm to 100sccm, H2Gas flow be 200sccm to 800sccm.
Based on the gas flow of the setting, pressure and etch period are set in zone of reasonableness value, with
Improve the removal effect to the graph layer 530 and anti-reflecting layer 521 and improve etching efficiency.This implementation
In example, pressure is 5Torr to 30Torr, and etch period is 50s to 300s.
With reference to reference to Figure 20, it is necessary to illustrate, the manufacture method also includes：Described first is removed to open
After anti-reflecting layer 521 (as shown in figure 18) in mouth 600, first opening, 600 side walls are removed
Sacrifice layer 620 (as shown in figure 19).
In order to reduce loss of the technique for removing the sacrifice layer 620 to the gate oxide 411, and carry
In the homogeneity of high etch rate, the present embodiment, first opening 600 is removed using wet-etching technology
Bottom and side wall and the sacrifice layer 620 on the surface of I dielectric layer of the first area 460.The wet etching
The etching solution that technique is used is hydrofluoric acid solution.
It should be noted that the also conformal covering pseudo- surface of gate oxide 421 of the sacrifice layer 620,
First 600 bottoms of opening, and the sacrifice layer 620 also covers the surface of dielectric layer 460；Accordingly,
In the step of removing sacrifice layer 620 of first opening, 600 side walls, first opening 600 is also removed
Bottom and the sacrifice layer 620 (as shown in figure 19) on the surface of I dielectric layer of the first area 460.
With reference to Figure 21, in the surface of gate oxide 411, first 600 (as shown in figure 20) sides of opening
Gate dielectric layer (not shown) is formed on the bottom and side wall of wall and the second 610 (as shown in figure 20) of opening；
The filling metal level (not shown) in the described first opening 600 and the second opening 610.
In the present embodiment, gate oxide 411, gate dielectric layer and metal in the described first opening 600
Layer constitutes first grid structure 751, and the gate dielectric layer and metal level in the described second opening 610 are constituted
Second grid structure 752.
In the present embodiment, the first grid structure 751 is across first fin 410, including covering institute
State the first gate dielectric layer 712 of the atop part surface of the first fin 410 and sidewall surfaces and positioned at described
First gate electrode layer 714 on one gate dielectric layer 712；The second grid structure 752 is across described second
Fin 420, includes the second gate medium of the covering atop part surface of the second fin 420 and sidewall surfaces
Layer 722 and the second gate electrode layer 724 on second gate dielectric layer 722
The first area I is used to form peripheral devices, and the second area II is used to form core devices,
Therefore, the gate oxide 411 and gate dielectric layer of first gate dielectric layer 712 as peripheral devices,
Second gate dielectric layer 722 as core devices gate dielectric layer.
In the present embodiment, the material of first gate dielectric layer 712 and second gate dielectric layer 722 is
High-k gate dielectric material, wherein, high-k gate dielectric material refers to that relative dielectric constant is more than silica
The gate dielectric material of relative dielectric constant, high-k gate dielectric material can be HfO2、HfSiO、HfSiON、
HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3。
The material of the metal level is Al, Cu, Ag, Au, Pt, Ni, Ti or W.In the present embodiment,
The material of the metal level is W, accordingly, the first gate electrode layer 714 and the second gate electrode layer 724
Material be W.
In the present embodiment, opened in the surface of gate oxide 411, the first 600 side walls of opening and second
Formed on mouthfuls 610 bottom and side wall after gate dielectric layer, formed on the gate dielectric layer metal level it
Before, the step of forming the first grid structure 751 and second grid structure 752 also includes：Described
Gate dielectric layer surface forms work-function layer (not indicating).
Therefore, the first grid structure 751 also includes：Positioned at first gate dielectric layer 712 and institute
The first work-function layer 713 between first gate electrode layer 714 is stated, first work-function layer 713 is used to adjust
Save the threshold voltage of peripheral devices；The second grid structure 752 also includes：It is situated between positioned at the second gate
The second work-function layer 723 between matter layer 722 and second gate electrode layer 724, second work function
Layer 723 is used for the threshold voltage for adjusting the core devices.
In the present embodiment, when the first area I and second area II are N-type region, the work-function layer
For N-type work function material；When the first area I and second area II is p type island regions, the work function
Layer is p-type work function material.
Specifically, the first area I and second area II are N-type region, and the work-function layer is N-type
Work function material, N-type work function material workfunction range is 3.9ev to 4.5ev, for example, 4ev, 4.1ev
Or 4.3ev.The work-function layer is single layer structure or laminated construction, and the material of the work-function layer includes
One or more in TiAl, TaAlN, TiAlN, MoN, TaCN and AlN.In the present embodiment,
The material of the work-function layer is TiAl；Accordingly, the work function of the first work-function layer 713 and second
The material of layer 723 is TiAl.
Or, the first area I and second area II are p type island region, and the work-function layer is p-type work(
Function material, p-type work function material workfunction range is 5.1ev to 5.5ev, for example, 5.2ev, 5.3ev
Or 5.4ev.The work-function layer is single layer structure or laminated construction, the material of the work-function layer include Ta,
One or more in TiN, TaN, TaSiN and TiSiN.In the present embodiment, the work-function layer
Material is TiN；Accordingly, the material of the work-function layer 723 of the first work-function layer 713 and second is
TiN。
Specifically, the step of forming the first grid structure 751 and second grid structure 752 includes：
The surface of gate oxide 411, the first opening 600 in described first 600 (as shown in figure 20) bottoms of opening
Side wall, the second 610 (as shown in figure 20) bottoms of opening and the side wall formation gate medium of the second opening 610
Layer, the gate dielectric layer also covers the surface of dielectric layer 460；Work(is formed on the gate dielectric layer surface
Function layer；In the work-function layer forming metal layer on surface, full first opening of metal level filling
600 and second are open at the top of 610 and the metal level higher than the top of dielectric layer 460；Grinding removes high
Metal level in the top of the dielectric layer 460, forms the on the work-function layer surface of the first area I
One gate electrode layer 714, the second gate electrode layer 724 is formed on the work-function layer surface of the second area II.
It should be noted that while grinding removes the metal level higher than the top of dielectric layer 460, also
Grinding removes the gate dielectric layer and work-function layer higher than the top of dielectric layer 460, in the first area
I forms the first gate dielectric layer 712 positioned at the surface of gate oxide 411 and the first 600 side walls of opening,
And the first work-function layer 713 positioned at the surface of the first gate dielectric layer 712, in the second area II
The second gate dielectric layer 722 for being located at the described second 610 side walls of opening and bottom is formed, and positioned at described the
Second work-function layer 723 on the surface of two gate medium 722.
It should be noted that in order to improve between the fin 410 of first grid structure 751 and first,
Interface performance between the fin 420 of second grid structure 752 and second, is forming the first grid
Before the gate dielectric layer 722 of dielectric layer 712 and second, the manufacture method also includes：Opened described first
The surface of gate oxide 411 of 600 bottoms of mouth forms the first boundary layer 711, at the described second 610 bottoms of opening
The surface of second fin 420 in portion forms second interface layer 721；Accordingly, the step of the gate dielectric layer is formed
Suddenly include：The surface of the first boundary layer 711, the first 600 sides of opening in the described first 600 bottoms of opening
Wall, the surface of second interface layer 721 of the second 610 bottoms of opening and the side wall formation institute of the second opening 610
State gate dielectric layer.
The present invention is removing the described first pseudo- gate electrode layer 413 (as shown in figure 12) and the second pseudo- gate electrode
After 423 (as shown in figure 12) of layer, in the described first 600 (as shown in figure 13) of opening and the second opening
In 610 (as shown in figure 13) before filling anti-reflective film 520 (as shown in figure 15), described second
(as shown in figure 14) side wall formation sacrifice layer 620 (as shown in figure 14) of opening 610, the sacrifice layer
620 can protect to the material layer of the described second 610 side walls of opening, it is to avoid remove the anti-reflecting layer
The technique of residue 522 produces harmful effect to the quality of the material layer of the described second 610 side walls of opening,
It is also possible that the second grid structure formed in the second opening 610 has higher width uniformity,
And second grid structure side wall pattern is good, and then improve the electric property of semiconductor devices.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (18)
1. a kind of manufacture method of semiconductor structure, it is characterised in that including：
Semiconductor base is provided, the semiconductor base includes substrate and the fin on the substrate,
The substrate includes first area and second area；
Fin portion surface in the first area forms the first pseudo- grid structure and in the fin of the second area
Surface forms the second pseudo- grid structure, wherein, the described first pseudo- grid structure includes gate oxide and the first pseudo- grid
Electrode layer, the described second pseudo- grid structure includes pseudo- gate oxide and the second pseudo- gate electrode layer；
Dielectric layer, the dielectric layer and the described first pseudo- grid structure and the second pseudo- grid are formed over the substrate
Structure flushes and exposes the described first pseudo- gate electrode layer and the second pseudo- gate electrode layer；
The described first pseudo- gate electrode layer is removed, first is formed in the dielectric layer and is open, described the is removed
Two pseudo- gate electrode layers, form the second opening in the dielectric layer；
In second opening sidewalls formation sacrifice layer；
Formed after the sacrifice layer, the filling anti-reflective film in the described first opening and the second opening；
The anti-reflective film in second opening is removed, patterned anti-reflecting layer is formed；
Using the anti-reflecting layer as mask, the sacrifice layer and the second open bottom of second opening sidewalls are removed
The pseudo- gate oxide in portion；
After the pseudo- gate oxide for removing second open bottom, the antireflection in first opening is removed
Layer；
Formed on the gate oxide surface, the bottom of the first opening sidewalls and the second opening and side wall
Gate dielectric layer；
Metal level is filled in the described first opening and the second opening.
2. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that the sacrifice layer
Material is silica.
3. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that the sacrifice layer
Thickness isExtremely
4. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that form described sacrifice
The technique of layer is atom layer deposition process.
5. the manufacture method of semiconductor structure as claimed in claim 4, it is characterised in that the atomic layer deposition
The technological parameter of product technique includes：The presoma being passed through into ald room is siliceous presoma,
Technological temperature be 100 degrees Celsius to 500 degrees Celsius, pressure be 5 millitorrs to 20 supports, frequency of depositing is
5 times to 40 times.
6. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that remove described second
The step of anti-reflective film in opening, includes：The anti-reflective film in second opening is removed, figure is formed
The anti-reflecting layer of shape, wherein, there is anti-reflecting layer residue in second opening；
Cleaning processing is carried out to the described second opening, the anti-reflecting layer residue in second opening is removed.
7. the manufacture method of semiconductor structure as claimed in claim 6, it is characterised in that open described second
The technique that mouth carries out cleaning processing is cineration technics.
8. the manufacture method of semiconductor structure as claimed in claim 7, it is characterised in that the cineration technics
Processing step include：Reacting gas is passed through, is removed using the reacting gas in second opening
Anti-reflecting layer residue, the reacting gas be O2、N2And H2Mixed gas, the mixing
The gas flow of gas is 500sccm to 8000sccm, and pressure is 1 standard atmospheric pressure, and temperature is
150 DEG C to 350 DEG C, the process time is 100 seconds to 1000 seconds.
9. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that remove described second
The technique of the sacrifice layer of opening sidewalls and the pseudo- gate oxide of the second open bottom is dry etch process.
10. the manufacture method of semiconductor structure as claimed in claim 9, it is characterised in that the dry etching
Technique is SiCoNi etching technics.
11. the manufacture method of semiconductor structure as claimed in claim 10, it is characterised in that the SiCoNi
The step of etching technics, includes：
With NF3And NH3As reacting gas to generate etching gas；
The sacrifice layer and pseudo- gate oxide are etched by the etching gas.
12. the manufacture method of semiconductor structure as claimed in claim 11, it is characterised in that the SiCoNi
The technological parameter of etching technics includes：NF3Gas flow be 20sccm to 200sccm, NH3's
Gas flow is 20sccm to 500sccm, and chamber pressure is 1Torr to 100Torr, and the process time is
10S to 200S.
13. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that remove described first
The technique of anti-reflecting layer in opening is plasma dry etch process.
14. the manufacture method of semiconductor structure as claimed in claim 13, it is characterised in that the plasma
The technological parameter of dry etch process includes：Etching gas are CH4、H2And N2Mixed gas,
CH4Gas flow be 10sccm to 100sccm, N2Gas flow for 10sccm to 100sccm,
H2Gas flow be 200sccm to 800sccm, pressure be 5Torr to 30Torr, etch period
For 50s to 300s.
15. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that opened described second
In the step of mouth side wall formation sacrifice layer, the sacrifice layer is also formed into first opening sidewalls；
The manufacture method also includes：Remove after the anti-reflecting layer in first opening, in the grid oxygen
Change and formed on layer surface, the bottom of the first opening sidewalls and the second opening and side wall before gate dielectric layer,
Remove the sacrifice layer of first opening sidewalls.
16. the manufacture method of semiconductor structure as claimed in claim 15, it is characterised in that remove described first
The technique of the sacrifice layer of opening sidewalls is wet-etching technology.
17. the manufacture method of semiconductor structure as claimed in claim 16, it is characterised in that the wet etching
The etching solution that technique is used is hydrofluoric acid solution.
18. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that in the technique with along with
In step, etching removes the described first pseudo- gate electrode layer and the second pseudo- gate electrode layer.
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| CN107275213B (en) | 2020-11-27 |
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