CN107275213B - Method for manufacturing semiconductor structure - Google Patents
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- CN107275213B CN107275213B CN201610216872.0A CN201610216872A CN107275213B CN 107275213 B CN107275213 B CN 107275213B CN 201610216872 A CN201610216872 A CN 201610216872A CN 107275213 B CN107275213 B CN 107275213B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A method of fabricating a semiconductor structure, comprising: providing a substrate comprising a first region and a second region and a fin part positioned on the substrate; forming a first dummy gate structure comprising a first dummy gate electrode layer on the surface of the fin part of the first region, and forming a second dummy gate structure comprising a second dummy gate electrode layer on the surface of the fin part of the second region; forming a dielectric layer on a substrate; removing the first dummy gate electrode layer and the second dummy gate electrode layer, and respectively forming a first opening and a second opening in the dielectric layer; forming a sacrificial layer on the sidewall of the second opening; filling an antireflection film in the first opening and the second opening; and removing the anti-reflection film in the second opening to form a patterned anti-reflection layer. Before the anti-reflection film is filled, a sacrificial layer is formed on the side wall of the second opening, the sacrificial layer can protect the material layer on the side wall of the second opening, the adverse effect of the process for forming the patterned anti-reflection layer on the quality of the material layer on the side wall of the second opening is avoided, and the electrical performance of the semiconductor device is improved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a manufacturing method of a semiconductor structure.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFET fets has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE) phenomenon, so-called short-channel effect (SCE), is easier to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFET transistors to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, the control capability of the gate on a channel is much stronger than that of a planar MOSFET device, and the short channel effect can be well inhibited; and compared with other devices, the FinFET has better compatibility of the existing integrated circuit manufacturing technology.
The finfet is mainly divided into a Core (Core) device and a peripheral (I/O) device (or called an input/output device) according to functional distinction. According to the electrical type of the fin field effect transistor, the core devices can be divided into core NMOS devices and core PMOS devices, and the peripheral devices can be divided into peripheral NMOS devices and peripheral PMOS devices.
Typically, the operating voltage of the peripheral devices is much greater than the operating voltage of the core device. In order to prevent the problems of electrical breakdown and the like, the gate dielectric layer of the device is required to be thicker when the working voltage of the device is larger, and therefore, the thickness of the gate dielectric layer of the peripheral device is generally larger than that of the gate dielectric layer of the core device.
However, the electrical properties of the semiconductor devices formed by the prior art need to be improved.
Disclosure of Invention
The invention provides a manufacturing method of a semiconductor structure, which improves the electrical performance of a semiconductor device.
To solve the above problems, the present invention provides a method for fabricating a semiconductor structure. The method comprises the following steps: providing a semiconductor base, wherein the semiconductor base comprises a substrate and a fin part positioned on the substrate, and the substrate comprises a first region and a second region; forming a first dummy gate structure on the surface of the fin part of the first region and forming a second dummy gate structure on the surface of the fin part of the second region, wherein the first dummy gate structure comprises a gate oxide layer and a first dummy gate electrode layer, and the second dummy gate structure comprises a dummy gate oxide layer and a second dummy gate electrode layer; forming a dielectric layer on the substrate, wherein the dielectric layer is flush with the first dummy gate structure and the second dummy gate structure and exposes the first dummy gate electrode layer and the second dummy gate electrode layer; removing the first dummy gate electrode layer, forming a first opening in the dielectric layer, removing the second dummy gate electrode layer, and forming a second opening in the dielectric layer; forming a sacrificial layer on the side wall of the second opening; filling an antireflection film in the first opening and the second opening after the sacrificial layer is formed; removing the anti-reflection film in the second opening to form a patterned anti-reflection layer; removing the sacrificial layer on the side wall of the second opening and the pseudo gate oxide layer at the bottom of the second opening by taking the anti-reflection layer as a mask; removing the anti-reflection layer in the first opening after removing the pseudo gate oxide layer at the bottom of the second opening; forming a gate dielectric layer on the surface of the gate oxide layer, the side wall of the first opening and the bottom and the side wall of the second opening; and filling a metal layer in the first opening and the second opening.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the invention, after the first dummy gate electrode layer and the second dummy gate electrode layer are removed and before antireflection films are filled in the first opening and the second opening, a sacrificial layer is formed on the side wall of the second opening, the sacrificial layer can protect the material layer on the side wall of the second opening, the adverse effect of the process for forming the patterned antireflection layer on the quality of the material layer on the side wall of the second opening is avoided, the second gate structure formed in the second opening has higher width uniformity, the side wall of the second gate structure has good appearance, and the electrical property of a semiconductor device is further improved.
In an alternative, the sacrificial layer is also formed on the sidewall of the first opening, so that the material layer on the sidewall of the first opening can be protected during the process of removing the anti-reflection layer in the first opening, and the electrical performance of the semiconductor device can be further improved.
Drawings
FIGS. 1-4 are schematic structural diagrams corresponding to steps of a method for fabricating a semiconductor structure according to the prior art;
fig. 5to 21 are schematic structural diagrams corresponding to steps in an embodiment of a method for fabricating a semiconductor structure according to the present invention.
Detailed Description
The electrical performance of the semiconductor devices of the prior art is poor, and the reason for this is analyzed in conjunction with the semiconductor structure manufacturing method. Referring to fig. 1to 4, schematic structural diagrams corresponding to steps of a method for manufacturing a semiconductor structure in the prior art are shown. The manufacturing method of the semiconductor structure comprises the following steps:
referring to fig. 1, a semiconductor base is formed, and the semiconductor base includes a substrate 100 and a fin portion on the substrate 100; the substrate 100 comprises a first area I and a second area II, wherein a fin portion on the substrate 100 in the first area I is a first fin portion 110, and a fin portion on the substrate 100 in the second area II is a second fin portion 120. The first area I is used for forming peripheral devices, and the second area II is used for forming core devices.
Specifically, the semiconductor substrate further includes a first dummy gate structure (not labeled) located in the first region i, a second dummy gate structure (not labeled) located in the second region ii, a first region source region or drain region 113 located at two sides of the first dummy gate structure, and a second region source region or drain region 123 located at two sides of the second dummy gate structure. The first dummy gate structure comprises a gate oxide layer 111 located on the surface of the first fin portion 110 and a first dummy gate electrode layer 112 located on the surface of the gate oxide layer 111, and the second dummy gate structure comprises a dummy gate oxide layer 121 located on the surface of the second fin portion 120 and a second dummy gate electrode layer 122 located on the surface of the dummy gate oxide layer 121. The semiconductor substrate further includes a dielectric layer 130 covering the first dummy gate structure and the second dummy gate structure.
Referring to fig. 2, the first dummy gate electrode layer 112 (shown in fig. 1) is etched away, and a first opening 200 is formed in the dielectric layer 130; the second dummy gate electrode layer 122 is removed (as shown in fig. 1), and a second opening 210 is formed in the dielectric layer 130.
Referring to fig. 3, an anti-reflection film 300 is filled in the first opening 200 (shown in fig. 2) and the second opening 210 (shown in fig. 2), and the anti-reflection film 300 further covers the surface of the dielectric layer 130; a pattern layer (not shown) is formed on the surface of the anti-reflection film 300.
Referring to fig. 4, the anti-reflection film 300 is patterned using the patterned layer as a mask to form an anti-reflection layer 301 in the first region i.
The working voltage of the core device is lower than that of the peripheral devices, and in order to prevent problems such as electric breakdown, the larger the working voltage of the device is, the thicker the gate dielectric layer of the device is required to be. Therefore, before forming the gate dielectric layer of the second region ii, the pattern layer and the antireflection layer 301 are used as masks to etch and remove the dummy gate oxide layer 121 at the bottom of the second opening 210, so that the thickness of the subsequently formed gate dielectric layer (not marked) of the peripheral device is greater than that of the gate dielectric layer (not marked) of the core device.
However, after patterning the anti-reflective film 300 (as shown in fig. 3) to form an anti-reflective layer 301, anti-reflective layer residues 311 are easily contained in the second opening 210, and the anti-reflective layer residues 311 are difficult to remove; in addition, the anti-reflection layer residues 311 also affect the subsequent etching process of the dummy gate oxide layer 121, so that the dummy gate oxide layer 121 covered by the anti-reflection layer residues 311 is difficult to remove, thereby affecting the formation quality of the subsequent second gate structure.
It is found that after the anti-reflective layer 301 is formed, a cleaning process may be performed on the second opening 210 (as shown in fig. 2) to remove the anti-reflective layer residue 311, but the cleaning process may easily adversely affect the material layer on the sidewall of the second opening 210, thereby causing a decrease in the electrical performance of the semiconductor device.
In order to solve the technical problem, the present invention provides a method for manufacturing a semiconductor device, including: providing a semiconductor base, wherein the semiconductor base comprises a substrate and a fin part positioned on the substrate, and the substrate comprises a first region and a second region; forming a first dummy gate structure on the surface of the fin part of the first region and forming a second dummy gate structure on the surface of the fin part of the second region, wherein the first dummy gate structure comprises a gate oxide layer and a first dummy gate electrode layer, and the second dummy gate structure comprises a dummy gate oxide layer and a second dummy gate electrode layer; forming a dielectric layer on the substrate, wherein the dielectric layer is flush with the first dummy gate structure and the second dummy gate structure and exposes the first dummy gate electrode layer and the second dummy gate electrode layer; removing the first dummy gate electrode layer, forming a first opening in the dielectric layer, removing the second dummy gate electrode layer, and forming a second opening in the dielectric layer; forming a sacrificial layer on the side wall of the second opening; filling an antireflection film in the first opening and the second opening after the sacrificial layer is formed; removing the anti-reflection film in the second opening to form a patterned anti-reflection layer; removing the sacrificial layer on the side wall of the second opening and the pseudo gate oxide layer at the bottom of the second opening by taking the anti-reflection layer as a mask; removing the anti-reflection layer in the first opening after removing the pseudo gate oxide layer at the bottom of the second opening; forming a gate dielectric layer on the surface of the gate oxide layer, the side wall of the first opening and the bottom and the side wall of the second opening; and filling a metal layer in the first opening and the second opening.
According to the invention, after the first dummy gate electrode layer and the second dummy gate electrode layer are removed and before antireflection films are filled in the first opening and the second opening, a sacrificial layer is formed on the side wall of the second opening, the sacrificial layer can protect the material layer on the side wall of the second opening, the adverse effect of the process for forming the patterned antireflection layer on the quality of the material layer on the side wall of the second opening is avoided, the second gate structure formed in the second opening has higher width uniformity, the side wall of the second gate structure has good appearance, and the electrical property of a semiconductor device is further improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5to 21 are schematic structural diagrams corresponding to steps in an embodiment of a method for fabricating a semiconductor structure according to the present invention.
Referring to fig. 5 and 6 in combination, fig. 6 is a schematic cross-sectional view taken along direction AA1 of fig. 5, and a semiconductor substrate is provided, where the semiconductor substrate includes a substrate 400 and a fin portion located on the substrate 400, and the substrate 400 includes a first region i (shown in fig. 6) and a second region ii (shown in fig. 6).
In this embodiment, the fin on the first region i substrate 400 is a first fin 410, and the fin on the second region ii substrate 400 is a second fin 420.
In this embodiment, the first region i is used to form peripheral devices (e.g., input/output devices), and the second region ii is used to form core devices. The first region I can be an N-type region or a P-type region, the second region II can be an N-type region or a P-type region, and the first region I and the second region II are of the same type.
The substrate 400 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 400 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the material of the first fin 410 and the second fin 420 includes silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 400 is a silicon substrate, and the first fin portion 410 and the second fin portion 420 are made of silicon.
Specifically, the step of providing the semiconductor substrate includes: providing an initial substrate, and forming a patterned hard mask layer 500 on the initial substrate; etching the initial substrate by taking the hard mask layer 500 as a mask to form a plurality of discrete protrusions; the protrusion is a fin portion, the etched initial substrate is used as a substrate 400, the substrate 400 comprises a first area I and a second area II, the fin portion located in the first area I is a first fin portion 410, and the fin portion located in the second area II is a second fin portion 420.
In this embodiment, the hard mask layer 500 is made of silicon nitride, and when a planarization process is performed subsequently, the surface of the hard mask layer 500 can be used as a stop position of the planarization process, and the hard mask layer 500 can also play a role in protecting the top of the first fin 410 and the top of the second fin 420.
With reference to fig. 7, it should be noted that after the semiconductor substrate is provided, the manufacturing method further includes: a linear oxide layer 401 is formed on the surfaces of the first fin portion 410 and the second fin portion 420 for repairing the first fin portion 410 and the second fin portion 420.
In the oxidation treatment process, because the convex edge angle part of first fin portion 410 and second fin portion 420 than the surface is bigger, is easier to be oxidized, follow-up get rid of after linear oxide layer 401, not only the defect layer on first fin portion 410 and second fin portion 420 surface is got rid of, and protruding edge angle part is also got rid of, makes the surface of first fin portion 410 and second fin portion 420 is smooth, and the lattice quality improves, avoids first fin portion 410 and second fin portion 420 apex angle point discharge problem is favorable to improving fin field effect transistor's performance.
In this embodiment, the linear oxide layer 401 is further located on the surface of the substrate 400, and the material of the linear oxide layer 401 is silicon oxide.
With reference to fig. 8, it should be noted that after the linear oxide layer 401 is formed, the manufacturing method further includes: an isolation layer 402 is formed on the surface of the substrate 400.
The isolation layer 402 serves as an isolation structure of the semiconductor structure and is used for isolating adjacent devices, and the isolation layer 402 may be made of silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation layer 402 is made of silicon oxide.
It should be noted that, in the present embodiment, the isolation layer 402 is a shallow trench isolation layer, but is not limited to a shallow trench isolation layer.
Specifically, the step of forming the isolation layer 402 includes: forming an isolation film on the surface of the linear oxide layer 401, wherein the top of the isolation film is higher than the top of the hard mask layer 500 (shown in fig. 7); grinding to remove the isolation film higher than the top of the hard mask layer 500; removing a portion of the thickness of the isolation film to form an isolation layer 402; the hard mask layer 500 is removed.
It should be noted that, in the process of removing the isolation film with a partial thickness, the linear oxide layer 401 on a portion of the fin surface is also removed.
Referring to fig. 9, fig. 9 is a schematic cross-sectional structure view along BB1 (shown in fig. 5), a first dummy gate structure (not shown) is formed on the fin surface of the first region i, and a second dummy gate structure (not shown) is formed on the fin surface of the second region ii, where the first dummy gate structure includes a gate oxide layer 411 and a first dummy gate electrode layer 413, and the second dummy gate structure includes a dummy gate oxide layer 421 and a second dummy gate electrode layer 423.
The first dummy gate structure and the second dummy gate structure occupy space positions for the subsequent formation of the first gate structure and the second gate structure.
In this embodiment, the fin portion of the first region i substrate 400 is a first fin portion 410, and the fin portion of the second region ii substrate 400 is a second fin portion 420. Accordingly, in the step of forming the first dummy gate structure and the second dummy gate structure, a first dummy gate structure (not shown) is formed on the surface of the first fin 410, and a second dummy gate structure (not shown) is formed on the surface of the second fin 420.
In this embodiment, the first dummy gate structure crosses over the surface of the first fin 410 and covers part of the top surface and the sidewall surface of the first fin 410, and includes a gate oxide layer 411 and a first dummy gate electrode layer 413 on the surface of the gate oxide layer 411; the second dummy gate structure crosses the surface of the second fin portion 420 and covers part of the top surface and the side wall surface of the second fin portion 420, and comprises a dummy gate oxide layer 421 and a second dummy gate electrode layer 423 on the surface of the dummy gate oxide layer 421.
The gate oxide layer 411 and the dummy gate electrode layer 421 are made of silicon oxide, and the first dummy gate electrode layer 413 and the second dummy gate electrode layer 423 are made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon. In this embodiment, the material of the first dummy gate electrode layer 413 and the second dummy gate electrode layer 423 is polysilicon.
Specifically, the step of forming the first and second dummy gate structures includes: forming a dummy gate oxide film covering the first fin portion 410 and the second fin portion 420; forming a pseudo gate electrode film on the surface of the pseudo gate oxide film; carrying out planarization treatment on the dummy gate electrode film; forming a first pattern layer 510 on the surface of the dummy gate electrode film; with the first pattern layer 510 as a mask, patterning the dummy gate electrode film and the dummy gate oxide film, forming a gate oxide layer 411 on the surface of the first fin portion 410, forming a first dummy gate electrode layer 413 on the surface of the gate oxide layer 411, forming a dummy gate oxide layer 421 on the surface of the second fin portion 420, and forming a second dummy gate electrode layer 423 on the surface of the dummy gate oxide layer 421; the first graphics layer 510 is removed.
In this embodiment, the first pattern layer 510 is a hard mask layer, and the first pattern layer 510 is made of silicon nitride.
With reference to fig. 10, it should be noted that after the first dummy gate structure and the second dummy gate structure are formed, the manufacturing method further includes: a first region first sidewall layer 414 is formed on the first dummy gate structure sidewall, and a second region first sidewall layer 424 is formed on the second dummy gate structure sidewall.
The material of the first-region first sidewall layer 414 and the second-region first sidewall layer 424 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and the first-region first sidewall layer 414 and the second-region first sidewall layer 424 may be a single-layer structure or a stacked-layer structure. In this embodiment, the first local first sidewall layer 414 and the second local first sidewall layer 424 are single-layer structures, and the material of the first local first sidewall layer 414 and the second local first sidewall layer 424 is silicon nitride.
Referring collectively to fig. 11, the method of manufacturing further comprises: forming a first-region second sidewall layer 415 on a surface of the first-region first sidewall layer 414, and forming a second-region second sidewall layer 425 on a surface of the second-region first sidewall layer 424; forming a first region stress layer 416 in the first fin 410 on two sides of the first dummy gate structure, and forming a second region stress layer 426 in the second fin 420 on two sides of the second dummy gate structure; a first area source or drain region (not shown) is formed in the first area stress layer 416, and a second area source or drain region (not shown) is formed in the second area stress layer 426.
The material of the first-region second sidewall layer 415 and the second-region second sidewall layer 425 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and the first-region second sidewall layer 415 and the second-region second sidewall layer 425 may be a single-layer structure or a stacked-layer structure. In this embodiment, the first regional second sidewall layer 415 and the second regional second sidewall layer 425 have a single-layer structure, and the material of the first regional second sidewall layer 415 and the second regional second sidewall layer 425 is silicon nitride.
Referring to fig. 12, a dielectric layer 460 is formed on the substrate 400, wherein the dielectric layer 460 is flush with the first dummy gate structure and the second dummy gate structure and exposes the first dummy gate electrode layer 413 and the second dummy gate electrode layer 423.
The dielectric layer 460 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the dielectric layer 460 is made of silicon oxide.
In this embodiment, the dielectric layer 460 is a stacked structure, and includes a first dielectric layer 440 on the substrate 400, and a second dielectric layer 450 on a surface of the first dielectric layer 440. The density of the second dielectric layer 450 is greater than that of the first dielectric layer 440, so that the surface flatness of the second dielectric layer 450 is improved in a planarization process.
Before forming the dielectric layer 460, the manufacturing method further includes: an etching barrier layer 430 is formed on the substrate 400, and the etching barrier layer 430 also covers the surface of the first dummy gate structure and the surface of the second dummy gate structure.
The etching stop layer 430 is used as an etching stop layer in a subsequent contact hole etching process and as a stop position for a subsequent planarization process. In this embodiment, the material of the etching stop layer 430 is silicon nitride.
Specifically, the step of forming the dielectric layer 460 includes: after the etching barrier layer 430 is formed, filling a first dielectric film on the substrate 400 between the fin portions, wherein the first dielectric film also covers the first dummy gate structure and the second dummy gate structure, and the top of the first dielectric film is higher than the top of the first dummy gate electrode layer 413 and the top of the second dummy gate electrode layer 423; planarizing the first dielectric film until the top surface of the etching barrier layer 430 is exposed; etching back to remove part of the thickness of the first dielectric film to form a first dielectric layer 440; forming a second dielectric film on the surface of the first dielectric layer 440, wherein the second dielectric film also covers the surfaces of the first dummy gate structure and the second dummy gate structure, and the top of the second dielectric film is higher than the top of the first dummy gate electrode layer 413 and the top of the second dummy gate electrode layer 423; and flattening the second dielectric film until the top surfaces of the first dummy gate electrode layers 413 and the second dummy gate electrode layers 423 are exposed to form a second dielectric layer 450.
It should be noted that, while the second dielectric film is planarized, the etching blocking layer 430 on top of the first dummy gate electrode layer 413 and on top of the second dummy gate electrode layer 423 are also removed, so that the top of the formed second dielectric layer 450 is flush with the top of the first dummy gate electrode layer 413 and the top of the second dummy gate electrode layer 423.
Referring to fig. 13, the first dummy gate electrode layer 413 is removed (as shown in fig. 12), a first opening 600 is formed in the dielectric layer 460, and the second dummy gate electrode layer 423 is removed (as shown in fig. 12), and a second opening 610 is formed in the dielectric layer 460.
In this embodiment, in the same process step, the first dummy gate electrode layer 412 and the second dummy gate electrode layer 422 are etched and removed.
In this embodiment, the first dummy gate electrode layer 413 and the second dummy gate electrode layer 423 are etched and removed by using a dry etching process, a wet etching process, or a process combining the dry etching process and the wet etching process. Since the etching process has a higher etching selection ratio for the first dummy gate electrode layer 413 and the second dummy gate electrode layer 423, that is, the etching rate of the etching process for the first dummy gate electrode layer 413 and the second dummy gate electrode layer 423 is greater than that for the dielectric layer 460, so that when the first dummy gate electrode layer 413 and the second dummy gate electrode layer 423 are removed by etching, the loss of the dielectric layer 460 can be reduced.
Referring to fig. 14, a sacrificial layer 620 is formed on sidewalls of the second opening 610.
The sacrificial layer 620 is used to protect the material layer on the sidewall of the second opening 610 in the subsequent process, i.e., protect the second local first sidewall layer 424, so as to avoid the adverse effect of the subsequent process on the second local first sidewall layer 424.
In this embodiment, the sacrificial layer 620 is further formed on the sidewall of the first opening 600.
In this embodiment, the sacrificial layer 620 is made of silicon oxide, and the process of forming the sacrificial layer 620 is an atomic layer deposition process.
Specifically, the process parameters of the atomic layer deposition process include: and introducing a precursor containing silicon into the atomic layer deposition chamber, wherein the process temperature is 100-500 ℃, the pressure is 5 mTorr-20 Torr, and the deposition times are 5-40 times.
When the process temperature is lower than 100 ℃, the deposition speed of each deposition process is easily caused to be too slow, so that the thickness of the sacrificial layer 620 is thin, or the process time needs to be increased to reach a target thickness value, so that the formation efficiency of the sacrificial layer 620 is reduced; when the process temperature is higher than 500 ℃, thermal decomposition of the precursor is easily caused, so that a phenomenon similar to chemical vapor deposition is introduced, the purity and the step coverage of the sacrificial layer 620 are affected, and the formation quality of the sacrificial layer 620 is finally reduced.
Based on the set process temperature, the chamber pressure, the gas flow and the deposition times are set within reasonable range values, and the phenomenon similar to chemical vapor deposition is avoided, so that the high purity and the good step coverage of the sacrificial layer 620 are ensured, and the formation quality of the sacrificial layer 620 is improved.
It should be noted that the thickness of the sacrificial layer 620 is not too thick, nor too thin. If the thickness of the sacrificial layer 620 is too thin, it is easily removed in a subsequent process, thereby making it difficult to protect the second regional first sidewall layer 424; in addition, since the opening sizes of the first opening 600 and the second opening 610 are limited, that is, the process window for forming the sacrificial layer 620 is limited, if the thickness of the sacrificial layer 620 is too thick, the sacrificial layer 620 occupies too much space in the first opening 600 and the second opening 610, which easily causes difficulty in forming an anti-reflection film in the first opening 600 and waste of manufacturing cost. For this purpose,in this embodiment, the thickness of the sacrificial layer 620 is
To
It should be noted that, through the atomic layer deposition process, the sacrificial layer 620 also conformally covers the surface of the dummy gate oxide layer 421 and the bottom of the first opening 600, and the sacrificial layer 620 also covers the surface of the dielectric layer 460.
Referring to fig. 15, an anti-reflection film 520 is filled in the first opening 600 (shown in fig. 14) and the second opening 610 (shown in fig. 14).
The anti-reflective film 520 is used to reduce standing wave effect to improve lithography quality. In this embodiment, the anti-reflection film 520 also covers the surface of the dielectric layer 460.
The anti-reflective film 520 is an organic material. In this embodiment, the anti-reflection film 520 is formed by a chemical vapor deposition process.
The manufacturing method further includes: a pattern layer 530 is formed on the surface of the anti-reflection film 520.
The pattern layer 530 serves as an etching mask for the subsequent patterning of the anti-reflection film 520 and also serves as an etching mask for the subsequent removal of the dummy gate oxide 421 at the bottom of the second opening 610 (shown in fig. 13).
In this embodiment, the pattern layer 530 is made of photoresist.
Referring to fig. 16 and 17, the anti-reflection film 520 (shown in fig. 15) in the second opening 610 is removed to form a patterned anti-reflection layer 521.
Specifically, the patterned layer 530 is used as a mask to etch and remove the anti-reflection film 520 in the second opening 610 and on the surface of the dielectric layer 460 in the second region ii, so as to form a patterned anti-reflection layer 521.
It should be noted that after the patterned anti-reflection layer 521 is formed through the etching process, the anti-reflection layer residue 522 is easily present in the second opening 610.
Accordingly, the step of forming the patterned anti-reflection layer 521 includes: removing the anti-reflection film 520 in the second opening 610 (as shown in fig. 15) to form a patterned anti-reflection layer 521, wherein the second opening 610 has an anti-reflection layer residue 522 therein (as shown in fig. 15); the second opening 610 is cleaned to remove the anti-reflection layer residue 522 in the second opening 610.
In this embodiment, a plasma dry etching process is adopted to remove the anti-reflection film 520 in the second opening 610 and on the surface of the dielectric layer 460 in the second region ii.
In this embodiment, the anti-reflection layer 521 is made of an organic material, and correspondingly, the anti-reflection layer residue 522 is made of an organic material.
In this embodiment, the process of cleaning the second opening 610 is an ashing process.
Specifically, the process steps of the ashing process include: introducing a reaction gas, and removing the anti-reflection layer residue 522 in the second opening 610 by using the reaction gas, wherein the reaction gas is O2、N2And H2The mixed gas of (1).
It should be noted that the gas flow rate of the mixed gas is not too high nor too low. If the gas flow is too low, it tends to result in too slow a rate of removal of the antireflective layer residue 522, which can reduce manufacturing efficiency; if the gas flow is too high, the process cost is wasted. Therefore, in the present embodiment, the gas flow rate of the mixed gas is 500sccm to 8000 sccm.
The pressure, temperature and process time are set within reasonable range values based on the set gas flow to improve the removal effect and removal efficiency of the anti-reflective layer residue 522. In this embodiment, the pressure is 1 standard atmosphere, the temperature is 150 ℃ to 350 ℃, and the process time is 100 seconds to 1000 seconds.
It should be noted that the sidewall of the second opening 610 is formed with a sacrificial layer 620, and the sacrificial layer 620 protects the material layer on the sidewall of the second opening 610 in the process of removing the anti-reflection layer residue 522 in the second opening 610, i.e. protects the second area first sidewall layer 424, so as to avoid the adverse effect of the process on the quality of the second area first sidewall layer 424, and further enable the width dimension of the second gate structure formed in the second opening in the following step to meet the requirement, and the sidewall of the second gate structure has a good profile.
It should be further noted that, in the subsequent process of etching and removing the dummy gate oxide 421 at the bottom of the second opening 610, the dummy gate oxide 421 covered by the anti-reflection layer residue 522 is difficult to be removed, so that a part of the dummy gate oxide 421 remains, and the quality of forming the second gate structure in the subsequent second opening 610 is affected. Therefore, by removing the residues 522 of the anti-reflection layer in the second opening 610, the quality of the formation of the second gate structure in the second opening 610 can be improved.
Referring to fig. 18, the anti-reflection layer 521 is used as a mask to remove the sacrificial layer 620 on the sidewall of the second opening 610 and the dummy gate oxide 421 on the bottom of the second opening 610 (as shown in fig. 17).
The first area I is used for forming peripheral devices (such as input/output devices), the second area II is used for forming core devices, the working voltage of the core devices is lower than that of the peripheral devices, and in order to prevent problems such as electric breakdown, when the working voltage of the devices is higher, the thickness of the gate dielectric layer of the devices is required to be thicker, namely, the thickness of the subsequently formed gate dielectric layer of the second area II is smaller than that of the first area I. For this reason, in this embodiment, before forming the gate dielectric layer in the second region ii, the dummy gate oxide layer 421 is removed, so that the thickness of the subsequently formed gate dielectric layer (not shown) of the peripheral device is greater than the thickness of the gate dielectric layer (not shown) of the core device.
It should be noted that a pattern layer 530 is formed on the surface of the anti-reflection layer 521, and in the step of removing the sacrificial layer 620 on the sidewall of the second opening 610 and the dummy gate oxide 421 at the bottom of the second opening 610, the pattern layer 530 and the anti-reflection layer 521 are used as masks.
It should be noted that, a sacrificial layer 620 is formed on the surface of the dummy gate oxide layer 421 and the surface of the second region ii dielectric layer 460, so that in the step of removing the sacrificial layer 620 on the sidewall of the second opening 610 and the dummy gate oxide layer 421 at the bottom of the second opening 610, the sacrificial layer 620 on the surface of the dummy gate oxide layer 421 and the surface of the second region ii dielectric layer 460 is also removed.
It should be further noted that the material of the sacrificial layer 620 is silicon oxide, and the material of the dummy gate oxide layer 421 is silicon oxide, so that the sacrificial layer 620 and the dummy gate oxide layer 421 can be removed in the same etching process.
In this embodiment, the sacrificial layer 620 and the dummy gate oxide 421 in the second region ii are removed by using a dry etching process, where the dry etching process is a SiCoNi etching process.
The etching rate of the SiCoNi etching process to the sacrificial layer 620 and the pseudo gate oxide layer 421 is greater than that to the dielectric layer 460, so that the loss to the dielectric layer 460 can be reduced while the sacrificial layer 620 and the pseudo gate oxide layer 421 are removed by etching; and the SiCoNi etching process is favorable for improving the load effect of the etching process on a pattern dense area and a pattern sparse area, so that the uniformity of the etching rate of each area on the sacrificial layer 620 and the pseudo gate oxide layer 421 is improved.
Specifically, the SiCoNi etching process comprises the following steps: with NF3And NH3As a reaction gas to generate an etching gas; and etching the sacrificial layer 620 and the pseudo gate oxide layer 421 of the second region II by the etching gas.
It should be noted that the gas flow of the etching gas affects the etching rate and the etching effect on the sacrificial layer 620 and the dummy gate oxide layer 421, and therefore, the gas flow of the etching gas is not too high or too low. In this example, NF3The gas flow rate of (1) is 20sccm to 200sccm, NH3The gas flow rate of (2) is 20sccm to 500 sccm.
And setting the pressure intensity and the process time within a reasonable range value based on the set gas flow so as to improve the etching effect and the etching efficiency of the sacrificial layer 620 and the pseudo gate oxide layer 421. In this embodiment, the chamber pressure is 1Torr to 100Torr, and the process time is 10S to 200S.
Referring to fig. 19, the anti-reflection layer 521 (shown in fig. 18) within the first opening 600 is removed.
In this embodiment, the manufacturing method further includes: before removing the anti-reflection layer 521, the patterning layer 530 is removed (as shown in fig. 18). In addition, the antireflection layer 521 on the surface of the first area i dielectric layer 460 is also removed while the antireflection layer 521 in the first opening 600 is removed.
The process of removing the anti-reflection layer 521 may be a wet etching process or a dry etching process. In this embodiment, the anti-reflection layer 521 is removed by a plasma dry etching process.
Specifically, the process parameters of the plasma dry etching process include: etching gas is CH4、H2And N2The mixed gas of (1).
It should be noted that the gas flow of the etching gas should not be too large or too small. If the gas flow of the etching gas is too small, the etching rate is easily too slow, so that the process time is increased, and the manufacturing efficiency is reduced; if the gas flow of the etching gas is too large, the etching stability is easily reduced. For this reason, in this embodiment, CH4The gas flow rate of (1) is 10sccm to 100sccm, N2The gas flow rate of (A) is 10sccm to 100sccm, H2The gas flow rate of (2) is 200sccm to 800 sccm.
Based on the set gas flow, the pressure and the etching time are set within reasonable range values to improve the removal effect of the pattern layer 530 and the anti-reflection layer 521 and improve the etching efficiency. In this embodiment, the pressure is 5Torr to 30Torr, and the etching time is 50s to 300 s.
With reference to fig. 20, it should be noted that the manufacturing method further includes: after removing the anti-reflection layer 521 (shown in fig. 18) in the first opening 600, the sacrificial layer 620 (shown in fig. 19) on the sidewall of the first opening 600 is removed.
In order to reduce the loss of the gate oxide 411 by the process of removing the sacrificial layer 620 and improve the uniformity of the etching rate, in this embodiment, a wet etching process is used to remove the sacrificial layer 620 on the bottom and the sidewall of the first opening 600 and the surface of the first i-region dielectric layer 460. The etching solution adopted by the wet etching process is a hydrofluoric acid solution.
It should be noted that the sacrificial layer 620 also conformally covers the surface of the dummy gate oxide layer 421 and the bottom of the first opening 600, and the sacrificial layer 620 also covers the surface of the dielectric layer 460; accordingly, in the step of removing the sacrificial layer 620 on the sidewall of the first opening 600, the sacrificial layer 620 on the bottom of the first opening 600 and the surface of the first regio i dielectric layer 460 is also removed (as shown in fig. 19).
Referring to fig. 21, a gate dielectric layer (not shown) is formed on the surface of the gate oxide layer 411, the sidewall of the first opening 600 (shown in fig. 20) and the bottom and sidewall of the second opening 610 (shown in fig. 20); the first opening 600 and the second opening 610 are filled with a metal layer (not shown).
In this embodiment, the gate oxide layer 411, the gate dielectric layer and the metal layer in the first opening 600 form a first gate structure 751, and the gate dielectric layer and the metal layer in the second opening 610 form a second gate structure 752.
In this embodiment, the first gate structure 751 crosses over the first fin 410, and includes a first gate dielectric layer 712 covering a portion of the top surface and sidewall surface of the first fin 410, and a first gate electrode layer 714 on the first gate dielectric layer 712; the second gate structure 752 crosses over the second fin portion 420 and includes a second gate dielectric layer 722 covering a portion of the top surface and the sidewall surface of the second fin portion 420 and a second gate electrode layer 724 located on the second gate dielectric layer 722
The first area i is used for forming peripheral devices, and the second area ii is used for forming core devices, so that the gate oxide layer 411 and the first gate dielectric layer 712 are used as gate dielectric layers of the peripheral devices, and the second gate dielectric layer 722 is used as a gate dielectric layer of the core device.
In this embodiment, the first gate dielectric layer 712 and the second gate dielectric layerThe material of the layer 722 is a high-k gate dielectric material, wherein the high-k gate dielectric material refers to a gate dielectric material with a relative dielectric constant greater than that of silicon oxide, and the high-k gate dielectric material may be HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3。
The metal layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the metal layer is made of W, and correspondingly, the first gate electrode layer 714 and the second gate electrode layer 724 are made of W.
In this embodiment, after forming a gate dielectric layer on the surface of the gate oxide layer 411, the sidewall of the first opening 600, and the bottom and the sidewall of the second opening 610, and before forming a metal layer on the gate dielectric layer, the step of forming the first gate structure 751 and the second gate structure 752 further includes: and forming a work function layer (not marked) on the surface of the gate dielectric layer.
Accordingly, the first gate structure 751 further comprises: a first work function layer 713 located between the first gate dielectric layer 712 and the first gate electrode layer 714, where the first work function layer 713 is used for adjusting a threshold voltage of a peripheral device; the second gate structure 752 further includes: a second work function layer 723 located between the second gate dielectric layer 722 and the second gate electrode layer 724, where the second work function layer 723 is used to adjust a threshold voltage of the core device.
In this embodiment, when the first region i and the second region ii are N-type regions, the work function layer is an N-type work function material; when the first area I and the second area II are P-type areas, the work function layer is made of P-type work function materials.
Specifically, the first region i and the second region ii are N-type regions, the work function layer is an N-type work function material, and the work function range of the N-type work function material is 3.9ev to 4.5ev, for example, 4ev, 4.1ev, or 4.3 ev. The work function layer is of a single-layer structure or a laminated structure, and the material of the work function layer comprises one or more of TiAl, TaAlN, TiAlN, MoN, TaCN and AlN. In this embodiment, the work function layer is made of TiAl; correspondingly, the material of the first work function layer 713 and the second work function layer 723 is TiAl.
Or, the first region i and the second region ii are P-type regions, the work function layer is a P-type work function material, and the work function range of the P-type work function material is 5.1ev to 5.5ev, for example, 5.2ev, 5.3ev, or 5.4 ev. The work function layer is of a single-layer structure or a laminated structure, and the material of the work function layer comprises one or more of Ta, TiN, TaN, TaSiN and TiSiN. In this embodiment, the work function layer is made of TiN; correspondingly, the material of the first work function layer 713 and the second work function layer 723 is TiN.
Specifically, the step of forming the first gate structure 751 and the second gate structure 752 includes: forming a gate dielectric layer on the surface of the gate oxide layer 411 at the bottom of the first opening 600 (as shown in fig. 20), on the sidewall of the first opening 600, on the bottom of the second opening 610 (as shown in fig. 20) and on the sidewall of the second opening 610, wherein the gate dielectric layer also covers the surface of the dielectric layer 460; forming a work function layer on the surface of the gate dielectric layer; forming a metal layer on the surface of the work function layer, wherein the first opening 600 and the second opening 610 are filled with the metal layer, and the top of the metal layer is higher than the top of the dielectric layer 460; and removing the metal layer higher than the top of the dielectric layer 460 by grinding, forming a first gate electrode layer 714 on the surface of the work function layer of the first region I, and forming a second gate electrode layer 724 on the surface of the work function layer of the second region II.
It should be noted that, while the metal layer higher than the top of the dielectric layer 460 is removed by grinding, the gate dielectric layer and the work function layer higher than the top of the dielectric layer 460 are also removed by grinding, a first gate dielectric layer 712 located on the surface of the gate oxide layer 411 and the sidewall of the first opening 600 and a first work function layer 713 located on the surface of the first gate dielectric layer 712 are formed in the first region i, a second gate dielectric layer 722 located on the sidewall and the bottom of the second opening 610 and a second work function layer 723 located on the surface of the second gate dielectric layer 722 are formed in the second region ii.
It should be noted that, in order to improve the interface performance between the first gate structure 751 and the first fin 410 and between the second gate structure 752 and the second fin 420, before the forming of the first gate dielectric layer 712 and the second gate dielectric layer 722, the manufacturing method further includes: forming a first interface layer 711 on the surface of the gate oxide layer 411 at the bottom of the first opening 600, and forming a second interface layer 721 on the surface of the second fin portion 420 at the bottom of the second opening 610; correspondingly, the step of forming the gate dielectric layer comprises the following steps: the gate dielectric layer is formed on the surface of the first interface layer 711 at the bottom of the first opening 600, the sidewall of the first opening 600, the surface of the second interface layer 721 at the bottom of the second opening 610, and the sidewall of the second opening 610.
In the invention, after the first dummy gate electrode layer 413 (shown in fig. 12) and the second dummy gate electrode layer 423 (shown in fig. 12) are removed, before the anti-reflection film 520 (shown in fig. 15) is filled in the first opening 600 (shown in fig. 13) and the second opening 610 (shown in fig. 13), the sacrificial layer 620 (shown in fig. 14) is formed on the sidewall of the second opening 610 (shown in fig. 14), the sacrificial layer 620 can protect the material layer on the sidewall of the second opening 610, the adverse effect of the process of removing the residues 522 of the anti-reflection layer on the quality of the material layer on the sidewall of the second opening 610 is avoided, the second gate structure formed in the second opening 610 has higher width uniformity, and the sidewall of the second gate structure has a good shape, so that the electrical performance of the semiconductor device is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor base, wherein the semiconductor base comprises a substrate and a fin part positioned on the substrate, and the substrate comprises a first region and a second region;
forming a first dummy gate structure on the surface of the fin part of the first region and forming a second dummy gate structure on the surface of the fin part of the second region, wherein the first dummy gate structure comprises a gate oxide layer and a first dummy gate electrode layer, and the second dummy gate structure comprises a dummy gate oxide layer and a second dummy gate electrode layer;
forming a dielectric layer on the substrate, wherein the dielectric layer is flush with the first dummy gate structure and the second dummy gate structure and exposes the first dummy gate electrode layer and the second dummy gate electrode layer;
removing the first dummy gate electrode layer, forming a first opening in the dielectric layer, removing the second dummy gate electrode layer, and forming a second opening in the dielectric layer;
forming a sacrificial layer on the side wall of the second opening;
filling an antireflection film in the first opening and the second opening after the sacrificial layer is formed;
removing the anti-reflection film in the second opening to form a patterned anti-reflection layer; the step of removing the antireflection film in the second opening includes: removing the anti-reflection film in the second opening to form a patterned anti-reflection layer, wherein the second opening is provided with anti-reflection layer residues;
cleaning the second opening to remove the residues of the antireflection layer in the second opening;
removing the sacrificial layer on the side wall of the second opening and the pseudo gate oxide layer at the bottom of the second opening by taking the anti-reflection layer as a mask;
removing the anti-reflection layer in the first opening after removing the pseudo gate oxide layer at the bottom of the second opening;
forming a gate dielectric layer on the surface of the gate oxide layer, the side wall of the first opening and the bottom and the side wall of the second opening;
and filling a metal layer in the first opening and the second opening.
2. The method of claim 1, wherein the sacrificial layer is silicon oxide.
3. Fabrication of a semiconductor structure as in claim 1The method is characterized in that the thickness of the sacrificial layer is
To
4. The method of fabricating a semiconductor structure according to claim 1, wherein the process of forming the sacrificial layer is an atomic layer deposition process.
5. The method of fabricating a semiconductor structure according to claim 4, wherein the process parameters of the atomic layer deposition process comprise: and introducing a precursor containing silicon into the atomic layer deposition chamber, wherein the process temperature is 100-500 ℃, the pressure is 5 mTorr-20 Torr, and the deposition times are 5-40 times.
6. The method according to claim 1, wherein a process of cleaning the second opening is an ashing process.
7. The method of manufacturing a semiconductor structure according to claim 6, wherein the process step of the ashing process comprises: introducing reaction gas, and removing the residues of the anti-reflection layer in the second opening by using the reaction gas, wherein the reaction gas is O2、N2And H2The gas flow of the mixed gas is 500sccm to 8000sccm, the pressure is 1 standard atmospheric pressure, the temperature is 150 ℃ to 350 ℃, and the process time is 100 seconds to 1000 seconds.
8. The method for manufacturing a semiconductor structure according to claim 1, wherein the process for removing the sacrificial layer on the sidewall of the second opening and the dummy gate oxide layer at the bottom of the second opening is a dry etching process.
9. The method of fabricating a semiconductor structure of claim 8, wherein the dry etching process is a SiCoNi etching process.
10. The method of fabricating a semiconductor structure of claim 9, wherein the step of the SiCoNi etching process comprises:
with NF3And NH3As a reaction gas to generate an etching gas;
and etching the sacrificial layer and the pseudo gate oxide layer by the etching gas.
11. The method of fabricating a semiconductor structure of claim 10, wherein the process parameters of the SiCoNi etch process include: NF3The gas flow rate of (1) is 20sccm to 200sccm, NH3The gas flow rate of the gas is 20sccm to 500sccm, the chamber pressure is 1Torr to 100Torr, and the process time is 10S to 200S.
12. The method of claim 1, wherein the process of removing the anti-reflective layer within the first opening is a plasma dry etching process.
13. The method of fabricating a semiconductor structure according to claim 12, wherein the process parameters of the plasma dry etching process include: etching gas is CH4、H2And N2Mixed gas of (2), CH4The gas flow rate of (1) is 10sccm to 100sccm, N2The gas flow rate of (A) is 10sccm to 100sccm, H2The gas flow rate is 200sccm to 800sccm, the pressure is 5Torr to 30Torr, and the etching time is 50s to 300 s.
14. The method for manufacturing a semiconductor structure according to claim 1, wherein in the step of forming a sacrificial layer on the sidewall of the second opening, the sacrificial layer is further formed on the sidewall of the first opening;
the manufacturing method further includes: and after removing the anti-reflection layer in the first opening, removing the sacrificial layer on the side wall of the first opening before forming a gate dielectric layer on the surface of the gate oxide layer, the side wall of the first opening and the bottom and the side wall of the second opening.
15. The method of manufacturing a semiconductor structure according to claim 14, wherein the process of removing the sacrificial layer on the sidewall of the first opening is a wet etching process.
16. The method of claim 15, wherein the wet etching process uses a hydrofluoric acid solution as an etching solution.
17. The method of manufacturing a semiconductor structure according to claim 1, wherein the first dummy gate electrode layer and the second dummy gate electrode layer are etched away in a same process step.
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| JP2008016522A (en) * | 2006-07-04 | 2008-01-24 | Sony Corp | Semiconductor device and method of manufacturing same |
| US8222132B2 (en) * | 2008-11-14 | 2012-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fabricating high-K/metal gate devices in a gate last process |
| US7838356B2 (en) * | 2008-12-31 | 2010-11-23 | Texas Instruments Incorporated | Gate dielectric first replacement gate processes and integrated circuits therefrom |
| CN103094213B (en) * | 2011-11-02 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for metal gate electrode of complementary metal oxide semiconductor (CMOS) device |
| KR102065973B1 (en) * | 2013-07-12 | 2020-01-15 | 삼성전자 주식회사 | Semiconductor device and fabricating method thereof |
| CN104733307A (en) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN104752175B (en) * | 2013-12-27 | 2018-04-13 | 中芯国际集成电路制造(上海)有限公司 | A kind of method for making semiconductor devices |
| CN105336688B (en) * | 2014-05-28 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN105448684B (en) * | 2014-06-13 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | The method for forming grid |
| KR102262887B1 (en) * | 2014-07-21 | 2021-06-08 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
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