JP2009277961A - Method of manufacturing cmis transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a CMIS transistor, capable of preventing composition of a silicide layer from varying on the PMIS transistor side and the NMIS transistor side, and also capable of preventing the gate shapes of the transistors from becoming unstable. <P>SOLUTION: A gate insulating film 103, N-metal 104, and poly-crystalline silicon 106 are laminated in this order to form a first gate structure G1. The gate insulating film 103, the poly-crystalline silicon 106 are laminated in this order to form a second structure G2. The top surfaces of the semiconductor substrate 101 on both sides of the respective gate structures G1, G2 are turned into silicide with the first and second gate structures masked. Also, the poly-crystalline silicon 106 composing the first and second gate structures G1, G2 are turned into silicide. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a CMIS transistor in which a PMIS transistor and an NMIS transistor are formed on a semiconductor substrate 1.

  When polycrystalline silicon is used for the gate electrode of the MIS transistor, the effective gate insulating film thickness is increased due to the gate depletion phenomenon. The increase in the effective gate insulating film hinders improvement in transistor performance. In order to suppress the gate depletion and improve the performance of the MIS transistor, a metal or silicide material is used as the gate electrode material instead of polycrystalline silicon. In particular, a full silicide (FUSI) gate structure in which all of the gate polycrystalline silicon is silicided is effective. The FUSI gate structure has good consistency with the conventional transistor fabrication flow, and is effective for suppressing the gate depletion.

  In a transistor having a FUSI gate structure, when a high dielectric constant (high-k) insulating film (for example, HfSiON) is used as a gate insulating film, a method of changing the silicide composition to control the threshold voltage Vth has been proposed. (For example, Non-Patent Document 1).

It is assumed that nickel is used as the silicide metal material. In this case, the effective work function of the FUSI gate made of Ni ₃ Si (trinickel silicide) having a higher nickel content than NiSi (nickel monosilicide) is about 0.35 eV compared to the effective work function of the FUSI gate made of NiSi. About high. In the said nonpatent literature 1, the phenomenon in which an effective work function changes according to the said silicide composition is utilized. Specifically, NiSi is used as the FUSI gate material for the NMIS transistor. For the PMIS transistor, nickel silicide having a high Ni content such as Ni ₃ Si is used as the FUSI gate material. Thereby, the said nonpatent literature 1 proposes that a low threshold voltage Vth device is realizable.

  As a method of forming the silicide phase controlled FUSI gate electrode, for example, the following manufacturing method can be cited. That is, a polycrystalline silicon film having the same film thickness is formed in both gate structures on the PMIS transistor side and the NMIS transistor side. Thereafter, for example, the thickness of the polycrystalline silicon film on the PMIS transistor side is reduced (thinned). Then, the polysilicon film is silicided in both gate structures on the PMIS transistor side and the NMIS transistor side.

  By this manufacturing method, a full silicide layer having a low silicide metal content is formed on the NMIS transistor side. On the other hand, on the PMIS transistor side, a full silicide layer having a high silicide metal content is formed. When this manufacturing method is adopted, there is an advantage that FUSI gate structures having different compositions can be formed simultaneously on the PMIS transistor side and the NMIS transistor side.

K. Takahashi et al. , IEDM 2004 Tech. Dig. , Pp91

  However, in the case of the manufacturing method exemplified above, the following problems occur.

  The first problem is variation in the composition of the full silicide layer.

  When forming a full silicide layer with a low silicide metal content on the NMIS transistor side, there is a concern that the composition of the formed full silicide layer varies depending on the gate length. For example, when the gate length is about 1 μm, the exposed area of the polycrystalline silicon gate is large. Therefore, in this case, the silicide metal and the polycrystalline silicon react in an ideal state (a state in which the reaction between the silicide metal and silicon proceeds one-to-one).

  On the other hand, for example, when the gate length is about 40 nm, the exposed area of the polycrystalline silicon gate is small. Therefore, in this case, the amount of diffusion of the metal silicide in the gate edge portion is relatively larger than that in the gate central portion. Therefore, there is a high possibility that a full silicide phase having a high silicidation metal content as compared with a desired composition is formed.

  Thus, transistors having different full silicide phases are formed depending on the gate length. Variation in the composition of the full silicide layer is a factor that causes variation in threshold voltage.

  The second problem is the instability of the gate shape of the transistor.

  In the PMIS transistor and the NMIS transistor, it is assumed that the full silicide gate is formed under the same Ni volume film thickness and the same silicidation heat treatment conditions. In this case, the polycrystalline silicon gate on the PMIS transistor side having a high silicide metal content needs to be thinned in advance. Specifically, a technique for etching back only the polycrystalline silicon gate electrode on the PMIS transistor side by the existing wet etching process or dry etching process is necessary before silicidation metal deposition.

  However, the above technique has a problem that the gate height is greatly different between the PMIS transistor side and the NMIS transistor side. For example, when the initial film thickness of the polycrystalline silicon is 100 nm, the polycrystalline silicon on the PMIS transistor side is etched back to about 35 nm. As a result, a full silicide gate having a high silicidation metal content is formed on the PMIS transistor side. However, as compared with the gate structure on the NMIS transistor side, the height variation of about 60 nm or more occurs, and the gate shape of the transistor becomes unstable.

  Accordingly, an object of the present invention is to provide a method for manufacturing a CMIS transistor, which can prevent variations in the composition of the silicide layer between the PMIS transistor side and the NMIS transistor side, and can prevent instability of the gate shape of the transistor. To do.

  In one embodiment of the present invention, a first gate structure in which a gate insulating film, a metal film, and a semiconductor film are stacked in this order is formed. Further, a second gate structure in which the gate insulating film and the semiconductor film are stacked in this order is formed. Then, the resistance on the semiconductor substrate on both sides of each gate structure is reduced in a state where the first gate structure and the second gate structure are masked. Then, the resistance of the semiconductor film constituting the first gate structure and the semiconductor film constituting the second gate structure is reduced.

  According to the above embodiment, for example, variations in the composition of the silicide layer can be prevented between the PMIS transistor side and the NMIS transistor side, and instability of the gate shape of the transistor can be prevented.

  In addition, by reducing the resistance of the active region and the resistance of the semiconductor film in separate steps, it is easy to control the reduction of the resistance of the semiconductor film.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

<Embodiment 1>
A manufacturing method of a CMIS (Complementary Metal Insulation Semiconductor) transistor according to this embodiment will be described with reference to process cross-sectional views.

  First, as shown in FIG. 1, a semiconductor substrate 101 having a first region S10 and a second region S20 is prepared. The semiconductor substrate 101 is formed, for example, by epitaxially growing a (100) plane of silicon.

  Here, a first MIS transistor of the first conductivity type is formed in the upper surface of the semiconductor substrate 101 in the first region S10. A second MIS transistor of the second conductivity type is formed in the upper surface of the semiconductor substrate 101 in the second region S20. In the present embodiment, the first conductivity type is “N type”. The second conductivity type is “P type”. Therefore, in the present embodiment, the first MIS transistor is an NMIS transistor, and the second MIS transistor is a PMIS transistor.

  Further, the NMIS transistor and the PMIS transistor are electrically separated by an isolation oxide film (STI: Shallow Trench Isolation) 102. The isolation oxide film 102 is formed in the surface of the semiconductor substrate 101 by combining partial etching, oxide film deposition, and planarization treatment on the semiconductor substrate 101.

  Further, an N-type well region and a P-type well region are formed in the semiconductor substrate 101 by a normal ion implantation process of each conductivity type (not shown in FIG. 1).

  Next, a first gate structure G1 is formed on the semiconductor substrate 101 in the first region S10, which is a stacked structure in which the gate insulating film 103, the metal film 104, and the semiconductor film 106 are stacked in this order. Further, a second gate structure G2 having a stacked structure in which the gate insulating film 103 and the semiconductor film 106 are stacked in this order is formed on the semiconductor substrate 101 in the second region S20.

  Here, the first gate structure G1 is a component of the NMIS transistor. The second gate structure G2 is a component of the PMIS transistor. In the following, a specific method for manufacturing the first gate structure G1 and the second gate structure G2 will be described with reference to FIGS.

  First, the gate insulating film 103 is formed on the upper surface of the semiconductor substrate 101 in the first region S10 and the second region S20 by a CVD (Chemical Vapor Deposition) method or the like (FIG. 2). As the gate insulating film 103, for example, a hafnium silicate film (HfSiO or HfSiON) can be employed.

  Next, as shown in FIG. 2, a metal film 104 is formed on the gate insulating film 103 by, eg, CVD. In the present embodiment, the metal film 104 is a metal having an N-type work function. Hereinafter, the metal film 104 is referred to as N-metal 104 in the present embodiment.

  Here, the metal having an N-type work function is a material having a work function corresponding to energy in the vicinity of the conduction band (Ec = 4.05 eV) end of silicon. Specifically, a metal having an N-type work function refers to a material having a work function value in the range of 4.05 ± 0.3 eV. Examples of the material of the N-metal 104 include Ta compounds (Ta, TaN, TaC, TaSiN, etc.) and Hf compounds (Hf, HfN, HfC, HfSiN, etc.). The film thickness of the N-metal 104 is preferably in the range of about 5 to 30 nm, for example, about 10 nm.

  Next, a resist 105 is formed on the N-metal 104. Thereafter, the resist 105 is patterned by a normal lithography process. Here, as shown in FIG. 3, the patterned resist 105 remains only in the first region S10. In other words, the resist 105 in the second region S20 is removed. Next, wet etching or the like is performed on the N-metal 104 using the patterned resist 105 as a mask. Thereby, as shown in FIG. 3, the N-metal 104 formed in the second region S20 is removed.

  After removing the resist 105 from the first region S10, a silicon film (which can be grasped as a semiconductor film) 106 is formed on the N-metal 104 and the gate insulating film 103 by CVD or the like (FIG. 4). The silicon film 106 may be polycrystalline or amorphous at the time of film formation. The silicon film 106 becomes the polycrystalline silicon film 106 by the activation heat treatment performed later. Here, the film thickness of the silicon film 106 is, for example, about 100 nm.

  Next, as shown in FIG. 4, a gate hard mask 107 such as a silicon oxide film or a silicon nitride film is formed on the silicon film 106. As will be described later, after the silicidation process of the source / drain regions, the polycrystalline silicon film 106 is separately fully silicided. The gate hard mask 107 functions as a protective film for the polycrystalline silicon film 106 so that the polycrystalline silicon film 106 is not silicided in the silicidation process of the source / drain regions.

  As can be seen from FIG. 4, the silicon film 106 and the gate hard mask 107 are formed in both the first region S10 and the second region S20.

  Next, dry etching, wet etching, or the like is performed on the gate insulating film 103, the N-metal 104, the silicon film 106, and the gate hard mask 107. Thereby, as shown in FIG. 5, the first gate structure G1 is formed on the semiconductor substrate 101 in the first region S10, and the second gate is formed on the semiconductor substrate 101 in the second region S20. Structure G2 is formed.

  Here, the first gate structure G1 is a stacked structure in which the gate insulating film 103, the N-metal 104, and the silicon film 106 are stacked in this order (FIG. 5). On the other hand, the second gate structure G2 is a stacked structure in which the gate insulating film 103 and the silicon film 106 are stacked in this order (FIG. 5). A gate hard mask 107 is formed on each of the first gate structure G1 and the second gate structure G2 (FIG. 5).

  Next, the second region S20 is masked, and N-type impurity ions are implanted into the semiconductor substrate 101 on both sides of the first gate structure G1. By the ion implantation, a relatively shallow impurity ion implantation region 108 is formed in the semiconductor substrate 101 on both sides of the first gate structure G1 (FIG. 6).

  On the other hand, with the first region S10 masked, P-type impurity ions are implanted into the semiconductor substrate 101 on both sides of the second gate structure G2. By this ion implantation, a relatively shallow impurity ion implantation region 109 is formed in the semiconductor substrate 101 on both sides of the second gate structure G2 (FIG. 6).

  Next, a silicon oxide film 110 and a silicon nitride film 111 are formed in this order on the semiconductor substrate 101 so as to cover the first gate structure G1 and the second gate structure G2. Thereafter, an anisotropic etching process is performed on the silicon oxide film 110 and the silicon nitride film 111. Thereby, as shown in FIG. 7, sidewall films 110 and 111 having a laminated structure are formed on both side surfaces of the first gate structure G1 and both side surfaces of the second gate structure G2.

  Next, the second region S20 is masked, and N-type impurity ions are implanted again into the semiconductor substrate 101 on both sides of the first gate structure G1. By the ion implantation, a relatively deep impurity ion implantation region 112 is formed in the semiconductor substrate 101 on both sides of the first gate structure G1 (FIG. 8).

  On the other hand, with the first region S10 masked, P-type impurity ions are implanted again into the semiconductor substrate 101 on both sides of the second gate structure G2. By the ion implantation, a relatively deep impurity ion implantation region 113 is formed in the semiconductor substrate 101 on both sides of the second gate structure G2 (FIG. 8).

  Next, in order to activate the impurity ion implantation regions 108, 109, 112, and 113, the structure shown in FIG. 8 is subjected to heat treatment. As a result, source / drain regions 108 and 112 constituting the NMIS transistor are formed in the surface of the semiconductor substrate 101 on both sides of the first gate structure G1. On the other hand, source / drain regions 109 and 113 constituting the PMIS transistor are formed in the surface of the semiconductor substrate 101 on both sides of the second gate structure G2. Note that the silicon film 106 becomes polycrystalline silicon 106 by heat treatment for activation.

  Next, with the first gate structure G1 and the second gate structure G2 masked, a step of reducing the resistance of the source / drain regions 108, 109, 112, 113 is performed.

  Specifically, a nickel film is formed on the semiconductor substrate 101 so as to cover the first gate structure G1 and the second gate structure G2. Then, silicidation processing (which can be understood as low resistance) is performed. Thereafter, the unreacted nickel film is removed. As a result, as shown in FIG. 9, nickel silicide 114 is formed in the surface of the source / drain regions 108, 109, 112, 113. That is, the formation of the nickel silicide 114 reduces the resistance of the upper surface of the semiconductor substrate 101 on both sides of the first gate structure G1 and the upper surface of the semiconductor substrate 101 on both sides of the second gate structure G2.

  Here, gate hard masks 107 are respectively formed on the upper surfaces of the first gate structure G1 and the second gate structure G2. In addition, sidewall films 110 and 111 are formed on both side surfaces of the first gate structure G1 and the second gate structure G2, respectively. Therefore, the gate hard mask 107 and the sidewall films 110 and 111 function as a cap layer, and the polycrystalline silicon film 106 is not silicided.

  Next, an interlayer liner film 115 and an interlayer insulating film 116 are formed in this order on the semiconductor substrate 101 so as to cover the first gate structure G1 and the second gate structure G2 (FIG. 10).

  Next, the upper surface of the polycrystalline silicon film 106 constituting the first gate electrode G1 and the upper surface of the polycrystalline silicon film 106 constituting the second gate electrode G2 are exposed. Thereafter, a process for reducing the resistance of each of the polycrystalline silicon films 106 (which can be grasped as a semiconductor film as described above) is performed.

  Specifically, a silicide metal (for example, Ni) is deposited on the exposed upper surface of each polycrystalline silicon film 106. Thereafter, heat treatment is performed on the semiconductor substrate 101 after the silicidation metal deposition. Thereby, each polycrystalline silicon film 106 is fully silicided (it can be grasped as low resistance). That is, as shown in FIG. 11, the first gate structure G1 has a stacked structure of the gate insulating film 103, the N-metal 104, and the full silicide film 117, and the second gate structure G2 has the gate insulating film 103 and the full silicide film. A laminated structure of the film 117 is obtained.

  In addition to Ni, examples of the silicide metal include Pt, Ti, Co, Hf, Ta, Yb, Er, and Al. Desirably, any one or more of these is included.

  Here, if the film thickness of the N-metal 104 is 5 nm or more, the N-metal 104 indicates the desired work function. If the N-metal 104 has the desired work function, the NMIS transistor can perform a desired threshold voltage operation. For this reason, the composition of the upper layer of the N-metal 104 does not need to be controlled to a desired composition regardless of the threshold voltage control. That is, the full silicide film 117 constituting the first gate structure G1 and the full silicide film 117 constituting the second gate structure G2 may both have the same composition.

  In the method described in the background art, it is necessary to form silicide films having different compositions on the NMIS transistor side and the PMIS transistor side. Therefore, it is necessary to perform a process for making the thickness of the polycrystalline silicon film on the NMIS transistor side different from the thickness of the PMIS polycrystalline silicon film.

  However, in the method according to the present embodiment, as described above, it is not necessary to make the composition of the full silicide film 117 separately on the NMIS transistor side and the PMIS transistor side. That is, the composition of the full silicide film 117 may be the same on the NMIS transistor side and the PMIS transistor side. Therefore, there is no need to selectively etch the polycrystalline silicon film constituting the other MIS transistor as described in the background art.

  When the full silicide film 117 is formed, the nickel silicide 114 in the source / drain region is covered with the interlayer insulating film 116. Therefore, the formation of the full silicide film 117 can prevent the nickel silicide 114 from being resilicided or subjected to etching damage. Therefore, desired device characteristics can be maintained.

In forming the full silicide film 117, the thickness of the silicide metal film, the silicidation heat treatment conditions, the timing of the heat treatment, the timing of removing the unreacted silicidation metal, and the like are controlled. Thereby, the full silicide film 117 constituting the first gate structure G1 and the second gate structure G2 can be a full silicide with a high silicide metal content. Full silicide with a high silicide metal content is a full silicide film having a composition of Ni ₃ Si, Ni ₃₁ Si ₁₂ , or Ni ₂ Si.

For example, a Ni film is deposited to a thickness of 70 nm or more as a silicide metal film on the polycrystalline silicon film 106 having a thickness of 50 nm. Thereafter, the first heat treatment is performed on the semiconductor substrate 101 after the Ni film is formed. Here, the first heat treatment is performed under conditions of 400 ° C. or lower and about 30 seconds. The polycrystalline silicon film 106 and the Ni film are reacted by the first heat treatment. Next, only the unreacted Ni film is removed by selective wet etching. Thereafter, the semiconductor substrate 101 is subjected to a second heat treatment. The second heat treatment is performed at 500 ° C. for about 30 seconds. Under the above formation conditions, a Ni full silicide layer (in this case, Ni ₃₁ Si ₁₂ layer) having a high silicide metal content is formed.

  Thus, at least in the second gate structure G2 constituting the PMIS transistor, the full silicide film 117 is made of full silicide with a high silicide metal content. Thereby, a desired threshold voltage operation can be performed also on the PMIS transistor side.

  After the formation of the full silicide film 117, an interlayer insulating film is stacked, and a normal back-end flow is performed through a flow of flattening by CMP (Chemical Mechanical Polishing) processing, contact plug formation, and the like. Thus, the CMIS transistor is completed.

By the way, in the said nonpatent literature 1, the phenomenon in which an effective work function changes according to the said silicide composition is utilized. Specifically, NiSi is used as the FUSI gate material for the NMIS transistor. For the PMIS transistor, nickel silicide having a high Ni content such as Ni ₃ Si is used as the FUSI gate material. Thereby, the said nonpatent literature 1 proposes that a low threshold voltage Vth device is realizable.

  As a method of forming the silicide phase controlled FUSI gate electrode, for example, the following manufacturing method can be cited.

  That is, the polycrystalline silicon films 1004 and 1005 having the same film thickness are formed in both gate structures on the PMIS transistor side and the NMIS transistor side (FIG. 12). Thereafter, the polycrystalline silicon film 1004 on the NMIS transistor side is covered with a resist 1016, and the thickness of the polycrystalline silicon film 1005 on the PMIS transistor side is reduced (thinned) (FIG. 13). Then, the polysilicon film is silicided in both gate structures on the PMIS transistor side and the NMIS transistor side (FIG. 14).

  By this manufacturing method, a full silicide film 1018 having a low silicide metal content is formed on the NMIS transistor side. On the other hand, on the PMIS transistor side, a full silicide film 1019 having a high silicide metal content is formed. When this manufacturing method is adopted, FUSI gate structures having different compositions are formed simultaneously on the PMIS transistor side and the NMIS transistor side.

  The manufacturing method of the CMIS transistor according to the present embodiment includes a step of forming N-metal 104 between the gate insulating film 103 and the polycrystalline silicon film 106 on the first gate structure G1 side.

  Therefore, it is not necessary to make the composition of the full silicide film 117 separately on the NMIS transistor side and the PMIS transistor side. Therefore, before the resistance reduction (silicidation) process of the polycrystalline silicon film 106, the process of changing the thickness of the polycrystalline silicon film 106 between the first gate structure G1 side and the second gate structure G2 side is also possible. It becomes unnecessary. In addition, the presence of the N-metal 104 eliminates the need to consider diffusion from the semiconductor substrate 101 side in the process of reducing the resistance (silicidation) of the polycrystalline silicon film 106. Therefore, the formation control of the full silicide film 117 can be easily controlled.

  For example, it is assumed that full silicide films having different compositions are formed simultaneously on the NMIS transistor side and the PMIS transistor side. In this case, since the process window in which the composition can be stably formed is narrow, the variation in the full silicide composition is regarded as a problem. For example, even if an attempt is made to form a full silicide film having a low metal content on the NMIS transistor side, a location where a large amount of Ni reaction appears locally and a full silicide phase having a high silicide metal content is formed. Conversely, even if an attempt is made to form a full silicide gate with a high metal content on the P-type transistor side, a portion with a small amount of Ni reaction appears locally and a full silicide phase with a low content of silicide metal is formed. A malfunction occurs.

  As described above, in the present embodiment, it is not necessary to make the composition of the full silicide film 117 separately on the NMIS transistor side and the PMIS transistor side. Therefore, when the full silicide film 117 is formed on the NMIS transistor side and the PMIS transistor side, the same composition can be made by the same heat treatment conditions and the same silicon / silicide metal film thickness. For this reason, the process control window is widened, and variations in the composition of the full silicide film 117 can be prevented.

  Further, when it is necessary to make the thickness of the polycrystalline silicon film 106 different between the first gate structure G1 side and the second gate structure G2 side, the existing sidewalls 110 and 111, offset spacers, The interlayer insulating film and the like are also etched. As a result, the gate shape before Ni deposition may deteriorate, or Ni silicide or the like formed in the source / drain regions 108, 109, 112, 113 may be exposed and deteriorated.

  In the present embodiment, as described above, there is no need to perform the process of making the thickness of the polycrystalline silicon film 106 different between the first gate structure G1 side and the second gate structure G2 side. Therefore, instability of the gate shape of the MIS transistor can be prevented.

  From the above viewpoints, the manufacturing method according to the present embodiment makes it possible to easily create a dual metal gate device (CMIS device) having good characteristics.

  In the CMIS transistor manufacturing method according to the present embodiment, the nickel silicide 114 forming process and the full silicide film 117 forming process are performed in separate silicide processes. In particular, after the formation process of the nickel silicide 114, the full silicide film 117 is formed.

  Therefore, it is possible to simultaneously satisfy the reduction in resistance of the source / drain regions 108, 109, 112, and 113 and the threshold control of the gate structures G1 and G2 having the full silicide film 117. In addition, when forming the nickel silicide 114, the formation of the full silicide film 117 can be controlled more easily by adopting the above-mentioned separate process than when a part of the polycrystalline silicon film 106 is silicided.

  In the CMIS transistor manufacturing method according to the present embodiment, only one layer of N-metal 104 is formed as the metal film 104. Therefore, the metal film 104 can be patterned more easily by the method according to the present embodiment than when the metal film 104 is a multilayer. That is, the first gate structure G1 can be formed more easily by the method according to the present embodiment.

  In the CMIS transistor manufacturing method according to the present embodiment, each polycrystalline silicon film 106 is fully silicided. Therefore, the overall resistance of the gate structures G1 and G2 can be reduced.

  In the CMIS transistor manufacturing method according to the present embodiment, the metal film 104 is an N-metal (Ta compound or Hf compound) 104 having an N-type work function. The NMIS transistor can perform a desired threshold voltage operation.

  In the CMIS transistor manufacturing method according to the present embodiment, the N-metal 104 having a thickness of about 5 to 30 nm is formed. Therefore, the work function of the N-metal 104 can be in the range of 4.05 ± 0.3 eV. As a result, the NMIS transistor can perform a desired threshold voltage operation.

In the CMIS transistor manufacturing method according to the present embodiment, the polycrystalline silicon film 106 constituting the second gate structure G2 is made to have any composition of Ni ₃ Si, Ni ₃₁ Si ₁₂ , and Ni ₂ Si. , Silicidation. Therefore, the PMIS transistor can perform a desired threshold voltage operation.

  In the CMIS transistor manufacturing method according to the present embodiment, the polycrystalline silicon film 106 is made of a metal containing at least one of Ni, Pt, Ti, Co, Hf, Ta, Yb, Er, and Al. It is fully silicided. Therefore, the full silicide film 117 can be easily formed.

  In the first embodiment, the case where the polycrystalline silicon film 106 is used as the semiconductor film 106 is described. However, a germanium film or a silicon germanium film may be used as the semiconductor film 106. In this case, the semiconductor film 106 becomes a full germanite gate or the like by the low resistance treatment.

  Thus, by using a germanium film or a silicon germanium film as the semiconductor film 106, the work function control range of the gate electrode after the resistance reduction is changed as compared with the case where the polycrystalline silicon film is employed. Therefore, a device having a desired threshold voltage can be realized by changing the material according to the specification of the device.

<Embodiment 2>
A method for manufacturing the CMIS transistor according to this embodiment will be described with reference to process cross-sectional views.

  First, as shown in FIG. 15, a semiconductor substrate 201 having a first region S30 and a second region S40 is prepared. The semiconductor substrate 201 is formed, for example, by epitaxially growing a (100) plane of silicon.

  Here, a first MIS transistor of the first conductivity type is formed in the upper surface of the semiconductor substrate 201 in the first region S30. A second MIS transistor of the second conductivity type is formed in the upper surface of the semiconductor substrate 201 in the second region S40. In the present embodiment, the first conductivity type is “P-type”. The second conductivity type is “N type”. Therefore, in the present embodiment, the first MIS transistor is a PMIS transistor, and the second MIS transistor is an NMIS transistor.

  Further, the NMIS transistor and the PMIS transistor are electrically separated by an isolation oxide film 202 formed in the surface of the semiconductor substrate 202. The method for forming the isolation oxide film 202 is the same as the method for forming the isolation oxide film 102 described in the first embodiment.

  Further, an N-type well region and a P-type well region are formed in the semiconductor substrate 201 by a normal ion implantation process of each conductivity type (not shown in FIG. 15).

  Next, a first gate structure G11 having a stacked structure in which a gate insulating film 203, a metal film 204, and a semiconductor film 206 are stacked in this order is formed on the semiconductor substrate 201 in the first region S30. Further, a second gate structure G12 having a stacked structure in which the gate insulating film 203 and the semiconductor film 206 are stacked in this order is formed on the semiconductor substrate 201 in the second region S40.

  Here, the first gate structure G11 is a component of the PMIS transistor. The second gate structure G12 is a component of the NMIS transistor. In the following, a specific method for manufacturing the first gate structure G11 and the second gate structure G12 will be described with reference to FIGS.

  First, the gate insulating film 203 is formed on the upper surface of the semiconductor substrate 201 in the first region S30 and the second region S40 by CVD or the like (FIG. 16). As the gate insulating film 203, for example, a hafnium silicate film (HfSiO or HfSiON) can be employed.

  Next, as shown in FIG. 16, a metal film 204 is formed on the gate insulating film 203 by, eg, CVD. In the present embodiment, the metal film 204 is a metal having a P-type work function. Hereinafter, the metal film 204 is referred to as P-metal 204 in the present embodiment.

Here, the metal having a P-type work function is a material having a work function corresponding to energy in the vicinity of the valence band (Ev = 5.12 eV) edge of silicon. Specifically, a metal having a P-type work function refers to a material having a work function value in the range of 5.17 ± 0.3 eV. Examples of the material of the P-metal 204 include Ti compounds (TiN, TiAlN, etc.), W compounds (W, WN, etc.), Ru compounds (Ru, RuO ₂ etc.), Pt compounds, and the like. The film thickness of the P-metal 204 is preferably in the range of about 5 to 30 nm, for example, about 10 nm.

  Next, a resist 205 is formed on the P-metal 204. Thereafter, the resist 205 is patterned by a normal lithography process. Here, as shown in FIG. 17, the patterned resist 205 remains only in the first region S30. In other words, the resist 205 in the second region S40 is removed. Next, wet etching or the like is performed on the P-metal 204 using the patterned resist 205 as a mask. As a result, as shown in FIG. 17, the P-metal 204 formed in the second region S40 is removed.

  After removing the resist 205 from the first region S30, a silicon film (which can be grasped as a semiconductor film) 206 is formed on the P-metal 204 and the gate insulating film 203 by CVD or the like (FIG. 18). The silicon film 206 may be polycrystalline or amorphous at the time of film formation. The silicon film 206 becomes the polycrystalline silicon film 206 by the activation heat treatment performed later. Here, the film thickness of the silicon film 206 is about 100 nm, for example.

  Next, as shown in FIG. 18, a gate hard mask 207 such as a silicon oxide film or a silicon nitride film is formed on the silicon film 206. As will be described later, after the silicidation process of the source / drain regions, the polycrystalline silicon film 206 is separately fully silicided. The gate hard mask 207 functions as a protective film for the polycrystalline silicon film 206 so that the polycrystalline silicon film 206 is not silicided in the silicidation process of the source / drain regions.

  As can be seen from FIG. 18, the silicon film 206 and the gate hard mask 207 are formed in both the first region S30 and the second region S40.

  Next, dry etching, wet etching, or the like is performed on the gate insulating film 203, the P-metal 204, the silicon film 206, and the gate hard mask 207. Accordingly, as shown in FIG. 19, the first gate structure G11 is formed on the semiconductor substrate 201 in the first region S30, and the second gate is formed on the semiconductor substrate 201 in the second region S40. Structure G2 is formed.

  Here, the first gate structure G11 is a stacked structure in which the gate insulating film 203, the P-metal 204, and the silicon film 206 are stacked in this order (FIG. 19). On the other hand, the second gate structure G12 is a stacked structure in which a gate insulating film 203 and a silicon film 206 are stacked in this order (FIG. 19). A gate hard mask 207 is formed on each of the first gate structure G11 and the second gate structure G12 (FIG. 19).

  Next, the second region S40 is masked, and P-type impurity ions are implanted into the semiconductor substrate 201 on both sides of the first gate structure G11. By the ion implantation, a relatively shallow impurity ion implantation region 208 is formed in the semiconductor substrate 201 on both sides of the first gate structure G11 (FIG. 20).

  On the other hand, masking the first region S30, N-type impurity ions are implanted into the semiconductor substrate 201 on both sides of the second gate structure G12. By the ion implantation, a relatively shallow impurity ion implantation region 209 is formed in the semiconductor substrate 201 on both sides of the second gate structure G12 (FIG. 20).

  Next, a silicon oxide film 210 and a silicon nitride film 211 are formed in this order on the semiconductor substrate 201 so as to cover the first gate structure G11 and the second gate structure G12. Thereafter, anisotropic etching is performed on the silicon oxide film 210 and the silicon nitride film 211. As a result, as shown in FIG. 21, sidewall films 210 and 211 having a laminated structure are formed on both side surfaces of the first gate structure G11 and both side surfaces of the second gate structure G12.

  Next, the second region S40 is masked, and P-type impurity ions are implanted again into the semiconductor substrate 201 on both sides of the first gate structure G11. By the ion implantation, a relatively deep impurity ion implantation region 212 is formed in the semiconductor substrate 201 on both sides of the first gate structure G11 (FIG. 22).

  On the other hand, the first region S30 is masked, and N-type impurity ions are again implanted into the semiconductor substrate 201 on both sides of the second gate structure G12. By the ion implantation, relatively deep impurity ion implantation regions 213 are formed in the semiconductor substrate 201 on both sides of the second gate structure G12 (FIG. 22).

  Next, in order to activate the impurity ion implantation regions 208, 209, 212, and 213, the structure shown in FIG. 22 is subjected to heat treatment. Thus, source / drain regions 208 and 212 constituting the PMIS transistor are formed in the surface of the semiconductor substrate 201 on both sides of the first gate structure G11. On the other hand, source / drain regions 209 and 213 constituting the NMIS transistor are formed in the surface of the semiconductor substrate 201 on both sides of the second gate structure G12. Note that the silicon film 206 becomes polycrystalline silicon 206 by heat treatment for activation.

  Next, a process of reducing the resistance of the source / drain regions 208, 209, 212, and 213 is performed in a state where the first gate structure G11 and the second gate structure G12 are masked.

  Specifically, a nickel film is formed on the semiconductor substrate 201 so as to cover the first gate structure G11 and the second gate structure G12. Then, silicidation processing (which can be understood as low resistance) is performed. Thereafter, the unreacted nickel film is removed. As a result, as shown in FIG. 23, nickel silicide 214 is formed in the surfaces of the source / drain regions 208, 209, 212, and 213. That is, the formation of the nickel silicide 214 reduces the resistance of the upper surface of the semiconductor substrate 201 on both sides of the first gate structure G11 and the upper surface of the semiconductor substrate 201 on both sides of the second gate structure G12.

  Here, gate hard masks 207 are respectively formed on the upper surfaces of the first gate structure G11 and the second gate structure G12. Further, sidewall films 210 and 211 are formed on both side surfaces of the first gate structure G11 and the second gate structure G12, respectively. Therefore, the gate hard mask 207 and the sidewall films 210 and 211 function as a cap layer, and the polycrystalline silicon film 206 is not silicided.

  Next, an interlayer liner film 215 and an interlayer insulating film 216 are formed in this order on the semiconductor substrate 201 so as to cover the first gate structure G11 and the second gate structure G12 (FIG. 24).

  Next, the upper surface of the polycrystalline silicon film 206 constituting the first gate electrode G11 and the upper surface of the polycrystalline silicon film 206 constituting the second gate electrode G12 are exposed. Thereafter, a process for reducing the resistance of each of the polycrystalline silicon films 206 (which can be grasped as a semiconductor film as described above) is performed.

  Specifically, a silicide metal (for example, Ni) is deposited on the exposed upper surface of each polycrystalline silicon film 206. Thereafter, a heat treatment is performed on the semiconductor substrate 201 after the silicidation metal deposition. Thereby, each polycrystalline silicon film 206 is fully silicided (it can be grasped as low resistance). That is, as shown in FIG. 25, the first gate structure G11 has a stacked structure of the gate insulating film 203, the P-metal 204, and the full silicide film 217, and the second gate structure G12 has the gate insulating film 203 and the full silicide film. A laminated structure of the film 217 is obtained.

  In addition to Ni, examples of the silicide metal include Pt, Ti, Co, Hf, Ta, Yb, Er, and Al. Desirably, any one or more of these is included.

  Here, if the film thickness of the P-metal 204 is 5 nm or more, the P-metal 204 indicates the desired work function. If the P-metal 204 has the desired work function, the PMIS transistor can perform a desired threshold voltage operation. For this reason, the composition of the upper layer of the P-metal 204 is not required to control the composition of the full silicide film 217 to a desired composition regardless of the threshold voltage control. That is, the full silicide film 217 constituting the first gate structure G11 and the full silicide film 217 constituting the second gate structure G12 may both have the same composition.

  In the method described in the background art, it is necessary to form silicide films having different compositions on the NMIS transistor side and the PMIS transistor side. Therefore, it is necessary to perform a process for making the thickness of the polycrystalline silicon film on the NMIS transistor side different from the thickness of the PMIS polycrystalline silicon film.

  However, in the method according to the present embodiment, as described above, it is not necessary to make the composition of the full silicide film 217 separately on the NMIS transistor side and the PMIS transistor side. That is, the composition of the full silicide film 217 may be the same on the NMIS transistor side and the PMIS transistor side. Therefore, there is no need to selectively etch the polycrystalline silicon film constituting the other MIS transistor as described in the background art.

  In forming the full silicide film 217, the nickel silicide 214 is covered with the interlayer insulating film 216. Therefore, the formation of the full silicide film 217 can prevent the nickel silicide 214 from being resilicided or suffering from etching damage. Therefore, desired device characteristics can be maintained.

In forming the full silicide film 217, the thickness of the silicide metal film, the silicidation heat treatment conditions, the timing of the heat treatment, the timing of removing the unreacted silicidation metal, and the like are controlled. Thereby, the full silicide film 217 constituting the first gate structure G11 and the second gate structure G12 can be made into a full silicide with a low silicide metal content. The full silicide with a low silicide metal content is a full silicide film having a composition such as NiSi or NiSi ₂ .

  For example, a Ni film is deposited with a thickness of 30 nm or more as a silicide metal film on the polycrystalline silicon film 206 having a thickness of 50 nm. Thereafter, the first heat treatment is performed on the semiconductor substrate 201 after the Ni film is formed. Here, the first heat treatment is performed under conditions of 400 ° C. or lower and about 30 seconds. The polycrystalline silicon film 206 and the Ni film are reacted by the first heat treatment. Next, only the unreacted Ni film is removed by selective wet etching. Thereafter, the semiconductor substrate 201 is subjected to a second heat treatment. The second heat treatment is performed at 500 ° C. for about 30 seconds. Under the above formation conditions, a Ni full silicide layer (in this case, a NiSi layer) having a low silicide metal content is formed.

  Thus, at least in the second gate structure G12 constituting the NMIS transistor, the full silicide film 217 is made of full silicide with a low silicide metal content. Thereby, a desired threshold voltage operation can be performed also on the NMIS transistor side.

  After the formation of the full silicide film 217, an interlayer insulating film is stacked, and a normal back-end flow is performed through a flow such as planarization by CMP processing and contact plug formation. Thus, the CMIS transistor is completed.

  The manufacturing method of the CMIS transistor according to the present embodiment includes a step of forming P-metal 204 between the gate insulating film 203 and the polycrystalline silicon film 206 on the first gate structure G11 side.

  Therefore, it is not necessary to make the composition of the full silicide film 217 separately on the NMIS transistor side and the PMIS transistor side. Therefore, before the resistance of the polycrystalline silicon film 206 is reduced (silicidation), the thickness of the polycrystalline silicon film 206 is different between the first gate structure G11 side and the second gate structure G12 side. It becomes unnecessary. Further, the presence of the P-metal 204 eliminates the need to consider diffusion from the semiconductor substrate 201 side when the resistance of the polycrystalline silicon film 206 is reduced (silicidation). Therefore, the formation control of the full silicide film 217 can be easily controlled.

  As described above, in the present embodiment, it is not necessary to make the composition of the full silicide film 217 separately on the NMIS transistor side and the PMIS transistor side. Therefore, when the full silicide film 217 is formed on the NMIS transistor side and the PMIS transistor side, the same composition can be produced by the same heat treatment conditions and the same silicon / silicide metal film thickness. For this reason, the process control window is widened, and variations in the composition of the full silicide film 217 can be prevented.

  In the present embodiment, as described above, there is no need to perform the process of making the thickness of the polycrystalline silicon film 206 different between the first gate structure G11 side and the second gate structure G12 side. Therefore, instability of the gate shape of the MIS transistor can be prevented.

  From the above viewpoints, the manufacturing method according to the present embodiment makes it possible to easily create a dual metal gate device (CMIS device) having good characteristics.

  In the CMIS transistor manufacturing method according to the present embodiment, the nickel silicide 214 formation process and the full silicide film 217 formation process are performed in separate silicide processes. In particular, the full silicide film 217 is formed after the nickel silicide 214 formation process.

  Therefore, it is possible to simultaneously satisfy the reduction in resistance of the source / drain regions 208, 209, 212, and 213 and the threshold control of the gate structures G11 and G12 having the full silicide film 217. In addition, when forming the nickel silicide 214, it is easier to control the formation of the full silicide film 217 by adopting the above-described separate process than when part of the polycrystalline silicon film 206 is silicided.

  In the CMIS transistor manufacturing method according to the present embodiment, only one layer of P-metal 204 is formed as the metal film 204. Therefore, the metal film 204 can be patterned more easily by the method according to the present embodiment than when the metal film 204 is a multilayer. That is, the first gate structure G11 can be formed more easily by the method according to the present embodiment.

  In the CMIS transistor manufacturing method according to the present embodiment, each polysilicon film 206 is fully silicided. Therefore, the overall resistance of the gate structures G11 and G12 can be reduced.

  In the CMIS transistor manufacturing method according to the present embodiment, the metal film 204 is P-metal (Ti compound, W compound, Ru compound, and Pt compound) 204 having a P-type work function. The PMIS transistor can perform a desired threshold voltage operation.

  Further, in the method for manufacturing the CMIS transistor according to the present embodiment, the P-metal 204 having a film thickness of about 5 to 30 nm is formed. Therefore, the work function of the P-metal 204 can be in the range of 5.17 ± 0.3 eV. As a result, the PMIS transistor can perform a desired threshold voltage operation.

In the CMIS transistor manufacturing method according to the present embodiment, the polycrystalline silicon film 206 constituting the second gate structure G12 is silicided with a composition of NiSi or NiSi ₂ . Therefore, the NMIS transistor can perform a desired threshold voltage operation.

  In the CMIS transistor manufacturing method according to the present embodiment, the polycrystalline silicon film 206 is made of a metal containing at least one or more of Ni, Pt, Ti, Co, Hf, Ta, Yb, Er, and Al. It is fully silicided. Therefore, the full silicide film 217 can be easily formed.

  In the second embodiment, the case where the polycrystalline silicon film 206 is used as the semiconductor film 206 is described. However, a germanium film or a silicon germanium film may be used as the semiconductor film 206. In this case, the semiconductor film 206 becomes a full germanite gate or the like by the low resistance treatment.

  Thus, by using a germanium film or a silicon germanium film as the semiconductor film 206, the work function control range of the gate electrode after the resistance reduction is changed as compared with the case where the polycrystalline silicon film is employed. Therefore, a device having a desired threshold voltage can be realized by changing the material according to the specification of the device.

<Embodiment 3>
A method for manufacturing the CMIS transistor according to this embodiment will be described with reference to process cross-sectional views.

  The steps from FIG. 1 to FIG. 10 are the same as those in the first embodiment. Therefore, detailed description of these steps is omitted here.

  Here, in the present embodiment, as in the first embodiment, the first MIS transistor of the first conductivity type is formed in the upper surface of the semiconductor substrate 101 in the first region S10. A second MIS transistor of the second conductivity type is formed in the upper surface of the semiconductor substrate 101 in the second region S20. In the present embodiment, the first conductivity type is “N type”. The second conductivity type is “P type”. Therefore, in the present embodiment, as in the first embodiment, the first MIS transistor is an NMIS transistor, and the second MIS transistor is a PMIS transistor.

  Next, in the configuration of FIG. 10, the upper surface of the polycrystalline silicon film 106 constituting the first gate electrode G1 and the upper surface of the polycrystalline silicon film 106 constituting the second gate electrode G2 are exposed. Next, the second region S20 is masked with a resist. Then, the polycrystalline silicon film 106 constituting the first gate structure G1 is doped with at least one or more of nitrogen, oxygen, phosphorus, etc. by ion implantation.

  By the ion implantation, as shown in FIG. 26, a polycrystalline silicon film 106a constituting the first gate structure G1 is formed. In the silicidation process of the polycrystalline silicon film 106a performed later, the polycrystalline silicon film 106a has a function of suppressing diffusion of silicide metal in the direction of the semiconductor substrate 101. Specifically, entry of silicide metal into the N-metal 104 film can be suppressed. FIG. 26 shows the configuration after removing the resist mask formed in the second region S20.

  Thereafter, a process for reducing the resistance of the polycrystalline silicon films 106 and 106a (which can be grasped as semiconductor films as described above) is performed.

  Specifically, a silicide metal (for example, Ni) is deposited on the exposed upper surfaces of the polycrystalline silicon films 106 and 106a. Thereafter, heat treatment is performed on the semiconductor substrate 101 after the silicidation metal deposition. Thereby, the polycrystalline silicon films 106 and 106a are silicided (it can be grasped as low resistance).

  Here, the polycrystalline silicon 106a suppresses diffusion of silicide metal. Therefore, all of the polycrystalline silicon 106a is not silicided on the first gate electrode G1 side. That is, as shown in FIG. 27, the first gate structure G1 has a laminated structure of the gate insulating film 103, the N-metal 104, the polycrystalline polysilicon film 106a into which impurity ions are implanted, and the silicide film 117. The second gate structure G2 is a stacked structure of the gate insulating film 103 and the full silicide film 117.

  In addition to Ni, examples of the silicide metal include Pt, Ti, Co, Hf, Ta, Yb, Er, and Al, and it is preferable that any one or more of these be included.

  Even when the polycrystalline silicon film 106a is formed, the NMIS transistor exhibits a desired work function if the film thickness of the N-metal 104 is 5 nm or more. Therefore, the NMIS transistor can perform a desired threshold voltage operation regardless of the electrode structure of the upper layer of the N-metal 104. For this reason, the composition of the upper layer of the N-metal 104 is not required to control the composition of the silicide film 117 to a desired composition regardless of the threshold voltage control. That is, the silicide film 117 constituting the first gate structure G1 and the full silicide film 117 constituting the second gate structure G2 may both have the same composition.

  When forming the silicide film 117, the nickel silicide 114 is covered with the interlayer insulating film 116. Therefore, the formation of the silicide film 117 can prevent the nickel silicide 114 from being resilicided or damaged by etching. Therefore, desired device characteristics can be maintained.

Further, when the silicide film 117 is formed, the thickness of the silicide metal film, the silicidation heat treatment conditions, the timing of the heat treatment, the timing of removing the unreacted silicidation metal, and the like are controlled (an example of the formation conditions is the first embodiment). As explained). Thereby, the silicide film 117 constituting the first gate structure G1 and the second gate structure G2 can be a full silicide with a high silicide metal content. A silicide having a high silicide metal content is a silicide film having any composition of Ni ₃ Si, Ni ₃₁ Si ₁₂ , and Ni ₂ Si.

  Thus, at least in the second gate structure G2 constituting the PMIS transistor, the full silicide film 117 is made of full silicide with a high silicide metal content. Thereby, a desired threshold voltage operation can be performed also on the PMIS transistor side.

  After the formation of the silicide film 117, an interlayer insulating film is stacked, and a normal back-end flow is performed through a flow such as planarization by CMP processing and contact plug formation. Thus, the CMIS transistor is completed.

  In the present embodiment, since the above steps are performed, in addition to the effects described in the first embodiment, the following effects are also obtained.

  Specifically, in the present embodiment, before siliciding the polycrystalline silicon 106 constituting the first gate structure G1, at least one of phosphorus, arsenic, and oxygen is formed on the polycrystalline silicon 106. Ion implantation.

  Accordingly, the formation of the ion-implanted polycrystalline silicon film 106a can suppress diffusion of silicide metal toward the semiconductor substrate 101 when the polycrystalline silicon film 106a is silicided. Specifically, intrusion of silicide metal into the N-metal 104 can be suppressed. Thereby, there is no influence such as changing the work function on the NMIS transistor side, and a stable CMIS device can be realized.

  By performing the ion implantation process, the first gate structure G1 includes a gate insulating film 103, an N-metal 104, a polycrystalline polysilicon film 106a into which impurity ions are implanted, and a silicide film 117, which are stacked in this order. It becomes a laminated structure.

  As the semiconductor film 106, a germanium film or a silicon germanium film may be used instead of polycrystalline silicon. In this case, the semiconductor film 106 becomes a germanite gate or the like by the resistance reduction treatment.

<Embodiment 4>
A method for manufacturing the CMIS transistor according to this embodiment will be described with reference to process cross-sectional views.

  The steps from FIG. 15 to FIG. 24 are the same as those in the second embodiment. Therefore, detailed description of these steps is omitted here.

  Here, in the present embodiment, as in the second embodiment, a first MIS transistor of the first conductivity type is formed in the upper surface of the semiconductor substrate 201 in the first region S30. A second MIS transistor of the second conductivity type is formed in the upper surface of the semiconductor substrate 201 in the second region S40. In the present embodiment, the first conductivity type is “P-type”. The second conductivity type is “N type”. Therefore, in the present embodiment, as in the second embodiment, the first MIS transistor is a PMIS transistor, and the second MIS transistor is an NMIS transistor.

  Next, in the configuration of FIG. 24, the upper surface of the polycrystalline silicon film 206 constituting the first gate electrode G11 and the upper surface of the polycrystalline silicon film 206 constituting the second gate electrode G12 are exposed. Next, the second region S40 is masked with a resist. The polycrystalline silicon film 206 constituting the first gate structure G11 is doped with at least one of nitrogen, oxygen, phosphorus, etc. by ion implantation.

  By the ion implantation, as shown in FIG. 28, a polycrystalline silicon film 206a constituting the first gate structure G11 is formed. In the silicidation step of the polycrystalline silicon film 206a performed later, the polycrystalline silicon film 206a has a function of suppressing diffusion of silicide metal in the direction of the semiconductor substrate 201. Specifically, entry of silicide metal into the P-metal 204 film can be suppressed. FIG. 28 shows the configuration after removing the resist mask formed in the second region S40.

  Thereafter, a process for reducing the resistance of the polycrystalline silicon films 206 and 206a (which can be grasped as semiconductor films as described above) is performed.

  Specifically, a silicide metal (for example, Ni or the like) is deposited on the exposed upper surfaces of the polycrystalline silicon films 206 and 206a. Thereafter, a heat treatment is performed on the semiconductor substrate 201 after the silicidation metal deposition. Thereby, the polycrystalline silicon films 206 and 206a are silicided (it can be grasped as low resistance).

  Here, the polycrystalline silicon 206a suppresses diffusion of silicide metal. Therefore, all of the polycrystalline silicon 206a is not silicided on the first gate electrode G11 side. That is, as shown in FIG. 29, the first gate structure G11 has a stacked structure of the gate insulating film 203, the P-metal 204, the polycrystalline polysilicon film 206a into which impurity ions are implanted, and the silicide film 217. The second gate structure G12 has a stacked structure of the gate insulating film 203 and the full silicide film 217.

  In addition to Ni, examples of the silicide metal include Pt, Ti, Co, Hf, Ta, Yb, Er, and Al, and it is preferable that any one or more of these be included.

  Even when the polycrystalline silicon film 206a is formed, the PMIS transistor exhibits a desired work function if the thickness of the P-metal 204 is 5 nm or more. Therefore, regardless of the electrode structure of the upper layer of the P-metal 204, the PMIS transistor can perform a desired threshold voltage operation. For this reason, the composition of the upper layer of the P-metal 204 is not required to control the composition of the silicide film 217 to a desired composition regardless of the threshold voltage control. That is, the silicide film 217 constituting the first gate structure G11 and the silicide film 217 constituting the second gate structure G12 may both have the same composition.

  Note that when the silicide film 217 is formed, the nickel silicide 214 is covered with the interlayer insulating film 216. Therefore, the formation of the silicide film 217 can prevent the nickel silicide 214 from being re-silicided or subjected to etching damage. Therefore, desired device characteristics can be maintained.

In forming the silicide film 217, the thickness of the silicide metal film, the silicidation heat treatment conditions, the timing of the heat treatment, the timing of removing the unreacted silicidation metal, and the like are controlled. As a result, the silicide film 217 constituting the first gate structure G11 and the second gate structure G12 can be a full silicide with a low silicide metal content. A silicide having a low silicide metal content is a silicide film having a composition such as NiSi or NiSi ₂ .

  Thus, at least in the second gate structure G12 constituting the NMIS transistor, the full silicide film 217 is made of full silicide with a low silicide metal content. Thereby, a desired threshold voltage operation can be performed also on the NMIS transistor side.

  After the formation of the silicide film 217, an interlayer insulating film is stacked, and a normal back-end flow is performed through a flow such as planarization by CMP processing and contact plug formation. Thus, the CMIS transistor is completed.

  In the present embodiment, since the above steps are performed, in addition to the effects described in the second embodiment, the following effects are also obtained.

  Specifically, in the present embodiment, before siliciding the polycrystalline silicon 206 constituting the first gate structure G11, at least one of phosphorus, arsenic, and oxygen is formed on the polycrystalline silicon 206. Ion implantation.

  Accordingly, the formation of the ion-implanted polycrystalline silicon film 206a can suppress diffusion of silicide metal in the direction of the semiconductor substrate 201 when the polycrystalline silicon film 206a is silicided. Specifically, intrusion of silicide metal into the P-metal 204 can be suppressed. Thereby, there is no influence such as changing the work function on the PMIS transistor side, and a stable CMIS device can be realized.

  By performing the ion implantation process, the first gate structure G11 includes a gate insulating film 203, a P-metal 204, a polycrystalline polysilicon film 206a into which impurity ions are implanted, and a silicide film 217, which are stacked in this order. It becomes a laminated structure.

  Further, as the semiconductor film 206, a germanium film or a silicon germanium film may be used instead of polycrystalline silicon. In this case, the semiconductor film 206 becomes a germanite gate or the like by the low resistance treatment.

<Embodiment 5>
The CMIS transistor manufacturing method according to the present embodiment is an application of the CMIS transistor manufacturing method according to the first embodiment. A manufacturing method according to the present embodiment will be described with reference to process cross-sectional views.

  The semiconductor substrate 101 shown in FIG. 1 is prepared. As described in the first embodiment, the NMIS transistor is formed in the first region S10, and the PMIS transistor is formed in the second region S20. By the ion implantation process, an N-type well region and a P-type well region are formed in the semiconductor substrate 101 (not shown in FIG. 1).

  Next, a stack in which a gate insulating film 103, a metal film (N-metal) 104, an upper metal film 404, and a semiconductor film (polycrystalline silicon film) 106 are stacked in this order on the semiconductor substrate 101 in the first region S10. A first gate structure G31, which is a structure, is formed. In addition, a second gate structure G2 having a stacked structure in which a gate insulating film 103 and a semiconductor film (polycrystalline silicon film) 106 are stacked in this order is formed on the semiconductor substrate 101 in the second region S20.

  Here, the first gate structure G31 is a component of the NMIS transistor. The second gate structure G2 is a component of the PMIS transistor. In the following, a specific method for manufacturing the first gate structure G31 and the second gate structure G2 will be described with reference to FIGS.

  First, as described in the first embodiment, the gate insulating film 103 made of a hafnium silicate film is formed on the semiconductor substrate 101 in the first region S10 and the second region S20 (FIG. 30). Next, as in Embodiment 1, N-metal 104 is formed on the gate insulating film 103 (FIG. 30). The film thickness of N-metal 104 is about 5 nm to 30 nm, for example, 10 nm.

  Next, in this embodiment, an upper metal film 404 is formed on the N-metal 104 (FIG. 30). The upper metal film 404 functions as an antioxidant film for the N-metal 104. For example, any one of TiN, TaN, and HfN is suitable as the upper metal film 404 having the function.

  Next, a resist 105 having a predetermined pattern is formed on the upper metal film 404 (FIG. 31). As shown in FIG. 31, the patterned resist 105 remains only in the first region S10. Next, using the patterned resist 105 as a mask, wet etching or the like is performed on the upper metal film 404 and the N-metal 104. Thereby, as shown in FIG. 31, the upper metal film 404 and the N-metal 104 formed in the second region S20 are removed.

  After removing the resist 105 from the first region S10, the silicon film 106 described in Embodiment 1 is formed over the upper metal film 404 and the gate insulating film 103 (FIG. 32). Next, as shown in FIG. 32, the gate hard mask 107 shown in the first embodiment is formed on the polycrystalline silicon film 106. As can be seen from FIG. 32, the polycrystalline silicon film 106 and the gate hard mask 107 are formed in both the first region S10 and the second region S20.

  Next, dry etching, wet etching, or the like is performed on the gate insulating film 103, the N-metal 104, the upper metal film 404, the polycrystalline silicon film 106, and the gate hard mask 107. Thus, as shown in FIG. 33, the first gate structure G31 is formed on the semiconductor substrate 101 in the first region S10, and the second gate is formed on the semiconductor substrate 101 in the second region S20. Structure G2 is formed.

  Here, the first gate structure G31 is a stacked structure in which the gate insulating film 103, the N-metal 104, the upper metal film 404, and the polycrystalline silicon film 106 are stacked in this order (FIG. 33). On the other hand, the second gate structure G2 is a stacked structure in which the gate insulating film 103 and the polycrystalline silicon film 106 are stacked in this order (FIG. 33). A gate hard mask 107 is formed on each of the first gate structure G31 and the second gate structure G2 (FIG. 33).

  Thereafter, as in the first embodiment, formation of source / drain regions 108, 112, 109, 113, formation of sidewall films 110, 111, formation of nickel silicide 114, formation of interlayer liner film 115 and interlayer insulating film 116, Further, a full silicidation process or the like of the polycrystalline silicon film 106 is performed.

  Thereby, the structure shown in FIG. 34 is formed. As shown in FIG. 34, the first gate structure G31 has a stacked structure of the gate insulating film 103, the N-metal 104, the upper metal film 404, and the full silicide film 117, and the second gate structure G2 has the gate insulating film 103. In addition, a stacked structure of the full silicide film 117 is obtained. As described in the first embodiment, the full silicide film 117 constituting the second gate structure G2 is full silicide having a high silicide metal content.

  After the formation of the full silicide film 117, an interlayer insulating film is stacked, and a normal back-end flow is performed through a flow such as planarization by CMP processing and contact plug formation. Thus, the CMIS transistor is completed.

  In the present embodiment, since the above steps are performed, in addition to the effects described in the first embodiment, the following effects are also obtained.

  Specifically, in this embodiment mode, the gate insulating film 103, the N-metal 104, the upper metal film 404, and the polycrystalline silicon film 106 (which later becomes the full silicide film 117) are stacked in that order. And a step of forming the first gate structure G31. Here, the upper metal film 404 is one of TiN, TaN, and HfN.

  Therefore, since the upper metal film 404 is formed on the N-metal 104, it is possible to prevent the silicide metal from entering the N-metal 104 when the polycrystalline silicon 106 is fully silicided. Furthermore, since the upper metal film 404 is made of TiN, TaN, HfN, or the like, it functions as an anti-oxidation layer for the N-metal 104. Therefore, the N-metal 104 can be prevented from being deteriorated during the wafer process. As described above, stable device characteristics can be realized.

  As the semiconductor film 106, a germanium film or a silicon germanium film may be used instead of polycrystalline silicon. In this case, the semiconductor film 106 becomes a full germanite gate or the like by the low resistance treatment.

<Embodiment 6>
The CMIS transistor manufacturing method according to the present embodiment is an application of the CMIS transistor manufacturing method according to the second embodiment. A manufacturing method according to the present embodiment will be described with reference to process cross-sectional views.

  A semiconductor substrate 201 shown in FIG. 15 is prepared. As described in the second embodiment, the PMIS transistor is formed in the first region S30, and the NMIS transistor is formed in the second region S40. By the ion implantation process, an N-type well region and a P-type well region are formed in the semiconductor substrate 201 (not shown in FIG. 15).

  Next, a stack in which a gate insulating film 203, a metal film (P-metal) 204, an upper metal film 504, and a semiconductor film (polycrystalline silicon film) 206 are stacked in this order on the semiconductor substrate 201 in the first region S30. A first gate structure G41, which is a structure, is formed. In addition, a second gate structure G12 having a stacked structure in which a gate insulating film 203 and a semiconductor film (polycrystalline silicon film) 206 are stacked in this order is formed on the semiconductor substrate 201 in the second region S40.

  Here, the first gate structure G41 is a component of the PMIS transistor. The second gate structure G12 is a component of the NMIS transistor. In the following, a specific method for manufacturing the first gate structure G41 and the second gate structure G12 will be described with reference to FIGS.

  First, as described in the second embodiment, the gate insulating film 203 made of a hafnium silicate film is formed on the semiconductor substrate 201 in the first region S30 and the second region S40 (FIG. 35). Next, as in the second embodiment, P-metal 204 is formed on the gate insulating film 203 (FIG. 35). The film thickness of P-metal 204 is about 5 nm to 30 nm, for example, 10 nm.

  Next, in this embodiment, an upper metal film 504 is formed on the P-metal 204 (FIG. 35). The upper metal film 504 functions as an antioxidant film for P-metal 204. For example, any one of TiN, TaN, and HfN is suitable as the upper metal film 504 having the function.

  Next, a resist 205 having a predetermined pattern is formed on the upper metal film 504 (FIG. 36). As shown in FIG. 36, the patterned resist 205 remains only in the first region S30. Next, using the patterned resist 205 as a mask, wet etching or the like is performed on the upper metal film 504 and the P-metal 204. Thereby, as shown in FIG. 36, the upper metal film 504 and the P-metal 204 formed in the second region S40 are removed.

  After removing the resist 205 from the first region S30, the polycrystalline silicon film 206 shown in Embodiment Mode 2 is formed on the upper metal film 504 and the gate insulating film 203 (FIG. 37). Next, as shown in FIG. 37, the gate hard mask 207 shown in the second embodiment is formed on the polycrystalline silicon film 206. As can be seen from FIG. 37, the polycrystalline silicon film 206 and the gate hard mask 207 are formed in both the first region S30 and the second region S40.

  Next, dry etching, wet etching, or the like is performed on the gate insulating film 203, the P-metal 204, the upper metal film 504, the polycrystalline silicon film 206, and the gate hard mask 207. As a result, as shown in FIG. 38, the first gate structure G41 is formed on the semiconductor substrate 201 in the first region S30, and the second gate is formed on the semiconductor substrate 201 in the second region S40. Structure G12 is formed.

  Here, the first gate structure G41 is a stacked structure in which the gate insulating film 203, the P-metal 204, the upper metal film 504, and the polycrystalline silicon film 206 are stacked in this order (FIG. 38). On the other hand, the second gate structure G12 is a laminated structure in which the gate insulating film 203 and the polycrystalline silicon film 206 are laminated in this order (FIG. 38). A gate hard mask 207 is formed on each of the first gate structure G41 and the second gate structure G12 (FIG. 38).

  Thereafter, as in the second embodiment, formation of source / drain regions 208, 212, 209, 213, formation of sidewall films 210, 211, formation of nickel silicide 214, formation of interlayer liner film 215 and interlayer insulating film 216, Further, a full silicidation process or the like of the polycrystalline silicon film 206 is performed.

  Thereby, the structure shown in FIG. 39 is formed. As shown in FIG. 39, the first gate structure G41 has a stacked structure of the gate insulating film 203, the P-metal 204, the upper metal film 504, and the full silicide film 217, and the second gate structure G12 has the gate insulating film 203. Further, a laminated structure of the full silicide film 217 is obtained. As described in the second embodiment, the full silicide film 217 constituting the second gate structure G12 is a full silicide with a low silicide metal content.

  After the formation of the full silicide film 217, an interlayer insulating film is stacked, and a normal back-end flow is performed through a flow such as planarization by CMP processing and contact plug formation. Thus, the CMIS transistor is completed.

  In the present embodiment, since the above steps are performed, in addition to the effects described in the second embodiment, the following effects are also obtained.

  Specifically, in this embodiment mode, the gate insulating film 203, the P-metal 204, the upper metal film 504, and the polycrystalline silicon film 206 (which later becomes the full silicide film 217) are stacked in that order. And a step of forming the first gate structure G41. Here, the upper metal film 504 is any one of TiN, TaN, and HfN.

  Therefore, since the upper metal film 504 is formed on the P-metal 204, it is possible to suppress the silicide metal from entering the P-metal 204 when the polycrystalline silicon 206 is fully silicided. Furthermore, since the upper metal film 504 is made of TiN, TaN, HfN, or the like, it functions as an antioxidant layer for the P-metal 204. Therefore, the P-metal 204 can be prevented from being deteriorated during the wafer process. As described above, stable device characteristics can be realized.

  Further, as the semiconductor film 206, a germanium film or a silicon germanium film may be used instead of polycrystalline silicon. In this case, the semiconductor film 206 becomes a full germanite gate or the like by the low resistance treatment.

  The method for forming the CMIS transistor described in each of the above embodiments is applied to all silicon semiconductor integrated circuit products after the 45 nm node. In particular, it is suitable for a transistor in which improvement of the current drive capability of the transistor is desired. Specifically, the present invention is suitable for a logic circuit manufacturing method that requires high-speed operation.

8 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the first embodiment. FIG. 8 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the first embodiment. FIG. 8 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the first embodiment. FIG. 8 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the first embodiment. FIG. 8 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the first embodiment. FIG. 8 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the first embodiment. FIG. 8 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the first embodiment. FIG. 8 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the first embodiment. FIG. 8 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the first embodiment. FIG. 8 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the first embodiment. FIG. 8 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the first embodiment. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on a prior art. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on a prior art. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on a prior art. 11 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the second embodiment. FIG. 11 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the second embodiment. FIG. 11 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the second embodiment. FIG. 11 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the second embodiment. FIG. 11 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the second embodiment. FIG. 11 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the second embodiment. FIG. 11 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the second embodiment. FIG. 11 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the second embodiment. FIG. 11 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the second embodiment. FIG. 11 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the second embodiment. FIG. 11 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the third embodiment. FIG. 10 is a process cross-sectional view illustrating the method for manufacturing the CMIS transistor according to the third embodiment. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on Embodiment 4. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on Embodiment 4. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on Embodiment 5. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on Embodiment 5. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on Embodiment 5. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on Embodiment 5. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on Embodiment 5. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on Embodiment 6. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on Embodiment 6. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on Embodiment 6. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on Embodiment 6. FIG. It is process sectional drawing explaining the manufacturing method of the CMIS transistor which concerns on Embodiment 6. FIG.

Explanation of symbols

  101, 201 Semiconductor substrate, 103, 203 Gate insulating film, 104 Metal film (N-metal), 106, 206 Polycrystalline silicon (semiconductor film), 106a, 206a Ion-implanted polycrystalline silicon, 114, 214 Nickel silicide, 117, 217 Full silicide film (silicide film), 204 metal film (P-metal), 404, 504 upper metal film, G1, G11 first gate structure, G2, G12 second gate structure, S10, S30 first Area S20, S40 second area.

Claims (19)

(A) A semiconductor substrate having a first region where a first transistor of the first conductivity type is formed and a second region where a second transistor of the second conductivity type is formed is prepared. Process,
(B) On the semiconductor substrate in the first region, a gate insulating film, a metal film, and a semiconductor film are stacked in that order, and a first gate structure constituting the first transistor is formed. And a process of
(C) a step of forming a second gate structure constituting the second transistor, wherein the gate insulating film and the semiconductor film are stacked in that order on the semiconductor substrate in the second region; ,
(D) The semiconductor substrate on both sides of the first gate structure and on both sides of the second gate structure with the first gate structure and the second gate structure masked The process of reducing the resistance on the top,
(E) reducing the resistance of the semiconductor film constituting the first gate structure and the semiconductor film constituting the second gate structure,
A method of manufacturing a CMIS transistor. The semiconductor film is
A polycrystalline silicon film,
The method for producing a CMIS transistor according to claim 1. The step (E)
Each of the polycrystalline silicon films is a step of full silicidation.
The method for producing a CMIS transistor according to claim 2. The semiconductor film is
A germanium film,
The method for producing a CMIS transistor according to claim 1. The semiconductor film is
A silicon germanium film,
The method for producing a CMIS transistor according to claim 1. The step (E)
Each of the semiconductor films is a step of reducing resistance.
A method for manufacturing a CMIS transistor according to claim 4 or 5, wherein The first transistor is:
An N-type transistor,
The metal film is
A metal having an N-type work function,
The method for producing a CMIS transistor according to claim 1. The metal film is
A Ta compound or an Hf compound,
The method for producing a CMIS transistor according to claim 7. The second transistor is
A P-type transistor,
The step (E)
The step of siliciding the semiconductor film constituting the second gate structure into any composition of Ni ₃ Si, Ni ₃₁ Si ₁₂ , and Ni ₂ Si;
The method for producing a CMIS transistor according to claim 7. The first transistor is:
A P-type transistor,
The metal film is
A metal having a P-type work function,
The method for producing a CMIS transistor according to claim 1. The metal film is
Any one of a Ti compound, a W compound, a Ru compound, and a Pt compound,
The method for producing a CMIS transistor according to claim 10. The second transistor is
An N-type transistor,
The step (E)
A step of siliciding the semiconductor film constituting the first gate structure into a composition of NiSi or NiSi ₂ ;
The method for producing a CMIS transistor according to claim 10. The step (E)
After the step (D),
The method for producing a CMIS transistor according to claim 1. The step (E)
It is a silicidation process using a metal containing at least one or more of Ni, Pt, Ti, Co, Hf, Ta, Yb, Er, and Al.
The method for producing a CMIS transistor according to claim 1. The thickness of the metal film is
5-30 nm,
The method for producing a CMIS transistor according to claim 7 or 10, wherein: (F) before the step (E), further comprising a step of performing an ion implantation process on the polycrystalline silicon film constituting the first gate structure.
The method for producing a CMIS transistor according to claim 2. The step (F)
Injecting at least one of phosphorus, arsenic, and oxygen,
The method for producing a CMIS transistor according to claim 16. The step (B)
The step of forming the first gate structure is a stacked structure in which the gate insulating film, the metal film, the upper metal film, and the semiconductor film are stacked in this order.
The method for producing a CMIS transistor according to claim 1. The upper metal film is
Any of TiN, TaN, and HfN,
The method for producing a CMIS transistor according to claim 18.

Images