WO2009084376A1 - Semiconductor device and process for producing the semiconductor device - Google Patents

Semiconductor device and process for producing the semiconductor device Download PDF

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WO2009084376A1
WO2009084376A1 PCT/JP2008/072244 JP2008072244W WO2009084376A1 WO 2009084376 A1 WO2009084376 A1 WO 2009084376A1 JP 2008072244 W JP2008072244 W JP 2008072244W WO 2009084376 A1 WO2009084376 A1 WO 2009084376A1
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region
semiconductor device
insulating film
gate insulating
electrode
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PCT/JP2008/072244
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French (fr)
Japanese (ja)
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Kenzo Manabe
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Nec Corporation
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2

Definitions

  • the present invention relates to a semiconductor device having a full silicide gate electrode and a method for manufacturing the same, and more particularly to a technique related to high performance and high reliability of MOSFET (Metal Oxide Semiconductor Semiconductor Field Effect Transistor).
  • MOSFET Metal Oxide Semiconductor Semiconductor Field Effect Transistor
  • the threshold variation due to the impurity concentration fluctuation in the channel increases as the impurity concentration increases. Therefore, in order to suppress variations in threshold value due to fluctuations in impurity concentration, it is effective to reduce the impurity concentration in the channel and to reduce the electrical gate insulating film thickness during inversion.
  • Vth a low threshold voltage (hereinafter referred to as “Vth”) necessary for high-speed operation. ) And a high Vth necessary for reducing the off-current must be settable.
  • Vth For high-speed operation transistors, Vth needs to be about ⁇ 0.1 eV. Therefore, a material having a work function of n-type polycrystalline Si or less (4.0 eV) is used for the nMOSFET, and a material having a work function (5.2 eV) or more of the p-type polycrystalline Si is used for the pMOSFET. There is a need. On the other hand, in a MOSFET that requires a high threshold to reduce off-current, Vth needs to be about ⁇ 0.6 eV. Therefore, in the nMOSFET and the pMOSFET, it is necessary to use a material having an effective work function corresponding to the Si mid gap (4.6 eV) for the gate electrode.
  • Vth for high-speed operation transistors to about ⁇ 0.1 eV
  • different metals or alloys having different work functions are used separately for nMOSFET electrodes and pMOSFET electrodes, respectively.
  • a method of controlling Vth has been proposed.
  • the work functions of Ta and Ru formed on SiO 2 are 4.15 eV and 4.95 eV, respectively, and by using these, the work of 0.8 eV between the two electrodes described above is used. It is stated that function modulation is possible.
  • Patent Document 1 discloses an example in which SiO 2 is used as a gate insulating film and a Ni full silicide electrode obtained by completely siliciding a polycrystalline Si electrode implanted with impurities such as P and B with Ni is used as a gate electrode. It is disclosed.
  • This Ni full silicide electrode has (1) the formation process is highly compatible with the conventional CMOS process, and (2) the threshold voltage can be controlled by adding impurities to polycrystalline Si before silicidation on SiO 2. Therefore, it is considered as a promising metal gate material.
  • impurities pMOS: B, Al, Ga, In, Tl, nMOS: N, P, As, Sb, Bi
  • an effective work function of about 4.2 to 4.4 eV is obtained for an n-type transistor
  • an effective work function of about 4.7 to 4.9 eV is obtained for a p-type transistor.
  • the threshold control by addition of impurities in (2) can be made into pMOS / nMOS, so it is considered promising as a threshold control method for transistors using SiO 2 as a gate insulating film. Yes.
  • a full silicide electrode obtained by completely siliciding a polycrystalline Si electrode implanted with impurities such as P and B with Ni is applied to a device that needs to reduce Vth variation in particular. In this case, it is necessary to suppress variation in effective work function of the full silicide electrode.
  • An object of the present invention is to provide a semiconductor device capable of improving the characteristics and reliability of an element and a manufacturing method thereof.
  • the semiconductor device has a plurality of transistor structures in which a gate insulating film and a gate electrode are provided on a Si substrate.
  • the gate electrode has a metal silicide layer in a portion in contact with the gate insulating film, and each of the plurality of transistor structures is any of the first region, the second region, and the third region.
  • the first region includes a first impurity element at an interface between the metal silicide layer and the gate insulating film
  • the second region includes the second impurity element at an interface between the metal silicide layer and the gate insulating film.
  • the third region substantially does not include both the first impurity element and the second impurity element at the interface between the metal silicide layer and the gate insulating film, and the first impurity element and the second impurity element.
  • the element has a property of forming conductivity types opposite to each other in Si.
  • a method of manufacturing a semiconductor device includes a step of depositing polycrystalline Si on a gate insulating film, dividing the polycrystalline Si into a first region, a second region, and a third region, and forming a first region in the first region.
  • the impurity concentration in the metal silicide electrode with the impurity concentration in the semiconductor substrate kept constant.
  • impurities can be easily added by a PR (photoresist) process and an ion implantation process, so that a desired semiconductor device can be easily obtained.
  • the present inventor has obtained the following knowledge about a technique in which a full silicide electrode having high crystallinity is applied as a gate electrode on a gate insulating film having a Si oxide film or a Si oxynitride film as the outermost surface. Even if the metal composition of the silicide electrode is changed, the effective work function is almost constant at a value corresponding to the Si midgap (4.6 eV). On the other hand, when an impurity-added full silicide electrode with high crystallinity is applied as the gate electrode, the change in effective work function due to the addition of impurities increases as the Ni composition of the Ni silicide electrode decreases, resulting in a larger effective work than before. The change width of the function can be realized. The present invention has been made based on these findings.
  • a SiO 2 gate insulating film (film thickness: 3 nm) was formed on a Si substrate, and a polycrystalline Si electrode having a film thickness of 80 nm was formed thereon.
  • an additive element was ion-implanted into the polycrystalline Si electrode.
  • N, P, As, Sb, Bi, etc. which are n-type impurities with respect to Si
  • B which is a p-type impurity
  • Al, In, Ga, Tl, and the like were each ion-implanted.
  • a Ni film (film thickness: T Ni ) was deposited on the polycrystalline Si electrode (film thickness: T Si ), and the polycrystalline Si electrode was fully silicided by heat treatment.
  • the crystal phase of Ni silicide is determined stepwise with respect to the thickness of the Ni film deposited on the polycrystalline Si, that is, the amount of Ni supplied to the polycrystalline Si.
  • the Ni silicide crystal phase in the vicinity of the electrode / insulating film interface that affects the effective work function is mainly the NiSi phase
  • the ratio (T Ni / T Si ) may be set in the range of 0.55 to 0.95, and in the case where the NiSi 3 phase is mainly desired, T Ni / T Si may be set to 1.60 or more.
  • the silicidation temperature must be 600 ° C. or higher, preferably 650 ° C. or higher.
  • Ni / (Ni + Si) composition that determines the work function of Ni silicide is determined in a substantially self-aligned manner by the crystal phase of NiSi 2 , NiSi, Ni 3 Si, or the like. Therefore, since the margin of process conditions such as the deposited film thickness of the Ni film and the silicidation temperature capable of obtaining the same crystal phase (that is, obtaining the same work function) is wide, variations in the manufacturing process can be suppressed low.
  • FIG. 4 shows the result of measuring the impurity concentration profile in the full silicide gate electrode fabricated in this way by secondary ion mass spectrometry (SIMS).
  • SIMS secondary ion mass spectrometry
  • FIG. 3 summarizes the results of specifying the crystal phase of the MOS capacitor Ni silicide produced as described above by XRD.
  • T Ni / T Si 0.28 to 0.54
  • the formed Ni silicide is substantially made of NiSi 2 .
  • a weak NiSi peak is observed in the XRD spectrum.
  • the formed Ni silicide is substantially made of NiSi.
  • T Ni / T Si 0.55 to 0.95
  • the formed Ni silicide is substantially made of NiSi.
  • T Ni / T Si is 1.60 or more, the formed Ni silicide is substantially made of Ni 3 Si.
  • FIG. 5 shows the dependence of the Ni composition in the electrode on the ratio of Ni film thickness / polycrystalline Si film thickness (T Ni / T Si ) at the electrode / insulating film interface of the MOS capacitor fabricated as described above.
  • the Ni composition in the electrode was determined from XPS measurement.
  • the electrode composition error bars show variations in multipoint measurement by XPS.
  • Each of these compositions substantially matched NiSi 2 (33.3%), NiSi (50%), and Ni 3 Si (75%). This is considered to be due to the fact that the Ni composition in the electrode at the interface is determined in a self-aligned manner by the crystal phase seen in FIG.
  • FIG. 6 shows the dependency of the effective work function of crystallized Ni silicide in 3 ) on the silicide electrode composition near the interface.
  • the electrode composition error bars show variations in multipoint measurement by XPS. In the figure, the main crystal phase in the composition is shown.
  • the effective work function of crystallized Ni silicide hardly depends on the composition. That is, even if the metal composition of the silicide electrode is changed, the effective work function change is almost constant at an effective work function corresponding to the Si mid gap (4.6 eV). Therefore, even if the Ni composition varies, the threshold variation is suppressed. Therefore, in SRAMs and DRAMs that have a high need to suppress threshold variation, using a non-doped (non-doped) crystallized Ni silicide as a gate electrode is desirable while keeping the impurity concentration in the channel low. A high threshold value can be obtained.
  • the change in effective work function due to the addition of impurities increased as the Ni composition decreased (the Si composition increased).
  • the effective work function in the Ni composition range of 26% to 40% in which the main crystal phase is NiSi 2 is 4.0 eV when As is added, and 5.2 eV when B is added.
  • An effective work function (nMOS: 4.0 eV or less, pMOS: 5.2 eV or more) necessary for the nMOSFET device can be realized.
  • the effective work function in crystallized NiSi 2 is 4.0 eV or less in the case of n-type impurities (N, P, As, Sb, Bi, etc.), and p-type impurities (B, Al, In, Ga, Tl).
  • the effective work function nMOS: 4.0 eV or less, pMOS: 5.2 eV or more
  • the nMOSFET threshold (Vth) range that can be predicted from the effective work function is as shown in FIG. 7 with respect to the channel impurity concentration.
  • Vth the nMOSFET threshold
  • a crystallized Ni silicide electrode whose Ni composition does not exceed 40% was used.
  • a high-performance device having a low threshold value of about 0.1 V, which could not be produced by a conventional impurity-added NiSi electrode, is realized with a channel concentration (10 17 to 10 18 cm ⁇ 3 ) normally used in a CMOS device. be able to.
  • the impurity concentration in the channel is constant, and in the low Vth transistor, an impurity is added to the silicide electrode,
  • the impurity concentration in the channel can be reduced particularly in a transistor having a high threshold value as compared with the conventional transistor.
  • suppression of gate depletion can be realized by using a metal gate. As a result, improvement in mobility and suppression of threshold variation can be realized, and high performance of the transistor can be achieved.
  • the gate electrode materials of the nMOS transistor and the pMOS transistor having a low Vth and the MOS transistor having a high Vth are the same for cost reduction. Therefore, a crystallized Ni silicide electrode to which impurities are added is used as a gate electrode of an nMOS transistor having a low Vth and a pMOS transistor, and a crystallized Ni silicide electrode to which impurities are not added is gated as a gate electrode of a MOS transistor having a high Vth. This is achieved when used for electrodes.
  • the metal for siliciding the gate polycrystalline Si electrode is preferably a metal capable of forming a silicide capable of a salicide process. This is because when the silicidation of the gate polycrystalline Si electrode is performed after the metal silicide is formed on the source / drain diffusion layer contact region, the resistance value of the metal silicide formed in the source / drain diffusion layer contact region is increased. This is because silicidation needs to be possible at a temperature that does not allow it to occur. From this viewpoint, it is preferable that the metal is Ni.
  • the composition of the electrode is determined in a self-aligned manner during the full silicidation. Although it is preferable, this can be achieved by using crystallized Ni 3 Si doped with impurities for the gate electrode.
  • the necessary effective work function is ⁇ 0.2 eV each with respect to the Si mid gap (4.6 eV). (See FIG. 7).
  • the Ni silicide is expressed as Ni X Si 1-X as shown in FIG. 6, the Ni composition is preferably 0.4 ⁇ x ⁇ 0.6.
  • the composition of the electrode is determined in a self-aligned manner during the full silicidation. Although it is preferable, it is achieved if crystallized NiSi doped with impurities is used for the gate electrode.
  • the necessary effective work function is ⁇ 0.5 eV each with respect to the Si mid gap (4.6 eV). (See FIG. 7).
  • the Ni silicide is expressed as Ni X Si 1-X as shown in FIG. 6, the Ni composition is preferably 0 ⁇ x ⁇ 0.4.
  • the composition of the electrode is determined in a self-aligned manner during the full silicidation. Preferably, this is achieved if crystallized NiSi 2 doped with impurities is used for the gate electrode.
  • a Si oxide film or a Si oxynitride film can be used as the gate insulating film.
  • the gate insulating film may be HfSiON.
  • the threshold change width due to the addition of impurities is smaller than in the case of the SiO 2 and SiON gate insulating films, but the Si oxide film, the Si oxynitride film layer, or the Si nitride film is in contact with the gate electrode.
  • the effective work function change can be increased, and as a result, a low threshold can be realized in the MOSFET.
  • the impurity concentration in the substrate is constant and low Vth is realized with a polycrystalline Si electrode doped with a dopant. If a high Vth is realized by a non-doped silicide electrode having a Si midgap work function, the impurity concentration in the channel can be reduced as compared with the conventional transistor having a high Vth. At the same time, the gate depletion can be suppressed by using a metal gate in a transistor having a high Vth. As a result, improvement in mobility and suppression of threshold variation can be realized, and high performance of the transistor can be achieved.
  • the metal for siliciding the gate polycrystalline Si electrode is preferably a metal capable of forming a silicide capable of the salicide process. This is because silicidation must be possible at a temperature that does not increase the resistance value of the metal silicide formed in the source / drain diffusion layer contact region. From this viewpoint, it is preferable that the metal is Ni. Furthermore, a Si oxide film or a Si oxynitride film can be used as the gate insulating film.
  • the gate insulating film may be HfSiON, and a Si oxide film, a Si oxynitride film layer, or a Si nitride film layer may be inserted in a portion in contact with the gate electrode.
  • FIGS A structural diagram of a CMOSFET manufactured using a metal silicide satisfying the above-described functions and an additive element is shown in FIGS.
  • the impurity concentration in the substrate is kept constant.
  • the amount of impurities in the silicide electrode is controlled.
  • the impurity concentration in the substrate is reduced.
  • a low threshold is realized with a polycrystalline Si electrode doped with a dopant
  • a high threshold is realized with a silicide electrode having a Si midgap work function.
  • the impurity concentration in the channel can be reduced as compared with the conventional case, particularly in a transistor having a high threshold value.
  • gate depletion can be suppressed by using a metal gate at the same time. As a result, improvement in mobility and suppression of threshold variation can be realized, and high performance of the transistor can be achieved.
  • the manufacturing method of the present invention after the polycrystalline Si electrode is formed on the gate insulating film, there is no step of removing it again, so that the surface of the gate insulating film becomes wet etching solution or an organic solvent. It is not exposed for several degrees. Therefore, it is possible to manufacture a metal gate / gate insulating film CMOS transistor having excellent reliability.
  • the impurity addition can be easily performed by the PR process and the ion implantation process, a desired device can be easily obtained.
  • the semiconductor device of the first embodiment shown in FIG. 1 includes a gate insulating film 4 and a p-type full silicide electrode 112, an n-type full silicide electrode 212, and a non-doped full silicide electrode as a gate electrode on a Si substrate 1 as a semiconductor substrate. 312 and a plurality of transistor structures.
  • the p-type full silicide electrode 112, the n-type full silicide electrode 212, and the non-doped full silicide electrode 312 are metal silicide layers at portions in contact with the gate insulating film 4.
  • Each of the plurality of transistor structures belongs to one of the first region 100, the second region 200, and the third region 300.
  • the first region 100 includes an impurity element that becomes p-type in silicon at the interface between the p-type full silicide electrode 112 and the gate insulating film 4.
  • the second region 200 includes an impurity element that becomes n-type in silicon at the interface between the n-type full silicide electrode 212 and the gate insulating film 4.
  • the third region 300 does not substantially contain any impurity element at the interface between the non-doped full silicide electrode 312 and the gate insulating film 4.
  • the phrase “substantially free of any impurity element” as used herein includes a case in which both of the impurity elements are contained in an equal amount and are substantially intrinsic.
  • a MOSFET is manufactured using a CMP (Chemical Mechanical Polishing) technique capable of flattening by polishing the interlayer insulating film after it is formed and simultaneously exposing the upper portion of the gate electrode.
  • CMP Chemical Mechanical Polishing
  • the MOSFET according to this example includes a pMOSFET manufactured on the first region 100, an nMOSFET manufactured on the second region 200, and an nMOSFET (or pMOSFET) manufactured on the third region 300.
  • the element isolation region 2 was formed on the surface region of the Si substrate 1 in the first region 100, the second region 200, and the third region 300 by using STI (Shallow Trench Isolation) technology.
  • a sacrificial insulating film 3 was formed on the surface of the Si substrate from which the elements were separated.
  • a Si thermal oxide film having a thickness of about 10 nm can be used as the sacrificial insulating film 3.
  • n-type channel impurities are respectively formed on the surface region of the Si substrate 1 in the first region 100, the second region 200, and the third region 300 through the sacrificial insulating film 3.
  • P-type and p (or n) -type dopant elements were added by ion implantation, and the dopant was electrically activated by heat treatment.
  • the sacrificial insulating film 3 was removed, and a gate insulating film 4 was formed.
  • SiON was used for the gate insulating film 4.
  • a polycrystalline Si film 5 having a thickness of about 80 nm was formed on the gate insulating film 4.
  • Ion implantation was performed.
  • B is injected into the first region 100 and As is injected into the second region 200.
  • the implantation energy and dose amount were 2 keV and 6 ⁇ 10 15 cm ⁇ 2 for B implantation, and 5 keV and 5 ⁇ 10 15 cm ⁇ 2 for As implantation.
  • the polycrystalline Si film 5 on the first region 100, the second region 200, and the third region 300 is respectively a p-type doped polycrystalline Si film 105, an n-type doped.
  • a polycrystalline Si film 205 and a non-doped polycrystalline Si film 305 were obtained.
  • a Si oxide film 6 having a thickness of 150 nm was formed on the polycrystalline Si films 105, 205, and 305.
  • the laminated film composed of the polycrystalline Si film 5 and the 150 nm Si oxide film 6 is processed into a gate electrode by using a lithography technique and an RIE (Reactive Ion Etching) technique.
  • RIE Reactive Ion Etching
  • ion implantation was performed, and extension diffusion layer regions 107, 207, and 307 were formed in a self-aligned manner on the Si surfaces of the first region 100, the second region 200, and the third region 300 using the gate electrode as a mask.
  • a gate side wall 8 was formed by sequentially depositing a Si nitride film and a Si oxide film and then performing etch back. In this state, ion implantation is performed again, and activation annealing is performed to form source / drain diffusion layers 109, 209, and 309 on the Si surfaces of the first region 100, the second region 200, and the third region 300, respectively. .
  • a metal film having a thickness of 20 nm is deposited on the entire surface by sputtering, and a silicide layer 10 having a thickness of about 40 nm is formed only on the source / drain diffusion layer by using the salicide technique, using the gate electrode, the gate sidewall film, and the STI as a mask.
  • the silicide layer 10 is made of Ni monosilicide (NiSi) that can minimize the contact resistance. Co silicide or Ti silicide may be used instead of Ni silicide.
  • an interlayer insulating film 11 of a Si oxide film was formed by a CVD (Chemical Vapor Deposition) method.
  • the interlayer insulating film 11 is planarized by CMP technique as shown in FIG. 10H, and the interlayer insulating film is etched back to expose the polycrystalline Si films -105, 205, 305 of the gate electrode. .
  • Ni film for forming silicide with the polycrystalline Si films 105, 205, and 305 of the gate electrode was deposited.
  • the Ni film thickness in this step is set such that the composition on the side in contact with the gate insulating film becomes NiSi 2 when the polycrystalline Si and Ni are sufficiently reacted to be silicided.
  • Ni was deposited to a thickness of 25 nm at room temperature by DC magnetron sputtering.
  • polycrystalline Si and Ni were sufficiently reacted by heat treatment at 650 ° C. for 2 minutes to form a crystallized NiSi 2 electrode.
  • the additive element (B) in the polycrystalline Si electrode in the first region 100 is segregated at the electrode / insulating film interface as shown in FIG. 10 (i) (segregated impurities 113).
  • the additive element (As) in the polycrystalline Si electrode in the second region 200 is segregated at the electrode / insulating film interface as shown in FIG. 10 (i) (segregated impurities 213).
  • the dopant since the dopant is not added to the polycrystalline Si electrode in the third region 300, the dopant does not segregate at the electrode / insulating film interface.
  • the excess Ni film that did not undergo the silicidation reaction in the above heat treatment was removed by wet etching using a sulfuric acid hydrogen peroxide aqueous solution. Thereafter, a normal wiring process was performed.
  • FIG. 11 shows the gate voltage dependence of the drain current in an nMOSFET using NiSi 2 whose gate electrode is NiSi 2 whose effective work function is modulated to 4.1 eV.
  • the channel concentration is 2 ⁇ 10 17 cm ⁇ 3
  • Vth expected from the effective work function of FIG. 6 of 4.1 eV is 0.1V.
  • Vth of the nMOS transistor using NiSi 2 as an electrode is 0.1 V as predicted from the effective work function.
  • the electron mobility was equivalent to that of the transistor using the combination of polycrystalline Si / SiO 2 .
  • FIG. 12 shows the gate voltage dependence of the drain current in the pMOSFET using NiSi 2 whose effective work function is modulated to 5.1 eV as the gate electrode.
  • the channel concentration is 2 ⁇ 10 17 cm ⁇ 3
  • the Vth expected from the effective work function of FIG. 6 from 5.1 eV is ⁇ 0.1V.
  • the Vth of the pMOS transistor using NiSi 2 as an electrode is ⁇ 0.1 V as predicted from the effective work function.
  • the hole mobility was equivalent to that of a transistor using a polycrystalline Si / SiO 2 combination.
  • FIG. 13 shows the gate voltage dependence of the drain current in an nMOSFET using non-doped NiSi 2 having an effective work function of 4.6 eV as a gate electrode.
  • the channel concentration is 2 ⁇ 10 17 cm ⁇ 3
  • Vth predicted from the effective work function of FIG. 6 is 0.6V.
  • Vth of the nMOS transistor using non-doped NiSi 2 as an electrode is ⁇ 0.1 V as predicted from the effective work function.
  • FIG. 14 shows the effective electric field dependence of the electron mobility of this transistor.
  • FIG. 15 shows the channel impurity concentration (Nch) dependence of the threshold variation of an nMOS transistor using non-doped NiSi 2 as an electrode.
  • Ni full silicide electrodes of nMOS and pMOS transistors can be formed by a single silicidation for cost reduction by simplification of the process, but crystallized NiSi 2 doped with impurities is used as a gate electrode. This is achieved if used.
  • the manufacturing method of this example after forming the polycrystalline Si electrode on the gate insulating film, there is no step of removing it again, so that the surface of the gate insulating film is in a wet etching solution or an organic solvent. It is never exposed. Therefore, it is possible to manufacture a metal gate / gate insulating film CMOS transistor having excellent reliability. Moreover, according to the manufacturing method of this example, since the impurity addition can be easily performed by the PR process and the ion implantation process, a desired device can be easily obtained.
  • the MOSFET is fabricated by using a CMP technique that can be planarized by polishing the interlayer insulating film after it is formed and at the same time expose the upper portion of the gate electrode.
  • the MOSFET according to this example also includes a pMOSFET manufactured on the first region 100, an nMOSFET manufactured on the second region 200, and an nMOSFET (or pMOSFET) manufactured on the third region 300. .
  • the element isolation region 2 was formed on the surface region of the Si substrate 1 in the first region 100, the second region 200, and the third region 300 using the STI technique. Subsequently, a sacrificial insulating film 3 was formed on the surface of the Si substrate from which the elements were separated.
  • a sacrificial insulating film 3 for example, a Si thermal oxide film having a thickness of about 10 nm can be used.
  • n-type channel impurities are respectively formed on the surface regions of the Si substrate 1 in the first region 100, the second region 200, and the third region 300 through the sacrificial insulating film 3.
  • P-type, and p (or n) -type dopant elements were added by ion implantation, and the dopant was electrically activated by heat treatment.
  • the sacrificial insulating film 3 was removed, and a gate insulating film 4 was formed.
  • a gate insulating film 4 SiON was used.
  • a polycrystalline Si film 5 having a thickness of about 80 nm was formed on the gate insulating film 4.
  • the laminated film composed of the polycrystalline Si film 5 and the 150 nm Si oxide film 6 is processed into a gate electrode by using a lithography technique and an RIE technique, followed by ion implantation.
  • the extension diffusion layer regions 107, 207, and 307 were formed in a self-aligned manner using the gate electrode as a mask.
  • a gate side wall 8 was formed by sequentially depositing a Si nitride film and a Si oxide film and then performing etch back. In this state, ion implantation is performed again, and activation annealing is performed to form source / drain diffusion layers 109, 209, and 309 on the Si surfaces of the first region 100, the second region 200, and the third region 300, respectively. .
  • a metal film having a thickness of 20 nm is deposited on the entire surface by sputtering, and a silicide layer 10 having a thickness of about 40 nm is formed only on the source / drain diffusion layer by using the salicide technique, using the gate electrode, the gate sidewall film, and the STI as a mask.
  • the silicide layer 10 is made of Ni monosilicide (NiSi) that can minimize the contact resistance. Co silicide or Ti silicide may be used instead of Ni silicide.
  • an interlayer insulating film 11 made of Si oxide was formed by a CVD method.
  • the interlayer insulating film 11 was planarized by CMP technique as shown in FIG. 18G, and the interlayer insulating film was etched back to expose the polycrystalline Si films 105, 205, and 305 as gate electrodes.
  • Ni film for forming silicide with the polycrystalline Si film 5 of the gate electrode was deposited.
  • the Ni film thickness in this step is set such that the composition on the side in contact with the gate insulating film becomes NiSi 2 when the polycrystalline Si and Ni are sufficiently reacted to be silicided.
  • Ni was deposited to a thickness of 25 nm at room temperature by DC magnetron sputtering.
  • polycrystalline Si and Ni are sufficiently reacted by heat treatment at 650 ° C. for 2 minutes to form crystallized NiSi 2 electrode 12, and silicidation reaction is caused in the heat treatment described above.
  • the excess Ni film that did not exist was removed by wet etching using a hydrogen peroxide aqueous solution.
  • a normal PR process using a resist and ion implantation for polycrystalline Si on the first region 100 and the second region 200 are performed.
  • different impurity elements were ion-implanted.
  • B is implanted into the first region 100 and As is implanted into the second region 200.
  • the implantation energy and dose amount were 2 keV and 6 ⁇ 10 15 cm ⁇ 2 for B implantation, and 5 keV and 5 ⁇ 10 15 cm ⁇ 2 for As implantation.
  • annealing is performed at 500 ° C. for about 30 minutes, so that the additive element (B) in the crystallized NiSi 2 electrode 12 in the first region 100 becomes an electrode / insulator as shown in FIG. Segregates at the film interface (segregated impurities 113). Also, the additive element (As) of the crystallized NiSi 2 electrode 12 in the second region 200 is segregated at the electrode / insulating film interface as shown in FIG. 18 (i) (segregated impurities 213). On the other hand, since the dopant is not added to the polycrystalline Si electrode in the third region 300, the dopant does not segregate at the electrode / insulating film interface. Thereafter, a normal wiring process was performed.
  • the manufacturing method of this example after forming the polycrystalline Si electrode on the gate insulating film, there is no step of removing it again, so that the surface of the gate insulating film is in a wet etching solution or an organic solvent. It is never exposed. Therefore, it is possible to manufacture a metal gate / gate insulating film CMOS transistor having excellent reliability. Moreover, according to the manufacturing method of this example, since the impurity addition can be easily performed by the PR process and the ion implantation process, a desired device can be easily obtained.
  • the etching rate varies depending on the type of dopant, and therefore the gate size is different or the roughness of the gate edge is larger than in the case of non-doping. cause.
  • the gate polycrystalline Si can be made non-doped during the etching of the gate polycrystalline Si, the problems related to the gate size and shape due to the doping described above can be avoided.
  • the semiconductor device of the second embodiment shown in FIG. 2 includes a gate insulating film 4 and a p-type doped polycrystalline Si film 105, an n-type doped polycrystalline Si film 205 as a gate electrode, and a Si substrate 1 as a semiconductor substrate. It has a plurality of transistor structures provided with non-doped full silicide electrodes 312.
  • the non-doped full silicide electrode 312 is a metal silicide layer at a portion in contact with the gate insulating film 4.
  • Each of the plurality of transistor structures belongs to one of the first region 100, the second region 200, and the third region 300.
  • First region 100 includes an impurity element which becomes p-type in silicon at the interface between p-type doped polycrystalline Si film 105 and gate insulating film 4.
  • Second region 200 includes an impurity element that becomes n-type in silicon at the interface between n-type doped polycrystalline Si film 205 and gate insulating film 4.
  • the third region 300 does not substantially contain any impurity element at the interface between the non-doped full silicide electrode 312 and the gate insulating film 4.
  • the phrase “substantially free of any impurity element” as used herein includes a case in which both of the impurity elements are contained in an equal amount and are substantially intrinsic.
  • FIG. 19A to FIG. 21H are cross-sectional views showing the manufacturing process of the MOSFET according to the second embodiment of the present invention.
  • the MOSFET is planarized by polishing, and at the same time, a MOSFET is manufactured by using a CMP technique capable of exposing the upper portion of the gate electrode.
  • the MOSFET according to the present embodiment includes a pMOSFET manufactured on the first region 100, an nMOSFET manufactured on the second region 200, and an nMOSFET (or pMOSFET) manufactured on the third region 300. Become.
  • the element isolation region 2 was formed on the surface region of the Si substrate 1 in the first region 100, the second region 200, and the third region 300 using the STI technique. Subsequently, a sacrificial insulating film 3 was formed on the surface of the Si substrate from which the elements were separated.
  • a sacrificial insulating film 3 for example, a Si thermal oxide film having a thickness of about 10 nm can be used.
  • each of the first region 100, the second region 200, and the third region 300 through the sacrificial insulating film 3 is subjected to n as channel impurities with respect to the surface region of the Si substrate 1.
  • n channel impurities with respect to the surface region of the Si substrate 1.
  • Type, p-type, and p (or n) -type dopant elements were added by ion implantation, and the dopant was electrically activated by heat treatment.
  • the sacrificial insulating film 3 was removed, and a gate insulating film 4 was formed.
  • a gate insulating film 4 was formed.
  • SiON was used for the gate insulating film 4.
  • a polycrystalline Si film 5 having a thickness of about 80 nm was formed on the gate insulating film 4.
  • each different impurity element is ionized. Injected.
  • B is implanted into the first region 100 and P is implanted into the second region 200.
  • the implantation energy and dose amount were 2 keV and 6 ⁇ 10 15 cm ⁇ 2 for B implantation, and 5 keV and 5 ⁇ 10 15 cm ⁇ 2 for As implantation.
  • the polycrystalline Si film 5 on the first region 100, the second region 200, and the third region 300 is respectively a p-type doped polycrystalline Si film 105, an n-type doped.
  • a polycrystalline Si film 205 and a non-doped polycrystalline Si film 305 were obtained.
  • a Si oxide film 6 having a thickness of 150 nm was formed on the polycrystalline Si films 105, 205, and 305.
  • the laminated film composed of the polycrystalline Si film 5 and the 150 nm Si oxide film 6 is processed into a gate electrode using a lithography technique and an RIE technique, and then ion implantation is performed.
  • the extension diffusion layer regions 107, 207, and 307 were formed in a self-aligned manner using the gate electrode as a mask.
  • a Si side wall 8 was formed by sequentially depositing a Si nitride film and a Si oxide film and then etching back. In this state, ion implantation is performed again, and activation annealing is performed to form source / drain diffusion layers 109, 209, and 309 on the Si surfaces of the first region 100, the second region 200, and the third region 300, respectively. .
  • a metal film having a thickness of 20 nm is deposited on the entire surface by sputtering, and a silicide layer 10 having a thickness of about 40 nm is formed only on the source / drain diffusion layer by using the salicide technique, using the gate electrode, the gate sidewall film, and the STI as a mask.
  • the silicide layer 10 is made of Ni monosilicide (NiSi) that can minimize the contact resistance. Co silicide or Ti silicide may be used instead of Ni silicide.
  • an interlayer insulating film 11 of Si oxide film was formed by the CVD method.
  • the interlayer insulating film 11 is planarized by a CMP technique, and the interlayer insulating film on the third region 300 is selectively etched back using a resist mask, so that the number of gate electrodes on the third region 300 is increased.
  • the crystalline Si film 305 was exposed.
  • a Ni film for forming silicide with the polycrystalline Si film 305 of the gate electrode was deposited.
  • the Ni film thickness in this step is set such that the composition on the side in contact with the gate insulating film becomes NiSi 2 when the polycrystalline Si and Ni are sufficiently reacted to be silicided.
  • a film of Ni having a thickness of 25 nm is formed at room temperature by a DC magnetron sputtering method.
  • polycrystalline Si and Ni were sufficiently reacted by heat treatment at 650 ° C. for 2 minutes to form a crystallized NiSi 2 electrode.
  • the surplus Ni film that did not undergo the silicidation reaction in the above-described heat treatment was removed by wet etching using a sulfuric acid hydrogen peroxide solution.
  • an interlayer insulating film 11 of a Si oxide film was formed by the CVD method. Thereafter, a normal wiring process was performed.
  • a p-type doped polycrystalline Si film is formed at the gate electrode / gate insulating film interface according to the first region 100, the second region 200, and the third region 300 as shown in FIG. 105, a MOSFET having a gate electrode formed with an n-type doped polycrystalline Si film 205 and non-doped NiSi 2 312 was formed.
  • the effective work function of the NiSi 2 full silicide electrode 312 was 4.6 eV.
  • the Ni full silicide electrode of the nMOS transistor and the pMOS transistor can be formed by a single silicidation in order to reduce the cost by simplifying the process, but the crystallized NiSi 2 doped with an impurity is used as the gate electrode. This is achieved if used for.
  • the impurity concentration in the substrate is kept constant.
  • a low threshold is realized with a polycrystalline Si electrode doped with a dopant
  • a high threshold is realized with a silicide electrode having a Si midgap work function.
  • the impurity concentration in the channel can be reduced as compared with the conventional case, particularly in a transistor having a high threshold value.
  • suppression of gate depletion can be realized by using a metal gate. As a result, improvement in mobility and suppression of threshold variation can be realized, and high performance of the transistor can be achieved.
  • the manufacturing method of the present embodiment after forming the polycrystalline Si electrode on the gate insulating film, there is no step of removing it again, so that the surface of the gate insulating film becomes wet etching solution or an organic solvent. It is not exposed for several degrees. Therefore, it is possible to manufacture a metal gate / gate insulating film CMOS transistor having excellent reliability.
  • the gate polycrystalline Si of the MOS transistor having a high threshold value that most suppresses the characteristic variation can be made non-doped.
  • the roughness of the gate end becomes larger than that in the case of non-doping, which causes variation in characteristics. Therefore, according to the present embodiment, problems related to the gate shape due to doping can be avoided, so that variation in characteristics can be suppressed.
  • this invention is not limited to said each embodiment, In the range which does not deviate from the meaning of this invention, it is possible to select and implement a material and a structure. It is.
  • a GaAs substrate, Ge substrate, SiGe substrate, SiC substrate, SOI (Silicon On On Insulator) substrate, or the like may be used instead of the Si substrate.
  • a so-called high dielectric constant gate insulating film such as HfSiON can be used as the insulating film.
  • the threshold change is reduced as compared with the case where the Si oxide film or the Si oxynitride film is used.
  • an effective work function can be reduced by inserting a Si oxide film, a Si oxynitride film layer, or a Si nitride film layer in a portion in contact with the gate electrode. It was confirmed that a low threshold can be realized in
  • the third embodiment shown in FIG. 22 has a laminated structure of a gate insulating film 21 having HfSiON on the outermost surface and a SiO 2 or SiON cap film 22.
  • the present invention has been described with reference to each of the above embodiments, but the present invention is not limited to each of the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention. Further, the present invention includes a combination of some or all of the configurations of the above-described embodiments as appropriate.
  • the present invention can also be expressed as follows.
  • a complementary field effect transistor having a gate insulating film and a gate electrode in this order on a Si substrate
  • at least the composition of the portion of the gate electrode in contact with the previous gate insulating film is M X Si 1-X (0 ⁇ x ⁇ 1) is the main component of the metal silicide of the metal M, and the interface between the metal silicide and the gate insulating film included in the gate electrode on the first region and the vicinity thereof
  • the first impurity element is added, and the second impurity element is added to and near the interface between the metal silicide and the gate insulating film contained in the gate electrode on the second region, and the third region.
  • a semiconductor device characterized in that the interface between the metal silicide and the gate insulating film contained in the gate electrode on the region and the vicinity thereof does not substantially contain the first and second impurity elements. Is provided.
  • the impurity amounts in the channels on the first, second, and third regions are substantially the same.
  • the first impurity element is composed of at least one element selected from B, Al, Ga, In, and Tl.
  • the second impurity element is made of at least one element selected from N, P, As, Sb, and Bi.
  • the metal M is preferably a metal capable of forming a silicide capable of a salicide process.
  • the metal M is preferably Ni.
  • the portion of the silicide in which the metal M is Ni and is in contact with the gate insulating film is represented by Ni X Si 1-X (0 ⁇ x ⁇ 1), 0.6 ⁇ x ⁇ 1. it can.
  • the portion of the silicide in which the metal M is Ni and is in contact with the gate insulating film is expressed by Ni X Si 1-X (0 ⁇ x ⁇ 1), 0.4 ⁇ x ⁇ 0.6. be able to.
  • the portion of the silicide in which the metal M is Ni that is in contact with the gate insulating film contains a NiSi phase as a main component.
  • the portion of the silicide in which the metal M is Ni and is in contact with the gate insulating film is represented by Ni X Si 1-X (0 ⁇ x ⁇ 1), 0 ⁇ x ⁇ 0.4. it can.
  • a portion of the silicide in which the metal M is Ni is in contact with the gate insulating film contains a NiSi 2 phase as a main component.
  • the first and second impurity elements preferably have a concentration of 1 ⁇ 10 20 cm ⁇ 3 or more in the vicinity of the gate insulating film interface.
  • a Si oxide film or a Si oxynitride film can be used as the gate insulating film.
  • the gate insulating film may be HfSiON. In this case, it is preferable to have a Si oxide film, a Si oxynitride film layer, or a Si nitride film layer in a portion in contact with the gate electrode of the gate insulating film.
  • a complementary field effect transistor having a gate insulating film and a gate electrode in this order on a Si substrate
  • at least the gate insulating film on the first region is in contact with the gate insulating film.
  • the portion is made of polycrystalline Si doped in p-type
  • at least the portion in contact with the gate insulating film of the gate electrode on the second region is made of polycrystalline Si doped in n-type
  • the gate on the third region A semiconductor device is provided in which at least a portion of the electrode in contact with the gate insulating film does not substantially contain the p-type and n-type dopants.
  • the metal M is preferably a metal capable of forming a silicide capable of a salicide process. Still further, the metal M is preferably Ni. Further, a Si oxide film or a Si oxynitride film can be used as the gate insulating film.
  • the gate insulating film may be HfSiON. In this case, it is preferable to have a Si oxide film, a Si oxynitride film layer, or a Si nitride film layer in a portion in contact with the gate electrode of the gate insulating film.
  • polycrystalline Si (polycrystalline Si) is deposited on the gate insulating film, and B, Al, Ga, In are deposited on the polycrystalline Si on the first region.
  • Tl is selectively added using a resist mask and an ion implantation method, and at least one of N, P, As, Sb, and Bi is added to polycrystalline Si on the second region.
  • the polycrystalline Si is processed into a desired gate size, and the additive element in the polycrystalline Si is electrically activated by heat treatment.
  • the method includes a step of segregating the element to the interface between the gate electrode and the gate insulating film and a step of selectively etching away a metal portion that has not been silicided.
  • the second method for manufacturing a semiconductor device includes a step of depositing polycrystalline Si on the gate insulating film, processing the polycrystalline Si into a desired gate dimension, and forming a metal M thereon. Forming a metal silicide M X Si 1-X (0 ⁇ x ⁇ 1) as the gate electrode, and selectively removing the metal portion that has not been silicided by heat-treating them. And a step of applying a resist mask and an ion implantation method to at least one element of B, Al, Ga, In, and Tl with respect to the metal silicide M X Si 1-X (0 ⁇ x ⁇ 1) on the first region.
  • polycrystalline Si is deposited on the gate insulating film, and B, Al, Ga, In, and Tl are deposited on the polycrystalline Si on the first region. And selectively adding at least one element using a resist mask and an ion implantation method, and at least one element of N, P, As, Sb, and Bi with respect to polycrystalline Si on the second region.
  • the impurity concentration in the substrate is kept constant, Control the amount.
  • the impurity concentration in the substrate is kept constant and the threshold is low. The value is realized by a polycrystalline Si electrode to which a dopant is added, and a high threshold value is realized by a silicide electrode having a work function of Si mid gap.
  • the concentration of impurities in the channel can be reduced particularly in a transistor having a high threshold value as compared with the prior art.
  • suppression of gate depletion can be realized by using a metal gate.
  • improvement in mobility and suppression of threshold variation can be realized, and high performance of the transistor can be achieved.
  • the manufacturing method of the present invention since the impurity addition can be easily performed by the PR process and the ion implantation process, a desired device can be easily obtained.
  • the present invention it is possible to provide a semiconductor device capable of improving the characteristics and reliability of an element and a manufacturing method thereof.
  • FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. It is sectional drawing which shows 2nd embodiment of the semiconductor device which concerns on this invention. It is a graph which shows the relationship between Ni silicide crystal phase and Ni film thickness / Si film thickness before silicidation. It is a graph which shows the composition distribution of the thickness direction (depth direction) in a silicide electrode. It is a graph which shows the relationship between the crystallized Ni silicide composition and the Ni film thickness / Si film thickness before silicidation. It is a graph which shows the composition dependence of the effective work function of crystallized Ni silicide. It is a graph which shows the range of the threshold value of a transistor realizable by the work function of a silicide electrode.
  • FIG. 3 is a cross-sectional view (No. 1) illustrating a first example of a method of manufacturing the semiconductor device of FIG. 1.
  • FIG. 3 is a sectional view (No. 2) showing a first example of a method of manufacturing the semiconductor device of FIG. 1;
  • FIG. 3 is a sectional view (No. 3) showing a first example of a method of manufacturing the semiconductor device of FIG. 1;
  • 4 is a graph (part 1) showing a measurement result of drain current-gate voltage characteristics of a MOSFET according to the present invention. It is a graph (the 2) which shows the measurement result of the drain current-gate voltage characteristic of MOSFET which concerns on this invention.
  • FIG. 6 is a graph (part 3) showing a measurement result of drain current-gate voltage characteristics of the MOSFET according to the present invention. It is a graph which shows the measurement result of the effective electric field dependence of the electron mobility of MOSFET which concerns on this invention. It is a graph which shows the channel impurity concentration dependence of the threshold value dispersion
  • FIG. 6 is a cross-sectional view (No. 1) illustrating a second example of a method of manufacturing the semiconductor device of FIG. 1.
  • FIG. 8 is a cross-sectional view (No. 2) illustrating the second example of the method for manufacturing the semiconductor device of FIG. 1.
  • FIG. 9 is a sectional view (No. 3) showing a second example of the method for manufacturing the semiconductor device of FIG.
  • FIG. 3 is a sectional view (No. 1) showing a method for manufacturing the semiconductor device of FIG. 2;
  • FIG. 3 is a sectional view (No. 2) showing the method for manufacturing the semiconductor device of FIG. 2;
  • FIG. 3 is a sectional view (No. 3) showing the method for manufacturing the semiconductor device of FIG. 2;
  • It is sectional drawing which shows 3rd embodiment of the semiconductor device which concerns on this invention.
  • Silicide layer 11 Interlayer insulating film 112.
  • Full silicide electrode 212 N-type full silicide electrode 312 in the second region.
  • Non-doped full silicide electrode 113 in the third region P-type additive element 213 segregated at the electrode / insulating film interface in the first region.
  • Segregated n-type additive element 12 ...
  • First metal film 21 Gate insulating film 22 having HfSiON on the outermost surface... SiO 2 or SiON cap film

Abstract

Disclosed is a semiconductor device that can reduce a problem of the control of a threshold value of a CMOS transistor using a metal gate electrode and can significantly improve the properties of an element. A metal silicide layer is adopted in a part, in contact with a gate insulating film (4), in each of a p-type full silicide electrode (112), an n-type full silicide electrode (212) and a non-doped full silicide electrode (312). A first region (100) contains an impurity element, which is converted to a p type in silicon, at the interface of the p-type full silicide electrode (112) and the gate insulating film (4). A second region (200) contains an impurity element, which is converted to an n type in silicon, at the interface of the n-type full silicide electrode (212) and the gate insulating film (4). A third region (300) does not substantially contain any impurity element at the interface of the non-doped full silicide electrode (312) and the gate insulating film (4). A transistor having a plurality of threshold values is realized by preparing effective work functions of the impurity-added full silicide metal gate electrode separately from each other.

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
 本発明は、フルシリサイドゲート電極を有する半導体装置及びその製造方法に関するものであり、特にMOSFET(Metal Oxide Semiconductor Field Effect Transistor)の高性能化と高信頼性化に関する技術である。以下、元素名は原則として元素記号で表し、at%は単に%と略称する。 The present invention relates to a semiconductor device having a full silicide gate electrode and a method for manufacturing the same, and more particularly to a technique related to high performance and high reliability of MOSFET (Metal Oxide Semiconductor Semiconductor Field Effect Transistor). Hereinafter, in principle, element names are represented by element symbols, and at% is simply abbreviated as%.
 トランジスタの高性能化のため微細化が押し進められている。MOSFETが微細化されると、チャネル中の不純物配置のランダム性による特性ばらつきが無視できなくなり、45nmノード付近ではこのチャネル中の不純物濃度揺らぎがMOSFETのしきい値ばらつきの大きな要因の一つになる。特に、一般にSRAM(Static Random Access Memory)を構成するトランジスタや、オフ電流を一定値以下に抑制する必要があるDRAM(Dynamic Random Access Memory)のセルトランジスタでは、しきい値ばらつきによるデバイス特性への影響が大きいため、しきい値ばらつきを抑制する必要がある。 Miniaturization is being promoted to improve the performance of transistors. When the MOSFET is miniaturized, the characteristic variation due to the randomness of the impurity arrangement in the channel cannot be ignored, and the impurity concentration fluctuation in the channel becomes one of the major factors of the threshold variation of the MOSFET near the 45 nm node. . In particular, for transistors that make up SRAM (Static Random Access Memory) and cell transistors of DRAM (Dynamic Random Access Memory) that need to keep the off-state current below a certain value, the influence on device characteristics due to threshold variations Therefore, it is necessary to suppress variation in threshold value.
 非特許文献1によると、チャネル中の不純物濃度揺らぎによるしきい値ばらつきは、不純物濃度の増大とともに増大する。したがって、不純物濃度揺らぎによるしきい値ばらつきを抑制するには、チャネル中の不純物濃度を低減すること、及び反転時の電気的なゲート絶縁膜厚を低減することが有効である。 According to Non-Patent Document 1, the threshold variation due to the impurity concentration fluctuation in the channel increases as the impurity concentration increases. Therefore, in order to suppress variations in threshold value due to fluctuations in impurity concentration, it is effective to reduce the impurity concentration in the channel and to reduce the electrical gate insulating film thickness during inversion.
 しかしながら、しきい値ばらつきを抑制する必要性が高いSRAMやDRAMにおいては、デバイス特性上ある程度しきい値の絶対値を高く設定する必要があるので、例えばゲート電極としてドープ多結晶Si電極を用いる場合、基板中の不純物濃度を高くする必要があった。このため、不純物濃度揺らぎによるしきい値ばらつきが回避できなかった。また、チャネル中の不純物濃度を高い場合、チャネル中のキャリアの移動度が低下するため、デバイスの高速性を損なうというデメリットもあった。更に、GIDL(Gate Induced Drain Lowering)という現象によって、却ってオフ電流が増大するという問題があった。 However, in an SRAM or DRAM that is highly required to suppress threshold variation, it is necessary to set the absolute value of the threshold to be high to some extent in terms of device characteristics. For example, when a doped polycrystalline Si electrode is used as the gate electrode It was necessary to increase the impurity concentration in the substrate. For this reason, variation in threshold due to fluctuations in impurity concentration cannot be avoided. In addition, when the impurity concentration in the channel is high, the mobility of carriers in the channel is lowered, so there is a demerit that the high-speed performance of the device is impaired. Further, there is a problem that the off-current increases due to the phenomenon of GIDL (Gate Induced Drain Lowering).
 このような問題を解決するには、MOSFETのしきい値を従来のようにチャネル不純物濃度で行うのでなく、ゲート電極の仕事関数を実効的に変化させて行うことが有効だと考えられる。そのための方法としては、高速動作のために低いしきい値が必要なMOSFETのゲート電極と、オフ電流低減のため高いしきい値が必要なMOSFETのゲート電極とを、作り分けることが考えられる。これを実現するには、特にメタルゲート電極の使用が有効であると考えられる。メタルゲート電極の使用は、従来の多結晶Si電極の空乏化を完全に排除することができる。したがって、反転時の電気的なゲート絶縁膜厚を低減することにも有効であり、その観点からもしきい値ばらつきを低減するのに有効な手段といえる。 In order to solve such a problem, it is considered that it is effective to change the work function of the gate electrode effectively instead of using the MOSFET threshold value at the channel impurity concentration as in the prior art. As a method for that purpose, it is conceivable to separately form a MOSFET gate electrode that requires a low threshold value for high-speed operation and a MOSFET gate electrode that requires a high threshold value for reducing off-current. In order to realize this, use of a metal gate electrode is considered to be particularly effective. The use of the metal gate electrode can completely eliminate the depletion of the conventional polycrystalline Si electrode. Therefore, it is effective for reducing the electrical gate insulating film thickness at the time of inversion, and it can be said that it is an effective means for reducing the threshold variation from this viewpoint.
 メタルゲート電極に用いる材料として、純金属や金属窒化物あるいはシリサイド材料等が検討されているが、いずれの場合においても、高速動作のために必要な低いしきい値電圧(以下「Vth」という。)及びオフ電流低減のため必要な高いVthを設定可能でなければならない。 As materials used for the metal gate electrode, pure metals, metal nitrides, silicide materials, and the like have been studied. In any case, a low threshold voltage (hereinafter referred to as “Vth”) necessary for high-speed operation. ) And a high Vth necessary for reducing the off-current must be settable.
 高速動作トランジスタではVthを±0.1eV程度とする必要がある。そのため、nMOSFETでは仕事関数がn型多結晶Siの仕事関数(4.0eV)以下の材料を、pMOSFETではp型多結晶Siの仕事関数(5.2eV)以上の材料を、それぞれゲート電極に用いる必要がある。一方、オフ電流低減のため高いしきい値が必要なMOSFETでは、Vthを±0.6eV程度とする必要がある。そのため、nMOSFET及びpMOSFETでは、ともに実効的な仕事関数がSiミッドギャップ(4.6eV)に相当する材料をゲート電極に用いる必要がある。 For high-speed operation transistors, Vth needs to be about ± 0.1 eV. Therefore, a material having a work function of n-type polycrystalline Si or less (4.0 eV) is used for the nMOSFET, and a material having a work function (5.2 eV) or more of the p-type polycrystalline Si is used for the pMOSFET. There is a need. On the other hand, in a MOSFET that requires a high threshold to reduce off-current, Vth needs to be about ± 0.6 eV. Therefore, in the nMOSFET and the pMOSFET, it is necessary to use a material having an effective work function corresponding to the Si mid gap (4.6 eV) for the gate electrode.
 これらのうち特に高速動作トランジスタ用のVthを±0.1eV程度に実現する手段として、異なる仕事関数を持った異種の金属又は合金を、nMOSFETの電極とpMOSFETの電極とにそれぞれ使い分けることで、トランジスタのVthを制御する方法(デュアルメタルゲート技術)が提案されている。例えば、非特許文献2には、SiO上に形成したTaとRuの仕事関数はそれぞれ4.15eVと4.95eVであり、これらを用いることにより前述の二つの電極間で0.8eVの仕事関数変調が可能であると述べられている。 Among these, as a means for realizing Vth for high-speed operation transistors to about ± 0.1 eV, different metals or alloys having different work functions are used separately for nMOSFET electrodes and pMOSFET electrodes, respectively. A method of controlling Vth (dual metal gate technology) has been proposed. For example, in Non-Patent Document 2, the work functions of Ta and Ru formed on SiO 2 are 4.15 eV and 4.95 eV, respectively, and by using these, the work of 0.8 eV between the two electrodes described above is used. It is stated that function modulation is possible.
 また、多結晶Si電極をNi、Hf、Wなどで完全にシリサイド化したフルシリサイド電極に関する技術が最近注目されている。例えば、特許文献1には、SiOをゲート絶縁膜に用い、PやBなどの不純物を注入した多結晶Si電極をNiで完全にシリサイド化したNiフルシリサイド電極をゲート電極に用いた例が開示されている。このNiフルシリサイド電極は、(1)形成プロセスが従来CMOSプロセスと整合性が高いこと、(2)SiO上でシリサイド化前の多結晶Siへの不純物添加によりしきい値電圧制御が行えることから、有望なメタルゲート材料と考えられている。 In addition, a technique related to a full silicide electrode in which a polycrystalline Si electrode is completely silicided with Ni, Hf, W, or the like has recently attracted attention. For example, Patent Document 1 discloses an example in which SiO 2 is used as a gate insulating film and a Ni full silicide electrode obtained by completely siliciding a polycrystalline Si electrode implanted with impurities such as P and B with Ni is used as a gate electrode. It is disclosed. This Ni full silicide electrode has (1) the formation process is highly compatible with the conventional CMOS process, and (2) the threshold voltage can be controlled by adding impurities to polycrystalline Si before silicidation on SiO 2. Therefore, it is considered as a promising metal gate material.
 特に(2)の不純物添加によるしきい値制御では、従来の半導体プロセスで用いられている不純物(pMOS:B、Al、Ga、In、Tl、nMOS:N、P、As、Sb、Bi)を用いると、n型トランジスタ用には4.2~4.4eV程度の実効仕事関数が得られ、p型トランジスタ用には4.7~4.9eV程度の実効仕事関数が得られている。このようなしきい値変化は、シリサイド化時に上記の添加不純物がいわゆる「雪かき」効果によってNiSi/SiO界面に偏析すること、によって起こる。(2)の不純物添加によるしきい値制御は、pMOS/nMOSの作りわけが可能であることから、SiOをゲート絶縁膜に用いたトランジスタのしきい値制御法として有望であると考えられている。 In particular, in the threshold value control by impurity addition (2), impurities (pMOS: B, Al, Ga, In, Tl, nMOS: N, P, As, Sb, Bi) used in the conventional semiconductor process are used. When used, an effective work function of about 4.2 to 4.4 eV is obtained for an n-type transistor, and an effective work function of about 4.7 to 4.9 eV is obtained for a p-type transistor. Such a threshold change occurs due to segregation of the above-mentioned added impurities at the NiSi / SiO 2 interface by the so-called “snow plowing” effect during silicidation. The threshold control by addition of impurities in (2) can be made into pMOS / nMOS, so it is considered promising as a threshold control method for transistors using SiO 2 as a gate insulating film. Yes.
米国特許第7183182号明細書US Pat. No. 7,183,182
 しかしながら、上記の技術にはそれぞれ以下のような問題点が存在する。異なる仕事関数を持った異種の金属又は合金を作り分けるデュアルメタルゲート技術は、pMOSFETとnMOSFETのどちらかのゲート上に堆積された層をエッチング除去するプロセスが必要であり、エッチングの際にゲート絶縁膜の品質を劣化させてしまうため、素子の特性や信頼性が損なわれる。 However, each of the above technologies has the following problems. Dual metal gate technology that creates different metals or alloys with different work functions requires a process to etch away the layer deposited on the gate of either the pMOSFET or the nMOSFET, and the gate insulation during the etching is required. Since the quality of the film is deteriorated, the characteristics and reliability of the element are impaired.
 SiOゲート絶縁膜上へゲート電極として、PやBなどの不純物を注入した多結晶Si電極をNiで完全にシリサイド化したフルシリサイド電極を、特にVthばらつきを低減する必要があるデバイスに適用する場合、フルシリサイド電極の実効的な仕事関数のばらつきを抑制する必要がある。 As a gate electrode on the SiO 2 gate insulating film, a full silicide electrode obtained by completely siliciding a polycrystalline Si electrode implanted with impurities such as P and B with Ni is applied to a device that needs to reduce Vth variation in particular. In this case, it is necessary to suppress variation in effective work function of the full silicide electrode.
 本発明は、素子の特性や信頼性を向上させることが可能な半導体装置及びその製造方法を提供することを目的としている。 An object of the present invention is to provide a semiconductor device capable of improving the characteristics and reliability of an element and a manufacturing method thereof.
 本発明に係る半導体装置は、Si基板上にゲート絶縁膜及びゲート電極が設けられた複数のトランジスタ構造を有する。そして、本発明に係る半導体装置は、前記ゲート電極は前記ゲート絶縁膜に接する部分に金属シリサイド層を有し、前記複数のトランジスタ構造のそれぞれは第一領域、第二領域及び第三領域のいずれかに属し、前記第一領域は前記金属シリサイド層とゲート絶縁膜との界面に第一不純物元素を含み、前記第二領域は前記金属シリサイド層とゲート絶縁膜との界面に前記第二不純物元素を含み、前記第三領域は前記金属シリサイド層とゲート絶縁膜との界面に前記第一不純物元素及び前記第二不純物元素のいずれも実質的に含まず、前記第一不純物元素と前記第二不純物元素とはSi中で互いに反対の導電型を形成する性質を有する、ことを特徴とする。 The semiconductor device according to the present invention has a plurality of transistor structures in which a gate insulating film and a gate electrode are provided on a Si substrate. In the semiconductor device according to the present invention, the gate electrode has a metal silicide layer in a portion in contact with the gate insulating film, and each of the plurality of transistor structures is any of the first region, the second region, and the third region. The first region includes a first impurity element at an interface between the metal silicide layer and the gate insulating film, and the second region includes the second impurity element at an interface between the metal silicide layer and the gate insulating film. And the third region substantially does not include both the first impurity element and the second impurity element at the interface between the metal silicide layer and the gate insulating film, and the first impurity element and the second impurity element. The element has a property of forming conductivity types opposite to each other in Si.
 本発明に係る半導体装置の製造方法は、ゲート絶縁膜上に多結晶Siを堆積する工程と、前記多結晶Siを第一領域、第二領域及び第三領域に分け、前記第一領域に第一導電型となる第一不純物元素をイオン注入法によって添加し、前記第二領域に前記第一導電型とは逆の第二導電型となる第二不純物元素をイオン注入法によって添加する工程と、前記多結晶Siをゲート電極に加工する工程と、前記多結晶Si上に金属を成膜する工程と、前記多結晶Si及び前記金属を熱処理することによって、金属シリサイド層を形成するとともに前記第一不純物元素及び前記第二不純物元素を当該金属シリサイド層と前記ゲート絶縁膜との界面に偏析させる工程と、前記金属シリサイドにならなかった前記金属を除去する工程と、を含むことを特徴とする。 A method of manufacturing a semiconductor device according to the present invention includes a step of depositing polycrystalline Si on a gate insulating film, dividing the polycrystalline Si into a first region, a second region, and a third region, and forming a first region in the first region. Adding a first impurity element having one conductivity type by an ion implantation method, and adding a second impurity element having a second conductivity type opposite to the first conductivity type to the second region by an ion implantation method; A step of processing the polycrystalline Si into a gate electrode; a step of forming a metal on the polycrystalline Si; and heat-treating the polycrystalline Si and the metal to form a metal silicide layer and A step of segregating one impurity element and the second impurity element at an interface between the metal silicide layer and the gate insulating film, and a step of removing the metal that has not become the metal silicide. To.
 本発明に係る半導体装置によれば、低しきい値を持つトランジスタ及び高しきい値を持つトランジスタを1チップ上に作製する際、半導体基板中の不純物濃度を一定として金属シリサイド電極中の不純物量を制御することにより、特に高しきい値を持つトランジスタにおいて従来に比べチャネル中の不純物濃度を低減できる。また、同時にメタルゲート使用によってゲート空乏化抑制も実現できる。この結果、移動度の向上及びしきい値ばらつきの抑制を実現でき、トランジスタの高性能化が図れる。本発明に係る製造方法によれば、不純物添加をPR(フォトレジスト)工程及びイオン注入工程によって簡便に行うことができるため、簡便に所望の半導体装置を得ることができる。 According to the semiconductor device of the present invention, when producing a transistor having a low threshold value and a transistor having a high threshold value on one chip, the impurity concentration in the metal silicide electrode with the impurity concentration in the semiconductor substrate kept constant. By controlling the above, it is possible to reduce the impurity concentration in the channel as compared with the conventional case, particularly in a transistor having a high threshold. At the same time, suppression of gate depletion can be realized by using a metal gate. As a result, improvement in mobility and suppression of threshold variation can be realized, and high performance of the transistor can be achieved. According to the manufacturing method of the present invention, impurities can be easily added by a PR (photoresist) process and an ion implantation process, so that a desired semiconductor device can be easily obtained.
 以下、本発明を実施形態に基づき詳細に説明する。 Hereinafter, the present invention will be described in detail based on embodiments.
 本発明者は、Si酸化膜又はSi酸窒化膜を最表面とするゲート絶縁膜上に、ゲート電極として結晶性が高いフルシリサイド電極を適用した技術について、次の知見を得た。シリサイド電極の金属組成を変化させても、実効仕事関数はほとんどSiミッドギャップ(4.6eV)に相当する値で一定である。一方、ゲート電極として結晶性が高い不純物添加フルシリサイド電極を適用する場合、Niシリサイド電極のNi組成の減少に伴い不純物添加による実効仕事関数の変化幅が増大し、従来と比べてより大きな実効仕事関数の変化幅を実現できる。本発明は、これらの知見に基づきなされたものである。 The present inventor has obtained the following knowledge about a technique in which a full silicide electrode having high crystallinity is applied as a gate electrode on a gate insulating film having a Si oxide film or a Si oxynitride film as the outermost surface. Even if the metal composition of the silicide electrode is changed, the effective work function is almost constant at a value corresponding to the Si midgap (4.6 eV). On the other hand, when an impurity-added full silicide electrode with high crystallinity is applied as the gate electrode, the change in effective work function due to the addition of impurities increases as the Ni composition of the Ni silicide electrode decreases, resulting in a larger effective work than before. The change width of the function can be realized. The present invention has been made based on these findings.
 この知見は、以下のようなMOS容量を用いた予備実験から見い出されたものである。まず、Si基板上にSiOゲート絶縁膜(膜厚:3nm)を形成し、その上に膜厚80nmの多結晶Si電極を形成した。次に、多結晶Si電極に対して添加元素をイオン注入した。例えばnMOSトランジスタを実現するためには、Siに対してn型不純物であるN、P、As、Sb、Biなどを、pMOSトランジスタを実現するためには、Siに対してp型不純物であるB、Al、In、Ga、Tlなどを、それぞれイオン注入した。その後、多結晶Si電極(膜厚:TSi)上にNi膜(膜厚:TNi)を堆積して、熱処理によって多結晶Si電極をフルシリサイド化した。 This finding has been found from preliminary experiments using the following MOS capacitors. First, a SiO 2 gate insulating film (film thickness: 3 nm) was formed on a Si substrate, and a polycrystalline Si electrode having a film thickness of 80 nm was formed thereon. Next, an additive element was ion-implanted into the polycrystalline Si electrode. For example, in order to realize an nMOS transistor, N, P, As, Sb, Bi, etc., which are n-type impurities with respect to Si, and in order to realize a pMOS transistor, B, which is a p-type impurity, with respect to Si. , Al, In, Ga, Tl, and the like were each ion-implanted. Thereafter, a Ni film (film thickness: T Ni ) was deposited on the polycrystalline Si electrode (film thickness: T Si ), and the polycrystalline Si electrode was fully silicided by heat treatment.
 図3に示すように、Niシリサイドの結晶相は、多結晶Si上に堆積したNi膜の厚さ、すなわち、多結晶Siに供給されるNiの量に対して段階的に決まる。例えば、実効仕事関数に影響を与える電極/絶縁膜界面付近のNiシリサイドの結晶相を主にNiSi相としたい場合は、ゲート多結晶Siの厚さ(TSi)とNi膜(TNi)の比(TNi/TSi)を0.55~0.95の範囲に設定すればよく、また主にNiSi相にしたい場合は、TNi/TSiを1.60以上にすればよい。ただし、電極/絶縁膜界面付近のNiシリサイドの結晶相を、NiSi相を主成分とするシリサイドにする場合だけは、Ni膜厚をTNi/TSi=0.28~0.54の範囲にしてかつシリサイド化温度を600℃以上、好ましくは650℃以上にすることが必要である。 As shown in FIG. 3, the crystal phase of Ni silicide is determined stepwise with respect to the thickness of the Ni film deposited on the polycrystalline Si, that is, the amount of Ni supplied to the polycrystalline Si. For example, when the Ni silicide crystal phase in the vicinity of the electrode / insulating film interface that affects the effective work function is mainly the NiSi phase, the thickness of the gate polycrystalline Si (T Si ) and the Ni film (T Ni ) The ratio (T Ni / T Si ) may be set in the range of 0.55 to 0.95, and in the case where the NiSi 3 phase is mainly desired, T Ni / T Si may be set to 1.60 or more. However, the Ni film thickness is in the range of T Ni / T Si = 0.28 to 0.54 only when the crystal phase of Ni silicide in the vicinity of the electrode / insulating film interface is silicide mainly composed of NiSi 2 phase. And the silicidation temperature must be 600 ° C. or higher, preferably 650 ° C. or higher.
 更に、Niシリサイドの仕事関数を決定するNi/(Ni+Si)組成は、NiSi、NiSi、NiSiなどの結晶相によりほぼ自己整合的に決まる。そのため、同じ結晶相を得る(すなわち同じ仕事関数を得る)ことができるNi膜の堆積膜厚やシリサイド化温度などのプロセス条件のマージンが広いことから、製造プロセスのバラツキを低く抑えることができる。 Furthermore, the Ni / (Ni + Si) composition that determines the work function of Ni silicide is determined in a substantially self-aligned manner by the crystal phase of NiSi 2 , NiSi, Ni 3 Si, or the like. Therefore, since the margin of process conditions such as the deposited film thickness of the Ni film and the silicidation temperature capable of obtaining the same crystal phase (that is, obtaining the same work function) is wide, variations in the manufacturing process can be suppressed low.
 このフルシリサイド化の際に、添加元素が「雪かき」効果によってフルシリサイド電極/絶縁膜界面に偏析した。図4は、このようにして作製されたフルシリサイドゲート電極中の不純物濃度プロファイルを、二次イオン質量分析法(SIMS)で測定した結果である。この際、偏析不純物の濃度が、ゲート絶縁膜界面近傍において、1×1020cm-3を下回ると、ほとんど実効仕事関数が変化しなかった。したがって、不純物偏析により実効仕事関数変化を変化させるためには、偏析不純物の濃度がゲート絶縁膜界面近傍において1×1020cm-3以上であることが好ましい。 During the full silicidation, the additive elements segregated at the full silicide electrode / insulating film interface due to the “snow plowing” effect. FIG. 4 shows the result of measuring the impurity concentration profile in the full silicide gate electrode fabricated in this way by secondary ion mass spectrometry (SIMS). At this time, the effective work function hardly changed when the concentration of segregation impurities was below 1 × 10 20 cm −3 in the vicinity of the interface of the gate insulating film. Therefore, in order to change the effective work function change due to impurity segregation, the concentration of segregated impurities is preferably 1 × 10 20 cm −3 or more in the vicinity of the gate insulating film interface.
 上記のように作製したMOS容量のNiシリサイドの結晶相をXRDで特定した結果について、図3にまとめる。TNi/TSi=0.28~0.54の場合は、形成されるNiシリサイドは実質的にNiSiからなる。ただし、XRDスペクトルに弱くNiSiのピークが見られる。XPSによるシリサイド電極組成の深さ方向分析によれば、電極表面側に若干Ni組成がNiSiのものに比べて高いところがあり、NiSiは主にその部分に存在すると考えられる。TNi/TSi=0.55~0.95の場合は、形成されるNiシリサイドは実質的にNiSiからなる。また、TNi/TSiが1.60以上の場合は、形成されるNiシリサイドは実質的にNiSiからなる。 FIG. 3 summarizes the results of specifying the crystal phase of the MOS capacitor Ni silicide produced as described above by XRD. In the case of T Ni / T Si = 0.28 to 0.54, the formed Ni silicide is substantially made of NiSi 2 . However, a weak NiSi peak is observed in the XRD spectrum. According to the depth direction analysis of the silicide electrode composition by XPS, there is a portion where the Ni composition is slightly higher than that of NiSi 2 on the electrode surface side, and NiSi is considered to exist mainly in that portion. When T Ni / T Si = 0.55 to 0.95, the formed Ni silicide is substantially made of NiSi. When T Ni / T Si is 1.60 or more, the formed Ni silicide is substantially made of Ni 3 Si.
 図5は、上記のように作製したMOS容量の電極/絶縁膜界面における、電極中Ni組成のNi膜厚/多結晶Si膜厚の比(TNi/TSi)依存性である。電極中Ni組成はXPS測定から求めた。電極組成のエラーバーはXPSによる多点測定におけるバラつきを示す。図より界面における電極中Ni組成はTNi/TSi比に応じて段階的に決まる。例えば、TNi/TSi=0.28~0.54、0.55~0.95、及び1.60以上の場合、界面における電極中Ni組成は各々33.3±7%、50±5%、及び75±5%となった。これらの組成は各々実質的にNiSi(33.3%)、NiSi(50%)、及びNiSi(75%)に一致した。これは、界面における電極中Ni組成が、図3に見られる結晶相によって自己整合的に決定されていることに起因するものと考えられる。 FIG. 5 shows the dependence of the Ni composition in the electrode on the ratio of Ni film thickness / polycrystalline Si film thickness (T Ni / T Si ) at the electrode / insulating film interface of the MOS capacitor fabricated as described above. The Ni composition in the electrode was determined from XPS measurement. The electrode composition error bars show variations in multipoint measurement by XPS. From the figure, the Ni composition in the electrode at the interface is determined stepwise according to the T Ni / T Si ratio. For example, when T Ni / T Si = 0.28 to 0.54, 0.55 to 0.95, and 1.60 or more, the Ni composition in the electrode at the interface is 33.3 ± 7% and 50 ± 5, respectively. % And 75 ± 5%. Each of these compositions substantially matched NiSi 2 (33.3%), NiSi (50%), and Ni 3 Si (75%). This is considered to be due to the fact that the Ni composition in the electrode at the interface is determined in a self-aligned manner by the crystal phase seen in FIG.
 また、上記のようにして作製した、不純物を添加していない(ノンドープ)場合並びにAs及びBを添加した場合(As及びBの多結晶Si中への添加量は両方とも5×1020cm-3)における、結晶化Niシリサイドの実効仕事関数の界面付近のシリサイド電極組成依存性を図6に示す。電極組成のエラーバーはXPSによる多点測定におけるバラつきを示す。また、図中にはその組成における主結晶相を示した。 In addition, when the impurity was not added (non-doped) and when As and B were added as prepared above (As and B were both added to polycrystalline Si at 5 × 10 20 cm −). FIG. 6 shows the dependency of the effective work function of crystallized Ni silicide in 3 ) on the silicide electrode composition near the interface. The electrode composition error bars show variations in multipoint measurement by XPS. In the figure, the main crystal phase in the composition is shown.
 図6からわかるように、ノンドープの場合は結晶化Niシリサイドの実効仕事関数は組成にほとんど依存しない。すなわち、シリサイド電極の金属組成を変化させても、実効仕事関数変化がほとんどSiミッドギャップ(4.6eV)に相当する実効仕事関数で一定である。よって、たとえNi組成がばらついてもしきい値ばらつきは抑制される。したがって、しきい値ばらつきを抑制する必要性が高いSRAMやDRAMにおいては、不純物を添加していない(ノンドープ)結晶化Niシリサイドをゲート電極として用いると、チャネル中の不純物濃度を低く保ったまま所望の高いしきい値を得ることができる。そこで、従来の多結晶Si電極と高いチャネル不純物濃度とを用いる場合に比べて、不純物濃度揺らぎによるしきい値ばらつきを回避でき、高いキャリア移動度を実現できるためデバイスの高速性も図れる。更に、GIDLを抑制できるためオフ電流を低減できる。 As can be seen from FIG. 6, in the case of non-doping, the effective work function of crystallized Ni silicide hardly depends on the composition. That is, even if the metal composition of the silicide electrode is changed, the effective work function change is almost constant at an effective work function corresponding to the Si mid gap (4.6 eV). Therefore, even if the Ni composition varies, the threshold variation is suppressed. Therefore, in SRAMs and DRAMs that have a high need to suppress threshold variation, using a non-doped (non-doped) crystallized Ni silicide as a gate electrode is desirable while keeping the impurity concentration in the channel low. A high threshold value can be obtained. Therefore, as compared with the case where a conventional polycrystalline Si electrode and a high channel impurity concentration are used, variation in threshold value due to fluctuations in impurity concentration can be avoided and high carrier mobility can be realized, so that the speed of the device can be improved. Furthermore, since GIDL can be suppressed, off current can be reduced.
 一方、不純物を添加した場合を見ると、Ni組成の減少(Si組成の増加)に伴い、不純物添加による実効仕事関数変化が増大した。特に主結晶相がNiSiであるNi組成26%から40%の領域における実効仕事関数は、As添加の場合で4.0eVとなり、B添加の場合で5.2eVとなることにより、高性能用nMOSFETデバイスに必要な実効仕事関数(nMOS:4.0eV以下、pMOS:5.2eV以上)が実現できる。 On the other hand, in the case where impurities were added, the change in effective work function due to the addition of impurities increased as the Ni composition decreased (the Si composition increased). In particular, the effective work function in the Ni composition range of 26% to 40% in which the main crystal phase is NiSi 2 is 4.0 eV when As is added, and 5.2 eV when B is added. An effective work function (nMOS: 4.0 eV or less, pMOS: 5.2 eV or more) necessary for the nMOSFET device can be realized.
 不純物による実効仕事関数変化が、Niシリサイド中のNi組成の減少(Si組成の増加)に伴い増加する傾向は、仕事関数を変調する効果を持つすべての不純物に対して確認した。また、特に結晶化NiSiにおける実効仕事関数は、n型不純物(N、P、As、Sb、Biなど)の場合で4.0eV以下となり、p型不純物(B、Al、In、Ga、Tlなど)の場合で5.2eV以上となるので、高性能用nMOSFETデバイスに必要な実効仕事関数(nMOS:4.0eV以下、pMOS:5.2eV以上)が実現できることを確認した。 The tendency that the change in effective work function due to impurities increases as the Ni composition in Ni silicide decreases (increases in Si composition) was confirmed for all impurities having the effect of modulating the work function. In particular, the effective work function in crystallized NiSi 2 is 4.0 eV or less in the case of n-type impurities (N, P, As, Sb, Bi, etc.), and p-type impurities (B, Al, In, Ga, Tl). In this case, the effective work function (nMOS: 4.0 eV or less, pMOS: 5.2 eV or more) necessary for a high-performance nMOSFET device can be realized.
 酸化膜厚が1.8nmの場合、実効仕事関数から予想できるnMOSFETのしきい値(Vth)の範囲は、チャネル不純物濃度に対して図7のようになる。不純物元素を用いて実効仕事関数がnMOS用に4.0eV以下又はpMOS用に5.2eV以上に変調されているNi組成について、そのNi組成が40%を越えない結晶化Niシリサイド電極を用いた場合、CMOSデバイスで通常用いられるチャネル濃度(1017~1018cm-3)で、従来の不純物添加NiSi電極では作製できなかった0.1V程度の低しきい値持つ高性能用デバイスを実現することができる。 When the oxide film thickness is 1.8 nm, the nMOSFET threshold (Vth) range that can be predicted from the effective work function is as shown in FIG. 7 with respect to the channel impurity concentration. For a Ni composition whose effective work function is modulated to 4.0 eV or less for nMOS or 5.2 eV or more for pMOS using an impurity element, a crystallized Ni silicide electrode whose Ni composition does not exceed 40% was used. In this case, a high-performance device having a low threshold value of about 0.1 V, which could not be produced by a conventional impurity-added NiSi electrode, is realized with a channel concentration (10 17 to 10 18 cm −3 ) normally used in a CMOS device. be able to.
 したがって、低Vthを持つnMOSトランジスタ及びpMOSトランジスタ並びに高Vthを持つMOSトランジスタを1チップ上に作製する際、チャネル中の不純物濃度を一定として、低Vthトランジスタではシリサイド電極に不純物を添加し、高Vthトランジスタではシリサイド電極に不純物を添加しないとすれば、特に高しきい値を持つトランジスタにおいて従来に比べチャネル中の不純物濃度が低減できる。また、同時にメタルゲート使用によってゲート空乏化抑制も実現できる。この結果、移動度の向上及びしきい値ばらつきの抑制を実現でき、トランジスタの高性能化が図れる。 Therefore, when an nMOS transistor and a pMOS transistor having a low Vth and a MOS transistor having a high Vth are fabricated on one chip, the impurity concentration in the channel is constant, and in the low Vth transistor, an impurity is added to the silicide electrode, In the transistor, if no impurity is added to the silicide electrode, the impurity concentration in the channel can be reduced particularly in a transistor having a high threshold value as compared with the conventional transistor. At the same time, suppression of gate depletion can be realized by using a metal gate. As a result, improvement in mobility and suppression of threshold variation can be realized, and high performance of the transistor can be achieved.
 CMOSデバイスを作製する場合、コスト低減のため低Vthを持つnMOSトランジスタ及びpMOSトランジスタ並びに高Vthを持つMOSトランジスタのゲート電極材料が同一あることが好ましい。そこで、低Vthを持つnMOSトランジスタ及びpMOSトランジスタのゲート電極として不純物を添加した結晶化Niシリサイド電極を用い、高Vthを持つMOSトランジスタのゲート電極として不純物を添加していない結晶化Niシリサイド電極をゲート電極に用いれば、それが達成される。 When manufacturing a CMOS device, it is preferable that the gate electrode materials of the nMOS transistor and the pMOS transistor having a low Vth and the MOS transistor having a high Vth are the same for cost reduction. Therefore, a crystallized Ni silicide electrode to which impurities are added is used as a gate electrode of an nMOS transistor having a low Vth and a pMOS transistor, and a crystallized Ni silicide electrode to which impurities are not added is gated as a gate electrode of a MOS transistor having a high Vth. This is achieved when used for electrodes.
 ゲート多結晶Si電極をシリサイド化させる金属は、サリサイドプロセスが可能であるシリサイドを形成しうる金属であることが好ましい。なぜなら、ゲート多結晶Si電極のシリサイド化がソース・ドレイン拡散層コンタクト領域上に金属シリサイドが形成される後に行われる場合、ソース・ドレイン拡散層コンタクト領域に形成されている金属シリサイドの抵抗値を増大させない温度でシリサイド化が可能である必要があるからである。その観点から、前記金属が、Niであることが好ましい。 The metal for siliciding the gate polycrystalline Si electrode is preferably a metal capable of forming a silicide capable of a salicide process. This is because when the silicidation of the gate polycrystalline Si electrode is performed after the metal silicide is formed on the source / drain diffusion layer contact region, the resistance value of the metal silicide formed in the source / drain diffusion layer contact region is increased. This is because silicidation needs to be possible at a temperature that does not allow it to occur. From this viewpoint, it is preferable that the metal is Ni.
 ゲート電極にNiシリサイドを用いる場合、図6にあるように不純物添加による実効仕事関数変化量は、NiシリサイドのSi量の増加に伴い増加する。図7より、低Vthを持つnMOSトランジスタ及びpMOSトランジスタのVthをVth=±0.5V程度に設定したい場合、必要な実効仕事関数はSiミッドギャップ(4.6eV)を基準として各々±0.1eV程度である(図7参照)。これらの実効仕事関数を実現するには、図6より、NiシリサイドをNiSi1-Xと表した場合、Ni組成を各々0.6≦x<1とするとよい。また、トランジスタのしきい値ばらつきを抑制するためには、Niフルシリサイド電極の組成のばらつきを抑制する必要があり、そのためには電極の組成はフルシリサイド化時に自己整合的に決定されることが好ましいが、不純物を添加した結晶化NiSiをゲート電極に用いればそれが達成される。 When Ni silicide is used for the gate electrode, as shown in FIG. 6, the effective work function change amount due to the addition of impurities increases as the Si amount of Ni silicide increases. From FIG. 7, when it is desired to set the Vth of the nMOS transistor and the pMOS transistor having a low Vth to about Vth = ± 0.5 V, the necessary effective work function is ± 0.1 eV with respect to the Si mid gap (4.6 eV). (See FIG. 7). In order to realize these effective work functions, when Ni silicide is expressed as Ni X Si 1-X as shown in FIG. 6, the Ni composition is preferably 0.6 ≦ x <1. In addition, in order to suppress the variation in the threshold voltage of the transistor, it is necessary to suppress the variation in the composition of the Ni full silicide electrode. For this purpose, the composition of the electrode is determined in a self-aligned manner during the full silicidation. Although it is preferable, this can be achieved by using crystallized Ni 3 Si doped with impurities for the gate electrode.
 図7より、低Vthを持つnMOSトランジスタ及びpMOSトランジスタのVthをVth=±0.3V程度に設定したい場合、必要な実効仕事関数はSiミッドギャップ(4.6eV)を基準として各々±0.2eV程度である(図7参照)。これらの実効仕事関数を実現するには、図6より、NiシリサイドをNiSi1-Xと表した場合、Ni組成を各々0.4≦x<0.6とするとよい。また、トランジスタのしきい値ばらつきを抑制するためには、Niフルシリサイド電極の組成のばらつきを抑制する必要があり、そのためには電極の組成はフルシリサイド化時に自己整合的に決定されることが好ましいが、不純物を添加した結晶化NiSiをゲート電極に用いればそれが達成される。 From FIG. 7, when it is desired to set the Vth of the nMOS transistor and the pMOS transistor having a low Vth to about Vth = ± 0.3V, the necessary effective work function is ± 0.2 eV each with respect to the Si mid gap (4.6 eV). (See FIG. 7). In order to realize these effective work functions, when Ni silicide is expressed as Ni X Si 1-X as shown in FIG. 6, the Ni composition is preferably 0.4 ≦ x <0.6. In addition, in order to suppress the variation in the threshold voltage of the transistor, it is necessary to suppress the variation in the composition of the Ni full silicide electrode. For this purpose, the composition of the electrode is determined in a self-aligned manner during the full silicidation. Although it is preferable, it is achieved if crystallized NiSi doped with impurities is used for the gate electrode.
 図7より、低Vthを持つnMOSトランジスタ及びpMOSトランジスタのVthをVth=±0.1V程度に設定したい場合、必要な実効仕事関数はSiミッドギャップ(4.6eV)を基準として各々±0.5eV程度である(図7参照)。これらの実効仕事関数を実現するには、図6より、NiシリサイドをNiSi1-Xと表した場合、Ni組成を各々0<x<0.4とするとよい。また、トランジスタのしきい値ばらつきを抑制するためには、Niフルシリサイド電極の組成のばらつきを抑制する必要があり、そのためには電極の組成はフルシリサイド化時に自己整合的に決定されることが好ましいが、不純物を添加した結晶化NiSiをゲート電極に用いればそれが達成される。 As shown in FIG. 7, when it is desired to set the Vth of the nMOS transistor and the pMOS transistor having a low Vth to about Vth = ± 0.1 V, the necessary effective work function is ± 0.5 eV each with respect to the Si mid gap (4.6 eV). (See FIG. 7). In order to realize these effective work functions, when Ni silicide is expressed as Ni X Si 1-X as shown in FIG. 6, the Ni composition is preferably 0 <x <0.4. In addition, in order to suppress the variation in the threshold voltage of the transistor, it is necessary to suppress the variation in the composition of the Ni full silicide electrode. For this purpose, the composition of the electrode is determined in a self-aligned manner during the full silicidation. Preferably, this is achieved if crystallized NiSi 2 doped with impurities is used for the gate electrode.
 ゲート絶縁膜としてSi酸化膜又はSi酸窒化膜を用いることができる。また、前記ゲート絶縁膜はHfSiONであってもよい。この場合は、不純物添加によるしきい値変化幅はSiO及びSiONゲート絶縁膜の場合に比べて小さくなるが、ゲート電極と接する部分に、Si酸化膜、Si酸窒化膜層、又はSi窒化膜層を挿入することにより実効仕事関数変化を大きくでき、その結果MOSFETにおいて低いしきい値を実現することができる。 A Si oxide film or a Si oxynitride film can be used as the gate insulating film. The gate insulating film may be HfSiON. In this case, the threshold change width due to the addition of impurities is smaller than in the case of the SiO 2 and SiON gate insulating films, but the Si oxide film, the Si oxynitride film layer, or the Si nitride film is in contact with the gate electrode. By inserting layers, the effective work function change can be increased, and as a result, a low threshold can be realized in the MOSFET.
 また、低Vthを持つnMOSトランジスタ及びpMOSトランジスタ並びに高Vthを持つMOSトランジスタを1チップ上に作製する際、基板中の不純物濃度を一定として、低Vthをドーパントが添加された多結晶Si電極で実現し、高VthをSiミッドギャップの仕事関数を有するノンドープシリサイド電極で実現すれば、特に高Vthを持つトランジスタにおいて従来に比べチャネル中の不純物濃度が低減できる。また、同時に高Vthを持つトランジスタにおいてメタルゲート使用によってゲート空乏化抑制も実現できる。この結果、移動度の向上及びしきい値ばらつきの抑制を実現でき、トランジスタの高性能化が図れる。 In addition, when fabricating nMOS transistors and pMOS transistors with low Vth and MOS transistors with high Vth on a single chip, the impurity concentration in the substrate is constant and low Vth is realized with a polycrystalline Si electrode doped with a dopant. If a high Vth is realized by a non-doped silicide electrode having a Si midgap work function, the impurity concentration in the channel can be reduced as compared with the conventional transistor having a high Vth. At the same time, the gate depletion can be suppressed by using a metal gate in a transistor having a high Vth. As a result, improvement in mobility and suppression of threshold variation can be realized, and high performance of the transistor can be achieved.
 この場合であっても、ゲート多結晶Si電極をシリサイド化する金属は、サリサイドプロセスが可能であるシリサイドを形成しうる金属であることが好ましい。なぜなら、ソース・ドレイン拡散層コンタクト領域に形成されている金属シリサイドの抵抗値を増大させない温度でシリサイド化が可能である必要があるからである。その観点から、前記金属が、Niであることが好ましい。更に、ゲート絶縁膜としてSi酸化膜又はSi酸窒化膜を用いることができる。また、前記ゲート絶縁膜はHfSiONとしても、ゲート電極と接する部分に、Si酸化膜、Si酸窒化膜層、又はSi窒化膜層を挿入してもよい。 Even in this case, the metal for siliciding the gate polycrystalline Si electrode is preferably a metal capable of forming a silicide capable of the salicide process. This is because silicidation must be possible at a temperature that does not increase the resistance value of the metal silicide formed in the source / drain diffusion layer contact region. From this viewpoint, it is preferable that the metal is Ni. Furthermore, a Si oxide film or a Si oxynitride film can be used as the gate insulating film. The gate insulating film may be HfSiON, and a Si oxide film, a Si oxynitride film layer, or a Si nitride film layer may be inserted in a portion in contact with the gate electrode.
 以上の作用を満たす金属シリサイド及び添加元素を用いて作製したCMOSFETの構造図を図1及び図2に示す。図1に示した第一実施形態によれば、低しきい値を持つnMOSトランジスタ及びpMOSトランジスタ並びに高しきい値を持つMOSトランジスタを1チップ上に作製する際、基板中の不純物濃度を一定としてシリサイド電極中の不純物量を制御する。また、図2に示した第二実施形態によれば、低しきい値を持つnMOSトランジスタ及びpMOSトランジスタ並びに高しきい値を持つMOSトランジスタを1チップ上に作製する際、基板中の不純物濃度を一定として、低いしきい値をドーパントが添加された多結晶Si電極で実現し、高いしきい値をSiミッドギャップの仕事関数を有するシリサイド電極で実現する。この結果、特に高しきい値を持つトランジスタにおいて、従来に比べチャネル中の不純物濃度を低減できる。また、両実施形態において、同時にメタルゲート使用によってゲート空乏化抑制も実現できる。この結果、移動度の向上及びしきい値ばらつきの抑制を実現でき、トランジスタの高性能化が図れる。 A structural diagram of a CMOSFET manufactured using a metal silicide satisfying the above-described functions and an additive element is shown in FIGS. According to the first embodiment shown in FIG. 1, when an nMOS transistor and a pMOS transistor having a low threshold and a MOS transistor having a high threshold are fabricated on one chip, the impurity concentration in the substrate is kept constant. The amount of impurities in the silicide electrode is controlled. Further, according to the second embodiment shown in FIG. 2, when an nMOS transistor and a pMOS transistor having a low threshold value and a MOS transistor having a high threshold value are formed on one chip, the impurity concentration in the substrate is reduced. As a constant, a low threshold is realized with a polycrystalline Si electrode doped with a dopant, and a high threshold is realized with a silicide electrode having a Si midgap work function. As a result, the impurity concentration in the channel can be reduced as compared with the conventional case, particularly in a transistor having a high threshold value. In both the embodiments, gate depletion can be suppressed by using a metal gate at the same time. As a result, improvement in mobility and suppression of threshold variation can be realized, and high performance of the transistor can be achieved.
 また、本発明に係る製造方法によれば、ゲート絶縁膜上に多結晶Si電極を形成した後に、再度これを除去する工程がないために、ゲート絶縁膜表面がウェットエチング液や有機溶剤に数度にわたり晒されることがない。このため、信頼性に優れたメタルゲート/ゲート絶縁膜CMOSトランジスタを作製することが可能である。また、本発明に係る製造方法によれば、不純物添加をPR工程及びイオン注入工程によって簡便に行うことができるため、簡便に所望のデバイスを得ることができる。 In addition, according to the manufacturing method of the present invention, after the polycrystalline Si electrode is formed on the gate insulating film, there is no step of removing it again, so that the surface of the gate insulating film becomes wet etching solution or an organic solvent. It is not exposed for several degrees. Therefore, it is possible to manufacture a metal gate / gate insulating film CMOS transistor having excellent reliability. In addition, according to the manufacturing method of the present invention, since the impurity addition can be easily performed by the PR process and the ion implantation process, a desired device can be easily obtained.
 以下、本発明の実施形態を、図面を参照して詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
 図1に示す第一実施形態の半導体装置は、半導体基板としてのSi基板1上に、ゲート絶縁膜4とゲート電極としてのp型フルシリサイド電極112、n型フルシリサイド電極212及びノンドープフルシリサイド電極312とが設けられた複数のトランジスタ構造を有する。そして、p型フルシリサイド電極112、n型フルシリサイド電極212及びノンドープフルシリサイド電極312は、ゲート絶縁膜4に接する部分が金属シリサイド層になっている。複数のトランジスタ構造のそれぞれは、第一領域100、第二領域200及び第三領域300のいずれかに属する。第一領域100は、p型フルシリサイド電極112とゲート絶縁膜4との界面に、シリコン中でp型となる不純物元素を含む。第二領域200は、n型フルシリサイド電極212とゲート絶縁膜4との界面に、シリコン中でn型となる不純物元素を含む。第三領域300は、ノンドープフルシリサイド電極312とゲート絶縁膜4との界面にいずれの不純物元素も実質的に含まない。ここでいう「いずれの不純物元素も実質的に含まない」とは、両方の不純物元素を等量含むことにより、実質的に真性になっている場合も含むものとする。 The semiconductor device of the first embodiment shown in FIG. 1 includes a gate insulating film 4 and a p-type full silicide electrode 112, an n-type full silicide electrode 212, and a non-doped full silicide electrode as a gate electrode on a Si substrate 1 as a semiconductor substrate. 312 and a plurality of transistor structures. The p-type full silicide electrode 112, the n-type full silicide electrode 212, and the non-doped full silicide electrode 312 are metal silicide layers at portions in contact with the gate insulating film 4. Each of the plurality of transistor structures belongs to one of the first region 100, the second region 200, and the third region 300. The first region 100 includes an impurity element that becomes p-type in silicon at the interface between the p-type full silicide electrode 112 and the gate insulating film 4. The second region 200 includes an impurity element that becomes n-type in silicon at the interface between the n-type full silicide electrode 212 and the gate insulating film 4. The third region 300 does not substantially contain any impurity element at the interface between the non-doped full silicide electrode 312 and the gate insulating film 4. The phrase “substantially free of any impurity element” as used herein includes a case in which both of the impurity elements are contained in an equal amount and are substantially intrinsic.
 図8(a)~図10(i)は本発明の第一実施形態に係るMOSFETの製造工程の第一例を示した断面図である。本例は、層間絶縁膜形成後にこれを研磨することにより平坦化すると同時に、ゲート電極上部を露出させることが可能なCMP(Chemical Mechanical Polishing)技術を用いてMOSFETを製造する。また、本例に係るMOSFETは、第一領域100上に作製されるpMOSFETと、第二領域200上に作製されるnMOSFETと、第三領域300上に作製されるnMOSFET(又はpMOSFET)とからなる。 8 (a) to 10 (i) are cross-sectional views showing a first example of a MOSFET manufacturing process according to the first embodiment of the present invention. In this example, a MOSFET is manufactured using a CMP (Chemical Mechanical Polishing) technique capable of flattening by polishing the interlayer insulating film after it is formed and simultaneously exposing the upper portion of the gate electrode. Further, the MOSFET according to this example includes a pMOSFET manufactured on the first region 100, an nMOSFET manufactured on the second region 200, and an nMOSFET (or pMOSFET) manufactured on the third region 300. .
 まず、第一領域100、第二領域200及び第三領域300のSi基板1の表面領域に、STI(Shallow Trench Isolation)技術を用いて素子分離領域2を形成した。続いて、素子分離されたSi基板表面に犠牲絶縁膜3を形成した。犠牲絶縁膜3としては例えば厚さ10nm程度のSi熱酸化膜を用いることができる。 First, the element isolation region 2 was formed on the surface region of the Si substrate 1 in the first region 100, the second region 200, and the third region 300 by using STI (Shallow Trench Isolation) technology. Subsequently, a sacrificial insulating film 3 was formed on the surface of the Si substrate from which the elements were separated. As the sacrificial insulating film 3, for example, a Si thermal oxide film having a thickness of about 10 nm can be used.
 続いて、図8(a)に示すように、犠牲絶縁膜3を通して、第一領域100、第二領域200及び第三領域300のSi基板1の表面領域に対して、チャネル不純物として各々n型、p型及びp(又はn)型のドーパント元素をイオン注入法で添加し、熱処理によって前記ドーパントを電気的に活性化させた。 Subsequently, as shown in FIG. 8A, n-type channel impurities are respectively formed on the surface region of the Si substrate 1 in the first region 100, the second region 200, and the third region 300 through the sacrificial insulating film 3. , P-type and p (or n) -type dopant elements were added by ion implantation, and the dopant was electrically activated by heat treatment.
 続いて、犠牲絶縁膜3を除去し、ゲート絶縁膜4を形成した。ゲート絶縁膜4には、SiONを用いた。そして、ゲート絶縁膜4上に厚さ80nm程度の多結晶Si膜5を形成した。その後、図8(b)に示すように、第一領域100及び第二領域200上の多結晶Siに対しレジストを用いた通常のPRプロセスとイオン注入とを組み合わせることにより、おのおの異なる不純物元素をイオン注入した。例えば、第一領域100にはBを、第二領域200にはAsを注入した。各々の注入エネルギー及びドーズ量は、B注入の場合2keV及び6×1015cm-2、As注入の場合5keV及び5×1015cm-2であった。 Subsequently, the sacrificial insulating film 3 was removed, and a gate insulating film 4 was formed. For the gate insulating film 4, SiON was used. A polycrystalline Si film 5 having a thickness of about 80 nm was formed on the gate insulating film 4. After that, as shown in FIG. 8B, by combining a normal PR process using a resist with respect to the polycrystalline Si on the first region 100 and the second region 200 and ion implantation, different impurity elements are introduced. Ion implantation was performed. For example, B is injected into the first region 100 and As is injected into the second region 200. The implantation energy and dose amount were 2 keV and 6 × 10 15 cm −2 for B implantation, and 5 keV and 5 × 10 15 cm −2 for As implantation.
 その結果、図8(c)に示すように、第一領域100、第二領域200、及び第三領域300上の多結晶Si膜5は各々、p型ドープ多結晶Si膜105、n型ドープ多結晶Si膜205、及びノンドープ多結晶Si膜305となった。 As a result, as shown in FIG. 8 (c), the polycrystalline Si film 5 on the first region 100, the second region 200, and the third region 300 is respectively a p-type doped polycrystalline Si film 105, an n-type doped. A polycrystalline Si film 205 and a non-doped polycrystalline Si film 305 were obtained.
 その後、多結晶Si膜105,205,305上に厚さ150nmのSi酸化膜6を形成した。この多結晶Si膜5と150nmのSi酸化膜6とからなる積層膜を、図9(d)に示すように、リソグラフィー技術及びRIE(Reactive Ion Etching)技術を用いてゲート電極に加工し、引き続いてイオン注入を行い、第一領域100、第二領域200、及び第三領域300のSi表面上に、おのおのエクステンション拡散層領域107,207,307を、ゲート電極をマスクとして自己整合的に形成した。 Thereafter, a Si oxide film 6 having a thickness of 150 nm was formed on the polycrystalline Si films 105, 205, and 305. As shown in FIG. 9 (d), the laminated film composed of the polycrystalline Si film 5 and the 150 nm Si oxide film 6 is processed into a gate electrode by using a lithography technique and an RIE (Reactive Ion Etching) technique. Then, ion implantation was performed, and extension diffusion layer regions 107, 207, and 307 were formed in a self-aligned manner on the Si surfaces of the first region 100, the second region 200, and the third region 300 using the gate electrode as a mask. .
 更に、図9(e)に示すように、Si窒化膜とSi酸化膜とを順次堆積し、その後エッチバックすることによってゲート側壁8を形成した。この状態で再度イオン注入を行い、活性化アニールを経て、第一領域100、第二領域200、及び第三領域300のSi表面上に、おのおのソース・ドレイン拡散層109,209,309を形成した。 Further, as shown in FIG. 9E, a gate side wall 8 was formed by sequentially depositing a Si nitride film and a Si oxide film and then performing etch back. In this state, ion implantation is performed again, and activation annealing is performed to form source / drain diffusion layers 109, 209, and 309 on the Si surfaces of the first region 100, the second region 200, and the third region 300, respectively. .
 続いて、厚さ20nmの金属膜をスパッタにより全面に堆積し、サリサイド技術により、ゲート電極、ゲート側壁膜及びSTIをマスクとして、ソース・ドレイン拡散層のみに厚さ約40nmのシリサイド層10を形成した(図9(f))。このシリサイド層10は、コンタクト抵抗を最も低くすることができるNiモノシリサイド(NiSi)とした。Niシリサイドの代わりにCoシリサイドやTiシリサイドを用いてもよい。 Subsequently, a metal film having a thickness of 20 nm is deposited on the entire surface by sputtering, and a silicide layer 10 having a thickness of about 40 nm is formed only on the source / drain diffusion layer by using the salicide technique, using the gate electrode, the gate sidewall film, and the STI as a mask. (FIG. 9F). The silicide layer 10 is made of Ni monosilicide (NiSi) that can minimize the contact resistance. Co silicide or Ti silicide may be used instead of Ni silicide.
 更に、図10(g)に示すように、CVD(Chemical Vapor Deposition)法によってSi酸化膜の層間絶縁膜11を形成した。この層間絶縁膜11をCMP技術によって図10(h)に示すように平坦化し、更に、層間絶縁膜のエッチバックを行うことでゲート電極の多結晶Si膜-105,205,305を露出させた。 Further, as shown in FIG. 10G, an interlayer insulating film 11 of a Si oxide film was formed by a CVD (Chemical Vapor Deposition) method. The interlayer insulating film 11 is planarized by CMP technique as shown in FIG. 10H, and the interlayer insulating film is etched back to expose the polycrystalline Si films -105, 205, 305 of the gate electrode. .
 続いて、ゲート電極の多結晶Si膜105,205,305とのシリサイドを形成させるNi膜を堆積した。この工程でのNi膜厚は、多結晶SiとNiとが十分反応してシリサイド化したときに、ゲート絶縁膜に接している側の組成がNiSiとなるような膜厚を設定する。本例では、DCマグネトロンスパッタ法により室温でNiを25nm成膜した。その後、650℃かつ2分の熱処理により多結晶SiとNiとを十分に反応させて、結晶化NiSi電極を形成した。 Subsequently, a Ni film for forming silicide with the polycrystalline Si films 105, 205, and 305 of the gate electrode was deposited. The Ni film thickness in this step is set such that the composition on the side in contact with the gate insulating film becomes NiSi 2 when the polycrystalline Si and Ni are sufficiently reacted to be silicided. In this example, Ni was deposited to a thickness of 25 nm at room temperature by DC magnetron sputtering. Thereafter, polycrystalline Si and Ni were sufficiently reacted by heat treatment at 650 ° C. for 2 minutes to form a crystallized NiSi 2 electrode.
 このシリサイド化において、第一領域100の多結晶Si電極中の添加元素(B)は、図10(i)のように電極/絶縁膜界面に偏析する(偏析不純物113)。また、第二領域200の多結晶Si電極中の添加元素(As)も、図10(i)のように電極/絶縁膜界面に偏析する(偏析不純物213)。一方、第三領域300の多結晶Si電極では、ドーパントが添加されていないため、電極/絶縁膜界面にドーパントが偏析しない。最後に、前述の熱処理においてシリサイド化反応しなかった余剰のNi膜は、硫酸過酸化水素水溶液を用いてウェットエッチング除去した。その後通常の配線工程を行った。 In this silicidation, the additive element (B) in the polycrystalline Si electrode in the first region 100 is segregated at the electrode / insulating film interface as shown in FIG. 10 (i) (segregated impurities 113). Further, the additive element (As) in the polycrystalline Si electrode in the second region 200 is segregated at the electrode / insulating film interface as shown in FIG. 10 (i) (segregated impurities 213). On the other hand, since the dopant is not added to the polycrystalline Si electrode in the third region 300, the dopant does not segregate at the electrode / insulating film interface. Finally, the excess Ni film that did not undergo the silicidation reaction in the above heat treatment was removed by wet etching using a sulfuric acid hydrogen peroxide aqueous solution. Thereafter, a normal wiring process was performed.
 以上のような工程を経ることにより、図1に示すような第一領域100、第二領域200、及び第三領域300に応じて電極/絶縁膜界面に異なる添加元素が偏析したフルシリサイド電極をもつMOSFETを作製した。このようにして作製したMOSFETにおいて、NiSiフルシリサイド電極112,212,312の実効仕事関数はそれぞれ4.1eV,5.1eV,4.6eVであった。 Through the above steps, a full silicide electrode in which different additive elements segregate at the electrode / insulating film interface according to the first region 100, the second region 200, and the third region 300 as shown in FIG. A MOSFET having the same characteristics was produced. In the MOSFET manufactured as described above, the effective work functions of the NiSi 2 full silicide electrodes 112, 212, and 312 were 4.1 eV, 5.1 eV, and 4.6 eV, respectively.
 図11は、実効仕事関数が4.1eVに変調されているNiSiをゲート電極としたnMOSFETにおける、ドレイン電流のゲート電圧依存性を示したものである。チャネル濃度は2×1017cm-3であり、図6の実効仕事関数が4.1eVから予想されるVthは0.1Vである。図11より、NiSiを電極としたnMOSトランジスタのVthは、実効仕事関数から予想されたとおり0.1Vとなっている。更に、このトランジスタにおいて電子移動度は、多結晶Si/SiOの組み合わせによるトランジスタと同等の値が得られることを確認した。 FIG. 11 shows the gate voltage dependence of the drain current in an nMOSFET using NiSi 2 whose gate electrode is NiSi 2 whose effective work function is modulated to 4.1 eV. The channel concentration is 2 × 10 17 cm −3 , and Vth expected from the effective work function of FIG. 6 of 4.1 eV is 0.1V. From FIG. 11, Vth of the nMOS transistor using NiSi 2 as an electrode is 0.1 V as predicted from the effective work function. Furthermore, in this transistor, it was confirmed that the electron mobility was equivalent to that of the transistor using the combination of polycrystalline Si / SiO 2 .
 図12は、実効仕事関数が5.1eVに変調されているNiSiをゲート電極としたpMOSFETにおける、ドレイン電流のゲート電圧依存性を示したものである。チャネル濃度は2×1017cm-3であり、図6の実効仕事関数が5.1eVから予想されるVthは-0.1Vである。図12より、NiSiを電極としたpMOSトランジスタのVthは、実効仕事関数から予想されたとおり-0.1Vとなっている。更に、このトランジスタにおいて正孔移動度は、多結晶Si/SiOの組み合わせによるトランジスタと同等の値が得られることを確認した。 FIG. 12 shows the gate voltage dependence of the drain current in the pMOSFET using NiSi 2 whose effective work function is modulated to 5.1 eV as the gate electrode. The channel concentration is 2 × 10 17 cm −3 , and the Vth expected from the effective work function of FIG. 6 from 5.1 eV is −0.1V. From FIG. 12, the Vth of the pMOS transistor using NiSi 2 as an electrode is −0.1 V as predicted from the effective work function. Furthermore, in this transistor, it was confirmed that the hole mobility was equivalent to that of a transistor using a polycrystalline Si / SiO 2 combination.
 図13は、実効仕事関数が4.6eVであるノンドープNiSiをゲート電極としたnMOSFETにおける、ドレイン電流のゲート電圧依存性を示したものである。チャネル濃度は2×1017cm-3であり、図6の実効仕事関数から予想されるVthは0.6Vである。図13より、ノンドープNiSiを電極としたnMOSトランジスタのVthは、実効仕事関数から予想されたとおり-0.1Vとなっている。 FIG. 13 shows the gate voltage dependence of the drain current in an nMOSFET using non-doped NiSi 2 having an effective work function of 4.6 eV as a gate electrode. The channel concentration is 2 × 10 17 cm −3 , and Vth predicted from the effective work function of FIG. 6 is 0.6V. From FIG. 13, Vth of the nMOS transistor using non-doped NiSi 2 as an electrode is −0.1 V as predicted from the effective work function.
 図14は、このトランジスタの電子移動度の実効電界依存性である。比較のため、ゲート電極にnドープ多結晶Si電極を用い、Vth=0.6Vを得るためにチャネル不純物濃度を2×1018cm-3に増加させたトランジスタの電子移動度も示した。図14より、nドープ多結晶Si電極を用いた場合に比べてノンドープNiSiをゲート電極に用いた場合のほうが、移動度の絶対値自身が大きくなること及びゲート電圧Vg=1Vに対応する実効電界依存性が小さくなることから、電子移動度が12%程度増加することを確認した。 FIG. 14 shows the effective electric field dependence of the electron mobility of this transistor. For comparison, the electron mobility of a transistor in which an n-doped polycrystalline Si electrode is used as the gate electrode and the channel impurity concentration is increased to 2 × 10 18 cm −3 in order to obtain Vth = 0.6 V is also shown. FIG. 14 shows that the absolute value of the mobility itself is larger and the effective corresponding to the gate voltage Vg = 1V when non-doped NiSi 2 is used for the gate electrode than when the n-doped polycrystalline Si electrode is used. It was confirmed that the electron mobility increased by about 12% because the electric field dependency was reduced.
 図15は、ノンドープNiSiを電極としたnMOSトランジスタのしきい値ばらつきのチャネル不純物濃度(Nch)依存性である。図14で比較したノンドープNiSi電極(Nch=1×1017cm-3)及びnドープ多結晶Si電極(Nch=2×1018cm-3)のしきい値ばらつきは、各々2mV及び4mVであった。これは、Nchを低減したために、チャネル中の不純物濃度の揺らぎによるしきい値ばらつきが抑制できたためである。 FIG. 15 shows the channel impurity concentration (Nch) dependence of the threshold variation of an nMOS transistor using non-doped NiSi 2 as an electrode. The threshold variations of the non-doped NiSi 2 electrode (Nch = 1 × 10 17 cm −3 ) and the n-doped polycrystalline Si electrode (Nch = 2 × 10 18 cm −3 ) compared in FIG. 14 are 2 mV and 4 mV, respectively. there were. This is because variation in threshold due to fluctuations in the impurity concentration in the channel can be suppressed because Nch is reduced.
 なお、pMOS用Niフルシリサイド電極にB以外のp型ドーパント不純物(Al、In、Ga、Tlなど)を添加した場合、及びnMOS用Niフルシリサイド電極にAs以外のn型ドーパント不純物(N、P、Sb、Biなど)を添加した場合であっても、同じ効果が得られた。 In addition, when p-type dopant impurities (Al, In, Ga, Tl, etc.) other than B are added to the Ni full silicide electrode for pMOS, and n-type dopant impurities (N, P other than As) are added to the Ni full silicide electrode for nMOS. , Sb, Bi, etc.) were added, and the same effect was obtained.
 CMOSデバイスを作製する場合、工程の簡便化によるコスト低減のため一回のシリサイド化でnMOS及びpMOSトランジスタのNiフルシリサイド電極を形成できることが好ましいが、不純物を添加した結晶化NiSiをゲート電極に用いればそれが達成される。 When manufacturing a CMOS device, it is preferable that Ni full silicide electrodes of nMOS and pMOS transistors can be formed by a single silicidation for cost reduction by simplification of the process, but crystallized NiSi 2 doped with impurities is used as a gate electrode. This is achieved if used.
 また、本例の製造方法によれば、ゲート絶縁膜上に多結晶Si電極を形成した後に、再度これを除去する工程がないために、ゲート絶縁膜表面がウェットエチング液や有機溶剤に数度にわたり晒されることがない。このため、信頼性に優れたメタルゲート/ゲート絶縁膜CMOSトランジスタを作製することが可能である。また、本例の製造方法によれば、不純物添加をPR工程及びイオン注入工程によって簡便に行うことができるため、簡便に所望のデバイスを得ることができる。 Further, according to the manufacturing method of this example, after forming the polycrystalline Si electrode on the gate insulating film, there is no step of removing it again, so that the surface of the gate insulating film is in a wet etching solution or an organic solvent. It is never exposed. Therefore, it is possible to manufacture a metal gate / gate insulating film CMOS transistor having excellent reliability. Moreover, according to the manufacturing method of this example, since the impurity addition can be easily performed by the PR process and the ion implantation process, a desired device can be easily obtained.
 以上より、本例で示した実効的にNiSiの組成を持つ結晶化したNiフルシリサイド電極に、上記の不純物を添加したゲート電極とSiONゲート絶縁膜とを組み合わせることで、優れたトランジスタ特性を得ることができる。 As described above, excellent transistor characteristics can be obtained by combining the above-described impurity-added gate electrode and the SiON gate insulating film with the crystallized Ni full silicide electrode having an effective NiSi 2 composition shown in this example. Obtainable.
 図16(a)~図18(i)は本発明の第一実施形態に係るMOSFETの製造工程の第二例を示した断面図である。本例も、層間絶縁膜形成後にこれを研磨することにより平坦化すると同時に、ゲート電極上部を露出させることが可能なCMP技術を用いてMOSFETを作製する。また、本例に係るMOSFETも、第一領域100上に作製されるpMOSFETと、第二領域200上に作製されるnMOSFETと、第三領域300上に作製されるnMOSFET(又はpMOSFET)とからなる。 16 (a) to 18 (i) are cross-sectional views showing a second example of the MOSFET manufacturing process according to the first embodiment of the present invention. In this example as well, the MOSFET is fabricated by using a CMP technique that can be planarized by polishing the interlayer insulating film after it is formed and at the same time expose the upper portion of the gate electrode. In addition, the MOSFET according to this example also includes a pMOSFET manufactured on the first region 100, an nMOSFET manufactured on the second region 200, and an nMOSFET (or pMOSFET) manufactured on the third region 300. .
 まず、第一領域100、第二領域200、及び第三領域300のSi基板1の表面領域に、STI技術を用いて素子分離領域2を形成した。続いて、素子分離されたSi基板表面に犠牲絶縁膜3を形成した。犠牲絶縁膜3としては例えば厚さ10nm程度のSi熱酸化膜を用いることができる。 First, the element isolation region 2 was formed on the surface region of the Si substrate 1 in the first region 100, the second region 200, and the third region 300 using the STI technique. Subsequently, a sacrificial insulating film 3 was formed on the surface of the Si substrate from which the elements were separated. As the sacrificial insulating film 3, for example, a Si thermal oxide film having a thickness of about 10 nm can be used.
 続いて、図16(a)に示すように犠牲絶縁膜3を通して、第一領域100、第二領域200、及び第三領域300のSi基板1の表面領域に対して、チャネル不純物として各々n型、p型、及びp(又はn)型のドーパント元素をイオン注入法で添加し、熱処理によって前記ドーパントを電気的に活性化させた。 Subsequently, as shown in FIG. 16A, n-type channel impurities are respectively formed on the surface regions of the Si substrate 1 in the first region 100, the second region 200, and the third region 300 through the sacrificial insulating film 3. , P-type, and p (or n) -type dopant elements were added by ion implantation, and the dopant was electrically activated by heat treatment.
 続いて、犠牲絶縁膜3を除去し、ゲート絶縁膜4を形成した。ゲート絶縁膜4にはSiONを用いた。そして、ゲート絶縁膜4上に、厚さ80nm程度の多結晶Si膜5を形成した。 Subsequently, the sacrificial insulating film 3 was removed, and a gate insulating film 4 was formed. For the gate insulating film 4, SiON was used. Then, a polycrystalline Si film 5 having a thickness of about 80 nm was formed on the gate insulating film 4.
 その後、図16(b)に示すように、多結晶Si膜5上に厚さ150nmのSi酸化膜6を形成した。この多結晶Si膜5と150nmのSi酸化膜6とからなる積層膜を、図16(c)に示すように、リソグラフィー技術及びRIE技術を用いてゲート電極に加工し、引き続いてイオン注入を行い、第一領域100、第二領域200、及び第三領域300のSi表面上に、おのおのエクステンション拡散層領域107,207,307を、ゲート電極をマスクとして自己整合的に形成した。 Thereafter, as shown in FIG. 16B, a 150 nm thick Si oxide film 6 was formed on the polycrystalline Si film 5. As shown in FIG. 16C, the laminated film composed of the polycrystalline Si film 5 and the 150 nm Si oxide film 6 is processed into a gate electrode by using a lithography technique and an RIE technique, followed by ion implantation. On the Si surfaces of the first region 100, the second region 200, and the third region 300, the extension diffusion layer regions 107, 207, and 307 were formed in a self-aligned manner using the gate electrode as a mask.
 更に、図17(d)に示すように、Si窒化膜とSi酸化膜とを順次堆積し、その後エッチバックすることによってゲート側壁8を形成した。この状態で再度イオン注入を行い、活性化アニールを経て、第一領域100、第二領域200、及び第三領域300のSi表面上に、おのおのソース・ドレイン拡散層109,209,309を形成した。 Furthermore, as shown in FIG. 17D, a gate side wall 8 was formed by sequentially depositing a Si nitride film and a Si oxide film and then performing etch back. In this state, ion implantation is performed again, and activation annealing is performed to form source / drain diffusion layers 109, 209, and 309 on the Si surfaces of the first region 100, the second region 200, and the third region 300, respectively. .
 続いて、厚さ20nmの金属膜をスパッタにより全面に堆積し、サリサイド技術により、ゲート電極、ゲート側壁膜及びSTIをマスクとして、ソース・ドレイン拡散層のみに厚さ約40nmのシリサイド層10を形成した(図17(e))。このシリサイド層10は、コンタクト抵抗を最も低くすることができるNiモノシリサイド(NiSi)とした。Niシリサイドの代わりにCoシリサイドやTiシリサイドを用いてもよい。 Subsequently, a metal film having a thickness of 20 nm is deposited on the entire surface by sputtering, and a silicide layer 10 having a thickness of about 40 nm is formed only on the source / drain diffusion layer by using the salicide technique, using the gate electrode, the gate sidewall film, and the STI as a mask. (FIG. 17 (e)). The silicide layer 10 is made of Ni monosilicide (NiSi) that can minimize the contact resistance. Co silicide or Ti silicide may be used instead of Ni silicide.
 更に、図17(f)に示すように、CVD法によってSi酸化膜の層間絶縁膜11を形成した。この層間絶縁膜11をCMP技術によって図18(g)に示すように平坦化し、更に、層間絶縁膜のエッチバックを行うことでゲート電極の多結晶Si膜105,205,305を露出させた。 Furthermore, as shown in FIG. 17F, an interlayer insulating film 11 made of Si oxide was formed by a CVD method. The interlayer insulating film 11 was planarized by CMP technique as shown in FIG. 18G, and the interlayer insulating film was etched back to expose the polycrystalline Si films 105, 205, and 305 as gate electrodes.
 続いて、ゲート電極の多結晶Si膜5とのシリサイドを形成させるNi膜を堆積した。この工程でのNi膜厚は、多結晶SiとNiとが十分反応してシリサイド化したときに、ゲート絶縁膜に接している側の組成がNiSiとなるような膜厚を設定する。本例では、DCマグネトロンスパッタ法により室温でNiを25nm成膜した。 Subsequently, a Ni film for forming silicide with the polycrystalline Si film 5 of the gate electrode was deposited. The Ni film thickness in this step is set such that the composition on the side in contact with the gate insulating film becomes NiSi 2 when the polycrystalline Si and Ni are sufficiently reacted to be silicided. In this example, Ni was deposited to a thickness of 25 nm at room temperature by DC magnetron sputtering.
 その後、図18(h)に示すように、650℃かつ2分の熱処理により多結晶SiとNiとを十分に反応させて結晶化NiSi電極12を形成し、前述の熱処理においてシリサイド化反応しなかった余剰のNi膜を、硫酸過酸化水素水溶液を用いてウェットエッチング除去した。この結晶化NiSi電極12に対して、図18(h)に示すように、第一領域100及び第二領域200上の多結晶Siに対しレジストを用いた通常のPRプロセスとイオン注入とを組み合わせることにより、おのおの異なる不純物元素をイオン注入した。例えば、第一領域100にはBを注入し、第二領域200にはAsを注入した。各々の注入エネルギー及びドーズ量は、B注入の場合2keV及び6×1015cm-2、As注入の場合5keV及び5×1015cm-2であった。 Then, as shown in FIG. 18 (h), polycrystalline Si and Ni are sufficiently reacted by heat treatment at 650 ° C. for 2 minutes to form crystallized NiSi 2 electrode 12, and silicidation reaction is caused in the heat treatment described above. The excess Ni film that did not exist was removed by wet etching using a hydrogen peroxide aqueous solution. For this crystallized NiSi 2 electrode 12, as shown in FIG. 18 (h), a normal PR process using a resist and ion implantation for polycrystalline Si on the first region 100 and the second region 200 are performed. By combining, different impurity elements were ion-implanted. For example, B is implanted into the first region 100 and As is implanted into the second region 200. The implantation energy and dose amount were 2 keV and 6 × 10 15 cm −2 for B implantation, and 5 keV and 5 × 10 15 cm −2 for As implantation.
 このイオン注入後、例えば500℃かつ30分程度のアニールを行うことによって、第一領域100の結晶化NiSi電極12中の添加元素(B)は、図18(i)のように電極/絶縁膜界面に偏析する(偏析不純物113)。また、第二領域200の結晶化NiSi電極12の添加元素(As)も、図18(i)のように電極/絶縁膜界面に偏析する(偏析不純物213)。一方、第三領域300の多結晶Si電極では、ドーパントは添加されていないため、電極/絶縁膜界面にドーパントは偏析しない。その後、通常の配線工程を行った。 After this ion implantation, for example, annealing is performed at 500 ° C. for about 30 minutes, so that the additive element (B) in the crystallized NiSi 2 electrode 12 in the first region 100 becomes an electrode / insulator as shown in FIG. Segregates at the film interface (segregated impurities 113). Also, the additive element (As) of the crystallized NiSi 2 electrode 12 in the second region 200 is segregated at the electrode / insulating film interface as shown in FIG. 18 (i) (segregated impurities 213). On the other hand, since the dopant is not added to the polycrystalline Si electrode in the third region 300, the dopant does not segregate at the electrode / insulating film interface. Thereafter, a normal wiring process was performed.
 以上のような工程を経ることにより、図1に示すような第一領域100、第二領域200、及び第三領域300に応じて電極/絶縁膜界面に異なる添加元素が偏析したフルシリサイド電極をもつMOSFETを形成した。本例の場合においても、第一例で示した優れたトランジスタ特性を得ることができた。 Through the above steps, a full silicide electrode in which different additive elements segregate at the electrode / insulating film interface according to the first region 100, the second region 200, and the third region 300 as shown in FIG. A MOSFET having the same structure was formed. Also in this example, the excellent transistor characteristics shown in the first example could be obtained.
 また、本例の製造方法によれば、ゲート絶縁膜上に多結晶Si電極を形成した後に、再度これを除去する工程がないために、ゲート絶縁膜表面がウェットエチング液や有機溶剤に数度にわたり晒されることがない。このため、信頼性に優れたメタルゲート/ゲート絶縁膜CMOSトランジスタを作製することが可能である。また、本例の製造方法によれば、不純物添加をPR工程及びイオン注入工程によって簡便に行うことができるため、簡便に所望のデバイスを得ることができる。 Further, according to the manufacturing method of this example, after forming the polycrystalline Si electrode on the gate insulating film, there is no step of removing it again, so that the surface of the gate insulating film is in a wet etching solution or an organic solvent. It is never exposed. Therefore, it is possible to manufacture a metal gate / gate insulating film CMOS transistor having excellent reliability. Moreover, according to the manufacturing method of this example, since the impurity addition can be easily performed by the PR process and the ion implantation process, a desired device can be easily obtained.
 また、一般に、ドープされた多結晶Si電極をエッチングすると、ドーパントの種類によってエッチング速度が違うためゲート寸法が異なったり、ゲート端部のラフネスがノンドープの場合に比べて大きくなったりするので、特性ばらつきを引き起こす。本例の製造方法によれば、ゲート多結晶Siのエッチング時にはゲート多結晶Siをノンドープにしておけるため、上記のドーピングによるゲート寸法・形状に関わる問題を回避できる。 In general, when a doped polycrystalline Si electrode is etched, the etching rate varies depending on the type of dopant, and therefore the gate size is different or the roughness of the gate edge is larger than in the case of non-doping. cause. According to the manufacturing method of this example, since the gate polycrystalline Si can be made non-doped during the etching of the gate polycrystalline Si, the problems related to the gate size and shape due to the doping described above can be avoided.
 図2に示す第二実施形態の半導体装置は、半導体基板としてのSi基板1上に、ゲート絶縁膜4とゲート電極としてのp型ドープ多結晶Si膜105、n型ドープ多結晶Si膜205及びノンドープフルシリサイド電極312とが設けられた複数のトランジスタ構造を有する。そして、ノンドープフルシリサイド電極312は、ゲート絶縁膜4に接する部分が金属シリサイド層になっている。複数のトランジスタ構造のそれぞれは、第一領域100、第二領域200及び第三領域300のいずれかに属する。第一領域100は、p型ドープ多結晶Si膜105とゲート絶縁膜4との界面に、シリコン中でp型となる不純物元素を含む。第二領域200は、n型ドープ多結晶Si膜205とゲート絶縁膜4との界面に、シリコン中でn型となる不純物元素を含む。第三領域300は、ノンドープフルシリサイド電極312とゲート絶縁膜4との界面にいずれの不純物元素も実質的に含まない。ここでいう「いずれの不純物元素も実質的に含まない」とは、両方の不純物元素を等量含むことにより、実質的に真性になっている場合も含むものとする。 The semiconductor device of the second embodiment shown in FIG. 2 includes a gate insulating film 4 and a p-type doped polycrystalline Si film 105, an n-type doped polycrystalline Si film 205 as a gate electrode, and a Si substrate 1 as a semiconductor substrate. It has a plurality of transistor structures provided with non-doped full silicide electrodes 312. The non-doped full silicide electrode 312 is a metal silicide layer at a portion in contact with the gate insulating film 4. Each of the plurality of transistor structures belongs to one of the first region 100, the second region 200, and the third region 300. First region 100 includes an impurity element which becomes p-type in silicon at the interface between p-type doped polycrystalline Si film 105 and gate insulating film 4. Second region 200 includes an impurity element that becomes n-type in silicon at the interface between n-type doped polycrystalline Si film 205 and gate insulating film 4. The third region 300 does not substantially contain any impurity element at the interface between the non-doped full silicide electrode 312 and the gate insulating film 4. The phrase “substantially free of any impurity element” as used herein includes a case in which both of the impurity elements are contained in an equal amount and are substantially intrinsic.
 図19(a)~図21(h)は、本発明に係る第二実施形態に係るMOSFETの製造工程を示した断面図である。本実施形態は、層間絶縁膜形成後にこれを研磨することにより平坦化すると同時に、ゲート電極上部を露出させることが可能なCMP技術を用いてMOSFETを作製する。また、本実施形態に係るMOSFETは、第一領域100上に作製されるpMOSFETと、第二領域200上に作製されるnMOSFETと、第三領域300上に作製されるnMOSFET(又はpMOSFET)とからなる。 FIG. 19A to FIG. 21H are cross-sectional views showing the manufacturing process of the MOSFET according to the second embodiment of the present invention. In the present embodiment, after forming an interlayer insulating film, the MOSFET is planarized by polishing, and at the same time, a MOSFET is manufactured by using a CMP technique capable of exposing the upper portion of the gate electrode. The MOSFET according to the present embodiment includes a pMOSFET manufactured on the first region 100, an nMOSFET manufactured on the second region 200, and an nMOSFET (or pMOSFET) manufactured on the third region 300. Become.
 まず、第一領域100、第二領域200、及び第三領域300のSi基板1の表面領域に、STI技術を用いて素子分離領域2を形成した。続いて、素子分離されたSi基板表面に犠牲絶縁膜3を形成した。犠牲絶縁膜3としては例えば厚さ10nm程度のSi熱酸化膜を用いることができる。 First, the element isolation region 2 was formed on the surface region of the Si substrate 1 in the first region 100, the second region 200, and the third region 300 using the STI technique. Subsequently, a sacrificial insulating film 3 was formed on the surface of the Si substrate from which the elements were separated. As the sacrificial insulating film 3, for example, a Si thermal oxide film having a thickness of about 10 nm can be used.
 続いて、図19(a)に示すように、犠牲絶縁膜3を通して、第一領域100、第二領域200、及び第三領域300のSi基板1の表面領域に対して、チャネル不純物として各々n型、p型、及びp(又はn)型のドーパント元素をイオン注入法で添加し、熱処理によって前記ドーパントを電気的に活性化させた。 Subsequently, as shown in FIG. 19A, each of the first region 100, the second region 200, and the third region 300 through the sacrificial insulating film 3 is subjected to n as channel impurities with respect to the surface region of the Si substrate 1. Type, p-type, and p (or n) -type dopant elements were added by ion implantation, and the dopant was electrically activated by heat treatment.
 続いて、犠牲絶縁膜3を除去し、ゲート絶縁膜4を形成した。ゲート絶縁膜4には、SiONを用いた。そして、ゲート絶縁膜4上に厚さ80nm程度の多結晶Si膜5を形成した。 Subsequently, the sacrificial insulating film 3 was removed, and a gate insulating film 4 was formed. For the gate insulating film 4, SiON was used. A polycrystalline Si film 5 having a thickness of about 80 nm was formed on the gate insulating film 4.
 その後、図19(b)に示すように、第一領域100及び第二領域200上の多結晶Siに対しレジストを用いた通常のPRプロセスとイオン注入を組み合わせることにより、おのおの異なる不純物元素をイオン注入した。例えば、第一領域100にはBを、第二領域200にはPを注入した。各々の注入エネルギー及びドーズ量は、B注入の場合2keV及び6×1015cm-2、As注入の場合5keV及び5×1015cm-2であった。 Thereafter, as shown in FIG. 19B, by combining a normal PR process using a resist with respect to polycrystalline Si on the first region 100 and the second region 200 and ion implantation, each different impurity element is ionized. Injected. For example, B is implanted into the first region 100 and P is implanted into the second region 200. The implantation energy and dose amount were 2 keV and 6 × 10 15 cm −2 for B implantation, and 5 keV and 5 × 10 15 cm −2 for As implantation.
 その結果、図19(c)に示すように、第一領域100、第二領域200、及び第三領域300上の多結晶Si膜5は各々、p型ドープ多結晶Si膜105、n型ドープ多結晶Si膜205、及びノンドープ多結晶Si膜305となった。その後、多結晶Si膜105,205,305上に、厚さ150nmのSi酸化膜6を形成した。この多結晶Si膜5と150nmのSi酸化膜6とからなる積層膜を、図20(d)に示すように、リソグラフィー技術及びRIE技術を用いてゲート電極に加工し、引き続いてイオン注入を行い、第一領域100、第二領域200、及び第三領域300のSi表面上に、おのおのエクステンション拡散層領域107,207,307を、ゲート電極をマスクとして自己整合的に形成した。 As a result, as shown in FIG. 19 (c), the polycrystalline Si film 5 on the first region 100, the second region 200, and the third region 300 is respectively a p-type doped polycrystalline Si film 105, an n-type doped. A polycrystalline Si film 205 and a non-doped polycrystalline Si film 305 were obtained. Thereafter, a Si oxide film 6 having a thickness of 150 nm was formed on the polycrystalline Si films 105, 205, and 305. As shown in FIG. 20 (d), the laminated film composed of the polycrystalline Si film 5 and the 150 nm Si oxide film 6 is processed into a gate electrode using a lithography technique and an RIE technique, and then ion implantation is performed. On the Si surfaces of the first region 100, the second region 200, and the third region 300, the extension diffusion layer regions 107, 207, and 307 were formed in a self-aligned manner using the gate electrode as a mask.
 更に、図20(e)に示すように、Si窒化膜とSi酸化膜とを順次堆積し、その後エッチバックすることによってゲート側壁8を形成した。この状態で再度イオン注入を行い、活性化アニールを経て、第一領域100、第二領域200、及び第三領域300のSi表面上に、おのおのソース・ドレイン拡散層109,209,309を形成した。 Further, as shown in FIG. 20 (e), a Si side wall 8 was formed by sequentially depositing a Si nitride film and a Si oxide film and then etching back. In this state, ion implantation is performed again, and activation annealing is performed to form source / drain diffusion layers 109, 209, and 309 on the Si surfaces of the first region 100, the second region 200, and the third region 300, respectively. .
 続いて、厚さ20nmの金属膜をスパッタにより全面に堆積し、サリサイド技術により、ゲート電極、ゲート側壁膜及びSTIをマスクとして、ソース・ドレイン拡散層のみに厚さ約40nmのシリサイド層10を形成した(図20(f))。このシリサイド層10は、コンタクト抵抗を最も低くすることができるNiモノシリサイド(NiSi)とした。Niシリサイドの代わりにCoシリサイドやTiシリサイドを用いてもよい。 Subsequently, a metal film having a thickness of 20 nm is deposited on the entire surface by sputtering, and a silicide layer 10 having a thickness of about 40 nm is formed only on the source / drain diffusion layer by using the salicide technique, using the gate electrode, the gate sidewall film, and the STI as a mask. (FIG. 20 (f)). The silicide layer 10 is made of Ni monosilicide (NiSi) that can minimize the contact resistance. Co silicide or Ti silicide may be used instead of Ni silicide.
 更に、図21(g)に示すように、CVD法によってSi酸化膜の層間絶縁膜11を形成した。この層間絶縁膜11をCMP技術によって平坦化し、更に、第三領域300上の層間絶縁膜を、レジストマスクを用いて選択的にエッチバックを行うことで、第三領域300上のゲート電極の多結晶Si膜305を露出させた。 Further, as shown in FIG. 21 (g), an interlayer insulating film 11 of Si oxide film was formed by the CVD method. The interlayer insulating film 11 is planarized by a CMP technique, and the interlayer insulating film on the third region 300 is selectively etched back using a resist mask, so that the number of gate electrodes on the third region 300 is increased. The crystalline Si film 305 was exposed.
 続いて、ゲート電極の多結晶Si膜305とのシリサイドを形成させるNi膜を堆積した。この工程でのNi膜厚は、多結晶SiとNiとが十分反応してシリサイド化したときに、ゲート絶縁膜に接している側の組成がNiSiとなるような膜厚を設定する。本実施形態では、DCマグネトロンスパッタ法により室温でNiを25nm成膜した。その後、650℃かつ2分の熱処理により、多結晶SiとNiとを十分に反応させて結晶化NiSi電極を形成した。最後に、図21(h)に示すように、前述の熱処理においてシリサイド化反応しなかった余剰のNi膜を、硫酸過酸化水素水溶液を用いてウェットエッチング除去した。 Subsequently, a Ni film for forming silicide with the polycrystalline Si film 305 of the gate electrode was deposited. The Ni film thickness in this step is set such that the composition on the side in contact with the gate insulating film becomes NiSi 2 when the polycrystalline Si and Ni are sufficiently reacted to be silicided. In this embodiment, a film of Ni having a thickness of 25 nm is formed at room temperature by a DC magnetron sputtering method. Thereafter, polycrystalline Si and Ni were sufficiently reacted by heat treatment at 650 ° C. for 2 minutes to form a crystallized NiSi 2 electrode. Finally, as shown in FIG. 21H, the surplus Ni film that did not undergo the silicidation reaction in the above-described heat treatment was removed by wet etching using a sulfuric acid hydrogen peroxide solution.
 次いで、再び図21(i)に示すように、CVD法によってSi酸化膜の層間絶縁膜11を形成した。その後通常の配線工程を行った。 Next, as shown in FIG. 21 (i) again, an interlayer insulating film 11 of a Si oxide film was formed by the CVD method. Thereafter, a normal wiring process was performed.
 以上のような工程を経ることにより、図2に示すような第一領域100、第二領域200、及び第三領域300に応じてゲート電極/ゲート絶縁膜界面に各々p型ドープ多結晶Si膜105、n型ドープ多結晶Si膜205、及びノンドープNiSi312が形成されたゲート電極をもつMOSFETを形成した。 Through the steps as described above, a p-type doped polycrystalline Si film is formed at the gate electrode / gate insulating film interface according to the first region 100, the second region 200, and the third region 300 as shown in FIG. 105, a MOSFET having a gate electrode formed with an n-type doped polycrystalline Si film 205 and non-doped NiSi 2 312 was formed.
 このようにして作製したMOSFETにおいて、NiSiフルシリサイド電極312の実効仕事関数は4.6eVであった。実効仕事関数が4.6eVであるノンドープNiSiフルシリサイド電極312をゲート電極としたnMOSFETにおいて、ドレイン電流のゲート電圧依存性は図13に示すものと同等であり、Vth=0.6Vが得られている。このトランジスタの電子移動度の実効電界依存性は、図14に示すものと同等であり、ゲート電極にnドープ多結晶Si電極を用いVth=0.6Vを得るためにチャネル不純物濃度を2×1018cm-3に増加させたトランジスタの電子移動度と比較すると、ゲート電圧Vg=1Vのとき、電子移動度が12%程度増加することを確認した。 In the MOSFET manufactured in this manner, the effective work function of the NiSi 2 full silicide electrode 312 was 4.6 eV. In an nMOSFET using a non-doped NiSi 2 full silicide electrode 312 having an effective work function of 4.6 eV as a gate electrode, the gate voltage dependency of the drain current is equivalent to that shown in FIG. 13, and Vth = 0.6V is obtained. ing. The effective electric field dependence of the electron mobility of this transistor is equivalent to that shown in FIG. 14, and an n-doped polycrystalline Si electrode is used as the gate electrode, and the channel impurity concentration is set to 2 × 10 in order to obtain Vth = 0.6V. When compared with the electron mobility of the transistor increased to 18 cm −3 , it was confirmed that the electron mobility increased by about 12% when the gate voltage Vg = 1V.
 ノンドープNiSiを電極としたnMOSトランジスタのしきい値ばらつきは、各々2mVであった。この値は、ゲート電極にnドープ多結晶Si電極を用いVth=0.6Vを得るためにチャネル不純物濃度を2×1018cm-3に増加させたトランジスタのしきい値ばらつき(4mV)の半分になっている。これは、Nchを低減したためにチャネル中の不純物濃度の揺らぎによるしきい値ばらつきが抑制できたためである。 The threshold variation of the nMOS transistor using non-doped NiSi 2 as an electrode was 2 mV each. This value is half the threshold variation (4 mV) of a transistor in which an n-doped polycrystalline Si electrode is used as the gate electrode and the channel impurity concentration is increased to 2 × 10 18 cm −3 in order to obtain Vth = 0.6V. It has become. This is because the threshold value variation due to the fluctuation of the impurity concentration in the channel can be suppressed because Nch is reduced.
 なお、pMOS用Niフルシリサイド電極にB以外のp型ドーパント不純物(Al、In、Ga、Tlなど)を添加した場合、及びnMOS用Niフルシリサイド電極にAs以外のn型ドーパント不純物(N、P、Sb、Biなど)を添加した場合であっても、同じ効果が得られた。 In addition, when p-type dopant impurities (Al, In, Ga, Tl, etc.) other than B are added to the Ni full silicide electrode for pMOS, and n-type dopant impurities (N, P other than As) are added to the Ni full silicide electrode for nMOS. , Sb, Bi, etc.) were added, and the same effect was obtained.
 CMOSデバイスを作製する場合、工程の簡便化によるコスト低減のため一回のシリサイド化でnMOSトランジスタ及びpMOSトランジスタのNiフルシリサイド電極を形成できることが好ましいが、不純物を添加した結晶化NiSiをゲート電極に用いればそれが達成される。 When manufacturing a CMOS device, it is preferable that the Ni full silicide electrode of the nMOS transistor and the pMOS transistor can be formed by a single silicidation in order to reduce the cost by simplifying the process, but the crystallized NiSi 2 doped with an impurity is used as the gate electrode. This is achieved if used for.
 以上より本実施形態で示した構成をとれば、低しきい値を持つnMOSトランジスタ及びpMOSトランジスタ並びに高しきい値を持つMOSトランジスタを1チップ上に作製する際、基板中の不純物濃度を一定として低いしきい値をドーパントが添加された多結晶Si電極で実現し、高いしきい値をSiミッドギャップの仕事関数を有するシリサイド電極で実現する。この結果、特に高しきい値を持つトランジスタにおいて、従来に比べチャネル中の不純物濃度が低減できる。また、同時にメタルゲート使用によってゲート空乏化抑制も実現できる。この結果、移動度の向上及びしきい値ばらつきの抑制を実現でき、トランジスタの高性能化が図れる。 As described above, when the configuration shown in the present embodiment is employed, when an nMOS transistor and a pMOS transistor having a low threshold and a MOS transistor having a high threshold are fabricated on one chip, the impurity concentration in the substrate is kept constant. A low threshold is realized with a polycrystalline Si electrode doped with a dopant, and a high threshold is realized with a silicide electrode having a Si midgap work function. As a result, the impurity concentration in the channel can be reduced as compared with the conventional case, particularly in a transistor having a high threshold value. At the same time, suppression of gate depletion can be realized by using a metal gate. As a result, improvement in mobility and suppression of threshold variation can be realized, and high performance of the transistor can be achieved.
 また、本実施形態の製造方法によれば、ゲート絶縁膜上に多結晶Si電極を形成した後に、再度これを除去する工程がないために、ゲート絶縁膜表面がウェットエチング液や有機溶剤に数度にわたり晒されることがない。このため、信頼性に優れたメタルゲート/ゲート絶縁膜CMOSトランジスタを作製することが可能である。 In addition, according to the manufacturing method of the present embodiment, after forming the polycrystalline Si electrode on the gate insulating film, there is no step of removing it again, so that the surface of the gate insulating film becomes wet etching solution or an organic solvent. It is not exposed for several degrees. Therefore, it is possible to manufacture a metal gate / gate insulating film CMOS transistor having excellent reliability.
 また、本実施形態の製造方法によれば、最も特性ばらつきを抑制したい高しきい値を持つMOSトランジスタのゲート多結晶Siを、ノンドープにしておける。一般に、ドープされた多結晶Si電極をエッチングすると、ゲート端部のラフネスがノンドープの場合に比べて大きくなるので、特性ばらつきを引き起こす。したがって、本実施形態によれば、ドーピングによるゲート形状に関わる問題を回避できるため、特性ばらつきを抑制することができる。 In addition, according to the manufacturing method of the present embodiment, the gate polycrystalline Si of the MOS transistor having a high threshold value that most suppresses the characteristic variation can be made non-doped. In general, when a doped polycrystalline Si electrode is etched, the roughness of the gate end becomes larger than that in the case of non-doping, which causes variation in characteristics. Therefore, according to the present embodiment, problems related to the gate shape due to doping can be avoided, so that variation in characteristics can be suppressed.
 以上、本発明の実施形態を説明したが、本発明は上記各実施形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲内において、材料及び構造を選択して実施することが可能である。例えば、Si基板の代わりに、GaAs基板、Ge基板、SiGe基板、SiC基板、SOI(Silicon On Insulator)基板などを用いてもよい。 As mentioned above, although embodiment of this invention was described, this invention is not limited to said each embodiment, In the range which does not deviate from the meaning of this invention, it is possible to select and implement a material and a structure. It is. For example, a GaAs substrate, Ge substrate, SiGe substrate, SiC substrate, SOI (Silicon On On Insulator) substrate, or the like may be used instead of the Si substrate.
 例えば、ゲートリーク電流を低減したい場合には、絶縁膜としてHfSiONなどのいわゆる高誘電率ゲート絶縁膜を用いることもできる。この場合、Si酸化膜又はSi酸窒化膜を用いた場合に比べ、しきい値変化は減少する。しかし、例えば図22に示すように、ゲート電極と接する部分に、Si酸化膜、Si酸窒化膜層又はSi窒化膜層を挿入することにより、実効仕事関数を小さくすることができ、その結果nMOSFETにおいて低いしきい値を実現できることを確認した。図22に示す第三実施形態では、HfSiONを最表面に持つゲート絶縁膜21とSiO又はSiONキャップ膜22との積層構造になっている。 For example, when it is desired to reduce the gate leakage current, a so-called high dielectric constant gate insulating film such as HfSiON can be used as the insulating film. In this case, the threshold change is reduced as compared with the case where the Si oxide film or the Si oxynitride film is used. However, as shown in FIG. 22, for example, an effective work function can be reduced by inserting a Si oxide film, a Si oxynitride film layer, or a Si nitride film layer in a portion in contact with the gate electrode. It was confirmed that a low threshold can be realized in The third embodiment shown in FIG. 22 has a laminated structure of a gate insulating film 21 having HfSiON on the outermost surface and a SiO 2 or SiON cap film 22.
 以上、上記各実施形態を参照して本発明を説明したが、本発明は上記各実施形態に限定されるものではない。本発明の構成や詳細については、当業者が理解し得るさまざまな変更を加えることができる。また、本発明には、上記各実施形態の構成の一部又は全部を相互に適宜組み合わせたものも含まれる。 As described above, the present invention has been described with reference to each of the above embodiments, but the present invention is not limited to each of the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention. Further, the present invention includes a combination of some or all of the configurations of the above-described embodiments as appropriate.
 なお、本発明は次のように表現することもできる。 The present invention can also be expressed as follows.
 本発明の1観点によれば、Si基板上に、ゲート絶縁膜とゲート電極とをこの順に有する相補型電界効果型トランジスタにおいて、少なくとも、前記ゲート電極の前期ゲート絶縁膜に接する部分の組成はMSi1-X(0<x<1)で表される金属Mの金属シリサイドを主成分とし、第一領域上のゲート電極に含まれる前記金属シリサイドとゲート絶縁膜との界面及びその付近には第一不純物元素が添加されており、かつ第二領域上のゲート電極に含まれる前記金属シリサイドとゲート絶縁膜との界面及びその付近には第二不純物元素が添加されており、かつ第三領域上のゲート電極に含まれる前記金属シリサイドと前記ゲート絶縁膜との界面及びその付近は実質的に前記第一及び第二不純物元素を含まないことを特徴とする半導体装置が提供される。 According to one aspect of the present invention, in a complementary field effect transistor having a gate insulating film and a gate electrode in this order on a Si substrate, at least the composition of the portion of the gate electrode in contact with the previous gate insulating film is M X Si 1-X (0 <x <1) is the main component of the metal silicide of the metal M, and the interface between the metal silicide and the gate insulating film included in the gate electrode on the first region and the vicinity thereof The first impurity element is added, and the second impurity element is added to and near the interface between the metal silicide and the gate insulating film contained in the gate electrode on the second region, and the third region. A semiconductor device characterized in that the interface between the metal silicide and the gate insulating film contained in the gate electrode on the region and the vicinity thereof does not substantially contain the first and second impurity elements. Is provided.
 また、前記半導体装置において、第一、第二、及び第三領域上のチャネル中の不純物量が実質的に同一であることが好ましい。前記半導体装置において、前記第一不純物元素は、B、Al、Ga、In、Tlの中の少なくとも一つの元素からなる。また、前記半導体装置において、前記第二不純物元素は、N、P、As、Sb、Biの中の少なくとも一つの元素からなる。更に、前記金属Mが、サリサイドプロセスが可能であるシリサイドを形成しうる金属であることが好ましい。 In the semiconductor device, it is preferable that the impurity amounts in the channels on the first, second, and third regions are substantially the same. In the semiconductor device, the first impurity element is composed of at least one element selected from B, Al, Ga, In, and Tl. In the semiconductor device, the second impurity element is made of at least one element selected from N, P, As, Sb, and Bi. Further, the metal M is preferably a metal capable of forming a silicide capable of a salicide process.
 また更に、前記金属Mが、Niであることが好ましい。前記金属MがNiであるシリサイドの、前記ゲート絶縁膜に接する部分がNiSi1-X(0<x<1)で表されるとき、0.6≦x<1であるようすることができる。この場合、更に、前記金属MがNiであるシリサイドの、前記ゲート絶縁膜に接する部分がNiSi相を主成分として含むことが好ましい。また、前記金属MがNiであるシリサイドの、前記ゲート絶縁膜に接する部分がNiSi1-X(0<x<1)で表されるとき、0.4≦x<0.6とすることができる。この場合、更に、前記金属MがNiであるシリサイドの、前記ゲート絶縁膜に接する部分がNiSi相を主成分として含むことが好ましい。また、前記金属MがNiであるシリサイドの、前記ゲート絶縁膜に接する部分がNiSi1-X(0<x<1)で表されるとき、0<x<0.4とすることができる。この場合、更に、前記金属MがNiであるシリサイドの、前記ゲート絶縁膜に接する部分がNiSi相を主成分として含むことが好ましい。 Still further, the metal M is preferably Ni. When the portion of the silicide in which the metal M is Ni and is in contact with the gate insulating film is represented by Ni X Si 1-X (0 <x <1), 0.6 ≦ x <1. it can. In this case, it is further preferable that a portion of the silicide in which the metal M is Ni contacts the gate insulating film contains a Ni 3 Si phase as a main component. Further, when the portion of the silicide in which the metal M is Ni and is in contact with the gate insulating film is expressed by Ni X Si 1-X (0 <x <1), 0.4 ≦ x <0.6. be able to. In this case, it is further preferable that the portion of the silicide in which the metal M is Ni that is in contact with the gate insulating film contains a NiSi phase as a main component. Further, when the portion of the silicide in which the metal M is Ni and is in contact with the gate insulating film is represented by Ni X Si 1-X (0 <x <1), 0 <x <0.4. it can. In this case, it is further preferable that a portion of the silicide in which the metal M is Ni is in contact with the gate insulating film contains a NiSi 2 phase as a main component.
 また、前記第一及び第二不純物元素の濃度が、ゲート絶縁膜界面近傍において、1×1020cm-3以上であることが好ましい。また、前記ゲート絶縁膜としてSi酸化膜又はSi酸窒化膜を用いることができる。また、前記ゲート絶縁膜はHfSiONであってもよい。この場合ゲート絶縁膜の前記ゲート電極と接する部分に、Si酸化膜、Si酸窒化膜層、又はSi窒化膜層を有することが好ましい。 The first and second impurity elements preferably have a concentration of 1 × 10 20 cm −3 or more in the vicinity of the gate insulating film interface. Further, a Si oxide film or a Si oxynitride film can be used as the gate insulating film. The gate insulating film may be HfSiON. In this case, it is preferable to have a Si oxide film, a Si oxynitride film layer, or a Si nitride film layer in a portion in contact with the gate electrode of the gate insulating film.
 本発明の他の1観点によれば、Si基板上に、ゲート絶縁膜とゲート電極とをこの順に有する相補型電界効果型トランジスタにおいて、第一領域上の前記ゲート電極の少なくともゲート絶縁膜と接する部分はp型にドープされた多結晶Siからなり、第二領域上の前記ゲート電極の少なくともゲート絶縁膜と接する部分はn型にドープされた多結晶Siからなり、かつ第三領域上のゲート電極の少なくともゲート絶縁膜と接する部分は実質的に前記p型及びn型ドーパントを含まないことを特徴とする半導体装置が提供される。 According to another aspect of the present invention, in a complementary field effect transistor having a gate insulating film and a gate electrode in this order on a Si substrate, at least the gate insulating film on the first region is in contact with the gate insulating film. The portion is made of polycrystalline Si doped in p-type, and at least the portion in contact with the gate insulating film of the gate electrode on the second region is made of polycrystalline Si doped in n-type, and the gate on the third region A semiconductor device is provided in which at least a portion of the electrode in contact with the gate insulating film does not substantially contain the p-type and n-type dopants.
 前記半導体装置において、第一、第二、及び第三領域上のチャネル中の不純物量が実質的に同一であることが好ましい。更に、前記金属Mが、サリサイドプロセスが可能であるシリサイドを形成しうる金属であることが好ましい。また更に、前記金属Mが、Niであることが好ましい。また、前記ゲート絶縁膜としてSi酸化膜又はSi酸窒化膜を用いることができる。また、前記ゲート絶縁膜はHfSiONであってもよい。この場合ゲート絶縁膜の前記ゲート電極と接する部分に、Si酸化膜、Si酸窒化膜層、又はSi窒化膜層を有することが好ましい。 In the semiconductor device, it is preferable that the amounts of impurities in the channels on the first, second, and third regions are substantially the same. Further, the metal M is preferably a metal capable of forming a silicide capable of a salicide process. Still further, the metal M is preferably Ni. Further, a Si oxide film or a Si oxynitride film can be used as the gate insulating film. The gate insulating film may be HfSiON. In this case, it is preferable to have a Si oxide film, a Si oxynitride film layer, or a Si nitride film layer in a portion in contact with the gate electrode of the gate insulating film.
 本発明に係る第一の半導体装置の製造方法は、前記ゲート絶縁膜上に多結晶Si(多結晶Si)を堆積し、第一領域上の多結晶Siに対してB、Al、Ga、In、Tlの中の少なくとも一つの元素をレジストマスクとイオン注入法を用いて選択的に添加し、また第二領域上の多結晶Siに対してN、P、As、Sb、Biの中の少なくとも一つの元素をレジストマスクとイオン注入法を用いて選択的に添加した後、多結晶Siを所望のゲート寸法に加工する工程と、熱処理によって多結晶Si中の添加元素を電気的に活性化する工程と、多結晶Siの上方に金属Mを成膜する工程と、それらを熱処理することによって、前記ゲート電極として金属シリサイドMSi1-X(0<x<1)を形成するとともにイオン注入により添加した前記元素をゲート電極とゲート絶縁膜の界面に偏析させる工程と、シリサイド化しなかった金属部分を選択的にエッチング除去する工程と、を含むことを特徴とする。 In the first method for manufacturing a semiconductor device according to the present invention, polycrystalline Si (polycrystalline Si) is deposited on the gate insulating film, and B, Al, Ga, In are deposited on the polycrystalline Si on the first region. , Tl is selectively added using a resist mask and an ion implantation method, and at least one of N, P, As, Sb, and Bi is added to polycrystalline Si on the second region. After selectively adding one element using a resist mask and an ion implantation method, the polycrystalline Si is processed into a desired gate size, and the additive element in the polycrystalline Si is electrically activated by heat treatment. Forming a metal M film on the polycrystalline Si and heat-treating them to form a metal silicide M X Si 1-X (0 <x <1) as the gate electrode and ion implantation Before added by The method includes a step of segregating the element to the interface between the gate electrode and the gate insulating film and a step of selectively etching away a metal portion that has not been silicided.
 また、本発明に係る第二の半導体装置の製造方法は、前記ゲート絶縁膜上に多結晶Siを堆積し、多結晶Siを所望のゲート寸法に加工する工程と、その上方に金属Mを成膜する工程と、それらを熱処理することによって、前記ゲート電極として金属シリサイドMSi1-X(0<x<1)を形成する工程と、シリサイド化しなかった金属部分を選択的にエッチング除去する工程と、第一領域上の金属シリサイドMSi1-X(0<x<1)に対してB、Al、Ga、In、Tlの中の少なくとも一つの元素をレジストマスクとイオン注入法を用いて選択的に添加し、また第二領域上の金属シリサイドMSi1-X(0<x<1)に対してN、P、As、Sb、Biの中の少なくとも一つの元素をレジストマスクとイオン注入法を用いて選択的に添加した後、それらを熱処理することによって、イオン注入により添加した前記元素をゲート電極とゲート絶縁膜の界面に偏析させる工程と、を含むことを特徴とする。 The second method for manufacturing a semiconductor device according to the present invention includes a step of depositing polycrystalline Si on the gate insulating film, processing the polycrystalline Si into a desired gate dimension, and forming a metal M thereon. Forming a metal silicide M X Si 1-X (0 <x <1) as the gate electrode, and selectively removing the metal portion that has not been silicided by heat-treating them. And a step of applying a resist mask and an ion implantation method to at least one element of B, Al, Ga, In, and Tl with respect to the metal silicide M X Si 1-X (0 <x <1) on the first region. And selectively adding at least one element of N, P, As, Sb, and Bi with respect to the metal silicide M X Si 1-X (0 <x <1) on the second region. Mask and ion implantation After selectively added using, by heat-treating them, characterized in that it comprises a step of segregating the element added by ion implantation in the interface between the gate electrode and the gate insulating film.
 また、本発明に係る第三の半導体装置の製造方法は、前記ゲート絶縁膜上に多結晶Siを堆積し、第一領域上の多結晶Siに対してB、Al、Ga、In、Tlの中の少なくとも一つの元素をレジストマスクとイオン注入法を用いて選択的に添加し、また第二領域上の多結晶Siに対してN、P、As、Sb、Biの中の少なくとも一つの元素をレジストマスクとイオン注入法を用いて選択的に添加した後、多結晶Siを所望のゲート寸法に加工する工程と、熱処理によって多結晶Si中の添加元素を電気的に活性化する工程と、第三領域の多結晶Si上にのみに金属Mを成膜する工程と、それを熱処理することによって、第三領域における前記ゲート電極として金属シリサイドMSi1-X(0<x<1)を形成する工程と、シリサイド化しなかった金属部分を選択的にエッチング除去する工程と、を含むことを特徴とする。 In the third method of manufacturing a semiconductor device according to the present invention, polycrystalline Si is deposited on the gate insulating film, and B, Al, Ga, In, and Tl are deposited on the polycrystalline Si on the first region. And selectively adding at least one element using a resist mask and an ion implantation method, and at least one element of N, P, As, Sb, and Bi with respect to polycrystalline Si on the second region. Is selectively added using a resist mask and an ion implantation method, and then the step of processing polycrystalline Si into a desired gate size, the step of electrically activating the additive element in the polycrystalline Si by heat treatment, Forming the metal M only on the polycrystalline Si in the third region, and heat-treating it, the metal silicide M X Si 1-X (0 <x <1) as the gate electrode in the third region And the process of forming And a step of selectively etching away a metal portion that has not been formed.
 第一の本発明によれば、低しきい値を持つN/pMOSトランジスタ及び高しきい値を持つMOSトランジスタを1チップ上に作製する際、基板中の不純物濃度を一定としてシリサイド電極中の不純物量を制御する。また、第二の本発明によれば、低しきい値を持つN/pMOSトランジスタ及び高しきい値を持つMOSトランジスタを1チップ上に作製する際、基板中の不純物濃度を一定として低いしきい値をドーパントが添加された多結晶Si電極で、高いしきい値をSiミッドギャップの仕事関数を有するシリサイド電極で実現する。この結果、特に高しきい値を持つトランジスタにおいて従来に比べチャネル中の不純物濃度が低減できる。また、同時にメタルゲート使用によってゲート空乏化抑制も実現できる。この結果、移動度の向上及びしきい値ばらつきの抑制を実現でき、トランジスタの高性能化が図れる。また、本発明による作製方法によれば、不純物添加をPR工程及びイオン注入工程によって簡便に行うことができるため、簡便に所望のデバイスを得ることができる。 According to the first aspect of the present invention, when an N / pMOS transistor having a low threshold value and a MOS transistor having a high threshold value are fabricated on one chip, the impurity concentration in the substrate is kept constant, Control the amount. According to the second aspect of the present invention, when an N / pMOS transistor having a low threshold and a MOS transistor having a high threshold are fabricated on one chip, the impurity concentration in the substrate is kept constant and the threshold is low. The value is realized by a polycrystalline Si electrode to which a dopant is added, and a high threshold value is realized by a silicide electrode having a work function of Si mid gap. As a result, the concentration of impurities in the channel can be reduced particularly in a transistor having a high threshold value as compared with the prior art. At the same time, suppression of gate depletion can be realized by using a metal gate. As a result, improvement in mobility and suppression of threshold variation can be realized, and high performance of the transistor can be achieved. Further, according to the manufacturing method of the present invention, since the impurity addition can be easily performed by the PR process and the ion implantation process, a desired device can be easily obtained.
 以上、実施形態(及び実施例)を参照して本願発明を説明したが、本願発明は上記実施形態(及び実施例)に限定されるものではない。本願発明の構成や詳細には、本願発明のスコープ内で当業者が理解し得る様々な変更をすることができる。 As mentioned above, although this invention was demonstrated with reference to embodiment (and an Example), this invention is not limited to the said embodiment (and Example). Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
 この出願は2007年12月28日に出願された日本出願特願2007-339556を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2007-339556 filed on Dec. 28, 2007, the entire disclosure of which is incorporated herein.
 本発明によれば、素子の特性や信頼性を向上させることが可能な半導体装置及びその製造方法を提供することができる。 According to the present invention, it is possible to provide a semiconductor device capable of improving the characteristics and reliability of an element and a manufacturing method thereof.
本発明に係る半導体装置の第一実施形態を示す断面図である。1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. 本発明に係る半導体装置の第二実施形態を示す断面図である。It is sectional drawing which shows 2nd embodiment of the semiconductor device which concerns on this invention. Niシリサイド結晶相とシリサイド化前のNi膜厚/Si膜厚との関係を示す図表である。It is a graph which shows the relationship between Ni silicide crystal phase and Ni film thickness / Si film thickness before silicidation. シリサイド電極中の厚み方向(深さ方向)の組成分布を示すグラフである。It is a graph which shows the composition distribution of the thickness direction (depth direction) in a silicide electrode. 結晶化Niシリサイド組成とシリサイド化前のNi膜厚/Si膜厚との関係を示すグラフである。It is a graph which shows the relationship between the crystallized Ni silicide composition and the Ni film thickness / Si film thickness before silicidation. 結晶化Niシリサイドの実効仕事関数の組成依存性を示すグラフである。It is a graph which shows the composition dependence of the effective work function of crystallized Ni silicide. シリサイド電極の仕事関数により実現できるトランジスタのしきい値の範囲を示すグラフである。It is a graph which shows the range of the threshold value of a transistor realizable by the work function of a silicide electrode. 図1の半導体装置を製造する方法の第一例を示す断面図(その1)である。FIG. 3 is a cross-sectional view (No. 1) illustrating a first example of a method of manufacturing the semiconductor device of FIG. 1. 図1の半導体装置を製造する方法の第一例を示す断面図(その2)である。FIG. 3 is a sectional view (No. 2) showing a first example of a method of manufacturing the semiconductor device of FIG. 1; 図1の半導体装置を製造する方法の第一例を示す断面図(その3)である。FIG. 3 is a sectional view (No. 3) showing a first example of a method of manufacturing the semiconductor device of FIG. 1; 本発明に係るMOSFETのドレイン電流-ゲート電圧特性の測定結果を示すグラフ(その1)である。4 is a graph (part 1) showing a measurement result of drain current-gate voltage characteristics of a MOSFET according to the present invention. 本発明に係るMOSFETのドレイン電流-ゲート電圧特性の測定結果を示すグラフ(その2)である。It is a graph (the 2) which shows the measurement result of the drain current-gate voltage characteristic of MOSFET which concerns on this invention. 本発明に係るMOSFETのドレイン電流-ゲート電圧特性の測定結果を示すグラフ(その3)である。6 is a graph (part 3) showing a measurement result of drain current-gate voltage characteristics of the MOSFET according to the present invention. 本発明に係るMOSFETの電子移動度の実効電界依存性の測定結果を示すグラフである。It is a graph which shows the measurement result of the effective electric field dependence of the electron mobility of MOSFET which concerns on this invention. 本発明に係るMOSFETのしきい値ばらつきのチャネル不純物濃度依存性を示すグラフである。It is a graph which shows the channel impurity concentration dependence of the threshold value dispersion | variation of MOSFET which concerns on this invention. 図1の半導体装置を製造する方法の第二例を示す断面図(その1)である。FIG. 6 is a cross-sectional view (No. 1) illustrating a second example of a method of manufacturing the semiconductor device of FIG. 1. 図1の半導体装置を製造する方法の第二例を示す断面図(その2)である。FIG. 8 is a cross-sectional view (No. 2) illustrating the second example of the method for manufacturing the semiconductor device of FIG. 1. 図1の半導体装置を製造する方法の第二例を示す断面図(その3)である。FIG. 9 is a sectional view (No. 3) showing a second example of the method for manufacturing the semiconductor device of FIG. 1; 図2の半導体装置を製造する方法を示す断面図(その1)である。FIG. 3 is a sectional view (No. 1) showing a method for manufacturing the semiconductor device of FIG. 2; 図2の半導体装置を製造する方法を示す断面図(その2)である。FIG. 3 is a sectional view (No. 2) showing the method for manufacturing the semiconductor device of FIG. 2; 図2の半導体装置を製造する方法を示す断面図(その3)である。FIG. 3 is a sectional view (No. 3) showing the method for manufacturing the semiconductor device of FIG. 2; 本発明に係る半導体装置の第三実施形態を示す断面図である。It is sectional drawing which shows 3rd embodiment of the semiconductor device which concerns on this invention.
符号の説明Explanation of symbols
100・・・・・・・第一領域
200・・・・・・・第二領域
300・・・・・・・第三領域
101・・・・・・・第一領域のチャネル不純物注入
201・・・・・・・第二領域のチャネル不純物注入
301・・・・・・・第三領域のチャネル不純物注入
102・・・・・・・第一領域電極への不純物注入
202・・・・・・・第二領域電極への不純物注入
1・・・・・・・Si基板(半導体基板)
2・・・・・・・素子分離領域
3・・・・・・・犠牲酸化膜
4・・・・・・・ゲート絶縁膜
5・・・・・・・多結晶Si膜
6・・・・・・・Si酸化膜
107・・・・・・・第一領域のエクステンション拡散層領域
207・・・・・・・第二領域のエクステンション拡散層領域
307・・・・・・・第三領域のエクステンション拡散層領域
8・・・・・・・ゲート側壁
109・・・・・・・第一領域のソース・ドレイン拡散層
209・・・・・・・第二領域のソース・ドレイン拡散層
309・・・・・・・第三領域のソース・ドレイン拡散層
10・・・・・・・シリサイド層
11・・・・・・・層間絶縁膜
112・・・・・・・第一領域のp型フルシリサイド電極
212・・・・・・・第二領域のn型フルシリサイド電極
312・・・・・・・第三領域のノンドープフルシリサイド電極
113・・・・・・・第一領域の電極/絶縁膜界面に偏析したp型添加元素
213・・・・・・・第二領域の電極/絶縁膜界面に偏析したn型添加元素
12・・・・・・・第1金属膜
21・・・・・・・HfSiONを最表面に持つゲート絶縁膜
22・・・・・・・SiO又はSiONキャップ膜
100... First region 200... Second region 300... Third region 101. ... channel impurity implantation 301 in the second region ... channel impurity implantation 102 in the third region ... impurity implantation 202 into the first region electrode ... ..Implantation of impurities into second region electrode 1 ... Si substrate (semiconductor substrate)
2... Element isolation region 3... Sacrificial oxide film 4... Gate insulating film 5. ... Si oxide film 107 .... Extension diffusion layer region 207 in the first region ... Extension diffusion layer region 307 in the second region ... Extension diffusion layer region 8... Gate side wall 109... Source / drain diffusion layer 209 in the first region ... Source / drain diffusion layer 309 in the second region ... Third region source / drain diffusion layer 10... Silicide layer 11... Interlayer insulating film 112. Full silicide electrode 212... N-type full silicide electrode 312 in the second region. Non-doped full silicide electrode 113 in the third region... P-type additive element 213 segregated at the electrode / insulating film interface in the first region... Segregated n-type additive element 12... First metal film 21... Gate insulating film 22 having HfSiON on the outermost surface... SiO 2 or SiON cap film

Claims (26)

  1.  半導体基板上にゲート絶縁膜及びゲート電極が設けられた複数のトランジスタ構造を有する半導体装置において、
     前記ゲート電極は前記ゲート絶縁膜に接する部分に金属シリサイド層を有し、前記複数のトランジスタ構造のそれぞれは第一領域、第二領域及び第三領域のいずれかに属し、前記第一領域は前記金属シリサイド層とゲート絶縁膜との界面に第一不純物元素を含み、前記第二領域は前記金属シリサイド層とゲート絶縁膜との界面に前記第二不純物元素を含み、前記第三領域は前記金属シリサイド層とゲート絶縁膜との界面に前記第一不純物元素及び前記第二不純物元素のいずれも実質的に含まず、前記第一不純物元素と前記第二不純物元素とは半導体中で互いに反対の導電型を形成する性質を有する、
     ことを特徴とする半導体装置。
    In a semiconductor device having a plurality of transistor structures in which a gate insulating film and a gate electrode are provided on a semiconductor substrate,
    The gate electrode has a metal silicide layer in a portion in contact with the gate insulating film, each of the plurality of transistor structures belongs to one of a first region, a second region, and a third region, A first impurity element is included at an interface between the metal silicide layer and the gate insulating film, the second region includes the second impurity element at an interface between the metal silicide layer and the gate insulating film, and the third region is the metal The interface between the silicide layer and the gate insulating film does not substantially contain either the first impurity element or the second impurity element, and the first impurity element and the second impurity element are oppositely conductive in the semiconductor. Has the property of forming a mold,
    A semiconductor device.
  2.  前記トランジスタ構造におけるチャネルの不純物量が前記第一領域、前記第二領域及び前記第三領域において実質的に同一である、
     ことを特徴とする請求項1記載の半導体装置。
    The impurity amount of the channel in the transistor structure is substantially the same in the first region, the second region, and the third region.
    The semiconductor device according to claim 1.
  3.  前記第一不純物元素は、B、Al、Ga、In及びTlの中から選ばれた少なくとも一つの元素からなる、
     ことを特徴とする請求項1又は2記載の半導体装置。
    The first impurity element is composed of at least one element selected from B, Al, Ga, In, and Tl.
    The semiconductor device according to claim 1, wherein:
  4.  前記第二不純物元素は、N、P、As、Sb及びBiの中から選ばれた少なくとも一つの元素からなる、
     ことを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置。
    The second impurity element is composed of at least one element selected from N, P, As, Sb and Bi.
    The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
  5.  前記金属シリサイド層を構成する金属は、サリサイドプロセスによって当該金属シリサイド層を形成可能な金属である、
     ことを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。
    The metal constituting the metal silicide layer is a metal capable of forming the metal silicide layer by a salicide process.
    The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
  6.  前記金属シリサイド層を構成する金属がNiである、
     ことを特徴とする請求項1乃至5のいずれか一項に記載の半導体装置。
    The metal constituting the metal silicide layer is Ni.
    The semiconductor device according to claim 1, wherein:
  7.  前記金属シリサイド層の前記ゲート絶縁膜に接する部分の組成がNiSi1-Xで表されるとき、0.6≦x<1である、
     ことを特徴とする請求項6記載の半導体装置。
    When the composition of the portion of the metal silicide layer in contact with the gate insulating film is represented by Ni X Si 1-X , 0.6 ≦ x <1.
    The semiconductor device according to claim 6.
  8.  前記金属シリサイド層の前記ゲート絶縁膜に接する部分がNiSi相を主成分として含む、
     ことを特徴とする請求項7記載の半導体装置。
    A portion of the metal silicide layer that is in contact with the gate insulating film contains a Ni 3 Si phase as a main component.
    The semiconductor device according to claim 7.
  9.  前記金属シリサイド層の前記ゲート絶縁膜に接する部分の組成がNiSi1-Xで表されるとき、0.4≦x<0.6である、
     ことを特徴とする請求項6記載の半導体装置。
    When the composition of the portion of the metal silicide layer in contact with the gate insulating film is represented by Ni X Si 1-X , 0.4 ≦ x <0.6.
    The semiconductor device according to claim 6.
  10.  前記金属シリサイド層の前記ゲート絶縁膜に接する部分がNiSi相を主成分として含む、
     ことを特徴とする請求項9記載の半導体装置。
    The portion of the metal silicide layer that is in contact with the gate insulating film contains a NiSi phase as a main component.
    The semiconductor device according to claim 9.
  11.  前記金属シリサイド層の前記ゲート絶縁膜に接する部分の組成がNiSi1-Xで表されるとき、0<x<0.4である、
     ことを特徴とする請求項6記載の半導体装置。
    When the composition of the portion of the metal silicide layer in contact with the gate insulating film is represented by Ni X Si 1-X , 0 <x <0.4.
    The semiconductor device according to claim 6.
  12.  前記金属シリサイド層の前記ゲート絶縁膜に接する部分がNiSi相を主成分として含む、
     ことを特徴とする請求項11記載の半導体装置。
    A portion of the metal silicide layer that is in contact with the gate insulating film includes a NiSi 2 phase as a main component.
    The semiconductor device according to claim 11.
  13.  前記第一不純物元素及び前記第二不純物元素の濃度が前記金属シリサイド層と前記ゲート絶縁膜との界面においてそれぞれ1×1020cm-3以上である、
     ことを特徴とする請求項1乃至12のいずれか一項に記載の半導体装置。
    The concentrations of the first impurity element and the second impurity element are 1 × 10 20 cm −3 or more at the interface between the metal silicide layer and the gate insulating film, respectively.
    The semiconductor device according to claim 1, wherein:
  14.  前記ゲート絶縁膜がシリコン酸化膜又はシリコン酸窒化膜である、
     ことを特徴とする請求項1乃至13のいずれか一項に記載の半導体装置。
    The gate insulating film is a silicon oxide film or a silicon oxynitride film;
    The semiconductor device according to claim 1, wherein:
  15.  前記ゲート絶縁膜がHfSiONを含む、
     ことを特徴とする請求項1乃至14のいずれか一項に記載の半導体装置。
    The gate insulating film includes HfSiON;
    The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
  16.  前記ゲート絶縁膜の前記ゲート電極と接する部分に、シリコン酸化膜、シリコン酸窒化膜又はシリコン窒化膜を有する、
     ことを特徴とする請求項15記載の半導体装置。
    A portion of the gate insulating film in contact with the gate electrode has a silicon oxide film, a silicon oxynitride film, or a silicon nitride film.
    The semiconductor device according to claim 15.
  17.  前記第一領域は、前記金属シリサイド層に代えて、前記ゲート絶縁膜との界面に前記第一不純物元素を含む多結晶シリコン層を有し、
     前記第二領域は、前記金属シリサイド層に代えて、前記ゲート絶縁膜との界面に前記第二不純物元素を含む多結晶シリコン層を有する、
     ことを特徴とする請求項1記載の半導体装置。
    The first region has a polycrystalline silicon layer containing the first impurity element at the interface with the gate insulating film instead of the metal silicide layer,
    The second region has a polycrystalline silicon layer containing the second impurity element at the interface with the gate insulating film instead of the metal silicide layer.
    The semiconductor device according to claim 1.
  18.  前記トランジスタ構造におけるチャネルの不純物量が前記第一領域、前記第二領域及び前記第三領域において実質的に同一である、
     ことを特徴とする請求項17記載の半導体装置。
    The impurity amount of the channel in the transistor structure is substantially the same in the first region, the second region, and the third region.
    The semiconductor device according to claim 17.
  19.  前記金属シリサイド層を構成する金属は、サリサイドプロセスによって当該金属シリサイド層を形成可能な金属である、
     ことを特徴とする請求項17又は18記載の半導体装置。
    The metal constituting the metal silicide layer is a metal capable of forming the metal silicide layer by a salicide process.
    19. The semiconductor device according to claim 17, wherein the semiconductor device is characterized in that:
  20.  前記金属シリサイド層を構成する金属がNiである、
     ことを特徴とする請求項17乃至19のいずれか一項に記載の半導体装置。
    The metal constituting the metal silicide layer is Ni.
    The semiconductor device according to claim 17, wherein the semiconductor device is a semiconductor device.
  21.  前記ゲート絶縁膜がシリコン酸化膜又はシリコン酸窒化膜である、
     ことを特徴とする請求項17乃至20のいずれか一項に記載の半導体装置。
    The gate insulating film is a silicon oxide film or a silicon oxynitride film;
    21. The semiconductor device according to claim 17, wherein:
  22.  前記ゲート絶縁膜がHfSiONを含む、
     ことを特徴とする請求項17乃至21のいずれか一項に記載の半導体装置。
    The gate insulating film includes HfSiON;
    The semiconductor device according to claim 17, wherein:
  23.  前記ゲート絶縁膜の前記ゲート電極と接する部分に、シリコン酸化膜、シリコン酸窒化膜又はシリコン窒化膜を有する、
     ことを特徴とする請求項22に記載の半導体装置。
    A portion of the gate insulating film in contact with the gate electrode has a silicon oxide film, a silicon oxynitride film, or a silicon nitride film.
    The semiconductor device according to claim 22.
  24.  ゲート絶縁膜上に多結晶シリコンを堆積する第一工程と、
     前記多結晶シリコンを第一領域、第二領域及び第三領域に分け、前記第一領域に第一導電型となる第一不純物元素をイオン注入法によって添加し、前記第二領域に前記第一導電型とは逆の第二導電型となる第二不純物元素をイオン注入法によって添加する第二工程と、
     前記多結晶シリコンをゲート電極に加工する第三工程と、
     前記多結晶シリコン上に金属を成膜する第四工程と、
     前記多結晶シリコン及び前記金属を熱処理することによって、金属シリサイド層を形成するとともに前記第一不純物元素及び前記第二不純物元素を当該金属シリサイド層と前記ゲート絶縁膜との界面に偏析させる第五工程と、
     前記金属シリサイドにならなかった前記金属を除去する第六工程と、
     を含むことを特徴とする半導体装置の製造方法。
    A first step of depositing polycrystalline silicon on the gate insulating film;
    The polycrystalline silicon is divided into a first region, a second region, and a third region, a first impurity element having a first conductivity type is added to the first region by an ion implantation method, and the first region is added to the first region. A second step of adding a second impurity element having a second conductivity type opposite to the conductivity type by an ion implantation method;
    A third step of processing the polycrystalline silicon into a gate electrode;
    A fourth step of depositing a metal on the polycrystalline silicon;
    A fifth step of heat-treating the polycrystalline silicon and the metal to form a metal silicide layer and segregate the first impurity element and the second impurity element at an interface between the metal silicide layer and the gate insulating film. When,
    A sixth step of removing the metal that has not become the metal silicide;
    A method for manufacturing a semiconductor device, comprising:
  25.  前記第二工程及び前記第五工程に代えて、
     前記第六工程の次に、
     前記金属シリサイド層を第一領域、第二領域及び第三領域に分け、前記第一領域に第一導電型となる第一不純物元素をイオン注入法によって添加し、前記第二領域に前記第一導電型とは逆の第二導電型となる第二不純物元素をイオン注入法によって添加する工程と、
     前記金属シリサイド層を熱処理することによって、前記第一不純物元素及び前記第二不純物元素を当該金属シリサイド層と前記ゲート絶縁膜との界面に偏析させる工程とを含む、
     ことを特徴とする請求項24記載の半導体装置の製造方法。
    Instead of the second step and the fifth step,
    Following the sixth step,
    The metal silicide layer is divided into a first region, a second region, and a third region, a first impurity element having a first conductivity type is added to the first region by an ion implantation method, and the first region is added to the first region. Adding a second impurity element having a second conductivity type opposite to the conductivity type by an ion implantation method;
    Heat treating the metal silicide layer to segregate the first impurity element and the second impurity element at the interface between the metal silicide layer and the gate insulating film,
    25. A method of manufacturing a semiconductor device according to claim 24.
  26.  前記第四工程に代えて、
     前記多結晶シリコンの前記第三領域上にのみ金属を成膜する工程を、
     を含むことを特徴とする請求項24記載の半導体装置の製造方法。
    Instead of the fourth step,
    Forming a metal film only on the third region of the polycrystalline silicon;
    25. The method of manufacturing a semiconductor device according to claim 24, comprising:
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