JP2005129551A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a silicide gate electrode having a proper work function. <P>SOLUTION: The semiconductor device is equipped with a silicon substrate provided with a p-type active region and an n-type active region, a gate insulating film formed on the active region, a gate electrode which is formed on the gate insulating film formed of (Ni+Si) where the ratio of Ni to (Ni+Si) is set at 40 to 60 at%:100 at%; contains n-type impurities to Si over the p-type active region; and contains p-type impurities to Si over the n-type active region, n-type source/drain regions formed in the p-type active region on sides of the gate electrode, and p-type source/drain regions formed in the n-type active regions. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a low-resistance conductive gate electrode made of metal, silicide, or the like that can cope with miniaturization. Here, the silicide includes a mixture of a metal and Si and does not need to have a stoichiometric composition.

    Conventionally, in a MOSFET used in an integrated circuit, a gate electrode has been formed by polycide, which is a stack of a polycrystalline silicon layer and a silicide layer. As the silicide, a compound of metal such as W, Co, Ni and Si and Si was used.

  In general, after a gate insulating film such as silicon oxide is formed, a Si layer such as polycrystalline silicon or amorphous silicon is deposited thereon, and a thin metal layer is further formed thereon. A silicide layer is formed by reacting with the upper part of the Si layer. The silicide layer has a lower resistivity than the Si layer, and lowers the resistance value of the gate electrode.

  As integrated circuits become smaller, the gate electrode length becomes shorter. When the gate electrode length is 0.5 μm or less, it becomes difficult to obtain a sufficiently low resistance value in the polycide structure. For this reason, there has been proposed full silicidation in which a polycrystalline silicon layer is deposited as a gate electrode and then the entire polycrystalline silicon layer is silicided (Non-patent Document 1). By forming the entire gate electrode from silicide, the gate resistance can be reduced, and a depletion layer that can be generated in the silicon layer can be prevented, and the transistor characteristics can be improved.

Jakub Kedzierski et al., IEDM2002 Technical Digest, p. 247

  Transistors used for integrated circuits include n-channel transistors and p-channel transistors. In order to operate these transistors optimally, it is desired that each transistor has an optimum threshold voltage, and each gate electrode is required to have a work function within a predetermined range.

  It is desirable that the gate electrode of the p-channel (p-type) MOSFET has a work function of 5.1 eV, and the gate electrode of the n-channel (n-type) MOSFET has a work function of 4.1 eV. In the conventional polycide gate electrode, the work function is adjusted by the impurity species, acceleration voltage, and implantation amount of impurity ions implanted into the polycrystalline silicon layer.

  As in the case of polycrystalline Si, it has been reported that when an impurity is added to NiSi, the work function changes (Non-patent Document 2).

M. Qin et al., J. Electrochem.Soc., 148 (5), p.G271, 2001

  There is also a report that an n-channel MOSFET and a p-channel MOSFET are separately formed by adding impurities into the fully silicidated gate electrode (Non-patent Document 3).

Z. Krivokapic et al., IEDM 2002 Technical Digest, p.367

  In these reports, the change in work function is small, and a work function having the above-mentioned values suitable as an n-channel MOSFET and a p-channel MOSFET has not been obtained.

  In addition, it has been proposed to form a gate electrode with a metal such as Al, W, Cu, Mo, Ti, Ta, etc., which can be further reduced in resistance than silicide. It is particularly useful for MOSFETs having a gate length of 0.1 μm or less. There is also an advantage that generation of a depletion layer can be prevented.

  A replaceable material layer such as Al or Al-Ti is formed on the p-type disposable silicon gate electrode and the n-type disposable silicon gate electrode, and the metal gate electrode is formed by replacing the disposable gate electrode with a replaceable material by heat treatment. To do. The replacement Al gate electrode is described as providing a threshold voltage within ~ 0.2V of the n-type polysilicon gate electrode.

JP 11-251595 A JP-A-11-261063 JP 2001-24187 A

An object of the present invention is to provide a semiconductor device having a silicide gate electrode having an appropriate work function.
Another object of the present invention is to provide a semiconductor device including an n-channel MOSFET and a p-channel MOSFET having a silicide gate electrode having an appropriate work function.

  Still another object of the present invention is to provide a semiconductor device having (Ni + Si) gate electrodes that realize different work functions for a p-channel MOSFET and an n-channel MOSFET.

  According to one aspect of the present invention, a silicon substrate having an n-type active region, a gate insulating film formed on the active region, a ratio of Ni to (Ni + Si) formed on the gate insulating film, Ni / A gate electrode containing (Ni + Si) whose (Ni + Si) is 40 at% -70 at% and further containing a p-type impurity for Si, and a p-type source formed in the n-type active region on the side of the gate electrode / Drain region is provided.

  According to another aspect of the present invention, a silicon substrate having a p-type active region, a gate insulating film formed on the active region, a ratio of Ni to (Ni + Si) formed on the gate insulating film, Ni / (Ni + Si) is a base of (Ni + Si) with 30 at% -60 at%, and further includes a gate electrode containing an n-type impurity for Si, and an n-type formed in the p-type active region on the side of the gate electrode A semiconductor device having a source / drain region is provided.

Further, the silicon substrate includes a p-type active region and an n-type active region, and the gate electrode has a Ni ratio of Ni / (Ni + Si) to (Ni + Si) of 40 at% -60 at% (Ni + Si) as a base material. It is desirable. The impurity concentration is preferably 1 × 10 ²¹ cm ⁻³ or more in the vicinity of the interface with the gate insulating film.

  When (Ni + Si) is used as a gate electrode material, Ni / (Ni + Si) is selected to be 40 at% -70 at%, and a p-type impurity for Si is added, a large change in work function is obtained. A preferable work function is obtained as a gate electrode of a p-channel MOSFET.

  When (Ni—Si) is used as a gate electrode material, (Ni + Si) is selected to be 30 at% -60 at%, and an n-type impurity for Si is added, a large change in work function can be obtained. A preferable work function is obtained as a gate electrode of an n-channel MOSFET.

  When Ni / (Ni + Si) is selected to be 40 at% -60 at%, it is possible to obtain a preferable work function as the gate electrode of the n-channel MOSFET and the p-channel MOSFET by using the same gate electrode material (base material).

The present inventors formed a gate electrode using metal and silicon, and conducted a preliminary experiment described below in order to investigate what is possible in order to greatly change the work function.
As shown in FIG. 1A, the surface of a p-type Si substrate 1 having a low efficiency of 10 Ωcm was thermally oxidized to form a silicon oxide film 2. Three types of silicon oxide film 2 were prepared: 5 nm, 10 nm, and 15 nm.

  As shown in FIG. 1B, a polycrystalline silicon film 3 was formed on a silicon oxide gate insulating film 2 by thermal chemical vapor deposition (CVD) with a thickness of 50 nm. A sample without depositing a polycrystalline silicon film was also formed.

  As shown in FIG. 1C, a metal mask 4 was disposed above the Si substrate 1, and a Ni film 5 and a TiN film 6 were laminated by sputtering. The TiN film 6 has a thickness of 30 nm, and is used as a cap layer for preventing oxygen present in the atmosphere from oxidizing the Ni film 5 when performing a silicide reaction.

  The thickness of the Ni film 5 on the Si layer was changed, and the composition of the resulting (Ni + Si) film was changed. The thickness of the Ni film 5 was 18 nm, 24 nm, 30 nm, 36 nm, and 42 nm, and the ratio of Ni / (Ni + Si) was 30 at%, 40 at%, 50 at%, 60 at%, and 70 at%. In the sample in which the Si film 3 was not formed, the Ni film 5 was formed to a thickness of 50 nm. Thus, the ratio of Ni / (Ni + Si) was changed in the range of 30 at% -100 at%.

  As shown in FIG. 1D, heat treatment was performed in a vacuum at 400 ° C. for 1 minute to cause a silicide reaction between the Si film 3 and the Ni film 5, thereby generating a (Ni + Si) film 7. It is considered that the total thickness of the Ni layer 5 and the total thickness of the Si layer 3 therebelow reacted to produce a (Ni + Si) layer 7. (Ni + Si) is considered to be silicide, but strictly speaking, it may be considered that it is not silicide. It is considered that at least Ni and Si are mixed, and is represented as (Ni + Si).

  As shown in FIG. 1E, using the TiN film 6 as a mask, the polycrystalline Si film 3 outside the TiN layer 6 and the underlying silicon oxide gate insulating film 2 were removed by ion milling. In this way, a sample of a MOS diode structure for measuring the work function was formed.

The flat band voltage Vfb of the MOS diode has the following relationship with the work function ΦM of metal (here, metal silicide).
Vfb = ΦMS− (Qf / εox) * tox
ΦMS = ΦM-ΦS
Here, ΦS is a work function of silicon, ΦMS is a work function difference between a metal work function ΦM and a work function ΦS of Si, Qf is a fixed charge density, tox is an oxide film thickness, and εox is a dielectric constant of silicon oxide. The flat band voltage Vfb is measured, plotted against tox (5 nm, 10 nm, 15 nm), and extrapolated to tox = 0 to obtain ΦMS. The work function ΦM of the metal (here, the work function of silicide (Ni—Si)) is obtained from ΦMS calculated based on the measured ΦMS and a known value.

  FIG. 1F is a graph showing the relationship between the work function obtained from the measurement of the sample and the composition Ni / (Ni + Si) (at%) of the sample. By changing the composition of Ni / (Ni + Si) from 30 at% to 100 at%, the work function was changed from about 4.43 eV to about 5.1 eV.

  When Ni / (Ni + Si) = 100 at%, an appropriate work function of about 5.1 eV is obtained as a gate work function of a p-channel MOSFET, but an appropriate work function of about 4.1 eV as a gate electrode of an n-channel MOSFET cannot be obtained. It can be seen that when the composition of Ni / (Ni + Si) is changed in the range of 30 at% to 70 at%, the work function changes from about 4.4 eV to about 4.9 eV or more.

  When Ni is used as the gate electrode material, the desired work function of the gate electrode of the p-channel MOSFET is about 5.1 eV. In this case, however, the gate electrode of the n-channel MOSFET needs to be made of a different material. A method for forming an n-channel MOSFET and a p-channel MOSFET with the same material and obtaining a desired work function was further studied. An attempt was made to add p-type and n-type impurities to the finally obtained (Ni + Si) film 7 by adding impurities to the polycrystalline Si film 3 shown in FIG. 1B.

As shown in FIG. 2A, after the polycrystalline Si film 3 was formed in the process of FIG. 1B, p-type impurities B or In were ion-implanted into the polycrystalline Si film 3. The concentration of B or In was changed in the range of ^{1E19 (1 × 10 19) cm} -3 ~1E22cm -3.

  First, the case where B is added as a p-type impurity will be described. B was implanted at an acceleration voltage of 1 keV. The composition of Ni / (Ni + Si) was changed in the range of 30 at% to 70 at%. The B concentration is a value near the interface between the (Ni + Si) film 7 and the gate insulating film 2 in the configuration of FIG. 1E.

In the region where the B concentration is low, the work function is hardly changed by the added B. That is, it is almost the same as the work function by the composition of Ni / (Ni + Si) in FIG. 1F. When the B concentration was 1E21 cm ⁻³ or more, the work function increased rapidly regardless of the composition of Ni / (Ni + Si).

When the composition of Ni / (Ni + Si) was 30 at%, when the B concentration was 1E21 cm ⁻³ or more, the work function was about 4.9 eV. When the composition of Ni / (Ni + Si) was 40 at% -60 at%, when the B concentration was 1E21 cm ⁻³ or more, the work function was about 5.1 eV. When the Ni / (Ni + Si) composition was 70 at%, when the B concentration was 1E21 cm ⁻³ or more, the work function was about 5.3 eV.

When the composition of Ni / (Ni + Si) is 40 at% -70 at% and the B concentration is 1E21 cm ⁻³ or more, a work function of about 5.1 eV or more is obtained. If the composition of Ni / (Ni + Si) is 40 at% -60 at%, the work function obtained by adding B of 1E21 cm ⁻³ or more is about 5.1 eV.

Next, a case where In is used as a p-type impurity will be described.
FIG. 2C is a graph showing the dependence of the work function on the In concentration in (Ni + Si). In the region where the In concentration is low, the work function hardly changes due to the added In. That is, it is almost the same as the work function by the composition of Ni / (Ni + Si) in FIG. 1F. When the In concentration was 1E21 cm ⁻³ or higher, the work function increased rapidly regardless of the composition of Ni / (Ni + Si).

When Ni / (Ni + Si) was 30 at% and the In concentration was 1E21 cm ⁻³ or more, the obtained work function was about 4.9 eV. When Ni / (Ni + Si) was 40 at% to 60 at%, the work function obtained was about 5.1 eV when the In concentration was 1E21 cm ⁻³ or more. When Ni / (Ni + Si) was 70 at% and the In concentration was 1E21 cm ⁻³ or more, the obtained work function was about 5.3 eV.

When Ni / (Ni + Si) is 40 at% to 70 at%, a work function of about 5.1 eV or more can be obtained when the In concentration is 1E21 cm ⁻³ or more. Furthermore, when the Ni / (Ni + Si) ratio is selected from 40 at% to 60 at%, a work function of about 5.1 eV is obtained. Regarding the work function, the effect of B addition and the effect of In addition are considered to be almost the same. By using at least one of B and In as the p-type impurity, an effect of adjusting the work function will be obtained.

FIG. 3A shows a case where As or Sb is ion-implanted as an n-type impurity 9 in the polycrystalline Si film.
FIG. 3B is a graph showing the results when As is ion-implanted into the Si film 3. The concentration of As was changed from 1E19-1E22 cm ⁻³ . As is apparent from the figure, when As was added in an amount of 1E21 cm ⁻³ or more, the work function was significantly reduced.

When the composition of Ni / (Ni + Si) was 70 at%, when As was added at 1E21 cm ⁻³ or more, the work function was about 4.7 eV. When the composition of Ni / (Ni + Si) was 40 at% -60 at%, when As was added at 1E21 cm ⁻³ or more, a work function of about 4.1 eV was obtained. When the composition of Ni / (Ni + Si) was 30 at%, a work function of about 3.9 eV was obtained when As was added at 1E21 cm ⁻³ or more. When the ratio of Ni / (Ni + Si) is selected to be 30 at% -60 at%, a work function of about 4.1 eV or less is obtained.

FIG. 3C shows the results when Sb is used as the n-type impurity. As in the case of As, when the Sb concentration was 1E21 cm ⁻³ or more, the work function was significantly reduced. When Ni / (Ni + Si) was 70 at%, the amount of decrease in work function obtained when the Sb concentration was 1E21 cm ⁻³ or more was relatively small, and the work function obtained was about 4.6 eV. When the composition of Ni / (Ni + Si) was 40 at% -60 at%, the work function was about 4.1 eV when the Sb concentration was 1E21 cm ⁻³ or more. When the composition of Ni / (Ni + Si) was 30 at%, the work function was about 3.9 eV when the Sb concentration was 1E21 cm ⁻³ or more.

When the composition of Ni / (Ni + Si) is 30 at% -60 at%, when the Sb concentration is 1E21 cm ⁻³ or more, a work function of about 4.1 eV or less is obtained. Regarding the work function, it can be said that the effects of As addition and Sb addition are almost similar. Similar results were obtained using As and Sb, which are n-type impurities for Si. Similar results would be obtained using P, an n-type impurity for Si. The work function adjustment effect will be obtained by using at least one of P, As, and Sb as the n-type impurity.

From the results described above, (Ni + Si) is used as the gate electrode, the atomic ratio of Ni / (Ni + Si) is selected in the range of about 0.4 to 0.6, and the n-type impurity and the p-type impurity with respect to Si are about 1E21 cm. It was found that a work function of a gate electrode desirable as a CMOSFET can be obtained by adding ⁻³ or more.

  FIG. 1G is a schematic cross-sectional view showing a configuration example of a CMOSFET integrated circuit. An element isolation region 12 is formed on the surface of the Si substrate 1 by shallow trench isolation (STI). An n-type impurity and a p-type impurity are ion-implanted into the active region defined in the element isolation region 12 to form an n-type well 14 and a p-type well 15. A gate oxide film 2 is formed on the surface of the Si substrate by thermal oxidation, and a polycrystalline silicon layer is deposited thereon.

  As shown in FIGS. 2A and 3A, a p-type impurity and an n-type impurity are ion-implanted into the polycrystalline silicon layer, and then a silicide reaction is performed, whereby a p-type impurity added (Ni + Si) layer and an n-type impurity added ( A Ni + Si) layer is formed. By patterning this (Ni + Si) layer, a p-channel MOSFET gate electrode 7p and an n-channel MOSFET gate electrode 7n are formed.

  Using the formed gate electrode as a mask, an n-type impurity and a p-type impurity are separately ion-implanted to form an extension region. Further, an insulating film such as silicon nitride or silicon oxide is deposited, and reactive ion etching (RIE) or the like is performed to form the sidewall spacer SW. Further, n-type impurities and p-type impurities are ion-implanted to form p-type source / drain regions 21 and n-type source / drain regions 22.

  Thereafter, an interlayer insulating film 24 is deposited to form a contact hole. For example, a Ti plug, a TiN layer, and a W layer are deposited in the contact hole to form a contact plug. Thereafter, the necessary wiring is formed to obtain a CMOSFET integrated circuit structure.

  Note that silicidation may be performed after the gate electrode structure is formed using silicon. By selecting the atomic composition ratio of Ni / (Ni + Si) from 40 at% to 60 at%, an appropriate work function can be obtained as a gate electrode of a p-channel MOSFET and an n-channel MOSFET using the same gate electrode material (base material). Can do.

  When it is allowed to change the base material of the gate electrode between the n-channel MOSFET and the p-channel MOSFET, the gate electrode for the n-channel MOSFET uses 30 at% to 60 at% (Ni + Si), and the gate electrode for the p-channel MOSFET is 40 at. It is also possible to produce using (Ni + Si) of% to 70 at%.

  In the embodiment described above, a silicide material of (Ni + Si) is used as the gate electrode material. When a metal is used as the gate electrode material, a gate electrode having a resistance lower than that of silicide can be obtained. As a method for forming the Al gate electrode, a method using thermal substitution of Si and Al has been proposed. The present inventors examined whether or not the same effect can be obtained when an impurity is added to the (Ni + Si) silicide gate electrode by adding the impurity to the Al substitution gate electrode.

4A to 4G are cross-sectional views schematically showing a manufacturing process of a sample used for measuring the work function.
As shown in FIG. 4A, the surface of the Si substrate 1 was thermally oxidized to form a gate oxide film 2. A polycrystalline Si film 3 having a thickness of about 50 nm was formed on the gate oxide film 2 by thermal CVD.

As shown in FIG. 4B, boron ions 8 were ion-implanted into the polycrystalline Si film 3. The implantation amount was selected so that the impurity concentration of the finally obtained substituted Al gate electrode was in the range of 1E15 to 1E21 cm ⁻³ .

  As shown in FIG. 4C, a photoresist pattern PR was formed on the polycrystalline Si film 3 into which boron was ion-implanted, the photoresist pattern PR was formed, and the polycrystalline Si layer 3 was etched using the photoresist pattern PR as a mask. Thereafter, the photoresist pattern PR was removed.

As shown in FIG. 4D, an Al layer 11 having a thickness of about 50 nm was formed by sputtering so as to cover the patterned polycrystalline Si film 3.
As shown in FIG. 4E, the stack of the polycrystalline Si film and the Al layer was subjected to a heat treatment at 400 ° C. for 30 minutes to cause a substitution reaction between Si and Al. Si in the polycrystalline Si film 3 diffuses into the Al layer 11, Al diffuses into the polycrystalline Si film from the Al layer 11, and Si is replaced by Al to form an Al gate electrode 13.

As shown in FIG. 4F, anisotropic etching by RIE was performed to remove the Al layer 11 on the flat surface. Al sidewalls 11 remain on the sidewalls of the gate Al pattern.
As shown in FIG. 4G, isotropic etching was further performed to remove residual Al on the side wall of the gate electrode 13. The sample thus formed was measured for a flat band voltage to obtain a work function.

FIG. 5 is a graph showing the relationship between the obtained work function change and the concentration of the impurity (B) initially added to Si. When the added B concentration is less than 1E20 cm ⁻³ , the change in work function due to the added B is small. When the added B concentration is 1E20 cm ⁻³ or more, a sudden work function change occurs. At a B concentration of 1E21 cm ⁻³ or more, a significant work function change of 0.35 eV or more will be obtained. This change in work function can be considered as a characteristic similar to the change in work function shown in FIG. 2B.

  However, the work function is changed by adding impurities to Al only when B is used as an impurity. Even if other p-type impurities and n-type impurities are added, the work function can be changed. There wasn't. Al has a work function that can be used as a gate electrode of an n-channel MOSFET. However, when pure Al is used as the gate electrode, the work functions of the gate electrode of the n-channel MOSFET and the gate electrode of the p-channel MOSFET become equal. It is desirable to increase the work function of the p-channel MOSFET Al gate electrode. By using Al to which B is added for the gate electrode of the p-channel MOSFET, the work function can be greatly increased.

  By using Al to which B is added for the gate electrode of the p-channel MOSFET and using Al to which B is not added for the gate electrode of the n-channel MOSFET, the work function of the gate electrode is changed, and a more preferable CMOSFET is produced. Can do.

6A to 6F are cross-sectional views schematically showing a manufacturing process of a CMOS semiconductor integrated circuit device according to an embodiment of the present invention.
As shown in FIG. 6A, an element isolation region 12 by STI is formed on the surface of the silicon substrate 1, and n-type impurities and p-type impurities are ion-implanted to form an n-type well 14 and a p-type well 15. After forming the gate oxide film 2 by thermally oxidizing the substrate surface, a polycrystalline Si layer is deposited and patterned to form gate electrodes 16 and 17. The gate electrodes 16 and 17 have a height of 50 nm and a width of 40 nm, for example.

  A p-type impurity such as B is ion-implanted for the p-channel MOSFET, and an n-type impurity such as P or As is ion-implanted for the n-channel MOSFET to form p-type and n-type extensions 18 and 19. To do.

  Sidewall 20 is formed by depositing silicon nitride or silicon oxide by thermal CVD and performing anisotropic etching by RIE or the like. Further, p-type impurities such as B are ion-implanted for p-channel MOSFETs, and n-type impurities such as P and As are ion-implanted for n-type MOSFETs to form high-concentration source / drain regions 21 and 22. Form. A p-type impurity and an n-type impurity are also added to the gate electrode to form a p-type gate electrode 16 and an n-gate electrode 17. The above steps are conventional steps, and other known methods can be used.

  As shown in FIG. 6B, an interlayer insulating film 24 such as silicon oxide is formed so as to cover the gate electrodes 16 and 17. The interlayer insulating film 24 is polished by chemical mechanical polishing (CMP) or the like to expose the surfaces of the gate electrodes 16 and 17. The n-channel MOSFET region is covered with a photoresist pattern PR1, and B is ion-implanted. The concentration of B is preferably selected so that the B concentration in the gate electrode 16 is 1E21 or more. Thereafter, the resist pattern PR1 is removed.

As shown in FIG. 6C, for example, by annealing at 1000 ° C. for 3 seconds, B added to the gate electrode 16 is activated and diffused to obtain a B-added gate electrode 16x.
As shown in FIG. 6D, an Al layer 26 is deposited to a thickness of, for example, 500 nm so as to be in contact with the exposed gate electrodes 16x and 17. An annealing process is performed at 400 ° C. for 30 minutes in a state where the Si gate electrodes 16 x and 17 and the Al layer 26 are in contact with each other. Al and Si are replaced by annealing treatment. Si in the gate electrode diffuses into the Al layer 26, and Al diffuses from the Al layer 26 into the gate electrode.

  FIG. 6E shows the resulting configuration. The gate electrode 28 is made of substituted Al to which ion-implanted B is added, and the gate electrode 30 is made of substituted Al to which B is not added. The gate electrode 28 has a work function higher than that of the gate electrode 30 because B is added at a high concentration.

  As shown in FIG. 6F, the Al layer 26x diffused with Si on the gate electrode is removed by CMP or the like. Thereafter, an interlayer insulating film is further deposited, and contact holes and conductive plugs are formed to complete the transistor. Further, an interlayer insulating film and upper layer wiring are formed to form a CMOS integrated circuit device.

In the above-described embodiment, after forming the gate electrode, the Al gate electrode was formed by embedding with an insulating layer, exposing the gate electrode, and performing heat substitution.
7A-7H show another embodiment.

  As shown in FIG. 7A, an element isolation region 12, an n-type well 14 and a p-type well 15 are formed on a Si substrate 1, a gate insulating film 2 is formed by thermal oxidation, and then a polycrystalline Si layer 35 is deposited thereon. To do.

  As shown in FIG. 7B, a resist pattern PR1 is formed on the polycrystalline Si layer, and B is ion-implanted into the polycrystalline Si layer in the p-channel MOSFET region. A polycrystalline Si layer 35x to which B is added at a high concentration is formed. Note that the polycrystalline Si layer 35 on the n-channel MOSFET maintains a state where no impurity is added.

  As shown in FIG. 7C, the resist pattern PR1 is removed, and a resist pattern PR2 having a new gate electrode shape is formed. Using the resist pattern PR2 as a mask, the polycrystalline Si layers 35 and 35x are etched to obtain a gate electrode shape. Thereafter, the resist pattern PR2 is removed.

  As shown in FIG. 7D, the n-channel MOS transistor region is covered with a resist pattern PR3, and p-type impurities such as B are ion-implanted to form source / drain regions 21. Thereafter, the resist pattern PR3 is removed.

  As shown in FIG. 7E, the p-channel MOSFET region is covered with a resist pattern PR4, and an n-type impurity such as P or As is ion-implanted into the n-channel MOSFET region. The source / drain region 22 of the n-channel MOSFET is formed, and an n-type impurity is added to the gate electrode to form an n-type gate electrode 35y. Thereafter, the resist pattern PR4 is removed.

As shown in FIG. 7F, for example, a silicon nitride film 37 is deposited and anisotropic etching is performed by RIE or the like, thereby creating a sidewall SW on the side wall of the gate electrode.
As shown in FIG. 7G, an interlayer insulating film 38 such as silicon oxide is formed to cover the gate electrode. The interlayer insulating film 38 is polished by CMP or the like to expose the gate electrode surface.

  As shown in FIG. 7H, an Al layer 26 is deposited to a thickness of, for example, 500 nm so as to be in contact with the exposed gate electrode surface. Thereafter, for example, annealing is performed at 400 ° C. for 30 minutes as in the above-described embodiment to cause a substitution reaction between Al and Si. Thereafter, the Al layer 26 diffused with Si is removed.

8A-8E show a modification. FIG. 8A shows the structure of a semiconductor substrate that has undergone the same steps as FIG. 7A.
FIG. 8B is a step similar to the step shown in FIG. 7B, and B is ion-implanted into the polycrystalline Si film 35 in the p-channel MOSFET region, preferably 1E21 cm ⁻³ or more. Thereafter, the resist pattern PR1 is removed.

  FIG. 8C shows a process of depositing an Al layer 26 directly on the exposed polycrystalline Si film. In this state, for example, annealing is performed at 400 ° C. for 40 minutes to cause a substitution reaction between Si in the polycrystalline Si layers 35 and 35 x and Al in the Al layer 26. The polycrystalline Si layer on the silicon substrate disappears and becomes a substituted Al layer.

  FIG. 8D shows a state in which the resist pattern PR2 is formed on the Al layer 26, and the lower Al layer 26x and the replacement Al layer are patterned. In the p-channel MOSFET region, a substituted Al electrode 28 to which B is added is patterned, and in the n-channel MOSFET region, a substituted Al gate electrode 30 to which B is not added is formed. An Al layer 26x in which Si is diffused remains on each gate electrode. The Al layer 26x is made of metal and can be used as it is as a gate electrode.

  FIG. 8E shows another modification. After the step shown in FIG. 8B, an Al layer 26 having a thickness of 200 nm and a Ti layer 38 having a thickness of 500 nm are stacked on the polycrystalline Si layers 35 and 35x by sputtering, for example. The Ti layer 38 has a function of absorbing Si. Si diffused from the Si layers 35 and 35x into the Al layer 26 is further absorbed by the Ti layer 38 and stabilized as Ti silicide. For example, when a thermal substitution reaction is performed on the structure shown in FIG. 8E at 400 ° C. for 3 hours, Si is sucked from the layers 35 and 35x through the layer 26 to the Ti layer 38. The Al layer 26 can be an Al layer that hardly contains Si. Thereafter, the Ti layer 38 is removed, and the gate electrode is patterned by the same process as in FIG. 8D.

Although the present invention has been described with reference to the embodiments, it is obvious to those skilled in the art that the present invention is not limited to these embodiments. For example, various changes, improvements, and combinations are possible.
The features of the present invention will be described below.

(Appendix 1) a silicon substrate having an n-type active region;
A gate insulating film formed on the active region;
A gate electrode formed on the gate insulating film and having a Ni ratio of Ni / (Ni + Si) to (Ni + Si) of 40 at% -70 at% as a base material and further containing a p-type impurity with respect to Si;
A p-type source / drain region formed in the n-type active region on the side of the gate electrode;
A semiconductor device.

(Appendix 2) A silicon substrate having a p-type active region;
A gate insulating film formed on the active region;
A gate electrode formed on the gate insulating film and having a Ni ratio of Ni / (Ni + Si) to (Ni + Si) of 30 at% -60 at% as a base material and further containing an n-type impurity with respect to Si;
N-type source / drain regions formed in the p-type active region on the side of the gate electrode;
A semiconductor device.

    (Supplementary Note 3) (Ni + Si) in which the silicon substrate includes a p-type active region and an n-type active region, and the gate electrode has a Ni ratio of Ni / (Ni + Si) to (Ni + Si) of 40 at% -60 at%. The semiconductor device according to appendix 1 or 2.

(Additional remark 4) The semiconductor device of any one of additional remark 1-3 whose density | concentration of the said impurity is 1 * 10 < ²¹ > cm < ^-3 > or more in the interface vicinity with a gate insulating film.
(Supplementary note 5) The semiconductor device according to any one of supplementary notes 1-4, wherein the impurity is one or more of P, As, Sb, B, and In in each gate electrode.

(Appendix 6) A silicon substrate having a p-type active region and an n-type active region;
A gate insulating film formed on the active region;
(Ni + Si), which is formed on the gate insulating film and has a Ni ratio of Ni / (Ni + Si) to (Ni + Si) of 40 at% -60 at%, and includes an n-type impurity for Si above the p-type active region, Above the n-type active region, a gate electrode containing p-type impurities for Si;
On the side of the gate electrode, an n-type source / drain region formed in the p-type active region, a p-type source / drain region formed in the n-type active region,
A semiconductor device.

(Supplementary note 7) The semiconductor device according to supplementary note 6, wherein both the n-type impurity and the p-type impurity have a concentration of 1E21 cm ⁻³ or more.
(Supplementary note 8) The semiconductor device according to supplementary note 6 or 7, wherein the n-type impurity includes at least one of P, As, and Sb, and the p-type impurity includes at least one of B and In.

(Supplementary Note 9) A silicon substrate having an n-type active region;
A gate insulating film formed on the n-type active region;
A gate electrode formed on the gate insulating film and formed of substituted Al doped with B;
A p-type source / drain region formed in the n-type active region on the side of the gate electrode;
A semiconductor device.

(Appendix 10) Furthermore,
A p-type active region formed in the silicon substrate;
a gate insulating film formed on the p-type active region;
A gate electrode formed on the gate insulating film and formed of substituted Al not containing B;
N-type source / drain regions formed in the p-type active region on the side of the gate electrode;
The semiconductor device according to appendix 9, wherein

(Supplementary note 11) The semiconductor device according to Supplementary note 6 or 10, wherein the gate electrode formed of substituted Al to which B is added is formed of substituted Al in which Si to which B is added by 1E21 cm ⁻³ or more is substituted by Al.

(Supplementary Note 12) (a) forming a Si layer on a silicon substrate having an n-type active region, a p-type active region, and a gate insulating layer formed on these active regions;
(B) adding B to the Si layer above the n-type active region;
(C) patterning the Si layer to form a disposable gate electrode;
(D) forming an Al layer in contact with the disposable gate electrode;
(E) a step of causing substitution of Si and Al by annealing;
A method of manufacturing a semiconductor device including:

(Additional remark 13) The process of adding said B is the manufacturing method of the semiconductor device of Additional remark 12 which adds 1E21cm < ^-3 > or more of B.
(Additional remark 14) The manufacturing method of the semiconductor device of Additional remark 9 or 13 with which the said process (c) is performed before the said process (b).

    (Supplementary Note 15) Further, (f) before the step (d), includes a step of forming an insulating layer so as to cover the patterned disposable gate electrode and polishing to expose the surface of the disposable gate electrode. The method for manufacturing a semiconductor device according to any one of -14.

It is sectional drawing explaining the preliminary experiment which the present inventors performed, the graph which shows the obtained result, and sectional drawing which shows the structure of the semiconductor integrated circuit device produced using the result. It is sectional drawing which shows the structure of the sample which doped the p-type impurity as an impurity, and the graph which shows a measurement result. It is sectional drawing which shows the structure of the sample which ion-implanted the n-type impurity as an impurity, and the graph which shows the measurement result of a sample. It is sectional drawing which shows roughly the sample preparation process of the other preliminary experiment which the present inventors etc. performed. It is a graph which shows the measurement result obtained from the sample shown in FIG. It is sectional drawing which shows schematically the manufacturing process of the semiconductor integrated circuit device by another Example. It is sectional drawing which shows schematically the manufacturing process of the semiconductor integrated circuit device by another Example. It is sectional drawing which shows schematically the manufacturing process by a modification.

Explanation of symbols

1 Si substrate 2 Gate insulating film 3 Polycrystalline Si film 4 Metal mask 5 Ni layer 6 TiN layer 7 (Ni + Si) layer 8 p-type impurity 9 n-type impurity 11 Al layer 12 element isolation region 14 n-type well 15 p-type well 16 p-type MOSFET gate electrode 17 n-type MOSFET gate electrode 18 p-type extension region 19 n-type extension region 20, SW sidewall 21 p-type source / drain region 22 n-type source / drain region 24 interlayer insulating film 26 Al layer 28 Replacement Al gate electrode containing B 30 Replacement Al gate electrode not containing B 35 Polycrystalline Si layer 37 Silicon nitride layer 38 Interlayer insulating film

Claims (5)

a silicon substrate having an n-type active region;
A gate insulating film formed on the active region;
A gate electrode formed on the gate insulating film and having a Ni ratio of Ni / (Ni + Si) to (Ni + Si) of 40 at% -70 at% as a base material and further containing a p-type impurity with respect to Si;
A p-type source / drain region formed in the n-type active region on the side of the gate electrode;
A semiconductor device. a silicon substrate having a p-type active region;
A gate insulating film formed on the active region;
A gate electrode formed on the gate insulating film and having a Ni ratio of Ni / (Ni + Si) to (Ni + Si) of 30 at% -60 at% as a base material and further containing an n-type impurity with respect to Si;
N-type source / drain regions formed in the p-type active region on the side of the gate electrode;
A semiconductor device. The silicon substrate includes a p-type active region and an n-type active region, and the gate electrode is based on (Ni + Si) in which a ratio of Ni / (Ni + Si) to (Ni + Si) is 40 at% -60 at%. Item 3. The semiconductor device according to Item 1 or 2. 4. The semiconductor device according to claim 1, wherein the concentration of the impurity is 1 × 10 ²¹ cm ⁻³ or more in the vicinity of the interface with the gate insulating film. The semiconductor device according to claim 1, wherein the impurity is one or more of P, As, Sb, B, and In in each gate electrode.

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