201003849 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種CMOS電晶體及其製作方法，特別 是一種可防止鍺原子外擴（Ge out_diffusi〇n)的CM〇s電晶 體及其製作方法。 ％ 【先前技術】 : 近年來’利用微縮元件尺寸以提升金氧半導體 (metal-oxide semiconductor’以下簡稱MOS)電晶體表現六文 能的製程方向’遭逢微影製程技術瓶頸、昂貴花費等負面 因素影響’業界開始尋求其他的方法來改善MOS電晶體的 運作效能’其中以利用材料特性對MOS電晶體造成應變效 應（strain effect)的方式最受矚目。 例如，為提升設具有P型金氧半導體(PMOS)電晶體及 N型金氧半導體(NMOS)電晶體的互補式金氧半導體 (complementary metal-oxide semiconductor > 以下簡稱 CMOS)電晶體的驅動電流，業界發展出應變矽 (strained-silicon)技術，係利用製程技術或自然晶格常數的 差異，達成提升CMOS電晶體驅動電流的目的。一般來說， 應變;δ夕技術主要可概分為基板應變方法（substrate-strain based)與製程應變方法（process-induced strain based)二個系 統，基板應變方法係利用一應變矽基板或結合選擇性磊晶 6 201003849 成長（selective epitaxial growth)製程，由材料間晶袼常數的 差異來產生應變；而製程應變方法則係利用某些製程步 驟，在CMOS電晶體表面形成應力薄臈，例如：多晶矽應力 覆蓋層（cap poly stressor)或接觸洞蝕刻停止層（c〇ntact etch stop layer’以下簡稱CESL)等方式，進而對MOS電晶體施 加相對應之伸張應力或壓縮應力。上述二種應變石夕技術皆 可使CMOS電晶體閘極下方的通道區域矽晶格發生應變， 降低載子在通道區域遭受的阻力，使載子的遷移率增加， 以期改善CMOS電晶體效能。 請參考第1圖’第1圖為一習知之CMOS電晶體1〇 的示意圖。如第1圖所示’ CMOS電晶體10包含—PMOS 電晶體12以及一 NMOS電晶體14分別形成於一基底16， 且PMOS電晶體12與NMOS電晶體14間係設有淺溝隔離 (STI) 30以防止電晶體間發生短路，其中nm〇S電晶體14 a 係設置於基底16之一 Ρ型井18上，其包含一源極/汲極2〇Α 以及一閘極結構22A，PMOS電晶體12則係設置於基底16 之N型井24上，其包含一源極/汲極2〇b以及一閘極結構 22B，且PMOS電晶體12之源極/汲極20B係為一矽鍺化 合物（SiGe)磊晶’藉由矽鍺間晶格常數的差異來對pM〇s 電日日體12閘極結構22B下方之通道區域（0]^111^1 region) 產生擠壓的應力；此外，在PMOS電晶體12的源極/汲極 _ 20B和NMOS電晶體14的源極/汲極2〇a表面形成有一鎳 7 201003849 化矽層（nickel silicide)26，以提升金屬對矽材間進行歐姆式 接觸（Ohmic contact)的能力；再者，為加強NM〇s電晶體 14通道區域的載子遷移率，在CMOS電晶體1〇上另覆有 一具有伸張應力之高伸張力薄膜28覆蓋於閘極結構22A、 22B與源極/>及極20A、20B表面，並進行—紫外線硬化(uv curing)製程’照射紫外光以強化覆蓋於閘極結構22A與源 極/汲極20A表面之高伸張力薄膜28 ’藉以增加其伸張應 力，來拉大NMOS電晶體14閘極結構22A下方，亦即通 道區域之P型井18的晶格排列，進而提升通道區域的電子 遷移率以及NMOS電晶體14之驅動電流。 然而’在利用紫外線硬化製程調整高伸張力薄膜28之 伸張應力值時，覆蓋在CMOS電晶體10上之高伸張力薄 膜28的伸張應力卻會造成PMOS電晶體12之源極/汲極 20B發生鍺原子外擴（Ge 〇ut-diffusion)的現象，如第2圖所 示，由電子顯微鏡(SEM)照片可清楚的觀察到，在鎳化矽層 26的表面有黑色斑點形成，該些黑色斑點即為鍺原子外擴 的d據’此一現象將造成石夕化物結塊（silicide aggl〇merati〇n) 而使阻值升高，以及嚴重影響對PMOS電晶體閾值電壓 (threshold v〇ltage)的精準控制。 【發明内容】 為解決習知鍺外擴的現象，本發明揭露一種可遏止錯 8 201003849 外擴之CMOS電晶體的製作方法。首先，提供一半導體基 底，該半導體基底具有至少一 PMOS電晶體以及至少一 NM0S電晶體，且該PM0S及之源極/汲極包含鍺；接著形 成一碳摻雜層於該PM0S電晶體之該源極/汲極的上半部， 然後進行一自行對準金屬矽化物製程，接著再形成至少一 伸張應力薄膜（tensile thin film)覆蓋該半導體基底、該 NM0S電晶體以及該PM0S電晶體，之後對該伸張應力薄 ， 膜進行一表面處理製程，以強化該伸張應力薄膜。 另外，本發明另揭露一種CMOS電晶體，其包含有一 半導體基底、至少一 NM0S電晶體以及至少一 PMOS電晶 體形成於該半導體基底上以及一接觸洞蝕刻停止層覆蓋於 該PMOS電晶體及該NM0S電晶體上，其中該PMOS電晶 體之一源極/汲極包含鍺，且該PMOS電晶體之該源極汲極 上半部設有一碳摻雜層，以達成遏止鍺外擴的目的。 以本發明所示之方法所形成之CMOS電晶體，在 PMOS電晶體源極/汲極上半部形成有一碳摻雜層，可確保 鍺離子在PMOS電晶體之源極/汲極内的摻雜濃度’並改善 習知技藝中鍺外擴的問題。 【實施方式】 請參考第3圖至第10圖，第3圖至第9圖係依據本發 201003849 明之一較佳實施例所繪示之CM0S電晶體的製作方法示意 圖’第10圖係為製作本發明之可遏止鍺外擴的CMOS電 晶體的流程示意圖。如第3圖所示’提供一半導體基底30， 其包含至少一PMOS電晶體32以及至少一 NMOS電晶體 34，其中NMOS電晶體34係設置於半導體基底30之一 P 型井30内’其包含一設於半導體基底3〇表面之一閘極結 構38A以及—設於閘極結構38A兩側之一源極/汲極40 ; PM0S電晶體32則係設於半導體基底30之N型井44内， 其包含—設於半導體基底30表面之一閘極結構38B以及一 設於閘極結構38B兩侧之一源極/汲極46。 閘極結構38A、38B各包含一閘極介電層50、設於閘 極介電層50上方之一閘極52以及設於閘極52上方之一硬 遮罩層54 ’其中閘極介電層50可包含氧化矽、氮氧化矽、 亂化石夕荨傳統介電材料或金屬氧化物（metai 〇xide)、金屬石夕 西义鹽（metal silicate)、金屬铭酸鹽（metal aluminate)、金屬乳 氧化物(metal oxynitride)等高介電係數(high-k)介電材料或 河述材料之組合’藉由熱氧化、氮化、化學氣相沉積等製 程形成之；閘極52可包含多晶矽、矽鍺化合物（SiGe)、金 屬、金屬石夕化物、金屬氮化物或金屬氧化物或上述材料之 組合；而硬遮罩層54可包含氧化矽、氮化矽、碳化矽、氧 氮化矽等介電材料’且閘極結構38A、38B之側壁各設有 一熱氧化層（thermal oxide layer)56以及一側壁子58，侧壁 10 201003849 子58可以是單層或多層結構，且構成侧壁子58的材料可 包含氧化矽、氮化矽、氮氧化矽或其他的介電材料。另外， 為防止電晶體間發生短路，半導體基底30上另設有複數個 設於MOS電晶體間的絶緣結構，如設於pm〇S電晶體32 與NMOS電晶體34間的淺溝隔離48，且閘極結構38A、 38B兩側之半導體基底30分別設有一輕雜摻汲極(lightly doped drain, LDD)50A、50B，以防止 PMOS 電晶體 32 或 NMOS電晶體34的熱電子效應（hot electron effects)。 為增加PMOS電晶體32位於閘極結構38B下方之通 道區域的載子遷移速率，PMOS電晶體32之源極/汲極46 係包含鍺。以本較佳實施例為來說，形成PMOS電晶體32 之源極/汲極46 ’係先於NMOS電晶體34上形成一圖案化 光阻（圖未示）’再進行一蝕刻製程以於PMOS電晶體32閘 極結構38B的半導體基底30表面形成至少一凹槽（圖未 示）’之後再利用一選擇性遙晶成長（selective epitaxial growth)製程成長之一矽鍺化合物磊晶於該凹槽内，其中， 矽鍺化合物磊晶的晶格常數係大於半導體基板30之晶格 常數，並略微向電晶體通道區域的方向延伸，同時進行一 重摻雜製程，植入P型摻質（如硼（B))到閘極結構38B兩側 之該石夕鍺化合物蟲晶，並完成源極/：：及極46的製作。另外 為增加對通道區域的壓力同時避免後續形成的金屬矽化物 太過接近源極/汲極46接面，較佳之PMOS電晶體32之源 11 201003849 極/汲極46將略突出於半導體基板30之上表面；然而源極 /汲極46亦可與半導體基板30之上表面齊平，又或者是低 於半導體基板30之上表面，在此不多做限制。 如第4圖所示，隨後利用一遮罩（圖未示）蓋住NMOS 電晶體34 ’並進行一碳佈植（Carbon implantation)製程，以 對PM0S電晶體32的源極/汲極46植入做為摻質的碳，進 而在源極/汲極46的上半部形成一碳摻雜層60，其厚度約 在100埃（angstrom)到500埃之間，較佳之厚度約介於200 埃到300埃之間。碳佈植製程的佈植能量可依預定的佈植 深度而定，例如介於1 KeV至5 KeV之間，劑量可介於1〇13 至1016原子/平方公分(atom/cm2)，較佳之佈植能量約為 2KeV，較佳之佈植劑量約為1.05xl015 atom/cm2 ;然而本發 明之方法並不限定只對PMOS電晶體32的源極/汲極46植 入碳摻質，亦可全面性地對NMOS電晶體34以及PMOS 電晶體3 2進行碳佈植製程。接著可選擇性地進行一回火 (annealing)製程，例如一快速熱處理製程(rapid thermal process, RTP)，利用1000°C至1050°C的高溫來活化被植入 的碳摻質，並同時修補碳佈植製程中受損之半導體基底30 表面的晶格結構。之後再進行一自行對準金屬矽化物 (self-aligned silicide, salicide)製程，在源極/汲極 40、46 表 面形成金屬石夕化物62，例如一含鎳、銘等之金屬石夕化物， 且金屬矽化物62的厚度約在50埃到500埃之間，較佳之 12 201003849 厚度約在100埃到300埃之間，形成金屬矽化物62之該些 製程係為本領域之人或熟習該技藝者所熟知，故於此不再 贅述。 如第5圖所示，依序形成一第一襯墊層64、一伸張應 力薄膜65以及可選擇性地進行一表面處理製程，例如一快 速熱處理製程或一紫外線硬化(UV curing)製程，以強化伸 張應力緩衝薄膜65，接著沉積一第二襯墊層70，其中伸張 應力薄膜65係為一多層（multi-layered)應力薄膜，其包含 一伸張應力緩衝薄膜66以及一高伸張應力薄膜68，且其 中伸張應力緩衝薄膜66的伸張應力值會小於高伸張應力 薄膜68。此外，在形成一第一襯塾層64、一伸張應力薄膜 65以及一第二襯墊層70之前，本發明亦可選擇性地去除 PMOS電晶體32與NMOS電晶體34的側壁子58，以使伸 張應力薄膜65能更有效調整NMOS電晶體34通道區域的 晶格排列。 請參考第6圖，於第二襯墊層70形成後，進行一光阻 塗佈、曝光以及顯影製程，形成一第一圖案化光阻72以將 NMOS電晶體34蓋住，並進行一蝕刻製程，例如一非等向 性蝕刻製程，以第一圖案化光阻72為蝕刻遮罩，移除覆蓋 於PMOS電晶體32上的伸張應力緩衝薄膜66、高伸張應 力薄膜68以及第二襯墊層70，且於該蝕刻製程中，以氧 13 201003849 化石夕為主要材料的第一襯墊層64係做為I虫刻停止層之 用，藉以保護下方之PMOS電晶體32。接著如第7圖所示， 在第一圖案化光阻72移除後，形成一高壓縮應力薄膜74， 例如再次利用一電黎增強化學氣相沈積製程，沉積高壓縮 應力薄膜74全面性地覆蓋PMOS電晶體32、NMOS電晶 體34。 然後如第8圖所示，再次進行一光阻塗佈、曝光以及 顯影製程，以形成一第二圖案化光阻76並覆蓋整個PMOS 電晶體32。接著進行一蝕刻製程，以第二圖案化光阻76 為蝕刻遮罩去除未被第二圖案化光阻層76覆蓋的區域，亦 即覆蓋於NMOS電晶體34上的高壓縮應力薄膜74以及第 二襯墊層70，僅保留部分的高壓縮應力薄膜74覆蓋於 PMOS電晶體32的閘極結構38B與源極/汲極46表面。 隨後如第9圖所示，移除覆蓋於PMOS電晶體32上的 第二圖案化光阻層76，至此，以本發明之方法所製作之一 CMOS電晶體78於是完成其基礎的製作流程，且覆蓋於 PMOS電晶體32上的高壓縮應力薄膜74以及覆蓋於NMOS 電晶體34上的伸張應力薄膜65可做為CMOS電晶體78 的接觸洞蝕刻停止層之用。之後可於高伸張應力薄膜68及 高壓縮應力薄膜74上再覆蓋一層間介電層（inter-layer dielectric layer, ILD layer)(圖未示），然後利用一圖案化光 14 201003849 阻（圖未示）當作触刻遮罩並進行一非等向性触刻製程，在 該層間介電層與做為接觸洞蝕刻停止層的伸張應力薄膜65 及高壓縮應力薄膜74中形成複數個接觸洞（contact hole)(圖未示），作為PM0S電晶體32與NM0S電晶體34 之閘極結構38A、3 8B、或源極/汲極40、46與其他電子元 件連接的橋樑。 , 請參考第10圖，其係為本發明之CMOS電晶體的製 作方法之流程示意圖，包含以下步驟： 步驟100 :提供一半導體基底，其定義有至少一 PMOS電 晶體以及至少一 NMOS電晶體，且該PMOS電 晶體之一源極/汲極係為一矽鍺化合物磊晶； 步驟102 :對該PMOS電晶體之該源極/汲極進行一碳佈植 製程，形成一碳摻雜層於該PMOS電晶體之該源 極/汲極的上半部； V 步驟104 :進行一自行對準金屬矽化物製程，在PMOS電 晶體和NM0S電晶體之該源極/汲極表面形成金 屬矽化物； 步驟106 :形成一伸張應力薄膜，其包含一伸張應力緩衝 薄膜以及一高伸張應力薄膜，且該伸張應力緩衝 薄膜之伸強應力值係小於該高伸張應力薄膜； 步驟108 :進行一表面處理製程，例如一快速熱處理製程 或一紫外線硬化製程，以強化該伸張應力薄膜； 15 201003849 步驟110 :移除形成於該PMOS電晶體上之部分該伸張應 力薄膜； 步驟112:形成一高壓縮應力薄膜全面性地覆蓋於該PMOS 電晶體以及該NMOS電晶體；以及 步驟114 :移除形成於該NMOS電晶體上之部分該高壓縮 應力薄膜。 ： 此外，製作本發明之CMOS電晶體78時，在考量節 省製程步驟的前提下，PMOS電晶體32上的伸張應力薄膜 65亦可保留，另選擇性地形成高壓縮應力薄膜74覆蓋 PMOS電晶體32。 請參考第11圖，其為以本發明所述之方法所製作之 CMOS電晶體78的電子顯微鏡照片。請一併參考第2圖及 第11圖，經比較可以發現，以習知方法所製作之CMOS i 電晶體10表面會有鍺外擴的現象，因而在鎳化矽層26表 面形成黑色斑點，然，以本發明之方法所製作之CMOS電 晶體78，在金屬矽化物62表面並沒有觀察到任何的黑色 斑點形成。 為避免鍺外擴的情形發生，本發明係在金屬矽化物62 形成前，先將原子半徑小於矽且為電中性的碳原子佈植在 以矽鍺化合物磊晶為材料的PMOS電晶體32的源極/汲極 16 201003849 46中，另在高伸張應力薄膜68和金屬矽化物62間形成伸 張應力緩衝薄膜66。經實驗發現，僅形成伸張應力緩衝薄 膜66時，隨著伸張應力緩衝薄膜66的厚度增加，抑制鍺 外擴的效果也就愈好，然而伸張應力緩衝薄膜66的增厚並 不利於CMOS電晶體78的離子增益（ion gain)效應；因此 配合碳佈植製程，使得摻雜的碳原子停留在矽鍺化合物磊 晶的晶格内，不但增加了石夕鍺化合物蟲晶的穩定性，且可 ， 減少伸張應力緩衝薄膜66的厚度，以確保CMOS電晶體 78離子增益的效果，由此可知，本發明係藉由形成於PMOS 電晶體32之源極/汲極46表面的碳摻雜層60以及伸張應 力緩衝層66，有效遏止了 PMOS電晶體32之源極/汲極46 發生鍺外擴的現象。然而，若將碳佈植製程的碳原子取代 為同為電中性，且其原子半徑小於矽之其他惰性摻質來進 行佈植時，例如氬(Ar)、鍺、銦（In)，並無法達到如本發明 所示之遏止錯外擴的效果。201003849 IX. Description of the Invention: The present invention relates to a CMOS transistor and a method of fabricating the same, and more particularly to a CM〇s transistor capable of preventing germanium atom expansion (Ge out_diffusi〇n) and fabrication thereof method. % [Prior Art]: In recent years, 'Using the size of the miniature element to improve the process direction of the metal-oxide semiconductor (hereinafter referred to as MOS) transistor performance of the six-energy process' has been negatively affected by the technical bottleneck of the lithography process and the expensive cost. Impact 'The industry is looking for other ways to improve the operational performance of MOS transistors'. Among them, the way in which strain characteristics are applied to MOS transistors by using material properties is most noticed. For example, in order to improve the driving current of a complementary metal-oxide semiconductor (hereinafter referred to as CMOS) transistor having a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxide semiconductor (NMOS) transistor The industry has developed a strained-silicon technology that uses process technology or natural lattice constants to achieve the goal of increasing the drive current of CMOS transistors. In general, strain; Delta technology can be broadly divided into two systems: substrate-strain based and process-induced strain based. The substrate strain method uses a strained substrate or a combination of choices. Sexual epitaxy 6 201003849 The selective epitaxial growth process produces strain from the difference in the crystallization constant between materials. The process strain method uses some process steps to form a stress 臈 on the surface of a CMOS transistor, such as polycrystalline germanium. A cap poly stressor or a contact hole etch stop layer (CESL) is used to apply a corresponding tensile stress or compressive stress to the MOS transistor. Both of the above strains can make the lattice region of the channel under the CMOS transistor gate strain, reduce the resistance of the carrier in the channel region, and increase the mobility of the carrier, in order to improve the performance of the CMOS transistor. Please refer to FIG. 1 'Fig. 1 is a schematic diagram of a conventional CMOS transistor 1 。. As shown in FIG. 1 , the CMOS transistor 10 includes a PMOS transistor 12 and an NMOS transistor 14 respectively formed on a substrate 16 , and a shallow trench isolation (STI) is provided between the PMOS transistor 12 and the NMOS transistor 14 . 30 to prevent a short circuit between the transistors, wherein the nm〇S transistor 14a is disposed on one of the substrates 16 of the substrate 16, which includes a source/drain 2〇Α and a gate structure 22A, PMOS The crystal 12 is disposed on the N-type well 24 of the substrate 16, and includes a source/drain 2〇b and a gate structure 22B, and the source/drain 20B of the PMOS transistor 12 is a stack. Compound (SiGe) epitaxy generates compressive stress on the channel region (0]^111^1 region under the pM〇s electric solar body 12 gate structure 22B by the difference in the inter-turn lattice constant; Further, a nickel 7 201003849 nickel silicide 26 is formed on the surface of the source/drain _ 20B of the PMOS transistor 12 and the source/drain 2 〇a of the NMOS transistor 14 to lift the metal pair coffin The ability to perform Ohmic contact; in addition, to enhance the carrier mobility of the 14-channel region of the NM〇s transistor, in CMOS transistor The body 1 is further covered with a high tensile film 28 having tensile stress covering the surfaces of the gate structures 22A, 22B and the source/> and the poles 20A, 20B, and performing a UV curing process to irradiate the ultraviolet The light is used to strengthen the tensile film 28' of the gate structure 22A and the source/drain 20A surface to increase the tensile stress thereof to widen the NMOS transistor 14 under the gate structure 22A, that is, the P-type of the channel region. The lattice arrangement of well 18 enhances the electron mobility of the channel region and the drive current of NMOS transistor 14. However, when the tensile stress value of the high tensile film 28 is adjusted by the ultraviolet curing process, the tensile stress of the high tensile film 28 overlying the CMOS transistor 10 causes the source/drain 20B of the PMOS transistor 12 to occur. The phenomenon of Ge 〇ut-diffusion, as shown in Fig. 2, can be clearly observed by electron microscopy (SEM) photographs, in which black spots are formed on the surface of the nickel ruthenium layer 26, the black The spot is the d-base of the helium atom expansion. This phenomenon will cause the silicide aggl〇merati〇n to increase the resistance and seriously affect the threshold voltage of the PMOS transistor (threshold v〇ltage ) precise control. SUMMARY OF THE INVENTION In order to solve the phenomenon of the conventional expansion, the present invention discloses a method for fabricating a CMOS transistor that can be used to suppress the spread of the error. First, a semiconductor substrate is provided. The semiconductor substrate has at least one PMOS transistor and at least one NMOS transistor, and the PMOS and the source/drain include erbium; then a carbon doped layer is formed on the PMOS transistor. The upper half of the source/drain, then performing a self-aligned metal telluride process, and then forming at least one tensile thin film covering the semiconductor substrate, the NMOS transistor, and the PMOS transistor, after The tensile stress is thin, and the film is subjected to a surface treatment process to strengthen the tensile stress film. In addition, the present invention further discloses a CMOS transistor including a semiconductor substrate, at least one NMOS transistor, and at least one PMOS transistor formed on the semiconductor substrate and a contact etch stop layer overlying the PMOS transistor and the NMOS. In the transistor, one of the source/drain electrodes of the PMOS transistor includes germanium, and a carbon doped layer is disposed on the upper half of the source drain of the PMOS transistor to achieve the purpose of suppressing the external expansion. In the CMOS transistor formed by the method of the present invention, a carbon doping layer is formed on the upper half of the PMOS transistor source/drain to ensure doping of germanium ions in the source/drain of the PMOS transistor. Concentration' and improve the problem of the expansion of the know-how. [Embodiment] Please refer to FIG. 3 to FIG. 10, and FIG. 3 to FIG. 9 are schematic diagrams showing a method for fabricating a CMOS transistor according to a preferred embodiment of the present invention. A schematic diagram of the flow of the CMOS transistor capable of suppressing the external expansion of the present invention. As shown in FIG. 3, a semiconductor substrate 30 is provided which includes at least one PMOS transistor 32 and at least one NMOS transistor 34, wherein the NMOS transistor 34 is disposed in one of the P-wells 30 of the semiconductor substrate 30. A gate structure 38A disposed on the surface of the semiconductor substrate 3 and a source/drain 40 disposed on both sides of the gate structure 38A; the PM0S transistor 32 is disposed in the N-well 44 of the semiconductor substrate 30. The device includes a gate structure 38B disposed on a surface of the semiconductor substrate 30 and a source/drain 46 disposed on both sides of the gate structure 38B. Each of the gate structures 38A and 38B includes a gate dielectric layer 50, a gate 52 disposed above the gate dielectric layer 50, and a hard mask layer 54 ′ disposed above the gate 52. The layer 50 may comprise yttrium oxide, ytterbium oxynitride, chaotic stone dielectric traditional dielectric material or metal oxide (metai 〇xide), metal silicate, metal aluminate, metal A combination of a high-k dielectric material or a ferritic material such as a metal oxynitride is formed by thermal oxidation, nitridation, chemical vapor deposition, etc.; the gate 52 may comprise polysilicon a bismuth compound (SiGe), a metal, a metal cerium compound, a metal nitride or a metal oxide or a combination thereof; and the hard mask layer 54 may include yttrium oxide, tantalum nitride, tantalum carbide, yttrium oxynitride The dielectric material 'and the sidewalls of the gate structures 38A, 38B are each provided with a thermal oxide layer 56 and a sidewall spacer 58. The sidewall 10 201003849 sub 58 may be a single layer or a multilayer structure and constitute a sidewall. The material of the sub-58 may include cerium oxide, cerium nitride, nitrogen Of silicon or other dielectric material. In addition, in order to prevent short circuit between the transistors, the semiconductor substrate 30 is further provided with a plurality of insulating structures disposed between the MOS transistors, such as shallow trench isolation 48 disposed between the pm〇S transistor 32 and the NMOS transistor 34. And the semiconductor substrate 30 on both sides of the gate structures 38A, 38B are respectively provided with a lightly doped drain (LDD) 50A, 50B to prevent the hot electron effect of the PMOS transistor 32 or the NMOS transistor 34 (hot electron) Effects). To increase the carrier mobility of the PMOS transistor 32 in the channel region below the gate structure 38B, the source/drain 46 of the PMOS transistor 32 includes germanium. In the preferred embodiment, the source/drain 46' of the PMOS transistor 32 is formed prior to forming a patterned photoresist (not shown) on the NMOS transistor 34 to perform an etching process. The surface of the semiconductor substrate 30 of the PMOS transistor 32 gate structure 38B is formed with at least one recess (not shown) and then grown by a selective epitaxial growth process. In the trench, wherein the lattice constant of the germanium compound epitaxy is larger than the lattice constant of the semiconductor substrate 30, and slightly extends toward the transistor channel region, and a heavily doped process is performed to implant the P-type dopant (eg, Boron (B)) to the ceramsite compound on both sides of the gate structure 38B, and the fabrication of the source /:: and the pole 46 is completed. In addition, in order to increase the pressure on the channel region while avoiding the subsequent formation of the metal telluride too close to the source/drain 46 junction, the source 11 201003849 pole/drain 46 of the preferred PMOS transistor 32 will protrude slightly from the semiconductor substrate 30. The upper surface; however, the source/drain 46 may be flush with the upper surface of the semiconductor substrate 30 or lower than the upper surface of the semiconductor substrate 30, and is not limited thereto. As shown in Fig. 4, the NMOS transistor 34' is then covered with a mask (not shown) and subjected to a carbon implantation process to implant the source/drain 46 of the PMOS transistor 32. The carbon is doped, and a carbon doped layer 60 is formed in the upper half of the source/drain 46, and has a thickness of between about 100 angstroms and 500 angstroms, preferably about 200 angstroms. It is between 300 angstroms. The implantation energy of the carbon implantation process may be determined according to a predetermined implantation depth, for example, between 1 KeV and 5 KeV, and the dose may be between 1〇13 and 1016 atoms/cm2, preferably. The implantation energy is about 2KeV, and the preferred implantation dose is about 1.05xl015 atom/cm2; however, the method of the present invention is not limited to implanting only the carbon dopant in the source/drain 46 of the PMOS transistor 32. The carbon implantation process is performed on the NMOS transistor 34 and the PMOS transistor 32. An optional annealing process, such as a rapid thermal process (RTP), is used to activate the implanted carbon dopant at a high temperature of 1000 ° C to 1050 ° C and simultaneously repair The lattice structure of the surface of the damaged semiconductor substrate 30 in the carbon implantation process. Then, a self-aligned silicide (salicide) process is performed to form a metal lithium 62 on the surface of the source/drain electrodes 40, 46, for example, a metal cerium compound containing nickel, and the like. And the thickness of the metal telluride 62 is between about 50 angstroms and 500 angstroms, preferably 12 201003849 is between about 100 angstroms and 300 angstroms thick. The processes for forming the metal telluride 62 are those skilled in the art or are familiar with The skilled artisan is well known and will not be described here. As shown in FIG. 5, a first liner layer 64, a tensile stress film 65, and a surface treatment process, such as a rapid thermal processing process or a UV curing process, are sequentially formed. The tensile stress buffer film 65 is strengthened, followed by deposition of a second liner layer 70, wherein the tensile stress film 65 is a multi-layered stress film comprising a tensile stress buffer film 66 and a high tensile stress film 68. And wherein the tensile stress buffer film 66 has a tensile stress value that is smaller than the high tensile stress film 68. In addition, the present invention can also selectively remove the sidewalls 58 of the PMOS transistor 32 and the NMOS transistor 34 before forming a first liner layer 64, a tensile stress film 65, and a second liner layer 70. The tensile stress film 65 can more effectively adjust the lattice arrangement of the channel region of the NMOS transistor 34. Referring to FIG. 6, after the second liner layer 70 is formed, a photoresist coating, exposure, and development process is performed to form a first patterned photoresist 72 to cover the NMOS transistor 34 and perform an etching process. The process, such as an anisotropic etch process, uses the first patterned photoresist 72 as an etch mask, removes the tensile stress buffer film 66 overlying the PMOS transistor 32, the high tensile stress film 68, and the second liner. The layer 70, and in the etching process, the first liner layer 64, which is made of oxygen 13 201003849, is used as the I-stop layer to protect the underlying PMOS transistor 32. Next, as shown in FIG. 7, after the first patterned photoresist 72 is removed, a high compressive stress film 74 is formed. For example, a high compressive stress film 74 is deposited in a comprehensive manner by using an electric reinforced chemical vapor deposition process. The PMOS transistor 32 and the NMOS transistor 34 are covered. Then, as shown in Fig. 8, a photoresist coating, exposure, and development process is again performed to form a second patterned photoresist 76 and cover the entire PMOS transistor 32. Then, an etching process is performed to remove the region not covered by the second patterned photoresist layer 76, that is, the high compressive stress film 74 covering the NMOS transistor 34, and the second patterned photoresist 76 as an etch mask. The two liner layers 70 retain only a portion of the high compressive stress film 74 overlying the gate structure 38B and source/drain 46 surfaces of the PMOS transistor 32. Then, as shown in FIG. 9, the second patterned photoresist layer 76 overlying the PMOS transistor 32 is removed. Thus, one of the CMOS transistors 78 fabricated by the method of the present invention completes the basic fabrication process. The high compressive stress film 74 overlying the PMOS transistor 32 and the tensile stress film 65 overlying the NMOS transistor 34 can be used as a contact hole etch stop layer of the CMOS transistor 78. The high tensile stress film 68 and the high compressive stress film 74 may then be covered with an inter-layer dielectric layer (ILD layer) (not shown), and then patterned using a patterned light 14 201003849 (not shown) Illustrated as a etched mask and an anisotropic etch process, forming a plurality of contact holes in the interlayer dielectric layer and the tensile stress film 65 and the high compressive stress film 74 as the contact hole etch stop layer A contact hole (not shown) serves as a bridge connecting the gate structures 38A, 38B of the PMOS transistor 32 and the NMOS transistor 34, or the source/drain electrodes 40, 46 to other electronic components. Please refer to FIG. 10 , which is a schematic flowchart of a method for fabricating a CMOS transistor of the present invention, comprising the following steps: Step 100 : providing a semiconductor substrate defining at least one PMOS transistor and at least one NMOS transistor. And one of the source/drain electrodes of the PMOS transistor is a germanium compound epitaxial; step 102: performing a carbon implantation process on the source/drain of the PMOS transistor to form a carbon doped layer The upper half of the source/drain of the PMOS transistor; V step 104: performing a self-aligned metal telluride process to form a metal telluride on the source/drain surface of the PMOS transistor and the NMOS transistor Step 106: forming a tensile stress film comprising a tensile stress buffer film and a high tensile stress film, and the tensile stress buffer film has a tensile stress value less than the high tensile stress film; Step 108: performing a surface treatment a process, such as a rapid thermal processing process or an ultraviolet curing process, to strengthen the tensile stress film; 15 201003849 Step 110: removing a portion of the PMOS transistor formed on the stretch Force film; Step 112: forming a high compressive stress film to completely cover the PMOS transistor and NMOS transistor; and a step 114: removing the portion formed on the NMOS transistor of the high compressive stress films. In addition, when the CMOS transistor 78 of the present invention is fabricated, the tensile stress film 65 on the PMOS transistor 32 can be retained while the process step of saving the process is considered, and the high compressive stress film 74 is selectively formed to cover the PMOS transistor. 32. Please refer to Fig. 11, which is an electron micrograph of a CMOS transistor 78 fabricated by the method of the present invention. Referring to FIG. 2 and FIG. 11 together, it can be found that the surface of the CMOS i transistor 10 fabricated by the conventional method has a phenomenon of external expansion, thereby forming black spots on the surface of the nickel ruthenium layer 26. However, in the CMOS transistor 78 fabricated by the method of the present invention, no black spots were observed on the surface of the metal telluride 62. In order to avoid the occurrence of enthalpy expansion, the present invention first implants a carbon atom having an atomic radius smaller than 矽 and being electrically neutral in a PMOS transistor 32 which is epitaxially grown with bismuth compound before metal bismuth 62 is formed. In the source/drain 16 of the 201003849 46, a tensile stress buffer film 66 is formed between the high tensile stress film 68 and the metal telluride 62. It has been found through experiments that, when only the tensile stress buffer film 66 is formed, as the thickness of the tensile stress buffer film 66 increases, the effect of suppressing the expansion of the crucible is better, but the thickening of the tensile stress buffer film 66 is not advantageous for the CMOS transistor. 78 ion gain effect; therefore, in combination with the carbon implantation process, the doped carbon atoms stay in the crystal lattice of the bismuth compound, which not only increases the stability of the compound crystal of the compound, but also The thickness of the tensile stress buffer film 66 is reduced to ensure the effect of the ion gain of the CMOS transistor 78. Thus, the present invention is formed by the carbon doping layer 60 formed on the surface of the source/drain 46 of the PMOS transistor 32. And the tensile stress buffer layer 66 effectively suppresses the 锗-extension of the source/drain 46 of the PMOS transistor 32. However, if the carbon atoms of the carbon implantation process are replaced by other inert dopants which are electrically neutral and whose atomic radius is smaller than 矽, such as argon (Ar), bismuth, indium (In), and The effect of suppressing the error spread as shown in the present invention cannot be achieved.
U 此外，形成於PMOS電晶體32之源極/汲極46上半部 的碳摻雜層並不限於本較佳實施例所示，在形成金屬矽化 物前，進行碳佈植製程將碳植入PMOS電晶體32之源極/ 汲極46。碳摻雜層亦可在形成源極/汲極46的過程中加入， 例如在重摻雜製程植入P型摻質到半導體基底30之前，或 者在重摻雜製程後，進行碳佈植製程，將碳植入PMOS電 晶體32之源極/汲極46 ;此外亦可在以選擇性磊晶成長製 17 201003849 程形成做為PMOS電晶體32之源極/汲極46的矽鍺化合物 為晶的過程中直接加入碳做為蟲晶的材料之·一 5例如’在 形成^夕錯化合物遙晶的初期先加入少罝的碳做為推質’並 在矽鍺化合物磊晶形成的製程中，逐漸增加碳摻雜的比 例，因而在源極/汲極上半部形成碳摻雜層，且其碳摻質的 濃度相較於下半部先形成的矽鍺化合物磊晶内的碳摻質濃 度高，之後再形成一伸張應力緩衝薄膜以及一高伸張應力 ， 薄膜在CMOS電晶體表面，以期達成遏止鍺外擴的效果。 同時，在含有碳摻雜的矽鍺化合物磊晶形成後，亦可進行 本發明所揭示之製作CMOS電晶體的方法，選擇性地進行 碳佈植製程，以增加碳原子在PMOS電晶體之源極/汲極上 半部的掺質濃度。 以本發明所述之方法係在CMOS電晶體源極/汲極表 面的金屬矽化物形成前，先以碳佈植製程在PMOS電晶體 之源極/汲極的上半部植入相當濃度的碳原子，在源極/汲極 上半部，特別是接近表面的地方形成碳摻雜層，之後再形 成金屬石夕化物以及具有伸張或壓縮應力的钱刻停止層於 NMOS電晶體或PMOS電晶體上，以完成CMOS電晶體的 製作。此外，以本發明之方法所形成之CMOS電晶體，經 歷自行對準金屬矽化物製程、回火製程或快速熱處理製程 等高溫製程的過程中，碳摻雜層可具有阻障的功能，使得 PMOS源極/汲極内的鍺不會發生外擴的情形；其次，以本 18 201003849 發明之方法所製作之CMOS電晶體，無需在金屬矽化物與 源極/汲極間形成矽蓋層（silicon cap)，因此做為PMOS電晶 體源極/汲極的矽鍺化合物磊晶在侧壁子附近能保有斜角 (facet)，以便提供適度的壓縮應力擠壓PMOS電晶體的通 道區域，以達成提高載子在通道區域的遷移率。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 , 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為一習知之CMOS電晶體的示意圖。 第2圖為習知之CMOS電晶體的電子顯微鏡照片。 第3圖至第9圖係依據本發明之一較佳實施例所繪示之 CMOS電晶體的製作方法示意圖。 第10圖係為製作本發明之可遏止鍺外擴的CMOS電晶體 ( V 的流程示意圖。 第11圖為以本發明所述之方法所製作之CMOS電晶體的 電子顯微鏡照片。 【主要元件符號說明】 10 CMOS電晶靡 1 12 PMOS電晶體 14 NMOS電晶谱 1 16 基底 18 P型井 20A、20B 源極/汲極 19 201003849 22A 、 22B 閘極結構 24 N型井 26 錄化碎層 28 高伸張應力薄 膜 30 半導體基底 32 PMOS電晶體 34 NMOS電晶體 36 P型井 38A、38B 閘極結構 40 源極/沒極 44 N型井 46 源極/汲極 48 淺溝隔離 50 閘極介電層 52 閘極 54 硬遮罩層 56 熱氧化層 58 側壁子 60 碳摻雜層 62 金屬矽化物 64 第一襯墊層 65 伸張應力薄膜 66 伸張應力緩衝 薄膜 68 高伸張應力薄 膜 70 第二襯墊層 72 第一圖案化光 阻 74 高壓縮應力薄 膜 76 第二圖案化光 阻 78 CMOS電晶體 20Further, the carbon doped layer formed on the upper half of the source/drain 46 of the PMOS transistor 32 is not limited to that shown in the preferred embodiment, and the carbon implantation process is performed before the metal germanide is formed. The source/drain 46 of the PMOS transistor 32 is incorporated. The carbon doped layer may also be added during the process of forming the source/drain 46, for example, before the heavily doped process implants the P-type dopant into the semiconductor substrate 30, or after the heavily doped process, the carbon implantation process is performed. The carbon is implanted into the source/drain 46 of the PMOS transistor 32. Alternatively, the germanium compound formed as the source/drain 46 of the PMOS transistor 32 can be formed by selective epitaxial growth. In the process of crystallizing, carbon is directly added as a material for insect crystals. For example, 'in the early stage of forming the crystal of the compound, the first carbon is added as a pusher' and the process of epitaxial formation of the antimony compound is formed. Medium, gradually increasing the proportion of carbon doping, thus forming a carbon doped layer in the upper half of the source/drain, and the concentration of the carbon dopant is compared with the carbon doping in the epitaxial formation of the bismuth compound formed in the lower half. The high concentration is high, and then a tensile stress buffer film and a high tensile stress are formed. The film is on the surface of the CMOS transistor to achieve the effect of suppressing the external expansion. Meanwhile, after epitaxial formation of a carbon-doped cerium compound, the method of fabricating a CMOS transistor disclosed in the present invention can also be performed to selectively perform a carbon implantation process to increase the source of carbon atoms in the PMOS transistor. The dopant concentration in the upper half of the pole/bungee. Prior to the formation of the metal telluride on the source/drain surface of the CMOS transistor, the method of the present invention implants a considerable concentration in the upper half of the source/drain of the PMOS transistor by a carbon implantation process. a carbon atom, forming a carbon doped layer in the upper part of the source/drain, especially near the surface, and then forming a metal-lithium compound and a stop layer having a tensile or compressive stress on the NMOS transistor or PMOS transistor On, to complete the fabrication of CMOS transistors. In addition, the CMOS transistor formed by the method of the present invention undergoes self-alignment in a high temperature process such as a metal telluride process, a tempering process or a rapid heat treatment process, and the carbon doped layer may have a barrier function, so that the PMOS The 源 transistor in the source/drain is not expanded; secondly, the CMOS transistor fabricated by the method of the invention of 2010 201003849 does not need to form a cap layer between the metal telluride and the source/drain. Cap), therefore, the bismuth compound epitaxial as the source/drain of the PMOS transistor can maintain a facet near the sidewall to provide a moderate compressive stress to squeeze the channel region of the PMOS transistor to achieve Increase the mobility of the carrier in the channel region. The above is only the preferred embodiment of the present invention, and all changes and modifications made by the invention in accordance with the invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view of a conventional CMOS transistor. Figure 2 is an electron micrograph of a conventional CMOS transistor. 3 to 9 are schematic views showing a method of fabricating a CMOS transistor according to a preferred embodiment of the present invention. Fig. 10 is a flow chart showing the CMOS transistor (V) of the present invention for suppressing the expansion of the ytterbium. Fig. 11 is an electron micrograph of the CMOS transistor fabricated by the method of the present invention. Description] 10 CMOS transistor 121 12 PMOS transistor 14 NMOS crystallography 1 16 substrate 18 P-well 20A, 20B source/drain 19 201003849 22A, 22B gate structure 24 N-well 26 recording fragment 28 High tensile stress film 30 Semiconductor substrate 32 PMOS transistor 34 NMOS transistor 36 P-well 38A, 38B Gate structure 40 Source/no-pole 44 N-well 46 Source/drain 48 Shallow trench isolation 50 Gate dielectric Layer 52 Gate 54 Hard Mask Layer 56 Thermal Oxide Layer 58 Sidewall 60 Carbon Doped Layer 62 Metal Telluride 64 First Liner Layer 65 Tensile Stress Film 66 Tensile Stress Buffer Film 68 High Tensile Stress Film 70 Second Liner Layer 72 first patterned photoresist 74 high compressive stress film 76 second patterned photoresist 78 CMOS transistor 20