JP2008227165A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method, which has a high dielectric body as a gate insulating film, and has a proper threshold voltage. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 101, gate insulating films 108, 109 composed of a high dielectric body with high specific inductive capacity higher than a silicon oxide film, being prepared on the semiconductor substrate 101, a first gate electrode 110a for an N-type FET containing an aluminum layer prepared on the gate insulating film, and a second gate electrode 110b for P-type FET composed of Ni<SB>X</SB>Si<SB>Y</SB>(X>Y), being prepared on the gate insulating film. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, in order to reduce EOT (Equivalent Oxide Thickness) of a gate insulating film (for example, 1.3 nm or less) and suppress leakage current, proposals have been made to employ a high dielectric constant material for the gate insulating film. The high dielectric constant material is, for example, a metal oxide film having a relative dielectric constant higher than that of a silicon oxide film, a metal silicate film (metal silicate film) having a relative dielectric constant higher than that of a silicon oxide film, or a nitride film thereof. .

  When a high dielectric constant material is used for the gate insulating film, the threshold voltage of the FET (Field-Effect Transistor) is shifted. In an n-type MISFET (Metal-Insulator Semiconductor FET), the threshold voltage can be adjusted to a relatively appropriate value by injecting phosphorus or arsenic into the gate electrode. On the other hand, in the p-type MISFET, even if boron or boron fluoride is implanted into the gate electrode, the threshold voltage is greatly shifted to the negative side, so that it is difficult to adjust to an appropriate value. Furthermore, the p-type MISFET using a high dielectric constant material for the gate insulating film has a reduced capacitance on the inversion side. A p-type MISFET having a large threshold voltage shifted to the negative side and a small inversion capacitance has a problem that a desired drain current cannot be secured.

  In order to cope with a decrease in the inversion capacitance, a technique that employs a metal as a material of the gate electrode is considered. Here, the metal includes not only a simple metal or an alloy but also a nitride or silicide thereof. In particular, a full silicide gate electrode using nickel silicide can form a good gate insulating film because there is no restriction on temperature conditions in the gate insulating film forming step. Furthermore, since such a full silicide gate electrode is not depleted, a large inversion capacitance can be obtained.

However, the threshold voltages of the n-type MISFET and the p-type MISFET having a full silicide gate electrode using nickel silicide are both shifted from an appropriate value.
YH Kim et al. “Systematic Study of Workfunction Engineering and Scavenging Effect Using HiSi Alloy FUSI Metal Gate with Advanced Gate Stacks” IEDM2005 27.6

  A semiconductor device having a high dielectric as a gate insulating film and having an appropriate threshold voltage and a method for manufacturing the same are provided.

In a semiconductor device according to an embodiment of the present invention, a semiconductor substrate is provided on the semiconductor substrate, and is formed on a gate insulating film made of a high dielectric having a relative dielectric constant higher than that of a silicon oxide film, and on the gate insulating film. A first gate electrode for an N-type FET including an aluminum layer provided; and a second gate electrode for a P-type FET provided on the gate insulating film and made of Ni _X Si _Y (X>Y); It has.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate insulating film made of a high dielectric material having a relative dielectric constant higher than that of a silicon oxide film on a semiconductor substrate, and forming polysilicon on the gate insulating film. Alternatively, a gate electrode material made of amorphous silicon is deposited, and a first gate electrode for an N-type FET and a second gate electrode for a P-type FET are formed by processing the gate electrode material into a gate electrode pattern, A nickel film is deposited on the second gate electrode, an aluminum film is deposited on the first gate electrode, and a titanium film, a vanadium film, a molybdenum film, a rhodium film, a hafnium film, or a tungsten film is deposited on the aluminum film. The aluminum film is segregated at the bottom of the first gate electrode by depositing and heat-treating. And wherein the TiSi ₂ film or VSi ₂ film or MoSi ₂ film or RhSi film or HfSi film or WSi ₂ film is formed on the aluminum film, a polysilicon or amorphous silicon of the second gate electrode _Ni X _Si Y (X > Y) comprising silicidation.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate insulating film made of a high dielectric material having a relative dielectric constant higher than that of a silicon oxide film on a semiconductor substrate, and forming polysilicon on the gate insulating film. Alternatively, a gate electrode material made of amorphous silicon is deposited, and a first gate electrode for an N-type FET and a second gate electrode for a P-type FET are formed by processing the gate electrode material into a gate electrode pattern, A first nickel film is deposited on the second gate electrode, an aluminum film is deposited on the first gate electrode, and a titanium film, vanadium film, molybdenum film, rhodium film, or hafnium film is deposited on the aluminum film. Alternatively, a tungsten film is deposited, and the titanium film, vanadium film, molybdenum film, rhodium film, A second nickel film deposited on um film or tungsten film, by heat treatment, the aluminum film is segregated, Ni _{X Si} Y (X ≧ on the aluminum film on the bottom of the first gate electrode Y / 2) is formed, and a TiSi ₂ film, a VSi ₂ film, a MoSi ₂ film, a RhSi film, a HfSi film, or a WSi ₂ film is formed on the silicide layer, and the second gate electrode Siliciding polysilicon or amorphous silicon to Ni _X Si _Y (X> Y / 2).

  The semiconductor device and the manufacturing method thereof according to the present invention have a high dielectric as a gate insulating film and have an appropriate threshold voltage.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
(First embodiment)
1 to 18 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment. First, as shown in FIG. 1, an STI (Shallow Trench Isolation) 102 is formed by forming a trench in a silicon substrate 101 and embedding a silicon oxide film in the trench. A sacrificial oxide film 103 is formed on the surface of the silicon substrate 101.

  Next, as shown in FIG. 2, the n-type MISFET formation region is covered with a photoresist 104. In order to form an n-type well, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type MISFET formation region. Note that phosphorus is implanted not only for forming the diffusion layer but also for adjusting the threshold voltage of the transistor. Boron ions, indium ions, or the like may be implanted for fine adjustment of the threshold voltage of the transistor. Subsequently, as shown in FIG. 3, fluorine ions are implanted into the surface of the p-type MISFET formation region.

  Next, as shown in FIG. 4, the p-type MISFET formation region is covered with a photoresist 105. In order to form a p-type well, a p-type impurity (for example, boron) is ion-implanted into the n-type MISFET formation region. Note that boron is implanted not only for forming a diffusion layer but also for adjusting the threshold voltage of the transistor. In some cases, arsenic ions or phosphorus ions are implanted for fine adjustment of the threshold voltage of the transistor. Subsequently, as shown in FIG. 5, nitrogen ions are implanted into the surface of the n-type MISFET formation region. By thermally diffusing these impurities, an n-type well 106, a p-type well 107, a fluorine-containing layer 201, and a nitrogen-containing layer 203 are formed as shown in FIG. The fluorine-containing layer 201 and the nitrogen-containing layer 203 are formed on the surface portions of the p-type well 107 and the n-type well 106, respectively. The fluorine-containing layer 201 has a function of shifting the flat band potential to the positive side, and the nitrogen-containing layer 203 has a function of shifting the flat band potential to the negative side. Note that when the threshold voltage does not need to be lowered, the fluorine-containing layer 201 and the nitrogen-containing layer 203 do not need to be provided.

The sacrificial oxide film 103 is removed using an NH ₄ F aqueous solution. Immediately after the surface cleaning with 0.5 to 5% dilute hydrofluoric acid, a silicon oxide film 108 of about 0.5 nm to 0.8 nm is formed in an oxygen atmosphere. Further, a hafnium silicate film (HfSiO film) having a thickness of about 2.0 nm is formed on the silicon substrate 101 using tetrakisdiethylaminohafnium, diethylsilane, and oxygen.

Next, treatment is performed in a nitrogen plasma atmosphere or an NH ₃ atmosphere to add nitrogen to the HfSiO film, and then heat treatment is performed to modify the HfSiO film into a hafnium silicate nitride (HfSiON) film 109. Thereby, the structure shown in FIG. 7 is obtained. The HfSiON film 109 and the silicon oxide film 108 function as a gate insulating film. The gate insulating film 109 may be HfSiON, ZrSiO, ZrSiON, HfZrSiO, or HfZrSiON instead of the HfSiON film.

  Next, as shown in FIG. 8, an amorphous silicon film or a polysilicon film 110 is deposited on the HfSiON film 109 as a gate electrode material by using a CVD (Chemical Vapor Deposition) method.

  Next, a silicon oxide film or silicon nitride film (hereinafter referred to as a mask material) 115 is deposited on the amorphous silicon film or the polysilicon film 110 as a mask material. Subsequently, the mask material 115 is patterned into a gate electrode pattern by using a photolithography technique.

  Next, as shown in FIG. 9, using the mask material 115 as a hard mask, the amorphous silicon film or the polysilicon film 110 is processed into a gate electrode pattern. The first gate electrode of the n-type MISFET obtained at this time is 110a, and the second gate electrode of the p-type MISFET is 110b. At this time, the first gate electrode 110a and the second gate electrode 110b are made of amorphous silicon or polysilicon.

  Further, as shown in FIG. 10, the HfSiON film 109 is removed with dilute hydrofluoric acid or the like using the mask material 115 and the gate electrodes 110a and 110b as a mask. At this time, the hydrofluoric acid concentration and the etching time are selected so that the mask material 115 is not completely etched. That is, the etching solution and the etching time are appropriately determined based on the film type and film thickness of the high dielectric (in this embodiment, the HfSiON film 109). For example, the hydrofluoric acid concentration is preferably 1% or less, and the etching time is preferably 300 seconds or less. Since the silicon oxide film 108 is very thin, about 0.5 nm to 0.8 nm, it is usually removed by etching the HfSiON film 109. However, there is no problem even if the silicon oxide film 108 remains on the surface of the silicon substrate 101. The high dielectric is a material having a relative dielectric constant higher than that of the silicon oxide film and the silicon nitride film.

  Next, the side surfaces of the gate electrode materials 110a and 110b and the surface of the silicon substrate 101 are slightly oxidized. At this time, oxidation treatment was performed at about 1000 ° C. for about 5 seconds in an atmosphere containing about 0.2% oxygen. The oxide film thus formed had a thickness of about 2 nm. Thereafter, as shown in FIG. 11, an offset spacer 116 made of a silicon oxide film or a silicon nitride film is formed by using the CVD method and the RIE method. Further, sidewall spacers 121 and 122 made of a silicon oxide film and a silicon nitride film are formed by CVD and RIE, respectively.

  Next, using an photolithography technique, the n-type MISFET formation region is covered with a photoresist (not shown), and p-type impurities (for example, boron) are ion-implanted into the p-type MISFET formation region. Similarly, by using photolithography technology, the p-type MISFET formation region is covered with a photoresist, and n-type impurities (for example, phosphorus or arsenic) are ion-implanted into the n-type MISFET formation region.

  After removing the photoresist, the silicon substrate 101 is heat-treated to activate the impurities, thereby forming a p-type source / drain diffusion layer 117 and an n-type source / drain diffusion layer 118 as shown in FIG. The

  Next, after the sidewalls 121 and 122 are removed, the n-type MISFET formation region is covered with a photoresist (not shown) by using a photolithography technique, and the p-type MISFET formation region is covered with a p-type impurity (for example, boron). Ion implantation. Similarly, by using photolithography technology, the p-type MISFET formation region is covered with a photoresist, and n-type impurities (for example, phosphorus or arsenic) are ion-implanted into the n-type MISFET formation region.

  After removing the photoresist, the silicon substrate 101 is heat-treated to activate the impurities, thereby forming a p-type extension region 119 and an n-type extension region 120 as shown in FIG. Subsequently, halo implantation may be performed to suppress the short channel effect.

  Next, the sidewalls 121 and 122 are formed again on the side surfaces of the gate electrode materials 110a and 110b by using the CVD method and the RIE method. In this embodiment, a two-layer film of a silicon oxide film and a silicon nitride film is used as the sidewall. However, a three-layer film in which a silicon oxide film and a silicon nitride film are stacked may be used as the sidewall. Furthermore, a single layer film made of only a silicon nitride film may be used as the sidewall. The sidewall structure may be formed in accordance with the device.

  In the present embodiment, as described above, the ion implantation of the extension diffusion layer is performed after the ion implantation of the source / drain diffusion layer. This is to suppress the short channel effect by preventing excessive diffusion of the extension diffusion layer. However, the extension diffusion layer may be formed before forming the source / drain diffusion layer. In this case, it is not necessary to remove the sidewalls 121 and 122 once, so that the manufacturing process is shortened.

  Next, as shown in FIG. 12, a source / silicide film / drain / silicide film 123 (hereinafter referred to as an SD silicide layer) is formed on the surfaces of the source / drain diffusion layers 117 and 118 in a self-aligning manner. The material of the SD silicide film 123 may be any one of NiPtSix, NiSix, PtSi (used for the p-type MISFET region), ErSi (used for the n-type MISFET region), NiErSi (used for the n-type MISFET region), and the like.

  Next, as shown in FIG. 13, a silicon nitride film 124 is deposited by CVD, and a silicon oxide film 125 is further deposited thereon. The silicon nitride film 124 functions as an etch stopper. Subsequently, the silicon oxide film 125 is planarized using a CMP method, a dry etching method, or a wet etching method. At this time, the upper surfaces of the gate electrodes 110a and 110b are exposed by polishing the silicon oxide film 125, the silicon nitride film 124, and the hard mask 115.

Next, as shown in FIG. 14, a nickel film 126 is deposited. The thickness of the nickel film 126 is 1.1 times or more the thickness of the gate electrode 110b. Accordingly, the second gate electrode 110b can be silicided to Ni _X Si _Y (X> Y) in a later thermal process. For example, when the thickness of the nickel film 126 is 1.1 to 1.4 times the thickness of the gate electrode 110b, the second gate electrode 110b can be silicided to Ni ₂ Si. When the thickness of the nickel film 126 is 1.65 times or more the thickness of the gate electrode 110b, the second gate electrode 110b can be silicided to Ni ₃ Si or Ni ₃₁ Si ₁₂ .

  Subsequently, a silicon nitride film 310 is deposited on the nickel film 126. The silicon nitride film 310 on the N-type MISFET region is removed using a lithography technique and an RIE method. Further, by etching the nickel film 126 using the silicon nitride film 310 as a mask, the second gate electrode 110b remains covered with the nickel film 126 as shown in FIG. Expose the top surface.

  Next, as shown in FIG. 16, an aluminum film 320 is deposited on the n-type and P-type MISFET regions, and a titanium film 330 is deposited on the n-type MISFET region and the P-type MISFET region.

The structure shown in FIG. 16 is heat-treated at a temperature of 400 ° C. to 500 ° C. As a result, as shown in FIG. 17, the aluminum layer is segregated at the bottom of the first gate electrode 110a, and a titanium silicide (TiSi ₂ ) layer 112a is formed on the aluminum layer 111a. The second gate electrode 110b is silicided to Ni _X Si _Y (X> Y). As shown in FIG. 17, when the second gate electrode 110b is large, the second gate electrode 110b is considered to be formed of Ni ₃₁ Si ₁₂ or Ni ₃ Si.

In the first gate electrode 110a, an aluminum layer 111a and a titanium silicide 112a are formed as follows. In the thermal process, the aluminum layer 320 diffuses into the silicon without being silicided. Thereby, the mixture of silicon and aluminum comes into contact with the titanium layer 330. Since the titanium layer 330 reacts with silicon and is silicided, only silicon in the mixture of silicon and aluminum is absorbed to the titanium layer 330 side. As a result, the aluminum layer 111a is segregated under the first gate electrode 110a, and a titanium silicide (TiSi ₂ ) layer 112a is formed on the aluminum layer 111a.

In the second gate electrode 110b, the nickel film 126 is silicided to Ni _X Si _Y (X> Y) by reacting with silicon. Ni _X Si _Y is, for example, Ni ₂ Si, Ni ₃ Si, or Ni ₃₁ Si ₁₂ .

  Here, the thickness of the aluminum film 320 is preferably equal to or slightly smaller than the thickness of the first gate electrode 110a made of polysilicon or amorphous silicon. Thus, the thickness of the aluminum film 111a formed after the heat treatment is equal to or slightly smaller than the thickness of the first gate electrode 110a made of polysilicon or amorphous silicon. That is, the height level of the upper surface of the aluminum film 111a is equal to or slightly lower than the height level of the upper surfaces of the spacers 116 and 121, the sidewall film 122, and the like. Thereby, the aluminum film 111a is closed with the titanium silicide 112a. As a result, in the step of removing the unreacted aluminum film 320 and the unreacted titanium film 330, the aluminum film 111a is not etched. That is, the titanium silicide 112a functions as a protective film for the aluminum film 111a. The titanium silicide 112a can protect the aluminum film 111a even in the contact hole forming step. Further, the titanium silicide 112a also functions as an antioxidant film for the aluminum film 111a.

The thickness of the titanium film 330 is preferably at least ½ of the thickness of the first gate electrode 110a made of polysilicon or amorphous silicon. As a result, the titanium film 330 can absorb the entire polysilicon or amorphous silicon in the first gate electrode 110a and form a titanium silicide (TiSi ₂ ) layer 112a. In the present embodiment, the titanium film is used. However, the same effect can be obtained by using a vanadium film, a molybdenum film, a rhodium film, a hafnium film, or a tungsten film instead of the titanium film.

  The silicon nitride film 310 functions as a separation film that separates the nickel film 126 from the aluminum film 320 and the titanium film 330. By providing the silicon nitride film 310, the second gate electrode 110b can be silicided independently of the first gate electrode 110a.

  Next, as shown in FIG. 18, the unreacted titanium film 330 and the unreacted aluminum film 320 are removed. The titanium silicide layer 112a may be left to protect the aluminum layer 111a as described above, but may be removed from the viewpoint of the work function of an N-type MISFET described later.

  Thereafter, using a known method, an interlayer insulating film (not shown) is deposited, contacts are formed on the interlayer insulating film, and wirings and the like are further formed. In the subsequent process, the semiconductor device according to the first embodiment is completed by annealing using a forming gas.

The semiconductor device according to the first embodiment is provided on a silicon substrate 101, a silicon substrate 101, a gate insulating film 109 made of HfSiO, HfSiON, ZrSiO, ZrSiON, HfZrSiO, or HfZrSiON, and a gate insulating film 109. The first gate electrode 110a including the aluminum layer 111a and the second gate electrode 110b provided on the gate insulating film 109 and made of Ni _X Si _Y (X> Y) are provided. A titanium silicide film 112a may be provided on the aluminum layer 111a. The second gate electrode 110b can be formed of any of Ni ₂ Si, Ni ₃ Si, or Ni ₃₁ Si ₁₂ . Further, a nitrogen-containing layer 203 is provided on the surface of the semiconductor substrate under the first gate electrode 110a, and a fluorine-containing layer 201 is provided on the surface of the semiconductor substrate under the second gate electrode 110b.

The effect of the semiconductor device having the above configuration will be described with reference to FIG. FIG. 19 is a graph showing work functions of the gate electrodes of the p-type MIS and the n-type MIS according to the first embodiment. When the gate electrode is made of nickel silicide having a composition of Ni ₂ Si as in the first embodiment, the work function of the gate electrode is about 4.70 eV.

The second gate electrode 110b of the p-type FET is provided with a fluorine-containing layer 201 in the channel region below it. Since the flat band potential is shifted to the positive side due to the fluorine-containing layer 201, the apparent work function of the second gate electrode 110b is 5.02 eV or more and falls within the range of the region Rp. When the second gate electrode 110b is made of Ni ₃ Si, the work function of the second gate electrode 110b is 4.80 eV, and when the second gate electrode 110b is made of Ni ₃₁ Si ₁₂ , the second gate The work function of the electrode 110b is 4.85 eV. Further, when the fluorine-containing layer 201 is provided, the apparent work function of the second gate electrode 110b is 5.10 eV (in the case of Ni ₃ Si) and 5.15 eV (in the case of Ni ₃₁ Si ₁₂ ). Therefore, even when the second gate electrode 110b is made of Ni ₃ Si or Ni ₃₁ Si ₁₂ , the apparent work function of the second gate electrode 110b is sufficiently within the range of the region Rp.

Ni ₃ Si and Ni ₃₁ Si ₁₂ have a higher work function than Ni ₂ Si. Therefore, from the viewpoint of work function, the second gate electrode 110b is preferably composed of Ni ₃ Si or Ni ₃₁ Si ₁₂ rather than Ni ₂ Si.

However, Ni ₂ Si has a lower nickel content than Ni ₃ Si and Ni ₃₁ Si ₁₂ . Therefore, Ni ₂ Si is not easily etched when removing unreacted nickel in the silicide process of the second gate electrode 110b. Furthermore, Ni ₂ Si has a lower specific resistance than Ni ₃ Si and Ni ₃₁ Si ₁₂ . Therefore, the second gate electrode 110b made of _Ni 2 Si will lower resistance than the second gate electrode 110b made of _Ni 3 Si or _Ni 31 _{Si 12.} Furthermore, Ni ₂ Si has a smaller volume expansion than Ni ₃ Si or Ni ₃₁ Si ₁₂ . Therefore, the second gate electrode 110b made of Ni ₂ Si is not easily deformed. Thus, from the viewpoint of ease of manufacture, it can be said that the second gate electrode 110b is preferably Ni ₂ Si rather than Ni ₃ Si or Ni ₃₁ Si ₁₂ .

  The first gate electrode 110a of the n-type MIS is an aluminum layer 111a. In this case, the work function of the first gate electrode 110a is 4.20 eV. Even if the titanium silicide layer 112a is provided on the aluminum layer 111a, the work function of the first gate electrode 110a does not change. Further, since the nitrogen-containing layer 203 having a function of shifting the flat band potential to the negative side is provided in the channel region, the work function of the gate electrode is sufficiently within the range of the region Rn. Thus, even when a high dielectric is used as the gate insulating film, the threshold voltages of the p-type MISFET and the n-type MISFET can be set to appropriate values.

  The shift amount of the flat band potential is affected by the ion implantation used for adjusting the threshold voltage and the ion implantation of fluorine or nitrogen. For example, the shift amount of the entire flat band potential is the sum of the shift amount due to counter ion implantation for adjusting the threshold voltage and the shift amount due to fluorine or nitrogen implantation.

  In the p-type FET, the fluorine concentration has a peak at the interface between the channel and the gate insulating film, and the mobility of the p-type FET increases. Thereby, there is an advantage that the reliability is further improved.

In the n-type FET, nitrogen diffuses under the gate insulating film. In the use of a normal n-type FET, the gate electric field becomes a high electric field of about 0.6 MV / cm ² or more. When used in such a high gate electric field, the mobility can be increased even if nitrogen diffuses under the gate insulating film. As a result, both the p-type FET and the n-type FET have no deterioration in mobility on the high electric field side, and high mobility is maintained, so that a high drain current can be obtained.

  Usually, the modulation of the work function means that the flat band potential is shifted by changing the composition of the gate electrode or the impurity concentration. However, in the first embodiment, the flat band potential is shifted by changing the impurity concentration of the channel region. In this specification, the shift of the flat band potential due to the change of the channel region is also included in the “work function modulation”. This kind of work function modulation is called “apparent work function modulation”.

  In the first embodiment, HfSiON is used as the gate insulating film. However, HfSiO may be employed as the gate insulating film instead of HfSiON. Further, Hr may be replaced with Zr, and ZrSiO or ZrSiON may be employed as the gate insulating film. Furthermore, HfZrSiO or HfZrSiON containing both Hf and Zr may be employed as the gate insulating film. These gate insulating films may further contain Ti, La, or Ta.

  HfSiON is superior in heat resistance compared to HfSiO. However, it is possible to employ HfSiO as the gate insulating film by shortening the heat treatment time in the manufacturing process.

  In general, miniaturization of a large-scale integrated circuit is accompanied by thinning of a gate insulating film. For example, when the gate length is 40 nm or less, the EOT (Equivalent Oxide Thickness) of the gate insulating film must be 1.3 nm or less. Under such circumstances, when a silicon oxide film or a silicon oxynitride film is used as the gate insulating film, the leakage current increases. For this reason, it has been studied to employ a metal oxide film or metal silicate film having a relative dielectric constant higher than that of a silicon oxide film or silicon oxynitride film, or the use of these nitride films as a gate insulating film.

  When such a high dielectric is used for the gate insulating film, there arises a problem that the threshold voltage of the MISFET shifts. In particular, in the P-type MISFET, the threshold voltage is greatly shifted to the negative side. There is also a problem that the capacity of the inversion layer is small and the drain current is small.

  In order to cope with these problems, it has been studied to employ a metal gate electrode. The metal in this case includes not only a single metal or an alloy but also a nitride or silicide thereof. In particular, a full silicide gate using nickel silicide can ensure a large inversion capacity. However, since the work function of nickel monosilicide (NiSi) is 4.5 eV, it is difficult to obtain a work function in the vicinity of the Si band gap necessary for the N-type FET and the P-type FET.

The present embodiment employs aluminum for the gate electrode of the N-type FET, and uses nickel-rich silicide (Ni _X Si _Y (X> Y)) for the gate electrode of the P-type FET. The above problem can be solved while adopting the gate insulating film. That is, the semiconductor device according to the present embodiment can sufficiently reduce the threshold voltages of the N-type MISFET and the P-type MISFET while suppressing the leakage current even if the gate length is reduced to 40 nm or less.

(Second Embodiment)
The second embodiment is different from the first embodiment in that a nickel layer 340 is deposited on the titanium layer 330 as shown in FIG. 20 after the steps shown in FIGS. Thereafter, heat treatment is performed at a temperature of 400 ° C. to 500 ° C. as in the first embodiment. As a result, as shown in FIG. 21, the aluminum layer 111a is segregated at the bottom of the first gate electrode 110a. A nickel silicide (NiSi ₂ ) layer 113a is formed on the aluminum layer 111a, and a titanium silicide (TiSi ₂ ) layer 112a is formed on the nickel silicide layer 113a. The second gate electrode 110b is silicided to Ni _X Si _Y (X> Y) as in the first embodiment.

  Next, as shown in FIG. 22, the unreacted nickel film 340, the unreacted titanium film 330, and the unreacted aluminum film 320 are removed. Thereafter, as in the first embodiment, an interlayer insulating film, contacts, wirings, and the like are formed using a known method. In the post-process, the semiconductor device according to the second embodiment is completed by annealing using a forming gas.

  The film thickness of the aluminum layer 320 is preferably less than or equal to half the film thickness of the first gate electrode 110a made of amorphous silicon or polysilicon so that the aluminum layer 111a and the aluminum film 320 are not connected. This is because if the aluminum layer 111a and the aluminum layer 320 are connected, the aluminum layer 111a may be etched when the unreacted aluminum layer 320 is removed.

  The thickness of the titanium film 330 is preferably 5 nm to 30 nm. This is because when the titanium film 330 is thicker than that, nickel in the nickel film 340 cannot diffuse through the titanium film 330 and pass through the titanium film 330.

Thickness _{T Ni} of the nickel film 340 _is preferably a _{T Ni ≧ 0.55 (T Si -T} Al). T _Si is the thickness of the first gate electrode 110 a made of amorphous silicon or polysilicon, and T _Al is the thickness of the aluminum film 320. When the film thickness T _Ni of the nickel film 340 satisfies T _Ni ≧ 0.5 (T _Si —T _Al ), the nickel silicide layer 113a formed between the aluminum layer 111a and the titanium silicide layer 112a has Ni _X Fully silicided to Si _Y (X> Y / 2). For example, the nickel silicide layer 113a _is, NiSi _2, NiSi, may be fully silicided _{Ni 31 Si 12, Ni 3 Si} .

  In the heat treatment, the aluminum film 320 diffuses into amorphous silicon or polysilicon (110a) and segregates under the first gate electrode 110a. The nickel film 340 passes through the titanium film 330 and reacts with silicon. Thereby, the nickel silicide film 113a is formed on the aluminum layer 111a. Further, the titanium film 330 absorbs amorphous silicon or polysilicon, and a titanium silicide layer 112a is formed on the nickel silicide film 113a. The first gate electrode 110a shown in FIG. 22 is formed in this way.

  In the second embodiment, the nickel silicide film 113a covers the aluminum layer 111a, and the titanium silicide layer 112a covers the nickel silicide film 113a. Thereby, the aluminum layer 111a is more completely protected. For example, the aluminum layer 111a can be better prevented from being etched when the aluminum film 320 is removed.

  Since the nickel silicide layer 113a and the titanium silicide layer 112a are conductive materials, they may be left in the finished product.

The first gate electrode 110a according to the second embodiment includes a silicide layer 113a made of Ni _x Si _Y (X ≧ Y / 2) provided on the aluminum layer 111a and a titanium silicide provided on the silicide layer 113a. Layer 112a. Other configurations of the second embodiment may be the same as those of the first embodiment.

The first and second gate electrodes according to the second embodiment have work functions similar to those of the first embodiment. Therefore, the second embodiment can obtain the same effects as those of the first embodiment. Note that the work function of the first gate electrode 110a is determined by the aluminum layer 111a provided at the bottom thereof, so the composition of the silicide layer 113a may be NiSi ₂ or NiSi.

  In the second embodiment, the titanium film 330 is used, but the same effect can be obtained by using a vanadium film, a molybdenum film, a rhodium film, a hafnium film, or a tungsten film instead of the titanium film.

Sectional drawing which shows the manufacturing method of the semiconductor device by 1st Embodiment. Sectional drawing which shows the manufacturing method of a semiconductor device following FIG. FIG. 3 is a cross-sectional view illustrating the method for manufacturing the semiconductor device following FIG. 2. FIG. 4 is a cross-sectional view illustrating the method for manufacturing the semiconductor device following FIG. 3. FIG. 5 is a cross-sectional view illustrating the method for manufacturing the semiconductor device following FIG. 4. FIG. 6 is a cross-sectional view illustrating the method for manufacturing the semiconductor device following FIG. 5. Sectional drawing which shows the manufacturing method of a semiconductor device following FIG. FIG. 8 is a cross-sectional view illustrating the method for manufacturing the semiconductor device following FIG. 7. FIG. 9 is a cross-sectional view showing the method for manufacturing the semiconductor device following FIG. 8. FIG. 10 is a cross-sectional view illustrating the method for manufacturing the semiconductor device following FIG. 9. FIG. 11 is a cross-sectional view illustrating the method for manufacturing the semiconductor device following FIG. 10. FIG. 12 is a cross-sectional view illustrating the method for manufacturing the semiconductor device following FIG. 11. FIG. 13 is a cross-sectional view showing the method for manufacturing the semiconductor device following FIG. 12. FIG. 14 is a cross-sectional view illustrating the method for manufacturing the semiconductor device following FIG. 13. FIG. 15 is a cross-sectional view illustrating the method for manufacturing the semiconductor device following FIG. 14. FIG. 16 is a cross-sectional view showing the method for manufacturing the semiconductor device following FIG. 15. FIG. 17 is a cross-sectional view showing the method for manufacturing the semiconductor device following FIG. 16. FIG. 18 is a cross-sectional view showing the method for manufacturing the semiconductor device following FIG. 17. The graph which shows the work function of each gate electrode of p-type MIS and n-type MIS by 1st Embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device by 2nd Embodiment. FIG. 21 is a cross-sectional view showing the method for manufacturing the semiconductor device following FIG. 20. FIG. 22 is a cross-sectional view showing the method for manufacturing the semiconductor device following FIG. 21.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Semiconductor substrate 109 ... HfSiON film 110a ... 1st gate electrode 111a ... Aluminum layer 112a ... Titanium silicide layer 110b ... 2nd gate electrode 201 ... Fluorine-containing layer 203 ... Nitrogen-containing layer 320 ... Aluminum film 330 ... Titanium film

Claims (5)

A semiconductor substrate;
A gate insulating film made of a high dielectric material provided on the semiconductor substrate and having a relative dielectric constant higher than that of the silicon oxide film;
A first gate electrode for an N-type FET including an aluminum layer provided on the gate insulating film;
A semiconductor device comprising: a second gate electrode for a P-type FET that is provided on the gate insulating film and made of Ni _X Si _Y (X> Y). The first gate electrode further comprises a TiSi ₂ film, a VSi ₂ film, a MoSi ₂ film, a RhSi film, a HfSi film, or a WSi ₂ film provided on the aluminum layer. Semiconductor device. The first gate electrode further includes a silicide layer made of Ni _X Si _Y (X ≧ Y / 2) provided on the aluminum layer and a TiSi ₂ film provided on the silicide layer. The semiconductor device according to claim 1. A gate insulating film made of a high dielectric material having a relative dielectric constant higher than that of a silicon oxide film is formed on a semiconductor substrate,
Depositing a gate electrode material made of polysilicon or amorphous silicon on the gate insulating film,
Forming a first gate electrode for an N-type FET and a second gate electrode for a P-type FET by processing the gate electrode material into a gate electrode pattern;
Depositing a nickel film on the second gate electrode;
Depositing an aluminum film on the first gate electrode;
A titanium film, a vanadium film, a molybdenum film, a rhodium film, a hafnium film, or a tungsten film is deposited on the aluminum film;
By performing heat treatment, the aluminum film is segregated at the bottom of the first gate electrode, and a TiSi ₂ film, VSi ₂ film, MoSi ₂ film, RhSi film, HfSi film, or WSi ₂ film is formed on the aluminum film. A method of manufacturing a semiconductor device comprising: forming and siliciding polysilicon or amorphous silicon of the second gate electrode into Ni _X Si _Y (X> Y). A gate insulating film made of a high dielectric material having a relative dielectric constant higher than that of a silicon oxide film is formed on a semiconductor substrate,
Depositing a gate electrode material made of polysilicon or amorphous silicon on the gate insulating film,
Forming a first gate electrode for an N-type FET and a second gate electrode for a P-type FET by processing the gate electrode material into a gate electrode pattern;
Depositing a first nickel film on the second gate electrode;
Depositing an aluminum film on the first gate electrode;
A titanium film, a vanadium film, a molybdenum film, a rhodium film, a hafnium film, or a tungsten film is deposited on the aluminum film;
Depositing a second nickel film on the titanium film, vanadium film, molybdenum film, rhodium film, hafnium film or tungsten film;
By performing heat treatment, the aluminum film is segregated at the bottom of the first gate electrode, and a silicide layer made of Ni _x Si _Y (X ≧ Y / 2) is formed on the aluminum film, and the silicide layer A TiSi ₂ film, a VSi ₂ film, a MoSi ₂ film, an RhSi film, an HfSi film, or a WSi ₂ film is formed thereon, and the polysilicon or amorphous silicon of the second gate electrode is made of Ni _X Si _Y (X> Y / 2). And 4) a method for manufacturing a semiconductor device.

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