JP2008243942A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for improving performance of a semiconductor device equipped with a MIS transistor where a whole region of a gate electrode is silicificated. <P>SOLUTION: A gate insulating film 502, a gate electrode 503 and source/drain regions 506 of the MIS transistor are formed on a semiconductor substrate 501. A diffusion suppression film 511 for suppressing diffusion of a metal required for silicide reaction is formed on the source/drain regions 506. A metal film 531 formed of the metal whose diffusion is suppressed by the diffusion suppression film 511 is formed on the gate electrode 503 and the diffusion suppression film 511. The metal film 531 and the gate electrode 503 are made to react to each other and the whole region of the gate electrode 503 is silicificated. The metal film 531 and the source/drain regions 506 are made to react to each other through the diffusion suppression film 511, and the source/drain regions 506 are silicificated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a MIS transistor in which an entire region of a gate electrode is silicided and a method for manufacturing the same.

  In a MIS transistor typified by a MOS transistor, depletion of the gate electrode increases the effective thickness of the gate insulating film. Therefore, in order to improve transistor performance, depletion of the gate electrode must be suppressed. desirable. Therefore, a full silicide (FUSI) technology for siliciding the entire region of the gate electrode made of polysilicon has been proposed. This technique has good consistency with the conventional process flow, and is considered as a promising means for suppressing depletion of the gate electrode. A gate electrode whose entire region is silicided is called a FUSI gate electrode.

  In general, a MIS transistor having a FUSI gate electrode has a problem that it is difficult to adjust its threshold voltage. In particular, when a high dielectric film (for example, HfSiON film) is used for the gate insulating film and the entire region of the gate electrode is formed of NiSi (nickel silicide), the threshold voltage becomes considerably higher than a normally used value. It is difficult to obtain a practical MIS transistor.

Therefore, Non-Patent Documents 1 and 2 propose a technique for adjusting the threshold voltage of both transistors by changing the metal composition ratio of the silicide constituting the gate electrode between the NMOS transistor and the PMOS transistor. . In the techniques of Non-Patent Documents 1 and 2, NiSi is used for the silicide of the gate electrode in the NMOS transistor, and Ni ₃ Si is used for the silicide of the gate electrode in the PMOS transistor. Since the work function of Ni ₃ Si is about 300 mV higher than that of NiSi, the threshold value of the PMOS transistor can be reduced.

  As described above, a semiconductor device in which the metal composition ratio of the silicide constituting the gate electrode is different between the NMOS transistor and the PMOS transistor can be manufactured by, for example, the method disclosed in Non-Patent Document 2. In the manufacturing method of Non-Patent Document 2, just before the FUSI process, only the gate electrode of the PMOS transistor is etched out of the gate electrodes of the NMOS transistor and the PMOS transistor, and the film thickness is reduced. The metal composition ratio of the silicide at the gate electrode is changed.

  Patent Documents 1 to 3 also disclose techniques related to a MIS transistor having a FUSI gate electrode.

  Patent Documents 4 and 5 disclose techniques related to a MIS transistor having a gate electrode containing silicide.

  Patent Documents 6 and 7 propose a technique for improving the performance of the MIS transistor by generating local strain in the channel region of the MIS transistor using a silicon nitride film.

Kensuke Takahashi et al., “Dual Workfunction Ni-Silicide / HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45nm-node LSTP and LOP Devices”, IEDM Tech. Dig., 2004, p.91 A. Lauwers et al., “CMOS Integration of Dual Work Function Phase Controlled Ni FUSI with Simultaneous Silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) Gates on HfSiON”, IEDM Tech. Dig., 2005, p.661 JP 2005-150267 A JP 2006-114681 A JP 2006-196646 A Japanese Patent Laid-Open No. 11-11980 JP 2004-39943 A JP 2005-5633 A Japanese Patent Laid-Open No. 2003-60076

  Now, it is necessary to form the source / drain region of the MIS transistor as shallow as possible for miniaturization of the semiconductor device. Generally, in the case of a 65-nm transistor, the thickness (depth) of the source / drain region is It is difficult to make it larger than 30 nm. On the other hand, the thickness of the gate electrode of the MIS transistor is used to prevent impurities from penetrating through the gate electrode and entering the channel region below it during ion implantation when forming the source / drain regions, and other reasons. Therefore, in general, it is difficult to set the transistor to 80 nm or less for a 65 nm generation transistor.

  As described above, since the thickness of the source / drain region is much smaller than the thickness of the gate electrode, it is difficult to simultaneously silicide the gate electrode and the source / drain region. In other words, if both gates are simultaneously silicided to match the thickness of the gate electrode, the silicide layer in the source / drain region becomes too thick and leakage current increases, and conversely, both are silicided simultaneously according to the depth of the source / drain region. As a result, the entire region of the gate electrode cannot be silicided.

  Therefore, conventionally, after the silicidation of the source / drain regions is performed, the entire region of the gate electrode is silicided. However, in this method, the heat treatment performed when the gate electrode is silicided causes the silicide in the source / drain regions to agglomerate, increasing the electrical resistance of the source / drain regions, or causing a large variation in the electrical resistance. Sometimes it becomes.

  As described above, when manufacturing a semiconductor device in which the metal composition ratio of silicide at the gate electrode is different between the N-type MIS transistor and the P-type MIS transistor, conventionally, the gate electrode of the P-type MIS transistor is etched. And the film thickness is made small. Since there is no structure serving as an etching stopper in the gate electrode, it is difficult to keep the etching amount for the gate electrode of the P-type MIS transistor constant within the wafer surface or between lots. For this reason, the height of the gate electrode of the P-type MIS transistor before full silicidation tends to vary within the wafer surface or from lot to lot. This causes variations in the amount of silicon that reacts with the metal during silicidation, and as a result, the metal composition ratio of the silicide at the gate electrode of the P-type MIS transistor becomes unstable.

  Further, in a technique for generating local strain in the channel region of the MIS transistor using a silicon nitride film, it is desired to further improve the performance of the MIS transistor by increasing the amount of strain in the channel region.

  Therefore, the present invention has been made in view of the above points, and an object thereof is to provide a technique for improving the performance of a semiconductor device including a MIS transistor in which the entire region of the gate electrode is silicided.

  In the method of manufacturing a semiconductor device according to the embodiment of the present invention, the source / drain regions of the MIS transistor are formed in the upper surface of the semiconductor substrate, and the gate insulating film and the gate electrode of the MIS transistor are formed on the upper surface of the semiconductor substrate. It is formed by laminating in this order. Then, on the source / drain regions, a diffusion suppressing film that suppresses diffusion of metal necessary for the silicide reaction is formed. Next, a metal film made of a metal that suppresses diffusion is formed on the gate electrode and the diffusion suppression film. After that, the metal film and the gate electrode are reacted to silicidize the entire region of the gate electrode, and the metal film and the source / drain region are reacted via the diffusion suppression film to silicidize the source / drain region. To do.

  In the method of manufacturing a semiconductor device according to another embodiment of the present invention, the source / drain regions of the N-type MIS transistor and the P-type MIS transistor are formed in the upper surface of the semiconductor substrate, and the upper surface of the semiconductor substrate is formed. A gate insulating film and a gate electrode of each of the N-type MIS transistor and the P-type MIS transistor are stacked in this order. Next, a diffusion suppressing film that suppresses the diffusion of the metal necessary for the silicide reaction is formed on the gate electrode of the N-type MIS transistor. A metal film made of a metal that suppresses diffusion is formed on the diffusion suppression film and the gate electrode of the P-type MIS transistor. Thereafter, the metal film and the gate electrode of the N-type MIS transistor are reacted through the diffusion suppression film, and the metal film and the gate electrode of the P-type MIS transistor are reacted to form the gate electrode of the P-type MIS transistor. The entire region of each gate electrode of the N-type MIS transistor and the P-type MIS transistor is silicided so that the metal composition ratio of the silicide is larger than the metal composition ratio of the silicide formed on the gate electrode of the N-type MIS transistor. It becomes.

  In the method of manufacturing a semiconductor device according to another embodiment of the present invention, the gate insulating film and the gate electrode of each of the N-type MIS transistor and the P-type MIS transistor are stacked in this order on the upper surface of the semiconductor substrate. It is formed. Then, the gate electrode of the N-type MIS transistor is silicided. Next, a diffusion blocking film is formed on the gate electrode of the N-type MIS transistor to block the diffusion of metal necessary for the silicide reaction. Then, a metal film made of a metal that prevents diffusion from being formed on the diffusion blocking film and the gate electrode of the P-type MIS transistor is formed. Thereafter, a silicide reaction is caused between the metal film and the gate electrode of the P-type MIS transistor. In the obtained structure, the entire region of the gate electrode of each of the N-type MIS transistor and the P-type MIS transistor is silicided, and the metal composition ratio of silicide formed in the P-type MIS transistor is equal to that of the N-type MIS transistor. It is larger than the metal composition ratio of silicide formed in the gate electrode.

  In the semiconductor device according to the embodiment of the present invention, the gate electrode of the MIS transistor whose entire region is silicided is formed on the semiconductor substrate. The source / drain regions of the MIS transistor are formed on the semiconductor substrate. A silicon oxide film is formed on the side surface of the gate electrode. A single silicon nitride film is formed from the silicon oxide film to the source / drain regions so as to be in contact with the silicon oxide film and the source / drain regions.

  According to the method of manufacturing a semiconductor device according to the embodiment of the present invention, since the diffusion suppression film that suppresses the diffusion of the metal necessary for the silicide reaction is formed on the source / drain region, it is formed relatively shallow. The silicidation of the source / drain regions and the full silicidation of the relatively thick gate electrode can be performed in the same process. As a result, it is possible to suppress unnecessary heat from being applied to the silicide in the gate electrode and the source / drain regions, and to suppress deterioration of the characteristics of the silicide. Therefore, the performance of the MIS transistor is improved. Further, since the process of supplying metal from the metal film to the gate electrode and the source / drain region is only required for silicidation, the method for manufacturing the semiconductor device can be simplified.

  Further, according to the method of manufacturing a semiconductor device according to another embodiment of the present invention, the gate electrode of the P-type MIS transistor is etched by using the diffusion suppression film that suppresses the diffusion of the metal necessary for the silicide reaction. Without this, the metal composition ratio of the silicide formed on the gate electrode can be changed between the N-type MIS transistor and the P-type MIS transistor. Therefore, it is possible to prevent instability of the metal composition ratio of the silicide at the gate electrode due to the variation in the etching amount with respect to the gate electrode of the P-type MIS transistor. As a result, the performance of the semiconductor device is improved.

  Further, according to the method of manufacturing a semiconductor device according to another embodiment of the present invention, the gate electrode of the P-type MIS transistor is etched by using the diffusion blocking film that blocks the diffusion of the metal necessary for the silicide reaction. Without this, the metal composition ratio of the silicide formed on the gate electrode can be changed between the N-type MIS transistor and the P-type MIS transistor. Therefore, it is possible to prevent instability of the metal composition ratio of the silicide at the gate electrode due to the variation in the etching amount with respect to the gate electrode of the P-type MIS transistor. As a result, the performance of the semiconductor device is improved.

  In addition, according to the semiconductor device of one embodiment of the present invention, a single silicon nitride film is formed from the silicon oxide film to the source / drain regions so as to be in contact with the silicon oxide film and the source / drain regions. Therefore, the silicon nitride film in contact with the source / drain regions can be disposed close to the channel region of the MIS transistor. Therefore, the amount of strain formed in the channel region of the MIS transistor due to the silicon nitride film can be increased. Therefore, the performance of the MIS transistor can be improved.

Embodiment 1 FIG.
1 to 8 are cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. In the first embodiment, a method for manufacturing a semiconductor device including a MIS transistor having a FUSI gate electrode will be described.

  First, a silicon oxide film is formed on a semiconductor substrate 501 that is a silicon substrate, and a polysilicon film is formed with a thickness of, for example, about 100 nm on the silicon oxide film. Then, a silicon nitride film is formed on the polysilicon film with a thickness of about 40 nm, for example. Next, a photoresist having a predetermined opening pattern is formed on the silicon nitride film, and the silicon nitride film, the polysilicon film, and the silicon oxide film are sequentially etched and partially removed using the photoresist as a mask. To do. Thereby, as shown in FIG. 1, a gate insulating film 502 made of a silicon oxide film, a gate electrode 503 made of a polysilicon film, and a hard mask film 504 made of a silicon nitride film are laminated in this order on the semiconductor substrate 501. Formed.

  Next, using the gate insulating film 502, the gate electrode 503, and the hard mask film 504 as a mask, a conductivity type impurity corresponding to the conductivity type of the MIS transistor is introduced into the semiconductor substrate 501 by an ion implantation method, for example. As a result, as shown in FIG. 1, an extension region 506a to be a part of the source / drain region of the MIS transistor is formed. Within the upper surface of the semiconductor substrate 501, two extension regions 506a are formed apart from each other. The gate insulating film 502, the gate electrode 503, and the hard mask film 504 are stacked on the semiconductor substrate 501 between the two extension regions 506a.

  Next, a silicon nitride film is formed on the entire surface of the semiconductor substrate 501 so as to cover the gate insulating film 502, the gate electrode 503, and the hard mask film 504. Then, the silicon nitride film is etched using an anisotropic dry etching method having a high etching rate in the thickness direction of the semiconductor substrate 501. As a result, as shown in FIG. 1, sidewalls 505 made of a silicon nitride film are formed on the side surfaces of the gate insulating film 502, the gate electrode 503, and the hard mask film 504 so as to cover the ends of the extension regions 506a. The

  Next, using the gate insulating film 502, the gate electrode 503, the hard mask film 504, and the side wall 505 as a mask, a conductivity type impurity corresponding to the conductivity type of the MIS transistor is introduced into the semiconductor substrate 501 by an ion implantation method, for example. To do. Thus, an impurity region 506b having a higher impurity concentration than the extension region 506a and deeper than the extension region 506a is formed in the semiconductor substrate 501 so as to be connected to the extension region 506a. As a result, as shown in FIG. 2, source / drain regions 506 including extension regions 506a and impurity regions 506b are formed. Thereafter, an annealing process for activating the impurities in the source / drain regions 506 is performed.

  Next, as shown in FIG. 2, a diffusion suppression film 511 that suppresses diffusion of a metal necessary for the silicidation reaction, for example, nickel (Ni), is formed on the entire surface with a thickness of about 1 nm to 15 nm (for example, 4 nm). For example, the diffusion suppression film 511 is formed using a deposition method such as a CVD (Chemical Vapor Deposition) method. As a result, a diffusion suppression film 511 is formed on the source / drain region 506. The diffusion suppression film 511 is made of, for example, a silicon nitride film.

  Next, as shown in FIG. 3, an insulating film 521 made of, for example, a silicon oxide film is formed on the diffusion suppressing film 511 with a thickness of about 500 nm. Then, the insulating film 521 is polished from the upper surface by a CMP (Chemical Mechanical Polishing) method using the hard mask film 504 as a stopper film. As a result, the hard mask film 504 is exposed as shown in FIG. The diffusion suppression film 511 is formed of a silicon nitride film as in the case of the hard mask film 504. However, since the film thickness is small, the diffusion suppression film 511 cannot be used as a stopper film in the CMP method, and is on the hard mask film 504. The diffusion suppressing film 511 is polished together with the insulating film 521.

  Next, the exposed hard mask film 504 is removed by, for example, dry etching to expose the gate electrode 503. Then, the remaining insulating film 512 is removed by wet etching using hydrofluoric acid.

  Next, as shown in FIG. 5, a metal film 531 made of a metal that suppresses diffusion by the diffusion suppression film 511 is formed on the entire surface with a thickness of about 200 nm. As a result, a metal film 531 is formed on the gate electrode 503 and the diffusion suppression film 511. The metal film 531 is made of nickel, for example.

Next, the obtained structure is heat-treated at about 280 ° C. to 400 ° C. (for example, 300 ° C.) for several minutes. As a result, a silicide reaction occurs between the metal film 531 and the gate electrode 503 in contact therewith, and a silicide layer 513 made of Ni ₂ Si is formed from the center to the upper end of the gate electrode 503 as shown in FIG. Is done. At the same time, the metal film 531 and the source / drain region 506 undergo a silicide reaction via the diffusion suppressing film 511, and a silicide made of Ni ₂ Si is formed at the upper end of the source / drain region 506 as shown in FIG. Layer 516 is formed. On the source / drain region 506, the diffusion suppression film 511 is present with a thickness of slightly less than 4 nm (because it is exposed to hydrofluoric acid when removing the insulating film 521, it is slightly thinner than immediately after deposition). Since the diffusion of nickel constituting the metal film 531 into the source / drain region 506 is suppressed by the diffusion suppressing film 511, the silicide layer 516 in the source / drain region 506 is more than the silicide layer 513 in the gate electrode 503. Thinly formed. Therefore, as in the first embodiment, the relatively thick gate electrode 503 and the relatively thin source / drain regions 506 can be silicided simultaneously. Thereafter, the metal film 531 that has not reacted with silicon is removed by wet etching using, for example, a mixed liquid of phosphoric acid and nitric acid. At this time, the diffusion suppressing film 511 made of the silicon nitride film is removed by phosphoric acid.

  Next, the obtained structure is subjected to heat treatment for several tens of seconds at a temperature of 400 ° C. or higher, which is higher than the heat treatment temperature in the previous silicidation. For example, heat treatment is performed at 500 ° C. As a result, nickel diffuses in the gate electrode 503 and the source / drain region 506 to cause a silicide reaction, and the entire region of the gate electrode 503 is formed of NiSi as shown in FIG. A silicide layer 526 made of NiSi is formed in the source / drain region 506. The thickness of the silicide layer 526 is, for example, 35 nm or less.

  Next, as shown in FIG. 8, a first interlayer insulating film 561 made of, for example, a silicon nitride film and a second interlayer insulating film 562 made of, for example, a silicon oxide film are sequentially formed on the entire surface. Then, using the first interlayer insulating film 561 as an etching stopper, the second interlayer insulating film 562 is partially etched from its upper surface, thereby removing the exposed first interlayer insulating film 561. As a result, a plurality of contact holes 563 reaching the silicide layer 526 and the gate electrode 503 in the source / drain region 506 are formed in the first and second interlayer insulating films 561 and 562. Thereafter, a plurality of contact plugs 564 filling the plurality of contact holes 563 are formed.

  As described above, in the method of manufacturing a semiconductor device according to the first embodiment, the diffusion suppression film 511 that suppresses the diffusion of metal necessary for the silicide reaction is formed on the source / drain region 506. The silicidation of the source / drain region 506 formed relatively shallow and the full silicidation of the gate electrode 503 formed relatively thick can be performed in the same process. As a result, it is possible to suppress unnecessary heat from being applied to the silicide of the gate electrode 503 and the source / drain region 506, and to suppress deterioration of the characteristics of the silicide. Therefore, the performance of the MIS transistor is improved. In addition, since the process of supplying metal from the metal film 531 to the gate electrode 503 and the source / drain region 506 is performed only once for silicidation, the manufacturing method of the semiconductor device can be simplified.

  In the first embodiment, since the diffusion suppression film 511 made of a silicon nitride film is formed on the semiconductor substrate 501 by using a deposition method, the semiconductor substrate 501 is thermally nitrided to form a diffusion suppression film 511 made of a silicon nitride film. As compared with the case of forming the film, the processing temperature when forming the diffusion suppressing film 511 can be lowered. Therefore, it is possible to suppress the deterioration of the characteristics of the already formed source / drain region 506 due to the influence of the high processing temperature.

  In the first embodiment, the metal film 531 is made of nickel, but may be made of other metals such as cobalt, titanium, molybdenum, tungsten, palladium, and platinum.

  In the first embodiment, the diffusion suppressing film 511 is composed of a silicon nitride film. However, it may be composed of another film as long as it is a film that suppresses the diffusion of metal necessary for the silicide reaction. That is, the diffusion suppression film 511 is a film in which the amount of metal supplied from the metal film 531 to the source / drain region 506 is smaller than when the metal film 531 is formed directly on the source / drain region 506. I need it.

  In the first embodiment, NiSi is formed in the gate electrode 503 and the source / drain regions 506 by performing heat treatment at a relatively low temperature and heat treatment at a relatively high temperature twice. NiSi may be formed in the gate electrode 503 and the source / drain regions 506 by multiple heat treatments. That is, as shown in FIG. 5, after the metal film 531 is formed on the gate electrode 503 and the diffusion suppression film 511, heat treatment is performed at a high temperature of 400 ° C. or higher, so that the entire region of the gate electrode 503 and the source / drain regions are formed. NiSi may be formed at 506. In this case, since the heat treatment process for silicidation is only required once, the method for manufacturing the semiconductor device is simplified. However, the diffusion suppression effect on the metal necessary for the silicide reaction in the diffusion suppression film 511 made of a silicon nitride film is easier to control by the heat treatment at a low temperature. Therefore, as in the present embodiment, the diffusion suppression film 511 When the metal film 531 and the source / drain region 506 are reacted at a relatively low temperature via the gate, the thickness of the silicide formed in the source / drain region 506 can be easily adjusted.

  In Embodiment Mode 1, hydrofluoric acid is used when the insulating film 521 is removed. At this time, the sidewall 505 is also exposed to the hydrofluoric acid. Therefore, the sidewall 505 is preferably formed of a silicon nitride film that is selective with respect to hydrofluoric acid as in the first embodiment. However, when a silicon nitride film is directly formed on a semiconductor substrate 501 made of a silicon substrate, an interface state is formed on the surface of the semiconductor substrate 501 and the performance and reliability of the MIS transistor may be lowered. Therefore, the side wall 505 made of a silicon nitride film is used as the outer side wall 505, and as shown in FIG. 9, between the side wall 505 and the semiconductor substrate 501, and between the side wall 505 and the gate electrode 503, A sidewall 571 made of a silicon oxide film is formed. The sidewall 571 is formed by thermal oxidation instead of deposition. Specifically, immediately after the gate insulating film 502, the gate electrode 503, and the hard mask film 504 are formed, the exposed side surface of the gate electrode 503 and the exposed upper surface of the semiconductor substrate 501 are thermally oxidized. Then, a silicon oxide film having a thickness of about 1 to 10 nm is formed. Thereafter, a silicon nitride film is formed on the entire surface. Then, by performing anisotropic etching on the silicon nitride film and the silicon oxide film, a side wall 505 made of a silicon nitride film and a side wall 571 made of a silicon oxide film are formed. Since a silicon oxide film formed by thermal oxidation has higher selectivity to hydrofluoric acid than a silicon oxide film formed by a deposition method such as a CVD method, the insulating film 521 formed by the deposition method is used as the hydrofluoric acid. When removing by (1), the sidewall 571 can be prevented from being completely removed, and the sidewall 505 made of a silicon nitride film can be prevented from coming into direct contact with the semiconductor substrate 501.

Embodiment 2. FIG.
FIG. 10 is a sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the second embodiment includes an N-type MIS transistor 10n and a P-type MIS transistor 20p, and the metal composition ratio of silicide at the gate electrode 12n of the P-type MIS transistor 10n is N-type MIS transistor 20p. It is set to be larger than that at the gate electrode 22p.

  As shown in FIG. 10, an element isolation structure 2 is formed on a semiconductor substrate 1 which is a silicon substrate. The element isolation structure 2 is, for example, a silicon oxide film, and partitions on the semiconductor substrate 1 an active region where the N-type MIS transistor 10n is formed and an active region where the P-type MIS transistor 20p is formed. Each of the N-type MIS transistor 10n and the P-type MIS transistor 20p is, for example, a MOS transistor.

  In the upper surface of the semiconductor substrate 1, two source / drain regions 14n of the N-type MIS transistor 10n are formed apart from each other. In each source / drain region 14n, a silicide layer 15n made of, for example, NiSi is formed. Further, in the upper surface of the semiconductor substrate 1, two source / drain regions 24p of the P-type MIS transistor 20p are formed apart from each other. In each source / drain region 24p, a silicide layer 25p made of, for example, NiSi is formed.

On the semiconductor substrate 1 between the two source / drain regions 14n, the gate insulating film 11n and the gate electrode 12n of the N-type MIS transistor 10n are formed in this order. On the semiconductor substrate 1 between the two source / drain regions 24p, the gate insulating film 21p and the gate electrode 22p of the P-type MIS transistor 20p are stacked in this order. The gate electrodes 12n and 22p are both FUSI gate electrodes, and the gate electrode 22p is formed thicker than the gate electrode 12n. For example, the gate electrode 12n is made of NiSi, and the gate electrode 22p is made of Ni ₃ Si or Ni ₃₁ Si ₁₂ . Each of the gate insulating films 11n and 21p is made of, for example, a silicon oxide film.

  Sidewalls 13n are formed on the side surfaces of the gate insulating film 11n and the gate electrode 12n so as to cover the end portions of the source / drain regions 14n. Sidewalls 23p are formed on the side surfaces of the gate insulating film 21p and the gate electrode 22p so as to cover the end portions of the source / drain regions 24p. Each of the sidewalls 13n and 23p is made of, for example, a silicon oxide film.

  On the semiconductor substrate 1, a silicon nitride film is formed in contact with the sidewalls 13n and 23p and the silicide layers 15n and 25p so as to expose the upper surfaces of the sidewalls 13n and 23p and the upper surfaces of the gate electrodes 12n and 22p. 30 is formed. An interlayer insulating film 40 is formed on the silicon nitride film 30 and on the exposed portions of the sidewalls 13n and 23p and the gate electrodes 12n and 22p from the silicon nitride film 30. In the interlayer insulating film 40, a plurality of contact plugs 50 are formed in contact with the upper surfaces of the gate electrodes 12n and 22p, respectively. Further, in the interlayer insulating film 40 and the silicon nitride film 30, a plurality of contacts respectively contacting the silicide layer 15 n in one of the two source / drain regions 14 n and the silicide layer 25 p in one of the two source / drain regions 24 p. A contact plug 50 is formed. For example, the interlayer insulating film 40 is made of a silicon oxide film, and the contact plug 50 is made of a metal.

  In the semiconductor device according to the second embodiment, when tensile stress is generated in the silicon nitride film 30, tensile stress is also applied to the channel region of the N-type MIS transistor 10n formed in the lower portion of the gate electrode 12n in the semiconductor substrate 1. appear. As a result, the current drive capability of the N-type MIS transistor 10n is improved, and the performance is improved. On the other hand, when compressive stress is generated in the silicon nitride film 30, compressive stress is also generated in the channel region of the P-type MIS transistor 20p formed in the lower portion of the semiconductor substrate 1 below the gate electrode 22p. As a result, the current driving capability of the P-type MIS transistor 20p is improved, and the performance is improved.

  In a normal MIS transistor in which the gate electrode is not fully silicided, the silicon nitride film covering the gate electrode does not have a defective portion. However, in the semiconductor device according to the second embodiment, the gate electrodes 12n and 22p are not formed. The silicon nitride film 30 that should be completely covered is absent on the upper surfaces of the gate electrodes 12n and 22p. This is an inevitable structure for fully siliciding the gate electrodes 12n and 22p, as will be apparent from the following description. However, it has been confirmed by simulation and the like that the amount of distortion in the channel regions of the N-type MIS transistor 10n and the P-type MIS transistor 20p is not reduced by the lack of the silicon nitride film 30 on the upper surfaces of the gate electrodes 12n and 22p. Yes.

  In the second embodiment, the single layer of silicon nitride film 30 is formed from the sidewall 13n to the source / drain region 14n so as to be in contact with the sidewall 13n and the source / drain region 14n. Of the silicon nitride film 30 in contact with the region 14n, a portion provided on the side surface of the gate electrode 12n via the sidewall 13n can be disposed close to the channel region below the gate electrode 12n.

  On the other hand, as in the structure shown in FIG. 9 described above, a second sidewall made of a silicon nitride film is formed on the sidewall 13n, and is in contact with the second sidewall and the source / drain region 14n. Thus, when the silicon nitride film 30 is formed from the second sidewall to the source / drain region 14n, the gate electrode 12n and the silicon nitride are compared with the semiconductor device according to the second embodiment. Since the thickness of the film existing between the films 30 increases, the distance between the portion of the silicon nitride film 30 on the side surface of the gate electrode 12n and the channel region of the N-type MIS transistor 10n increases. As a result, the amount of distortion generated in the channel region of the N-type MIS transistor 10n is reduced.

  In the second embodiment, since the portion of the silicon nitride film 30 on the side surface of the gate electrode 12n can be arranged close to the channel region of the N-type MIS transistor 10n, the distortion in the channel region of the N-type MIS transistor 10n The amount can be increased. Therefore, when tensile stress is generated in the silicon nitride film 30, the performance of the N-type MIS transistor 10n can be improved.

  Similarly, since one layer of the silicon nitride film 30 is formed from the sidewall 23p to the source / drain region 24p so as to be in contact with the sidewall 23p and the source / drain region 24p, it is in contact with the source / drain region 24p. A portion of the silicon nitride film 30 on the side surface of the gate electrode 22p can be disposed close to the channel region of the P-type MIS transistor 20p. For this reason, the amount of distortion in the channel region of the P-type MIS transistor 20p can be increased. Therefore, when compressive stress is generated in the silicon nitride film 30, the performance of the P-type MIS transistor 20p can be improved.

  Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. 11 to 22 are cross-sectional views showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps. First, an element isolation structure 2 is formed on a semiconductor substrate 1 to form an active region (hereinafter referred to as an “N-type MIS transistor formation region”) where an N-type MIS transistor 10 n is formed and a P-type MIS transistor 20 p. An active region (hereinafter referred to as “P-type MIS transistor formation region”) is partitioned into the semiconductor substrate 1.

  Next, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1, and a polysilicon film is formed on the silicon oxide film with a thickness of about 30 to 60 nm (for example, 40 nm). Then, a silicon nitride film is formed on the polysilicon film with a thickness of about 30 to 90 nm (for example, 60 nm). The total value of the thickness of the polysilicon film and the thickness of the silicon nitride film thereon is preferably 80 nm or more.

  Next, a photoresist having a predetermined opening pattern is formed on the silicon nitride film, and the silicon nitride film, the polysilicon film, and the silicon oxide film are sequentially etched and partially removed using the photoresist as a mask. To do. Thus, as shown in FIG. 11, a gate insulating film 11n made of a silicon oxide film, a gate electrode 12n made of a polysilicon film, and a hard mask film 17n made of a silicon nitride film are laminated in this order on the semiconductor substrate 1. Formed. At the same time, a gate insulating film 21p made of a silicon oxide film, a gate electrode 22p made of a polysilicon film, and a hard mask film 27p made of a silicon nitride film are laminated on the semiconductor substrate 1 in this order.

  Next, the P-type MIS transistor formation region is covered with a photoresist, and the photoresist, the gate insulating film 11n, the gate electrode 12n, and the hard mask film 17n are used as a mask, for example, by ion implantation to form an N-type. Impurities of a conductivity type corresponding to the conductivity type of the MIS transistor 10n are introduced into the semiconductor substrate 1. As a result, as shown in FIG. 11, an extension region 114n to be a part of the source / drain region 14n of the N-type MIS transistor 10n is formed. In the upper surface of the semiconductor substrate 1, two extension regions 114n are formed apart from each other. The gate insulating film 11n, the gate electrode 12n, and the hard mask film 17n are stacked on the semiconductor substrate 1 between the two extension regions 114n.

  Next, the N-type MIS transistor formation region is covered with a photoresist, and the photoresist, the gate insulating film 21p, the gate electrode 22p, and the hard mask film 27p are used as a mask, for example, an ion implantation method to form a P-type. Impurities of a conductivity type corresponding to the conductivity type of the MIS transistor 20p are introduced into the semiconductor substrate 1. As a result, as shown in FIG. 11, an extension region 124p that becomes a part of the source / drain region 24p of the P-type MIS transistor 20p is formed. In the upper surface of the semiconductor substrate 1, two extension regions 124p are formed apart from each other. The gate insulating film 21p, the gate electrode 22p, and the hard mask film 27p are stacked on the semiconductor substrate 1 between the two extension regions 124p.

  Next, as shown in FIG. 12, a silicon oxide film 60 and a silicon nitride film 61 are formed in this order on the semiconductor substrate 1 so as to cover the gate insulating films 11n and 21p, the gate electrodes 12n and 22p, and the hard mask films 17n and 27p. Laminate. At this time, the silicon oxide film 60 is formed with a thickness of about 10 nm, and the silicon nitride film 61 is formed with a thickness of about 50 nm.

  Next, the silicon nitride film 61 and the silicon oxide film 60 are etched using an anisotropic dry etching method having a high etching rate in the thickness direction of the semiconductor substrate 1. Thus, as shown in FIG. 13, on the side surfaces of the gate insulating film 11n, the gate electrode 12n, and the hard mask film 17n, the sidewall 13n made of the silicon oxide film 60 is formed so as to cover the end of the extension region 114n. (Hereinafter referred to as “first sidewall 13n”) is formed, and a sidewall 16n (hereinafter referred to as “second sidewall 16n”) made of the silicon nitride film 61 is formed on the first sidewall 13n. The At the same time, on the side surfaces of the gate insulating film 21p, the gate electrode 22p, and the hard mask film 27p, a sidewall 23p made of the silicon oxide film 60 (hereinafter referred to as “first sidewall 23p”) is formed so as to cover the end of the extension region 124p. ”And a sidewall 26p made of the silicon nitride film 61 (hereinafter referred to as“ second sidewall 26p ”) is formed on the first sidewall 23p.

  Next, the P-type MIS transistor formation region is covered with a photoresist, and the photoresist, the gate insulating film 11n, the gate electrode 12n, the hard mask film 17n, the first sidewall 13n, and the second sidewall 16n are masked. Then, for example, an impurity of a conductivity type corresponding to the conductivity type of the N-type MIS transistor 10n is introduced into the semiconductor substrate 1 by an ion implantation method. Thus, an impurity region 115n having a higher impurity concentration than the extension region 114n and deeper than the extension region 114n is formed in the semiconductor substrate 1 so as to be connected to the extension region 114n. As a result, as shown in FIG. 14, source / drain regions 14n including extension regions 114n and impurity regions 115n are formed.

  Next, the N-type MIS transistor formation region is covered with a photoresist, and the photoresist, the gate insulating film 21p, the gate electrode 22p, the hard mask film 27p, the first sidewall 23p, and the second sidewall 26p are masked. Then, for example, an impurity of a conductivity type corresponding to the conductivity type of the P-type MIS transistor 20p is introduced into the semiconductor substrate 1 by an ion implantation method. Thus, an impurity region 125p having an impurity concentration higher than that of the extension region 124p and deeper than the extension region 124p is formed in the semiconductor substrate 1 so as to be connected to the extension region 124p. As a result, as shown in FIG. 14, source / drain regions 24p including extension regions 124p and impurity regions 125p are formed. Thereafter, annealing is performed to activate the impurities in the source / drain regions 14n and 24p.

  Next, a metal film made of nickel necessary for the silicide reaction is formed on the entire surface. Then, heat treatment is performed on the obtained structure to cause a silicide reaction between the metal film and each of the source / drain regions 14n and 24p. Thereafter, the unreacted metal film is removed. Thus, as shown in FIG. 15, a silicide layer 15n made of NiSi is formed in the source / drain region 14n, and a silicide layer 25p made of NiSi is formed in the source / drain region 24p. Since the hard mask films 17n and 27p made of a silicon nitride film are formed on the gate electrodes 12n and 22p, the silicide reaction at the gate electrodes 12n and 22p is suppressed.

  Next, as shown in FIG. 16, the hard mask films 17n and 27p made of a silicon nitride film and the second sidewalls 16n and 26p also made of a silicon nitride film are removed. At this time, isotropic dry etching selective to the silicon oxide film, NiSi, and silicon is performed. Therefore, only the exposed silicon nitride film is removed.

  In the above example, after the source / drain regions 14n and 24p are silicided, the hard mask films 17n and 27p and the second sidewalls 16n and 26p are removed by dry etching, but other methods may be used. . For example, before siliciding the source / drain regions 14n, 24p, the second sidewalls 16n, 26p made of a silicon nitride film are removed using phosphoric acid, and then the source / drain regions 14n, 24p are silicidized. The mask films 17n and 27p may be removed. In this case, when the hard mask films 17n and 27p are removed when the second sidewalls 16n and 26p are removed with phosphoric acid, the gate electrodes 12n and 12p are formed during the subsequent silicidation of the source / drain regions 14n and 24p. Since 22p is also silicided together, in order to prevent this, the hard mask films 17n and 27p are formed of a silicon oxide film selective to phosphoric acid. Since the first sidewalls 13n and 23p made of a silicon oxide film are formed under the second sidewalls 16n and 26p, respectively, after the second sidewalls 16n and 26p are removed with phosphoric acid, the gate electrodes 12n and 22p The side is never exposed.

  Next, as shown in FIG. 17, a silicon nitride film 30 and a silicon oxide film 41 are laminated on the entire surface in this order. At this time, the silicon nitride film 30 is formed with a thickness of about 10 to 50 nm (for example, 25 nm), and the silicon oxide film 41 is formed with a thickness of several hundreds of nm (for example, 250 nm).

  Next, the silicon oxide film 41 is polished from its upper surface by CMP using the silicon nitride film 30 as a stopper film. As a result, as shown in FIG. 18, the silicon nitride film 30 on the first sidewalls 13n and 23p and the gate electrodes 12n and 22p is exposed. Note that when the silicon nitride film 30 is exposed using the CMP method, a part of the gate electrodes 12n and 22p is formed due to a step formed between the upper surface of the semiconductor substrate 1 and the upper surface of the element isolation structure 2. When the silicon nitride film 30 is not exposed, the silicon oxide film 41 existing on the silicon nitride film 30 is removed by wet etching.

  Next, as shown in FIG. 19, the silicon nitride film 30 on the gate electrodes 12n and 22p is removed by using a dry etching method or a wet etching method to expose the gate electrodes 12n and 22p.

  Next, as shown in FIG. 20, a diffusion suppression film 100 that suppresses the diffusion of the metal required for the silicide reaction, in this example, nickel, is formed on the entire surface with a thickness of about 1 nm to 15 nm (for example, 3 nm). For example, the diffusion suppression film 100 is made of a silicon nitride film, and is formed using a plasma CVD method, an atomic layer deposition method (ALD: Atomic Layer Deposition), or the like. Thereafter, a photoresist 110 covering the N-type MIS transistor formation region is formed on the diffusion suppression film 100.

  Next, using the photoresist 110 as a mask, the diffusion suppressing film 100 exposed from the photoresist 110 is removed by etching. Thereby, as shown in FIG. 21, the diffusion suppression film 100 is formed on the upper surface of only the gate electrode 12n among the gate electrodes 12n and 22p. Thereafter, a metal film 120 made of nickel is formed on the entire surface with a thickness of about 100 nm.

  Next, heat treatment is performed on the obtained structure. As a result, the metal film 120 and the gate electrode 22p in contact therewith undergo a silicide reaction, and the entire region of the gate electrode 22p is silicided as shown in FIG. At the same time, the metal film 120 and the gate electrode 12n undergo a silicide reaction via the diffusion suppressing film 100, and the entire region of the gate electrode 12n is silicided as shown in FIG.

Here, in the present second embodiment, since the diffusion suppression film 100 is formed on the gate electrode 12n, the diffusion of nickel constituting the metal film 120 into the gate electrode 12n is suppressed by the diffusion suppression film 100. . Therefore, the amount of nickel supplied to the gate electrode 22p is larger than the amount of nickel supplied to the gate electrode 12n. Therefore, a large amount of nickel and silicon react in the gate electrode 22p as compared with the gate electrode 12n. As a result, the metal composition ratio of silicide at the gate electrode 22p is larger than that at the gate electrode 12n. That is, the gate electrode 22p is made of Ni ₃ Si or Ni ₃₁ Si ₁₂ and the gate electrode 12n is made of NiSi.

As in this example, when nickel and silicon are reacted through the diffusion suppressing film 100, NiSi ₂ that is normally formed only at high temperature annealing such as 700 ° C. or higher is formed by heat treatment at a relatively low temperature. Can be formed. NiSi ₂ has a work function smaller than that of NiSi, and thus is a preferable material for use in the FUSI gate electrode of the N-type MIS transistor. However, in general, after the step of forming the interlayer insulating film, the temperature is 700 ° C. or higher. Since heat treatment is not performed, it is difficult to form the FUSI gate electrode of the N-type MIS transistor with NiSi ₂ . However, as described above, when nickel is supplied to the gate electrode 12n through the diffusion suppressing film 100, the silicide reaction proceeds in the gate electrode 12n in a state where the amount of nickel supplied is small. NiSi ₂ can be formed on the gate electrode 12n even at a heat treatment temperature of about a degree.

  Further, since the volume expansion amount of the gate electrode increases according to the amount of the reacting metal, the gate electrode 22p becomes thicker than the gate electrode 12n after being fully silicided.

  Next, the metal film 120 unreacted with silicon is removed by wet etching using a mixed solution of phosphoric acid and nitric acid, for example. At this time, the diffusion suppression film 100 on the gate electrode 12n made of the silicon nitride film is removed by phosphoric acid. When a silicon oxide film is formed on the entire surface, an interlayer insulating film 40 composed of the silicon oxide film and the silicon oxide film 41 is completed. Thereafter, a plurality of contact holes are formed in the interlayer insulating film 40 and the silicon nitride film 30, and a plurality of contact plugs 50 filling the plurality of contact holes are formed. Thereby, the structure shown in FIG. 10 is completed.

  As described above, in the manufacturing method of the semiconductor device according to the second embodiment, the gate electrode 22p of the P-type MIS transistor 20p is formed by using the diffusion suppression film 100 that suppresses the diffusion of the metal necessary for the silicide reaction. The metal composition ratio of the silicide formed on the gate electrode can be changed between the N-type MIS transistor 10n and the P-type MIS transistor 20p without etching. Therefore, instability of the metal composition ratio of the silicide at the gate electrode 22p due to the variation in the etching amount with respect to the gate electrode 22p of the P-type MIS transistor 10n can be prevented. As a result, the performance of the semiconductor device is improved.

  In the technique of Non-Patent Document 2 described above, the gate electrode 22p of the P-type MIS transistor 20p needs to be etched. It is necessary to form a thick silicon film in advance.

  On the other hand, in the second embodiment, it is not necessary to etch the gate electrode 22p, so that the polysilicon film to be the gate electrodes 12n and 22p can be formed thin. Therefore, the thickness of the gate electrodes 12n and 22p can be reduced. When the thickness of the gate electrodes 12n and 22p is reduced, the thickness of the silicon oxide film 41 required for exposing the upper surfaces of the gate electrodes 12n and 22p covered with the silicon nitride film 30 can be reduced. For example, if the thickness of the gate electrodes 12n and 22p is set to about 100 nm as in the first embodiment, the thickness of the silicon oxide film 41 is required to be about 500 nm. However, as in the second embodiment, the gate If the thickness of the electrodes 12n and 22p is set to about 30 nm, the thickness of the silicon oxide film 41 may be about 200 nm. Further, in the second embodiment, the hard mask films 17n and 27p are removed before the silicon oxide film 41 is formed, so that the thickness of the silicon oxide film 41 can be further reduced. Therefore, variation in the film thickness of the silicon oxide film 41 immediately after film formation can be reduced. Furthermore, the polishing amount for the silicon oxide film 41 using the CMP method can be reduced, and variations in the polishing amount can be reduced. As a result, variation in the thickness of the silicon oxide film 41 after polishing can be reduced, and variation in exposure of the gate electrodes 12n and 22p in FIG. 19 can be reduced. When the exposure of the gate electrodes 12n and 22p varies, the amount of reaction with nickel at the gate electrodes 12n and 22p varies, and thus the variation in the exposure of the gate electrodes 12n and 22p is reduced as in the second embodiment. As a result, the metal composition ratio of the silicide at the gate electrodes 12n and 22p is stabilized.

  Further, in the structure shown in FIG. 19 described above, when the gate electrode 22p is etched to reduce the film thickness as in the technique of Non-Patent Document 2, not only the gate electrode 22p but also the surrounding first electrode The sidewalls 23p, the silicon nitride film 30, and the silicon oxide film 41 are also etched. Therefore, the degree of exposure of the gate electrode 22p varies depending on the variation in the etching amount with respect to the first sidewall 23p, the silicon nitride film 30, and the silicon oxide film 41. Further, when the gate electrode 22p is etched, the structure on the N-type MIS transistor formation region is masked with a photoresist, and the structure is not etched. Therefore, the structure on the N-type MIS transistor formation region and the formation of the P-type MIS transistor The height of the sidewall on the side surface of the gate electrode and the thicknesses of the silicon nitride film 30 and the silicon oxide film 41 are different between the regions. As a result, in the interlayer insulating film 40 and the silicon nitride film 30, it is difficult to form contact holes simultaneously on both the N-type MIS transistor formation region and the P-type MIS transistor formation region.

  In the second embodiment, since it is not necessary to etch the gate electrode 22p, such a problem does not occur, and variations in the degree of exposure of the gate electrode 22p can be reduced. Therefore, the metal composition ratio of silicide at the gate electrode 22p is stabilized. Further, it becomes easy to form contact holes in the interlayer insulating film 40 and the silicon nitride film 30 both on the N-type MIS transistor formation region and on the P-type MIS transistor formation region.

  Further, since the second sidewall 16n is formed by etching the silicon nitride film 61, the film thickness of the second sidewall 16n is not uniform. Specifically, since the second sidewall 16n is formed by etching the silicon nitride film 61 using an anisotropic etching method having a high etching rate in the thickness direction of the semiconductor substrate 1, the second side 16n is formed. The film thickness of the wall 16n increases from the top surface to the bottom surface of the gate electrode 12n (see FIG. 13 and the like). Therefore, as shown in FIG. 23, when the present semiconductor device is manufactured with the second sidewall 16n left on the side surface of the gate electrode 12n, the silicon nitride film 30 on the gate electrode 12n is removed. When the etching amount with respect to the second sidewall 16n increases, the degree of exposure of the gate electrode 12n greatly changes. Therefore, the degree of exposure of the gate electrode 12n varies greatly due to variations in the etching amount with respect to the second sidewall 16n. FIG. 23 corresponds to FIG. 19 described above.

  In the second embodiment, since the silicon nitride film 30 is formed on the entire surface after removing the second sidewall 16n, the film thickness of the silicon nitride film 30 is almost uniform on the side surface of the gate electrode 12n. . Therefore, when removing the silicon nitride film 30 on the gate electrode 12n, even if the amount of etching with respect to the silicon nitride film 30 on the side surface of the gate electrode 12n varies, variation in the degree of exposure of the gate electrode 12n is suppressed. be able to. Therefore, the metal composition ratio of silicide at the gate electrode 12n is stabilized. The same applies to the gate electrode 22p of the P-type MIS transistor 20p.

  As shown in FIG. 23, when the semiconductor device is manufactured without removing the second sidewalls 16n and 26p, the first sidewall 23p made of a silicon oxide film is formed around the gate electrode 22p. The second sidewall 26p made of a silicon nitride film, the silicon nitride film 30, and the silicon oxide film 41 are present, and the film structure around the gate electrode 22p is very complicated. Since the silicon oxide film and the silicon nitride film have different etching rates, and even if they are made of the same material, the etching rate differs depending on the film forming method. Therefore, the film structure around the gate electrode 22p is complicated as shown in FIG. There are many factors that cause unevenness in the peripheral structure of the gate electrode 22p. Therefore, the unevenness formed in the peripheral structure of the gate electrode 22p increases, and the exposure variation of the gate electrode 22p increases. As a result, the metal composition ratio of silicide at the gate electrode 22p becomes unstable.

  In the second embodiment, since the silicon nitride film 30 is formed after the second sidewall 26p is removed, the film structure around the gate electrode 22p is simplified compared to the structure shown in FIG. The Therefore, there are fewer factors that cause unevenness in the peripheral structure of the gate electrode 22p, and variation in unevenness formed in the peripheral structure of the gate electrode 22p can be reduced. Therefore, variation in the exposure degree of the gate electrode 22p can be reduced, and the metal composition ratio of silicide in the gate electrode 22p is stabilized.

  In the second embodiment, since the silicon nitride film 30 is formed on the entire surface after the second sidewall 16n is removed, the silicon nitride film 30 in contact with the source / drain region 14n of the N-type MIS transistor 10n is formed. Of these, the portion on the side surface of the gate electrode 12n can be disposed close to the channel region of the N-type MIS transistor 10n. As a result, the amount of distortion in the channel region of the N-type MIS transistor 10n can be increased. Therefore, when tensile stress is generated in the silicon nitride film 30, the performance of the N-type MIS transistor 10n can be improved.

  Similarly, in the second embodiment, a portion of the silicon nitride film 30 in contact with the source / drain region 24p of the P-type MIS transistor 20p on the side surface of the gate electrode 22p is used as a channel region of the P-type MIS transistor 20p. Since they can be arranged close to each other, the amount of distortion in the channel region of the P-type MIS transistor 20p can be increased. Therefore, when compressive stress is generated in the silicon nitride film 30, the performance of the P-type MIS transistor 20p can be improved.

  Note that the diffusion suppressing film 100 made of a silicon nitride film is preferably formed by an atomic layer growth method. When the atomic layer growth method is formed on the silicon nitride film, the thickness of the silicon nitride film can be controlled with high accuracy, so that the variation in the thickness of the diffusion suppression film 100 can be reduced. When the variation in the thickness of the diffusion suppression film 100 increases, the diffusion suppression effect in the diffusion suppression film 100 varies, and the metal composition ratio of silicide in the gate electrode 12n varies. Therefore, the metal composition ratio of silicide in the gate electrode 12n is stabilized by reducing the variation in the film thickness of the diffusion suppressing film 100 as in the second embodiment.

  Further, when the diffusion suppression film 100 is formed by the atomic layer growth method, it is desirable to perform wet etching using hydrofluoric acid when the diffusion suppression film 100 is etched. When the silicon nitride film formed by the atomic layer growth method is wet-etched using hydrofluoric acid, the silicon nitride film can be processed with high accuracy, so that the workability of the diffusion suppressing film 100 is improved.

Embodiment 3 FIG.
24 to 27 are cross-sectional views showing the method of manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps. In Embodiment 2 described above, the metal composition ratio of the silicide formed on the gate electrode is changed between the N-type MIS transistor 10n and the P-type MIS transistor 20p by using the diffusion suppression film 100. In the third embodiment, the metal composition ratio of the silicide at the gate electrode is different between the N-type MIS transistor 10n and the P-type MIS transistor 20p by using a diffusion blocking film that blocks the diffusion of the metal necessary for the silicide reaction. Let Hereinafter, a method for manufacturing the semiconductor device according to the third embodiment will be described in detail. The finally manufactured structure is the same as that of the second embodiment, and is the structure shown in FIG.

First, the structure shown in FIG. 19 is manufactured in the same manner as in the manufacturing method according to the second embodiment. Next, as shown in FIG. 24, a metal film 200 made of nickel is formed on the entire surface with a thickness of about 100 nm. And the heat processing is performed with respect to the obtained structure at 350 degreeC for 100 second, for example. As a result, a silicide reaction occurs between the gate electrode 12n and the metal film 200 in contact with the gate electrode 12n, and a silicide layer 112n made of Ni ₂ Si is formed on the gate electrode 12n as shown in FIG. At the same time, a silicide reaction occurs between the gate electrode 22p and the metal film 200 in contact therewith, and as shown in FIG. 25, a silicide layer 122p made of Ni ₂ Si is formed on the gate electrode 22p. Thereafter, the metal film 200 unreacted with silicon is removed by wet etching with a mixed solution of phosphoric acid and nitric acid, for example.

  Next, as shown in FIG. 25, a diffusion blocking film 210 for blocking the diffusion of the metal required for the silicide reaction, in this example, nickel, is formed on the entire surface with a thickness of about 10 nm. The diffusion blocking film 210 is made of, for example, a silicon oxide film. Then, a photoresist 220 covering the N-type MIS transistor formation region is formed on the diffusion blocking film 210.

  Next, using the photoresist 220 as a mask, the diffusion barrier film 210 exposed from the photoresist 220 is removed by etching. Thereby, as shown in FIG. 26, the diffusion blocking film 210 is formed on the upper surface of only the gate electrode 12n among the gate electrodes 12n and 22p. Thereafter, a metal film 230 made of nickel necessary for the silicide reaction is formed on the entire surface with a thickness of about 100 nm.

Next, the obtained structure is heat-treated at 500 ° C. for 60 seconds, for example. As a result, nickel is supplied to the gate electrode 22p from the metal film 230 in contact therewith, the entire region of the gate electrode 22p is silicided, and the gate electrode 22p is composed of Ni ₃ Si or Ni ₃₁ Si _12. . On the other hand, since the diffusion blocking film 210 is formed on the gate electrode 12n, the gate electrode 12n is not supplied with nickel from the metal film 230 by the action of the diffusion blocking film 210. Therefore, in the gate electrode 12n, nickel diffuses downward from the upper silicide layer 112n formed in the previous step. As a result, the entire region of the gate electrode 12n is silicided, and the gate electrode 12n is made of NiSi. As described above, since the volume expansion amount of the gate electrode increases according to the amount of reacting silicon, the gate electrode 22p becomes thicker than the gate electrode 12n after being fully silicided. Thereafter, the metal film 230 unreacted with silicon is removed by wet etching with a mixed solution of phosphoric acid and nitric acid, for example. Thereby, the structure shown in FIG. 27 is obtained. Thereafter, in the same manner as in the second embodiment, the interlayer insulating film 40 and the contact plug 50 are formed.

  Thus, in the method of manufacturing the semiconductor device according to the third embodiment, the gate electrode 22p of the P-type MIS transistor 20p is etched by using the diffusion blocking film 210 that blocks the diffusion of the metal necessary for the silicide reaction. Without this, the metal composition ratio of the silicide formed on the gate electrode can be changed between the N-type MIS transistor 10n and the P-type MIS transistor 20p. Therefore, as in the second embodiment, it is possible to prevent instability of the metal composition ratio of silicide at the gate electrode 22p due to the variation in the etching amount with respect to the gate electrode 22p of the P-type MIS transistor 10n. As a result, the performance of the semiconductor device is improved.

  In the third embodiment, since it is not necessary to etch the gate electrode 22p, variation in the exposure degree of the gate electrode 22p can be reduced as in the second embodiment. Therefore, the metal composition ratio of silicide at the gate electrode 22p is stabilized, and contact holes are formed in the interlayer insulating film 40 and the silicon nitride film 30 both on the N-type MIS transistor formation region and on the P-type MIS transistor formation region. Easy to form.

  In the third embodiment, the diffusion blocking film 210 is formed of a silicon oxide film. However, the diffusion blocking film 210 may be formed of another film as long as the metal necessary for the silicide reaction such as nickel does not diffuse into the gate electrode. May be.

In addition the embodiment 3, by performing two times the heat treatment, and finally, NiSi is formed on the gate electrode 12n, and forms a Ni ₃ Si or Ni ₃₁ Si ₁₂ to the gate electrode 22p. Here, in the second heat treatment, when the optimum processing temperature for supplying the amount of nickel sufficient to generate Ni ₃ Si or Ni ₃₁ Si ₁₂ to the gate electrode 22p is as low as about 350 ° C., the gate electrode 12n There is a possibility that NiSi does not occur in the film. In this case, after removing the unreacted metal film 230, the third heat treatment is performed at a higher processing temperature of about 500 ° C., so that NiSi is surely generated in the gate electrode 12n.

As for the gate electrode 12n of the N-type MIS transistor 10n, a silicide layer 112n made of Ni ₂ Si is formed in a part of the first heat treatment, and nickel of the silicide layer 112n is diffused by the second heat treatment. Although the entire region of the electrode 12n is formed of NiSi, the entire region of the gate electrode 12n may be formed of NiSi by the first heat treatment. In this case, the entire region of the gate electrode 22p of the P-type MIS transistor 20p is also formed of NiSi by the first heat treatment. However, the temperature and time of the second heat treatment are adjusted and the second heat treatment is performed. By adjusting the amount of nickel supplied to the gate electrode 22p by the heat treatment, the entire region of the gate electrode 22p is formed of Ni ₃ Si or Ni ₃₁ Si ₁₂ by the second heat treatment.

Embodiment 4 FIG.
28 to 33 are cross-sectional views showing the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps. In the above-described third embodiment, since the metal composition ratio of silicide at the gate electrode is different between the N-type MIS transistor 10n and the P-type MIS transistor 20p, the diffusion prevention film is not used in the first heat treatment. Although the diffusion preventing film is used for the second heat treatment, in the fourth embodiment, the diffusion preventing film is used for both the first and second heat treatments. The method for manufacturing the semiconductor device according to the fourth embodiment will be described in detail below.

  First, the structure shown in FIG. 19 is manufactured in the same manner as in the manufacturing method according to the second embodiment. Next, as shown in FIG. 28, a diffusion blocking film 300 for blocking the diffusion of nickel necessary for the silicide reaction is formed on the entire surface with a thickness of about 5 nm. The diffusion blocking film 300 is made of, for example, a silicon oxide film. Then, a photoresist 310 is formed on the diffusion blocking film 300 so as to cover the P-type MIS transistor formation region.

  Next, using the photoresist 310 as a mask, the diffusion barrier film 300 exposed from the photoresist 310 is removed by etching. Thereby, as shown in FIG. 29, the diffusion barrier film 300 is formed on the upper surface of only the gate electrode 22p of the gate electrodes 12n and 22p. Thereafter, a metal film 320 made of nickel necessary for the silicide reaction is formed on the entire surface with a thickness of about 100 nm.

Next, the obtained structure is heat-treated at 350 ° C. for 100 seconds, for example. Thereby, nickel is supplied to the gate electrode 12n from the metal film 320 in contact therewith, and as shown in FIG. 30, the upper part of the gate electrode 12n is silicided, and a silicide layer 412n made of Ni ₂ Si is formed on the upper part. It is formed. At this time, the entire region of the gate electrode 12n may be formed of NiSi.

  On the other hand, since the diffusion blocking film 300 is formed on the gate electrode 22p, the gate electrode 22p is not supplied with nickel from the metal film 320 by the action of the diffusion blocking film 300. Therefore, in this step, the gate electrode 22p is not silicided. Thereafter, the metal film 320 that has not reacted with silicon and the diffusion blocking film 300 on the gate electrode 22p are removed.

  Next, as shown in FIG. 31, a diffusion blocking film 330 for blocking the diffusion of nickel necessary for the silicide reaction is formed on the entire surface with a thickness of about 5 nm. The diffusion blocking film 330 is made of, for example, a silicon oxide film. Then, a photoresist 340 is formed on the diffusion blocking film 330 so as to cover the N-type MIS transistor formation region.

  Next, using the photoresist 340 as a mask, the diffusion barrier film 330 exposed from the photoresist 340 is removed by etching. Thereby, as shown in FIG. 32, the diffusion barrier film 330 is formed on the upper surface of only the gate electrode 12n among the gate electrodes 12n and 22p. Thereafter, a metal film 350 made of nickel necessary for the silicide reaction is formed on the entire surface with a thickness of about 100 nm.

Next, the obtained structure is heat-treated at 500 ° C. for 60 seconds, for example. As a result, nickel is supplied to the gate electrode 22p from the metal film 350 in contact therewith, the entire region of the gate electrode 22p is silicided, and the gate electrode 22p is composed of Ni ₃ Si or Ni ₃₁ Si _12. . On the other hand, since the diffusion prevention film 330 is formed on the gate electrode 12n, the gate electrode 12n is not supplied with nickel from the metal film 350 by the action of the diffusion prevention film 330. Therefore, in the gate electrode 12n, nickel diffuses downward from the upper silicide layer 412n formed in the previous step. As a result, the entire region of the gate electrode 12n is silicided, and the gate electrode 12n is made of NiSi. Thereafter, the metal film 350 unreacted with silicon is removed. Thereby, the structure shown in FIG. 33 is obtained. Thereafter, in the same manner as in the second embodiment, the interlayer insulating film 40 and the contact plug 50 are formed.

  As described above, in the manufacturing method according to the fourth embodiment, the diffusion prevention film is formed independently and independently on the gate electrode 12n of the N-type MIS transistor 10n and the gate electrode 22p of the P-type MIS transistor 20p. Thus, silicidation of the gate electrode 12n and silicidation of the gate electrode 22p are performed separately and independently. Therefore, it becomes easy to control the metal composition ratio of silicide in the gate electrodes 12n and 22p.

  On the other hand, in the manufacturing method according to the above-described third embodiment, since the gate electrodes 12n and 22p are both silicided in the first heat treatment, it is not necessary to form a diffusion blocking film in the first heat treatment. Therefore, the manufacturing method can be simplified as compared with the fourth embodiment.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the modification of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method compared with the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process.

Explanation of symbols

  1,501 Semiconductor substrate, 10n N-type MIS transistor, 11n, 21p, 502 Gate insulating film, 12n, 22p, 503 Gate electrode, 13n, 23p First sidewall, 14n, 24p, 506 Source / drain region, 16n, 26p Second sidewall, 20p P-type MIS transistor, 30, 61 silicon nitride film, 60 silicon oxide film, 100, 511 diffusion suppression film, 115n, 125p impurity region, 120, 230, 320, 350, 531 metal film, 210, 330 Diffusion blocking film, 521 Insulating film.

Claims (22)

(A) preparing a semiconductor substrate in which the source / drain regions of the MIS transistor are formed in the upper surface, and the gate insulating film and the gate electrode of the MIS transistor are stacked in this order on the upper surface;
(B) forming a diffusion suppression film on the source / drain region to suppress diffusion of a metal necessary for the silicide reaction;
(C) forming a metal film made of the metal on the gate electrode and the diffusion suppressing film;
(D) reacting the metal film with the gate electrode to silicidize the entire region of the gate electrode, and reacting the metal film with the source / drain regions through the diffusion suppressing film; And a step of siliciding the source / drain regions. A method of manufacturing a semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the metal is nickel. A method of manufacturing a semiconductor device according to any one of claims 1 and 2,
The method of manufacturing a semiconductor device, wherein the diffusion suppression film is made of a silicon nitride film. A method of manufacturing a semiconductor device according to claim 3,
The step (d)
(D-1) By performing a heat treatment at a first processing temperature, the metal film reacts with the gate electrode and the source / drain regions to partially silicide the gate electrode and A step of siliciding the source / drain regions;
(D-2) removing the unreacted metal film in the step (d-1);
(D-3) After the step (d-2), by performing a heat treatment at a second processing temperature higher than the first processing temperature, the metal is diffused in the gate electrode, and the gate electrode And a step of silicidizing the entire region of the semiconductor device. A method of manufacturing a semiconductor device according to claim 3,
In the step (a), the semiconductor substrate in which a first insulating film made of a silicon nitride film is formed on the gate electrode is prepared,
The step (b)
(B-1) forming the diffusion suppression film on the entire surface of the semiconductor substrate by a deposition method so as to cover the gate insulating film, the gate electrode, and the first insulating film;
(B-2) forming a second insulating film on the entire surface of the diffusion suppressing film;
(B-3) polishing the structure obtained in the step (b-2) from its upper surface to expose the first insulating film;
(B-4) removing the first insulating film exposed in the step (b-3);
(B-5) A method for manufacturing a semiconductor device, comprising the step of removing the remaining second insulating film after the step (b-4). (A) preparing a semiconductor substrate in which the gate insulating film and the gate electrode of each of the N-type MIS transistor and the P-type MIS transistor are stacked on the upper surface in this order;
(B) forming a diffusion suppression film on the gate electrode of the N-type MIS transistor, which suppresses diffusion of a metal necessary for the silicidation;
(C) forming a metal film made of the metal on the diffusion suppression film and on the gate electrode of the P-type MIS transistor;
(D) The metal film and the gate electrode of the N-type MIS transistor are reacted through the diffusion suppression film, and the metal film and the gate electrode of the P-type MIS transistor are reacted to form the P The N-type MIS transistor and the metal composition ratio of the silicide formed on the gate electrode of the N-type MIS transistor are larger than the metal composition ratio of the silicide formed on the gate electrode of the N-type MIS transistor. And siliciding the entire region of the gate electrode of each P-type MIS transistor. A method of manufacturing a semiconductor device according to claim 6,
The method for manufacturing a semiconductor device, wherein the metal is nickel. A method of manufacturing a semiconductor device according to any one of claims 6 and 7,
The method of manufacturing a semiconductor device, wherein the diffusion suppression film is made of a silicon nitride film. A method for manufacturing a semiconductor device according to claim 8, comprising:
Wherein the gate electrode of the N-type MIS transistor consists of NiSi _2, the method of manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to claim 8, wherein:
The method of manufacturing a semiconductor device, wherein the gate electrode of the P-type MIS transistor is made of Ni ₃ Si or Ni ₃₁ Si ₁₂ . A method for manufacturing a semiconductor device according to claim 8, comprising:
In the step (b), the diffusion suppression film made of a silicon nitride film is formed by an atomic layer growth method. A method for manufacturing a semiconductor device according to claim 11, comprising:
The step (b)
(B-1) forming the diffusion suppression film made of a silicon nitride film on the entire surface of the structure obtained in the step (a) by an atomic layer growth method;
(B-2) A method of manufacturing a semiconductor device, comprising: removing the diffusion suppression film on the gate electrode of the P-type MIS transistor by performing wet etching using hydrofluoric acid. (A) preparing a semiconductor substrate in which the gate insulating film and the gate electrode of each of the N-type MIS transistor and the P-type MIS transistor are stacked on the upper surface in this order;
(B) siliciding at least the gate electrode of the N-type MIS transistor among the N-type MIS transistor and the P-type MIS transistor;
(C) after the step (b), forming a diffusion blocking film on the gate electrode of the N-type MIS transistor to prevent diffusion of a metal necessary for a silicide reaction;
(D) forming a metal film made of the metal on the diffusion barrier film and on the gate electrode of the P-type MIS transistor;
(E) a step of causing a silicide reaction between the metal film and the gate electrode of the P-type MIS transistor,
After the step (e), the entire region of the gate electrode of each of the N-type MIS transistor and the P-type MIS transistor is silicided, and the metal composition ratio of silicide formed in the P-type MIS transistor Is a method for manufacturing a semiconductor device, which is larger than a metal composition ratio of silicide formed on the gate electrode of the N-type MIS transistor. A method of manufacturing a semiconductor device according to claim 13,
A method of manufacturing a semiconductor device, wherein nickel silicide is formed in the steps (b) and (e). A method for manufacturing a semiconductor device according to claim 13, wherein:
A method of manufacturing a semiconductor device, wherein the diffusion barrier film is made of a silicon oxide film. A method for manufacturing a semiconductor device according to any one of claims 13 to 15,
In the step (b), the gate electrode of each of the N-type MIS transistor and the P-type MIS transistor is silicided. A method for manufacturing a semiconductor device according to any one of claims 13 to 15,
The step (b)
(B-1) forming a second diffusion blocking film for blocking the diffusion of the metal on the gate electrode of the P-type MIS transistor;
(B-2) forming a second metal film made of the metal on the gate electrode and the second diffusion blocking film of the N-type MIS transistor;
(B-3) A method for manufacturing a semiconductor device, comprising the step of silicidating the second metal film and the gate electrode of the N-type MIS transistor. A method of manufacturing a semiconductor device according to any one of claims 6 and 13,
(F) forming a first insulating film on the entire surface of the semiconductor substrate so as to cover the gate electrodes of the N-type MIS transistor and the P-type MIS transistor between the steps (a) and (b); ,
(G) before the step (b), forming a second insulating film on the first insulating film;
(H) Before the step (b), the structure obtained in the step (g) is polished from the upper surface, and the upper surface of the gate electrode of the N-type MIS transistor and the P-type MIS transistor is Exposing the first insulating film;
(I) Before the step (b), the first insulating film on the upper surface of the gate electrode of the N-type MIS transistor and the P-type MIS transistor exposed in the step (h) is removed, And a step of exposing the gate electrodes of the N-type MIS transistor and the P-type MIS transistor. A method of manufacturing a semiconductor device according to claim 18,
(J) forming a third insulating film on the entire surface of the semiconductor substrate so as to cover the gate electrodes of the N-type MIS transistor and the P-type MIS transistor between the steps (a) and (f); ,
(K) Before the step (f), the third insulating film is etched to form a side made of the third insulating film on the side surface of the gate electrode of the N-type MIS transistor and the P-type MIS transistor. Forming a wall;
(L) Before the step (f), an impurity is introduced into the semiconductor substrate using the gate electrode of the N-type MIS transistor and the sidewall on the side surface of the gate electrode as a mask, and the N-type Forming a source / drain region of a MIS transistor on the semiconductor substrate;
(M) Before the step (f), impurities are introduced into the semiconductor substrate using the gate electrode of the P-type MIS transistor and the sidewall on the side surface of the gate electrode as a mask, and the P-type Forming a source / drain region of a MIS transistor on the semiconductor substrate;
(N) After the steps (l) and (m) and before the step (f), the sidewalls on the side surfaces of the gate electrodes of the N-type MIS transistor and the P-type MIS transistor are removed. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 18,
The first insulating film is made of a silicon nitride film,
(J) During the steps (a) and (f), on the side surface of the gate electrode of each of the N-type MIS transistor and the P-type MIS transistor, a silicon oxide film is formed in order from the gate electrode side. Forming a sidewall in which three insulating films and a fourth insulating film made of a silicon nitride film are stacked;
(K) Before the step (f), impurities are introduced into the semiconductor substrate using the gate electrode of the N-type MIS transistor and the sidewall on the side surface of the gate electrode as a mask, and the N-type Forming a source / drain region of a MIS transistor on the semiconductor substrate;
(L) Before the step (f), impurities are introduced into the semiconductor substrate using the gate electrode of the P-type MIS transistor and the sidewall on the side surface of the gate electrode as a mask, and the P-type Forming a source / drain region of a MIS transistor on the semiconductor substrate;
(M) A method of manufacturing a semiconductor device, further comprising the step of removing the fourth insulating film on the sidewall after the steps (k) and (l) and before the step (f). A semiconductor substrate;
A gate electrode of a MIS transistor formed on the semiconductor substrate and silicided in its entire region;
A source / drain region of the MIS transistor formed in the semiconductor substrate;
A silicon oxide film formed on a side surface of the gate electrode;
A semiconductor device comprising: a silicon nitride film formed on the silicon oxide film and the source / drain regions so as to be in contact with the silicon oxide film and the source / drain regions. The semiconductor device according to claim 21, wherein
A semiconductor device, wherein the entire region of the gate electrode is made of nickel silicide.

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