JP2009043938A - Semiconductor apparatus and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus with a structure in which an SiGe layer is formed in a source-drain region of a PMOS transistor and the upper surface of the SiGe layer is silicided, wherein a contact resistance between the source-drain region and the metal silicide can be reduced. <P>SOLUTION: The semiconductor apparatus has a semiconductor substrate 1, an SiGe layer 7, a highly concentrated Ge layer 8, and a metal silicide layer 9. The SiGe layer 7 is formed within a front surface of the semiconductor substrate used as a source-drain region of the PMOS transistor 100. The highly concentrated Ge layer 8 is formed on an upper surface of the SiGe layer 7, and has a Ge concentration that is higher than the Ge concentration in the SiGe layer 7. The metal silicide layer 9 is formed on the highly concentrated Ge layer 8. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device including a PMOS transistor having a SiGe layer formed in a source / drain region and a method for manufacturing the semiconductor device. .

  With the demand for higher performance and higher integration of semiconductor devices, a technique for adding distortion to the channel region is becoming more and more important in order to improve the driving current of MOS (Metal Oxide Semiconductor) transistors. As a method for applying strain to the channel region, there is a technique for forming a high-stress silicon nitride film in an interlayer insulating film or a technique for forming semiconductors having different lattice constants in the source / drain regions. In the latter prior art, a compressive strain is generated in the channel layer of the PMOS transistor by forming a SiGe layer in a portion to be a source / drain region. The outline of the technique in which the SiGe layer whose upper surface is silicided is formed in the source / drain region of the PMOS is as follows.

  A gate structure including a gate insulating film and a gate electrode is formed on the semiconductor substrate. Next, a recess (concave portion) is formed on the upper surface of the semiconductor substrate in a portion to be a source / drain region. Next, a SiGe layer is formed in the recess by epitaxial growth. Next, a Ni film and a TiN film are stacked in this order on the semiconductor substrate so as to cover the gate structure. Thereafter, heat treatment is performed. Thereby, a Ni silicide film is formed on the upper surface of the gate electrode made of polysilicon and the upper surface of the SiGe layer.

  As described above, when a metal silicide is formed on the upper surface of the SiGe layer, the resistance of the metal silicide is remarkably increased. This is because the heat generated by reaction of Ge is smaller than that of Si, and preferentially reacts with Si, whereby metal silicide is formed unevenly and aggregation occurs. As a result of the increase in resistance of the metal silicide, a necessary voltage cannot be applied to the transistor, and the PMOS transistor does not operate normally.

  In order to solve the problem, there is a technique for forming a metal silicide on the SiGe layer by forming a Si layer on the SiGe layer, forming a metal on the Si layer, and reacting only the Si and the metal. is there.

  However, due to higher integration of semiconductor devices, transistor miniaturization has further progressed and the gate length is being further reduced. Thereby, while the channel resistance is reduced, the contact resistance between the metal silicide and the source / drain regions is further increasing due to the reduction of the gate width.

  The voltage necessary for transistor operation is applied via a contact hole connected to the metal silicide. Therefore, as the channel resistance decreases due to the miniaturization of the device, the influence of the contact resistance between the source / drain regions and the metal silicide cannot be ignored, which hinders the improvement of the driving current of the transistor.

  Therefore, the present invention reduces the contact resistance between the source / drain region and the metal silicide in the configuration in which the SiGe layer is formed in the source / drain region of the PMOS transistor and the upper surface of the SiGe layer is silicided. It is an object of the present invention to provide a semiconductor device that can be achieved and a method for manufacturing the semiconductor device.

  In one embodiment according to the present invention, a semiconductor device has the following configuration. That is, a semiconductor substrate on which a PMOS transistor is formed, a SiGe layer formed in the surface of the semiconductor substrate, a high concentration Ge layer formed on the upper surface of the SiGe layer, and a metal silicide layer formed on the high concentration Ge layer And has.

  According to the above embodiment, Ge has a narrower band gap than Si. Therefore, the contact resistance between the SiGe layer and the metal silicide layer can be reduced by forming a high concentration Ge layer between the SiGe layer and the metal silicide layer.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a configuration of a P-MOSFET (MOS Field Effect Transistor: hereinafter referred to as a PMOS transistor) 100 according to the present embodiment. FIG. 2 is an enlarged view of a portion C1 surrounded by a circle in FIG.

  As shown in FIG. 1, a PMOS transistor 100 is formed on the semiconductor substrate 1. The semiconductor substrate 1 contains n-type impurities and is made of silicon (that is, the semiconductor substrate 1 is n-type). An element isolation film 2 is formed in the surface of the semiconductor substrate 1, and the PMOS transistor 100 is electrically isolated from other semiconductor elements by the element isolation film 2. A stacked body (hereinafter referred to as a gate structure) in which a gate insulating film 3, a gate electrode 4, and a metal silicide layer 5 are stacked in this order is formed on the semiconductor substrate 1. A sidewall film 6 is formed on the side surface of the gate structure.

  As shown in FIGS. 1 and 2, a P-type SiGe (silicon-germanium) layer 7 is formed in the surface of the semiconductor substrate 1 on both sides of the gate structure. That is, the SiGe layer 7 is formed in the surface of the semiconductor substrate that becomes the source / drain regions of the PMOS transistor 100. Further, a high concentration Ge layer 8 is formed on the SiGe layer 7.

  Here, the high concentration Ge layer 8 is a layer having a Ge concentration higher than that in the SiGe layer 7. In this sense, the high concentration Ge layer 8 can also be referred to as a Ge segregation layer. Further, as shown in FIG. 1, the high concentration Ge layer 8 is formed at a deeper position including the upper surface of the semiconductor substrate 1. A metal silicide layer 9 is formed on the high concentration Ge layer 8.

  A channel region is formed near the surface of the semiconductor substrate 1 below the gate structure (in other words, between the source and drain regions).

  Next, a method for manufacturing the PMOS transistor 100 according to the present embodiment will be described with reference to process cross-sectional views.

  First, as shown in FIG. 3, the element isolation film 2 is formed in the surface of the semiconductor substrate 1 by STI (Shallow Trench Isolation) method. Next, a silicon oxide film (or an oxynitride film, an Hf oxide film, etc.) is formed on the semiconductor substrate 1. Then, a polysilicon layer is formed on the silicon oxide film. Further, a hard mask 12 made of a silicon nitride film or a silicon oxide film is formed on the polysilicon layer.

  After the hard mask 12 is patterned into a predetermined shape, the silicon oxide film and the polysilicon layer are etched using the patterned hard mask 12 as a mask. As a result, as shown in FIG. 4, a gate structure in which the gate insulating film 3 and the gate electrode 4 are laminated in this order on the semiconductor substrate 1 is formed. Note that the hard mask 12 remains on the gate electrode 4.

  Next, ion implantation is performed on the upper surface of the semiconductor substrate 1 using the hard mask 12 and the gate structure as a mask. By the ion implantation process, as shown in FIG. 5, extension regions 11 having shallow junctions are formed in the surface of the semiconductor substrate 1 on both sides of the gate structure.

  Next, a silicon oxide film (or a laminated structure film of a silicon oxide film and a silicon nitride film) is formed on the semiconductor substrate 1 so as to cover the hard mask 12 and the gate structure. Thereafter, an anisotropic etching process is performed on the silicon oxide film. Thereby, as shown in FIG. 6, sidewall spacers 6 are formed on both side surfaces of the gate structure.

  Next, an etching process is performed on the upper surface of the semiconductor substrate 1 using the sidewall spacer 6, the hard mask 12, and the element isolation film 2 as a mask. That is, the upper surface portion of the semiconductor substrate 1 which becomes the source / drain region of the PMOS transistor 100 is removed. By the etching process, as shown in FIG. 7, recess portions 15 are formed in the semiconductor substrate 1 on both sides of the gate structure. Here, the depth of the recess 15 is, for example, about 30 to 60 nm.

  Next, an epitaxial growth method is performed on the recess portion 15. Thereby, as shown in FIG. 8, the SiGe layer 7 is grown (formed) in the recess portion 15. Here, the concentration of Ge in the SiGe layer 7 is, for example, 10 to 20%. Further, the growth of the SiGe layer 7 is adjusted so that the upper surface position of the SiGe layer 7 formed in the recess 15 is lower than the upper surface position of the semiconductor substrate 1 (in other words, the bottom surface of the gate insulating film 3). You may do it (refer FIG. 8).

  Next, an epitaxial growth method is performed on the SiGe layer 7 under conditions different from the above. 9, a Si layer 18 having a thickness of about 10 to 15 nm is grown (formed) on the SiGe layer 7 as shown in FIG. Here, the layer thickness of the Si layer 18 is smaller than the layer thickness (for example, 12 to 20 nm) of the metal silicide layer 9 to be formed later. It should be noted that it is desirable to prevent the composition non-uniformity (aggregation) from occurring in the metal silicide layer 9 formed after the silicide treatment described later. Therefore, from this viewpoint, the thickness of the Si layer 18 is desirably about 80 to 90% of the thickness of the metal silicide layer 9 to be formed later.

  Next, the hard mask 12 on the gate electrode 4 is removed. Here, when the element isolation film 2 and the sidewall spacer 6 are formed of a silicon oxide film, it is desirable to use a silicon nitride film as the hard mask 12. Thereby, only the hard mask 12 can be selectively removed by phosphoric acid.

  Thereafter, the Ni layer 20 is formed on the semiconductor device in the middle of manufacture shown in FIG. 9 as a metal layer to be silicided by sputtering (see FIG. 10). Further, a TiN layer 21 is formed on the Ni layer 20 as a protective film by sputtering (see FIG. 10). Here, the layer thickness of the Ni layer 20 is about 6 to 12 nm, and the layer thickness of the TiN layer 21 is about 10 to 20 nm. Here, FIG. 11 shows an enlarged view of the SiGe layer 7 and the structure formed on the SiGe layer 7.

  Thereafter, heat treatment by an RTA (Rapid Thermal Anneal) method or the like is performed on the semiconductor device being manufactured shown in FIG. Here, the said heat processing is performed on the conditions for about 30 second at 250-400 degreeC, for example. By the heat treatment, the Ni layer 20 and the Si layer 18 are reacted, and the Ni layer 20 and the gate electrode 4 made of polysilicon are reacted (silicide treatment).

  Here, the Ni layer 20 formed above the SiGe layer 7 consumes the entire Si layer 18 and further reacts with Si in the SiGe layer 7. This is because the thickness of the Si layer 18 is set to be thinner than the thickness of the metal (Ni) silicide layer 9 in advance. With such a layer thickness setting, the Ni layer 20 and the Si in the SiGe layer 7 can be reliably reacted.

  The reaction heat between Ni and Si is -45 kJ / mol, whereas the reaction heat of NiGe is -32 kJ / mol. Therefore, Ni exists more stably with Si. The layer thickness of the Si layer 18 is about 80 to 90% of the layer thickness of the Ni layer 20. Then, since most of the Ni layer 20 (about 80 to 90%) reacts with the Si layer 18 formed on the SiGe layer 7, a stable silicide reaction is possible. Further, the remainder (about 10 to 20%) of the Ni layer 20 reacts with the SiGe layer 7. However, Ni preferentially reacts with energetically favorable Si compared to Ge. Therefore, Ge is effectively segregated between the metal (Ni) silicide layer 9 and the SiGe layer 7. As a result, as shown in FIG. 2, the metal (Ni) silicide layer 9 and the SiGe layer 7 In the meantime, the high concentration Ge layer 8 is formed.

  That is, by the silicide treatment, a stacked body in which the SiGe layer 7, the high-concentration Ge layer 8, and the metal silicide layer 9 are formed in this order is formed (FIGS. 1 and 2). Furthermore, a metal silicide layer 5 is formed on (inside) the gate electrode 4 by the silicide treatment (FIG. 1).

  After the silicidation, the unreacted Ni layer 20 and TiN layer 21 are removed using a mixed chemical solution of sulfuric acid and hydrogen peroxide solution. Thereafter, in order to reduce the resistance of the metal silicide layers 5 and 9, heat treatment such as RTA is performed. The heat treatment is performed, for example, at 400 ° C. to 500 ° C. for about 30 seconds.

  Through the above steps, the configuration shown in FIG. 1 is completed. Thereafter, an interlayer insulating film is formed, and a contact hole reaching the gate electrode 4 and the metal silicide layer 9 is formed. Furthermore, a semiconductor device including the PMOS transistor 100 is formed by forming a conductive wiring in the upper layer.

  As described above, in the semiconductor device according to the present embodiment, the high concentration Ge layer 8 having a Ge concentration higher than the Ge concentration in the SiGe layer 7 is formed on the upper surface of the SiGe layer 7. Further, a metal silicide layer 9 is formed on the high concentration Ge layer 8.

  Ge has a narrower band gap than Si. Therefore, the contact resistance between the SiGe layer 7 and the metal silicide layer 9 can be reduced by forming the high-concentration Ge layer 8 between the SiGe layer 7 and the metal silicide layer 9. By reducing the contact resistance, the driving current of the PMOS transistor 100 can be increased.

  Further, as described above, the Si layer 18 having a layer thickness smaller than that of the metal silicide layer 9 is formed on the SiGe layer 7. Then, a metal layer (Ni layer) 20 to be subjected to a silicide reaction is formed on the Si layer 18. Thereafter, heat treatment is performed.

  As described above, the layer thickness of the Si layer 18 on the SiGe layer 7 is set to be thinner than the layer thickness of the metal silicide layer 9 formed thereafter. Thereby, the high-concentration Ge layer 8 can be effectively formed between the SiGe layer 7 and the metal silicide layer 9.

  Further, as shown in FIG. 12, a high concentration Ge layer 8 may be formed at a position above the upper surface of the semiconductor substrate 1. However, as shown in FIG. 1, it is desirable to form the high concentration Ge layer 8 at a position deeper (lower) than that including the upper surface of the semiconductor substrate 1.

  As described above, the high concentration Ge layer 8 is formed at the position shown in FIG. Here, since the lattice constant also changes depending on the Ge concentration, the lattice constant of the high concentration Ge layer 8 is larger than the lattice constant of the SiGe layer 7. Therefore, in the structure shown in FIG. 1, since the high-concentration Ge layer 8 exists near the channel between the source and drain regions, the compressive strain generated in the channel can be further promoted as compared with the structure shown in FIG. it can. Therefore, the drive current of the PMOS transistor 100 can be further increased. That is, a semiconductor device capable of higher speed operation can be provided.

  When the SiGe layer 7 is grown on the recess 15, the SiGe layer 7 is formed and grown so that the upper surface of the SiGe layer 7 is positioned below the upper surface position of the semiconductor substrate 1. Then, the subsequent formation process of the Si layer 18 and Ni layer 20 and the silicide process are performed. Thereby, the high-concentration Ge layer 8 can be easily formed at a position deeper (lower) than that including the upper surface of the semiconductor substrate 1.

  However, when the high concentration Ge layer 8 is formed at the position shown in FIG. 1, the SiGe layer 7 may be formed so that the upper surface of the SiGe layer 7 is located above the junction depth position of the extension region 11. desired. This is because the junction leakage current increases when the upper surface of the SiGe layer 7 becomes deeper than the junction depth of the extension region 11.

<Embodiment 2>
The semiconductor device according to the present embodiment is characterized in that a predetermined metal is contained in the metal (Ni) silicide layer 9 described in the first embodiment. Here, the predetermined metal is a metal having a Schottky barrier height (Schottky barrier) with P-type silicon, which is smaller than Ni.

  FIG. 13 is an enlarged view showing the configuration of the SiGe layer 7 and the structure formed above the SiGe layer 7 in the semiconductor device according to the present embodiment.

  On the SiGe layer 7 containing P-type impurities, the high-concentration Ge layer 8 described in the first embodiment is formed. Further, a Ni alloy silicide layer 59 is formed on the high concentration Ge layer 8.

  Here, in the present embodiment, the Ni alloy silicide layer 59 contains a predetermined metal in addition to the main component Ni. As described above, the Schottky barrier height of a given metal for P-type silicon is smaller than the Schottky barrier height of Ni for P-type silicon. Further, the concentration of the predetermined metal in the Ni silicide layer 59 is higher as it is closer to the high concentration Ge layer 8.

  That is, as shown in FIG. 13, the Ni alloy silicide layer 59 includes a layer 59a having a relatively high concentration of a predetermined metal and a layer 59b having a lower concentration of the predetermined metal than the layer 59a. As described above, the layer 59a is located on the high-concentration Ge layer 8, and the layer 59b is located on the layer 59a.

  As the predetermined metal, ruthenium (Ru), platinum (Pt), vanadium (V), palladium (Pd), or the like can be used. Note that the Ni alloy silicide layer 59 may include at least two kinds of the respective elements.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described using an enlarged cross-sectional view in the vicinity of the SiGe layer 7.

  First, as shown in FIG. 8, the SiGe layer 7 is formed in the recess portion 15 formed in the semiconductor substrate 1. Next, a Si layer 18 having a thickness of about 10 to 15 nm is formed on the SiGe layer 7 (FIG. 14). Here, the SiGe layer 7 and the Si layer 18 contain P-type impurities by the ion implantation process.

  Next, a predetermined metal layer 31 made of the predetermined metal listed above is formed on the Si layer 18 by sputtering or the like (FIG. 14). Here, the layer thickness of the predetermined metal layer 31 is about 1 to 3 nm. Further, similarly to the first embodiment, the Ni layer 20 (layer thickness of 5 to 10 nm) is formed on the predetermined metal layer 31, and the TiN film 21 is formed on the Ni layer 20 (FIG. 14).

  Thereafter, heat treatment by the RTA method or the like is performed on the semiconductor device in the middle of manufacture having the configuration shown in FIG. Here, the said heat processing is performed on 200-450 degreeC conditions, for example. The structure shown in FIG. 15 is formed by the heat treatment (silicide treatment). That is, the high concentration Ge layer 8 is formed on the SiGe layer 7, and the Ni alloy silicide layer 59 is formed on the high concentration Ge layer 8. Here, the predetermined metal layer 31 was formed closer to the SiGe layer 7. Therefore, in the Ni alloy silicide layer 59, the concentration of the predetermined metal on the high concentration Ge layer 8 side is relatively high (that is, the Ni alloy silicide layer 59 is formed in the order of deposition of the layers 59a and 59b).

  The formation principle of the high concentration Ge layer 8 is as described in the first embodiment. In addition, if an element that easily reacts with Ge as compared with Ni is selected as the predetermined metal, the concentration of the predetermined metal in the Ni alloy silicide layer 59 on the high concentration Ge layer 8 side can be more effectively increased. Can be.

  For example, the reaction heat of PtGe is −46 kJ / mol, and the PtGe compound is more stable than the PtNi compound. The reaction heat of PtSi is −59 kJ / mol. Therefore, Pt reacts preferentially with Si, and high concentration Ge is segregated in the upper part of the SiGe layer 7. However, since the PtGe compound is more stable than the PtNi compound, Pt is formed on the SiGe layer 7 side. That is, if an element that easily reacts with Ge is selected as the predetermined metal as compared with Ni, the configuration of FIG. 15 is more effectively formed.

  Thereafter, the unreacted Ni layer 20 and the TiN layer 21 are selectively removed, and a heat treatment for reducing the resistance of the Ni alloy silicide layer 59 is performed. Here, the said heat processing is performed on the conditions of the temperature of 400-600 degreeC.

  Subsequent steps are the same as those in the first embodiment.

  As described above, in the present embodiment, the SiGe layer 7 contains P-type impurities, and a predetermined metal is added to the Ni alloy silicide layer 59. Here, the predetermined metal has a Schottky barrier height with P-type silicon, which is smaller than Ni.

  Therefore, the contact resistance between the SiGe layer 7 and the Ni alloy silicide layer 59 can be further reduced as compared with the first embodiment.

  As described above, the concentration of the predetermined metal in the Ni alloy silicide layer 59 is desirably higher as it is closer to the high concentration Ge layer 8 (FIG. 13). Thereby, for example, the contact resistance can be further reduced as compared with the case where a predetermined metal is uniformly added in the Ni alloy silicide layer 59.

  Further, as described above, the Si layer 18 is formed on the SiGe layer 7, and the predetermined metal layer 31 and the Ni layer 20 are formed on the Si layer 18 in this order. Thereby, the concentration of the predetermined metal in the Ni alloy silicide layer 59 on the high concentration Ge layer 8 side can be increased more effectively.

  If the concentration distribution of the predetermined metal in the Ni alloy silicide layer 59 is arbitrary, other manufacturing methods described below can be employed.

  That is, after the Si layer 18 is formed, a sputtering method is performed using a sputtering target composed of Ni and a predetermined metal (the atomic ratio of the metal is, for example, several atm% to 10 atm%). Thereby, the Ni alloy layer 35 is formed on the Si layer 18 (see FIG. 16). Thereafter, a TiN film 21 is formed as a protective film on the Ni alloy layer 35 (see FIG. 16). Thereafter, heat treatment (200 to 300 ° C.) is performed. As a result, the high concentration Ge layer 8 is formed on the SiGe layer 7 and the Ni alloy silicide layer 59 containing a predetermined metal is formed on the high concentration Ge layer 8. Here, the concentration distribution of the predetermined metal in the Ni alloy silicide layer 59 formed by this method is uniform. Further, heat treatment at about 400 to 600 ° C. is then performed to reduce the resistance of the Ni silicide layer.

  Also in the case of the other manufacturing method, a predetermined metal (for example, Pt, V, etc.) having a higher reaction heat with Ge as compared with Ni is selected as the sputtering target. Thereby, also in the above method for forming the Ni alloy layer 35, the concentration of the predetermined metal can be increased on the high concentration Ge layer side in the Ni alloy silicide layer 59.

<Embodiment 3>
In the present embodiment, a manufacturing method other than the second embodiment in which a predetermined metal in the Ni alloy silicide layer 59 is included at a high concentration on the high concentration Ge layer 8 side will be described. Here, as described above, the predetermined metal has a Schottky barrier height (Schottky barrier) with P-type silicon, which is smaller than Ni.

  A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to an enlarged sectional view in the vicinity of the SiGe layer 7.

  First, as shown in FIG. 8, the SiGe layer 7 is formed in the recess portion 15 formed in the semiconductor substrate 1. Next, a Si layer 18 having a thickness of about 10 to 15 nm is formed on the SiGe layer 7 (FIG. 17). Here, the SiGe layer 7 and the Si layer 18 contain P-type impurities by the ion implantation process.

  Next, a sputtering method is performed using a sputtering target composed of Ni (main component) and Pd (3% to 10%). Thereby, a Ni—Pd alloy layer 41 having a thickness of about 5 to 12 nm is formed on the Si layer 18 (FIG. 17). Thereafter, a TiN film 21 having a thickness of about 15 nm is formed as a protective film on the Ni—Pd alloy layer 41 (FIG. 17). The Pd is the predetermined metal described in the second embodiment, and is an element that undergoes a silicide reaction at a lower temperature than Ni.

  Thereafter, a first heat treatment is performed for silicidation. By the first heat treatment, the Si layer 18 and Pd in the Ni—Pd alloy layer 41 are preferentially reacted. Here, as the first heat treatment, RTA treatment under conditions of a temperature of 150 to 220 ° C. and a time of about 30 to 60 seconds can be employed. By the first heat treatment, as shown in FIG. 18, the layer thickness of the Si layer 18 decreases, and a Pd silicide layer 42 is formed on the Si layer 18. Note that, as Pd is silicided, the Ni—Pd alloy layer 41 becomes a Ni—Pd alloy layer 43 with a reduced Pd concentration (FIG. 18).

  Thereafter, a second heat treatment higher than the first heat treatment is performed for further Ni silicidation. By the second heat treatment, the remaining Si layer 18 reacts completely with the Ni layer 43, and after the reaction with the Si layer 18, the Ni layer 43 reacts with Si in the SiGe layer 7. Here, as the second heat treatment, RTA treatment under conditions of a temperature of 250 to 400 ° C. and a time of about 30 to 60 seconds can be employed.

  As described above, in the silicidation process, a two-stage heat treatment including a first heat treatment and a second heat treatment having a higher temperature than the first heat treatment is performed. By the first heat treatment, Pd is silicided preferentially, and a Pd silicide layer 42 is formed below the Ni layer 43 (FIG. 18). Therefore, by performing the second heat treatment, a Ni alloy silicide layer 59 is formed as shown in FIG. 13, and Pd (predetermined metal) is formed on the high concentration Ge layer 8 side in the Ni alloy silicide layer 59. ) Is included in high concentrations.

  Thereafter, in order to reduce the resistance of the Ni alloy silicide layer 59, a heat treatment at about 400 to 600 ° C. is performed. The subsequent steps are the same as those in the first embodiment.

  In the present embodiment, the Ni—Pd alloy layer 41 is formed on the Si layer 18 using a sputtering target in which Pd is added to Ni. However, even if a Ni—Pt alloy layer is formed on the Si layer 18 by using a sputtering target in which Pt is added to Ni, and then the first heat treatment and the second heat treatment are performed for silicidation. good. Also in this case, as shown in FIG. 13, Pt (predetermined metal) can be contained at a high concentration on the high concentration Ge layer 8 side in the Ni alloy silicide layer 59.

  Further, a Ni—Pt—Pd alloy layer is formed on the Si layer 18 by using a sputtering target obtained by adding Pd and Pt to Ni, and then the first heat treatment and the second heat treatment are performed for silicidation. You may heat-process.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. It is an expanded sectional view showing composition near a SiGe layer. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. It is an expanded sectional view showing composition near a SiGe layer. FIG. 6 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view showing a configuration near a SiGe layer of a semiconductor device according to a second embodiment. FIG. 10 is an enlarged process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is an enlarged process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is an enlarged process cross-sectional view for explaining another method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is an enlarged process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the third embodiment. FIG. 10 is an enlarged process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the third embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Element isolation film, 3 Gate insulating film, 4 Gate electrode, 5,9 Metal (Ni) silicide layer, 6 Side wall spacer, 7 GeSi layer, 8 High concentration Ge layer, 9a Predetermined metal high concentration layer 11 Extension region 15 Recess portion 18 Si layer 20, 43 Ni layer 21 TiN layer 31 Predetermined metal layer 35 Ni alloy layer 41 Ni-Pd alloy layer 42 Pd silicide layer 59 Ni alloy silicide Layer, 100 PMOSFET (PMOS transistor).

Claims (10)

A semiconductor substrate on which a PMOS transistor is formed;
A SiGe layer formed in a surface of the semiconductor substrate to be a source / drain region of the PMOS transistor;
A high concentration Ge layer formed on the SiGe layer and having a Ge concentration higher than a Ge concentration in the SiGe layer;
A metal silicide layer formed on the high-concentration Ge layer,
A semiconductor device. The high-concentration Ge layer is
Formed at a depth position below the upper surface of the semiconductor substrate;
The semiconductor device according to claim 1. An extension region formed in the surface of the semiconductor substrate;
The top surface of the SiGe layer is
Located above the junction depth position of the extension region,
The semiconductor device according to claim 2. In the SiGe layer,
P-type impurities are included,
The metal silicide layer is
A Ni alloy silicide layer comprising a predetermined metal having a smaller Schottky barrier height between Ni and P-type silicon than Ni.
The semiconductor device according to claim 1. The concentration of the predetermined metal in the Ni alloy silicide layer is:
The closer to the high concentration Ge layer, the higher the concentration.
The semiconductor device according to claim 4. (A) forming a recess portion by removing an upper surface portion of a semiconductor substrate which becomes a source / drain region of a PMOS transistor;
(B) forming a SiGe layer in the recess;
(C) forming a Si layer on the SiGe layer;
(D) forming a metal layer on the Si layer;
(E) reacting the Si layer and the metal layer by heat treatment to form a metal silicide layer, and
The step (C)
Forming the Si layer having a layer thickness smaller than that of the metal silicide layer,
The step (E)
The Si layer and the metal layer are reacted by the heat treatment, and Si in the SiGe layer is reacted with the metal layer, whereby a high concentration Ge layer and the metal silicide layer are formed on the SiGe layer. Is a step of forming
A method for manufacturing a semiconductor device. The step (B)
The step of forming the SiGe layer such that the upper surface of the SiGe layer is positioned below the upper surface position of the semiconductor substrate.
The method of manufacturing a semiconductor device according to claim 6. (F) further comprising a step of forming an extension region in the surface of the semiconductor substrate;
The step (B)
Forming the SiGe layer so that the upper surface of the SiGe layer is positioned above the junction depth position of the extension region;
The method of manufacturing a semiconductor device according to claim 7. The step (B)
Forming a SiGe layer containing a P-type impurity in the recess,
The step (D)
A step of forming a predetermined metal layer made of a predetermined metal whose Schottky barrier height with P-type silicon is smaller than Ni on the Si layer, and a Ni layer in that order.
The method of manufacturing a semiconductor device according to claim 6. The step (B)
Forming a SiGe layer containing a P-type impurity in the recess,
The step (D)
Forming the metal layer containing Ni and at least one of Pd and Pt on the Si layer;
The step (E)
(E-1) a step of siliciding the Pd or Pt preferentially over the Ni by a first heat treatment;
(E-2) including siliciding the Ni by a second heat treatment at a higher temperature than the first heat treatment,
The method of manufacturing a semiconductor device according to claim 6.

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