JP2004140262A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof in which a Schottky source/drain MOSFET is effectively microfabricated. <P>SOLUTION: After a sidewall 5 is formed, two layers of metal films 6 and 7 are sequentially deposited overall. When forming a p-type transistor as the metal film 6 of the lower layer, a Pt film is formed, for example, and when forming an n-type transistor, an Er film is formed, for example. As the metal film 7 of the upper layer, an Ni film, a Co film or a Ti film is formed, for example. Continuously, heat treatment is performed for about 30 minutes at 400°C, for example, to make react the metal films 6 and 7 and a semiconductor wafer 1. A chemical compound film 8 is composed of ErSi, PtSi and TiSi or NiSi films, for example, and a chemical compound film 9 is composed of NiSi and CoSi or TiSi films, for example. Because of presence of the chemical compound film 9, contact resistances between the chemical compound film 8 and a source wiring 10S, and between the film 8 and a dram wiring 10D are lowered farther than conventional contact resistances. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device including a field effect transistor (Schottky source / drain MOSFET) in which a source and a drain are Schottky-joined to a channel made of a semiconductor, and a method of manufacturing the same.
[0002]
[Prior art]
Recently, Schottky source / drain MOSFETs have been developed in response to demands for miniaturization and high speed of MOSFETs. In a conventional Schottky source / drain MOSFET, a source and a drain made of a metal are Schottky-joined to a channel made of a semiconductor.
[0003]
The current-voltage characteristics of the Schottky source / drain MOSFET having such a conventional structure are determined by the Schottky barrier formed between the source-channel junction.
[0004]
[Non-patent document 1]
"Introducing Schottky Source / Drain Technology into Strained SiGe MOSFETs," Nikkei Microdevices, August 2002, p. 51
[0005]
[Problems to be solved by the invention]
However, the metal selected to determine the Schottky barrier at the source-channel junction also determines the resistivity of the source and drain regions. For this reason, the conventional structure has a problem that it is not possible to cope with an increase in the resistance value of the source / drain region due to the effect of reducing the area of the source / drain region when improving the performance and the integration degree of the CMOS by miniaturization. .
[0006]
The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device capable of effectively miniaturizing a Schottky source / drain MOSFET and a method of manufacturing the same.
[0007]
[Means for Solving the Problems]
As a result of intensive studies, the inventor of the present application has come up with the following aspects of the invention.
[0008]
A semiconductor device according to a first aspect of the present invention includes a channel made of a semiconductor, a source and a drain in contact with the channel, and a source line and a drain line connected to the source and the drain, respectively. In the semiconductor device, at least one of the source and the drain is made of at least a metal or a compound of a metal and a semiconductor, and the first film and the first film that are Schottky-joined to the channel are A second film made of a different metal or a compound of a metal and a semiconductor and in contact with the source wiring or the drain wiring.
[0009]
In a second method for manufacturing a semiconductor device according to the present invention, a step of forming a gate insulating film, a gate electrode, and a side wall on a substrate having a semiconductor region on a surface, and forming a source and a drain in contact with the semiconductor region And a step of forming a source wiring and a drain wiring connected to the source and the drain, respectively. In this manufacturing method, the step of forming the source and the drain includes, in at least one of the source and the drain, a first film made of a metal or a compound of a metal and a semiconductor, and a Schottky junction with the semiconductor region. And a step of forming a second film made of a metal different from the first film or a compound of a metal and a semiconductor and in contact with the source wiring or the drain wiring.
[0010]
In the present invention, at least one of a source and a drain is provided with a first film which is in Schottky junction with a channel (semiconductor region) and a second film which is in contact with the source wiring or the drain wiring. The first film and the second film are made of different materials. Therefore, the resistance of the second film can be controlled independently of the resistance of the first film. Therefore, by applying the present invention to the CMOS, even if it is miniaturized to improve its performance and the degree of integration, In addition, it is possible to avoid an increase in the resistance value due to the area reduction effect.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. However, here, for convenience, the structure of the semiconductor device will be described together with its manufacturing method.
[0012]
(1st Embodiment)
First, a first embodiment of the present invention will be described. 1 to 3 are sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.
[0013]
In the present embodiment, first, as shown in FIG. 1A, an element isolation region is selectively formed on a surface of a semiconductor substrate 1 such as a Si substrate to partition an element active region. Next, a gate insulating film 3, a gate electrode 4, and a sidewall 5 are formed on the semiconductor substrate 1 in the element active region. Although the semiconductor substrate 1 is preferably made of an intrinsic semiconductor, impurities may be introduced.
[0014]
Next, as shown in FIG. 1B, two metal films 6 and 7 are sequentially deposited on the entire surface. When forming a P-type transistor, for example, a Pt film is formed as the lower metal film 6, and when an N-type transistor is formed, for example, an Er film or an Sm film is formed. Further, a Ti film or a Ni film may be formed. When a Ti film or a Ni film is formed, the device can operate as either a P-type transistor or an N-type transistor depending on the direction of voltage application. As the upper metal film 7, for example, a Ni film, a Co film, or a Ti film is formed. The thickness of the metal films 6 and 7 is, for example, about 10 nm.
[0015]
Subsequently, the metal films 6 and 7 react with the semiconductor substrate 1 by performing, for example, a heat treatment at 400 ° C. for about 30 minutes. As a result, compound films 8 and 9 of a semiconductor and a metal are formed on the surface of the semiconductor substrate 1 as shown in FIG. As for the stacking relationship between the compound films 8 and 9, the compound film 8 formed by the reaction between the metal film 6 and the semiconductor substrate 1 is changed to the compound film formed by the reaction between the metal film 7 and the semiconductor substrate 1. 9 and the semiconductor substrate 1. The compound film 8 is made of, for example, ErSi, PtSi, SmSi, TiSi, or NiSi film, and the compound film 9 is made of, for example, a NiSi film, a CoSi film, a TiSi film, or the like.
[0016]
Thereafter, as shown in FIG. 2A, unreacted portions of the metal films 6 and 7 are removed.
[0017]
Next, as shown in FIG. 2B, an interlayer insulating film 11, a source wiring 10S, a gate wiring 10G, and a drain wiring 10D are formed. Both the source wiring 10S and the drain wiring 10D are connected to the compound film 9.
[0018]
Then, as shown in FIG. 3, a plurality of interlayer insulating films 21 and wirings 22 are further formed, and a cover film 23 is formed on the uppermost layer, thereby completing the semiconductor device.
[0019]
The structure of the semiconductor device manufactured in this manner is such that, in a Schottky source / drain MOSFET, not only a compound film 8 made of ErSi or PtSi for Schottky barrier modulation but also a NiSi , CoSi or TiSi is formed. Further, in the case of a compound of a semiconductor and a metal and a metal, the carrier density is at least one order of magnitude higher and the resistance value is significantly lower than that of a semiconductor layer in which impurities are doped to near the solid solubility limit. For this reason, according to the present embodiment, the presence of the compound film 9 makes it possible to lower the contact resistance between the compound film 8 and the source wiring 10S and the drain wiring 10D as compared with the conventional one. In particular, NiSi has a very low resistivity, so that the effect is remarkable.
[0020]
Further, in the laminated silicide structure, a reduction in parasitic resistance can be expected. In the present embodiment, since the stacked silicide structure of the compound films 8 and 9 is adopted for the source and the drain, the reduction of the parasitic resistance enables the high integration accompanying the reduction of the element area and the improvement of the DC characteristics and the high frequency characteristics. It becomes possible.
[0021]
(Second embodiment)
Next, a second embodiment of the present invention will be described. 4 to 6 are sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.
[0022]
In this embodiment, as shown in FIG. 4A, an SOI substrate 12 in which an insulating layer 14 and a silicon layer 15 are formed on a semiconductor substrate 13 such as a Si substrate is used as a substrate. First, as shown in FIG. 4A, the element isolation region is selectively formed on the surface of the silicon layer 15 to partition the element active region. At this time, the element isolation insulating film 2 is formed so as to reach, for example, the insulating layer 14. The thickness of the insulating layer 14 is, for example, about 100 nm, and the thickness of the silicon layer 15 is, for example, about 20 nm to 30 nm. Next, the gate insulating film 3, the gate electrode 4, and the sidewall 5 are formed on the silicon layer 15 in the element active region. The silicon layer 15 is preferably made of an intrinsic semiconductor, but may be doped with impurities.
[0023]
Next, as shown in FIG. 4B, the silicon layer 15 is etched by about 10 nm. As the etching method at this time, for example, wet etching using TMAH (tetramethyl ammonium hydroxide) or RIE (reactive ion etching) is employed.
[0024]
Next, as shown in FIG. 4C, a metal film 6 is sequentially deposited on the entire surface. As the metal film 6, when forming a P-type transistor, for example, a Pt film is formed, and when forming an N-type transistor, for example, an Er film or an Sm film is formed. Further, a Ti film or a Ni film may be formed. The thickness of the metal film 6 is, for example, about 10 nm.
[0025]
Subsequently, the metal film 6 and the silicon layer 15 are reacted by, for example, performing a heat treatment at 400 ° C. for about 30 minutes. As a result, a compound film 8 of silicon and metal is formed on the insulating layer 14 as shown in FIG. At this time, the entire exposed area of the silicon layer 15 reacts with the metal film 6, but a part of the silicon layer 15 remains below the gate insulating film 3 without reacting. The compound film 8 is made of, for example, an ErSi, PtSi, SmSi, TiSi, NiSi film, or the like.
[0026]
Thereafter, as shown in FIG. 5B, the unreacted portions of the metal film 6 are removed.
[0027]
Next, as shown in FIG. 5C, a metal film 7 is sequentially deposited on the entire surface. As the metal film 7, for example, a Ni film, a Co film, or a Ti film is formed. The thickness of the metal film 7 is, for example, about 10 nm.
[0028]
Next, for example, heat treatment is performed at 400 ° C. to 700 ° C. for about 30 minutes to cause the metal film 7 to react with silicon in the compound film 8. As a result, a compound film 9 of silicon and metal is formed on the insulating layer 14 as shown in FIG. The entire exposed area of the compound film 8 reacts with the metal film 7, but a part of the compound film 8 remains below the sidewall 5 without reacting. The compound film 9 is made of, for example, a NiSi film, a CoSi film, a TiSi film, or the like.
[0029]
Subsequently, as shown in FIG. 6B, unreacted portions of the metal film 7 are removed.
[0030]
Thereafter, as shown in FIG. 6C, an interlayer insulating film 11, a source wiring 10S, a gate wiring 10G, and a drain wiring 10D are formed. Then, although not shown, an interlayer insulating film, wiring, a cover film, and the like are further formed to complete the semiconductor device.
[0031]
The structure of the semiconductor device manufactured in this manner is similar to that of the first embodiment. In the Schottky source / drain MOSFET, a compound film made of ErSi or PtSi for Schottky barrier modulation is formed on the source and the drain. In addition, a compound film 9 is formed between the compound film 8 and the source wiring 10S and the drain wiring 10D. Therefore, according to the present embodiment, the same effects as those of the first embodiment can be obtained.
[0032]
Furthermore, in the present embodiment, since the element active region is completely surrounded by the element isolation insulating film 2 and the insulating layer 14, that is, it is of a fully depleted type, current leakage to the outside is prevented. The effect of being prevented is also obtained.
[0033]
It should be noted that a partially depleted (partial depletion) type in which the silicon layer 15 is formed thicker than the fully depleted type of the second embodiment may be employed. FIG. 7 shows a structure when the partially depleted type is adopted. Although the partially depleted type cannot completely prevent the leak current as in the fully depleted type, the same effect as that of the first embodiment can be obtained.
[0034]
(Third embodiment)
Next, a third embodiment of the present invention will be described. 8 to 10 are sectional views showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps.
[0035]
In this embodiment, as in the second embodiment, the element isolation insulating film 2 is selectively formed on the surface of the silicon layer 15 of the SOI substrate 12 as shown in FIG. Partition the active area. At this time, the element isolation insulating film 2 is formed so as to reach, for example, the insulating layer 14. The thickness of the insulating layer 14 is, for example, about 100 nm, and the thickness of the silicon layer 15 is, for example, about 20 nm to 30 nm. Next, the gate insulating film 3, the gate electrode 4, and the sidewall 5 are formed on the silicon layer 15 in the element active region. The silicon layer 15 is preferably made of an intrinsic semiconductor, but may be doped with impurities.
[0036]
Next, as shown in FIG. 8B, the insulating layer 14 is exposed by etching all the exposed portions of the silicon layer 15. As an etching method at this time, for example, wet etching by TMAH or RIE (reactive ion etching) is employed.
[0037]
Next, as shown in FIG. 8C, a metal film 6 is sequentially deposited on the entire surface. As the metal film 6, when forming a P-type transistor, for example, a Pt film is formed, and when forming an N-type transistor, for example, an Er film or an Sm film is formed. Further, a Ti film or a Ni film may be formed. The thickness of the metal film 6 is, for example, about 10 nm.
[0038]
Subsequently, the metal film 6 and the silicon layer 15 are reacted by, for example, performing a heat treatment at 400 ° C. for about 30 minutes. As a result, a compound film 8 of silicon and metal is formed between the insulating layer 14 and the sidewall 5 as shown in FIG. At this time, a part of the silicon layer 15 remains below the gate insulating film 3 without reacting. The compound film 8 is made of, for example, an ErSi, PtSi, SmSi, TiSi, NiSi film, or the like.
[0039]
Thereafter, as shown in FIG. 9B, unreacted portions of the metal film 6 are removed.
[0040]
Next, as shown in FIG. 9C, a metal film 7 is sequentially deposited on the entire surface. As the metal film 7, for example, a Ni film, a Co film, or a Ti film is formed. The thickness of the metal film 7 is, for example, about 10 nm.
[0041]
Next, for example, heat treatment is performed at 400 ° C. to 700 ° C. for about 30 minutes to cause the metal film 7 to react with silicon in the compound film 8. As a result, a compound film 9 of silicon and a metal is formed between the insulating layer 14 and the sidewall 5 as shown in FIG. At this time, the compound film 8 remains between the compound film 9 and the silicon layer 15. The compound film 9 is made of, for example, a NiSi film, a CoSi film, a TiSi film, or the like.
[0042]
Subsequently, as shown in FIG. 10B, an unreacted portion of the metal film 7 is removed.
[0043]
Thereafter, as shown in FIG. 10C, an interlayer insulating film 11, a source wiring 10S, a gate wiring 10G, and a drain wiring 10D are formed. Then, although not shown, an interlayer insulating film, wiring, a cover film, and the like are further formed to complete the semiconductor device.
[0044]
The structure of the semiconductor device manufactured in this manner is similar to that of the first embodiment. In the Schottky source / drain MOSFET, a compound film made of ErSi or PtSi for Schottky barrier modulation is formed on the source and the drain. In addition, a compound film 9 is formed between the compound film 8 and the source wiring 10S and the drain wiring 10D. Therefore, according to the present embodiment, the same effects as those of the first embodiment can be obtained.
[0045]
Furthermore, as in the second embodiment, since a full-depression structure is employed, leakage of current is prevented.
[0046]
(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. 11 to 13 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.
[0047]
In the present embodiment, a double gate structure is employed as shown in FIG. That is, the back gate 16 is formed on the surface of the SOI substrate 12 in contact with the insulating layer 14 of the semiconductor substrate 13. The back gate 16 can be formed by, for example, the following two methods, but the method is not particularly limited.
[0048]
In the first method, a back gate 16 is formed by forming a groove in the surface of the semiconductor substrate 13 by using a damascene method, embedding a metal film in the groove, and planarizing the groove. After that, the insulating layer 14 and the silicon layer 15 are formed on the semiconductor substrate 13.
[0049]
In the second method, ions are implanted into the SOI substrate 12 to directly form the back gate 16.
[0050]
Then, in the present embodiment, the same steps as in the third embodiment are performed using the SOI substrate 12 having the back gate 16.
[0051]
That is, first, as shown in FIG. 11A, an interlayer insulating film 2, a gate insulating film 3, a gate electrode 4, and a sidewall 5 are formed. Next, as shown in FIG. 11B, a metal film 6 is formed. Next, a heat treatment is performed to form a compound film 8 as shown in FIG.
[0052]
Subsequently, as shown in FIG. 12A, unreacted portions of the metal film 6 are removed. Thereafter, as shown in FIG. 12B, a metal film 7 is formed, and heat treatment is performed to form a compound film 8 as shown in FIG. 12C.
[0053]
Next, as shown in FIG. 13A, unreacted portions of the metal film 7 are removed. Next, as shown in FIG. 13B, an interlayer insulating film 11, a source wiring 10S, a gate wiring 10G, and a drain wiring 10D are formed. Then, although not shown, an interlayer insulating film, wiring, a cover film, and the like are further formed to complete the semiconductor device.
[0054]
In the semiconductor device manufactured as described above, the same effects as in the third embodiment can be obtained. Further, since the double gate structure is employed, it is possible to cope with further miniaturization.
[0055]
Note that the back gate structure can be applied to the second embodiment.
[0056]
(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described. FIG. 14 is a sectional view showing the structure of the semiconductor device according to the fifth embodiment of the present invention.
[0057]
In this embodiment, a stacked channel is applied to the first embodiment. That is, in the present embodiment, as shown in FIG. 14, the SiGe film 17 and the Si film 18 are sequentially stacked on the semiconductor substrate 1, and this portion is used as a channel. Further, a large amount of strain is introduced into the SiGe film 17 due to a difference from the lattice constant of the semiconductor substrate (Si substrate) 1, and such a film is called strained SiGe. Also, a large amount of strain may be introduced into the Si film 18 due to a difference from the lattice constant of the SiGe film.
[0058]
In the fifth embodiment configured as described above, in addition to the same effects as those of the first embodiment, the effect of increasing the operation speed can be obtained by employing strained Si.
[0059]
Here, a method for manufacturing the semiconductor device according to the fifth embodiment will be described.
[0060]
First, a SiGe film 17 is deposited on the semiconductor substrate 1 by a chemical vapor deposition (CVD) method. The atomic ratio between Si and Ge is, for example, 0.7: 0.3. The thickness of the SiGe film 17 is, for example, about 10 nm. Next, a Si film 18 is deposited on the SiGe film 17 by a CVD method. The thickness of the Si film 18 is, for example, about 5 nm.
[0061]
After that, as in the first embodiment, the steps from the step of forming the element isolation insulating film 2 to the step of completing the semiconductor device are performed. Thus, the semiconductor device according to the fifth embodiment can be obtained.
[0062]
(Sixth to eighth embodiments)
Next, sixth to eighth embodiments of the present invention will be described. 15 to 17 are cross-sectional views showing the structures of the semiconductor devices according to the sixth to eighth embodiments of the present invention, respectively.
[0063]
As shown in FIGS. 15 to 17, in the sixth to eighth embodiments, the stacked channels are applied to the second to fourth embodiments, similarly to the fifth embodiment. It is.
[0064]
According to these embodiments, in addition to the effects obtained by the second to fourth embodiments, the effect of increasing the operation speed can be obtained.
[0065]
In the second to fourth embodiments, since the SOI substrate 12 is used, the silicon layer 15 is formed on the insulating layer 14, but the SiGe layer is formed instead of the silicon layer 15. Is also good. That is, as in FIGS. 6 to 8, after forming a SiGe film on an insulating film on a semiconductor substrate, an element isolation insulating film may be formed without forming a Si film. .
[0066]
In the case where a stacked channel is applied as in the fifth to eighth embodiments, a Schottky junction layer may be provided for the source and the drain for each layer included in the channel. However, even in this case, it is necessary to provide a low-resistance layer (corresponding to the compound film 9) in a portion connected to the wiring. By providing a Schottky junction layer for each channel layer, it is possible to select an optimum material for the Schottky junction for each channel layer.
[0067]
Further, the Schottky junction as described above does not necessarily need to be provided on both the source and the drain. If at least one is provided, the effect of the present invention can be obtained in the source or the drain.
[0068]
Further, in at least one of the source and the drain, all or a part of the stacked film may be a metal film instead of a compound film. In order to manufacture such a semiconductor device, for example, as shown in FIGS. 4B and 8B, after a semiconductor region is etched, a metal film is formed by a method such as evaporation. Thereafter, the semiconductor device is completed without converting the metal film into a silicide, or as shown in FIGS. 5B and 9B, after forming a compound film, the metal film which is the raw material film is removed. Alternatively, another metal film may be formed by a method such as evaporation, and then the semiconductor device may be completed without silicidation of the metal film.
[0069]
Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.
[0070]
(Supplementary Note 1) A channel made of a semiconductor,
A source and a drain in contact with the channel;
A source wiring and a drain wiring connected to the source and the drain, respectively;
Has,
At least one of the source and the drain is at least
A first film made of a metal or a compound of a metal and a semiconductor and Schottky-joined to the channel;
A second film made of a metal different from the first film or a compound of a metal and a semiconductor, and in contact with the source wiring or the drain wiring;
A semiconductor device comprising:
[0071]
(Supplementary Note 2) The channel has a plurality of semiconductor films that are heterojunction with each other,
2. The semiconductor device according to claim 1, wherein the first film includes a plurality of metal films or a compound film of a metal and a semiconductor, each of the plurality of metal films being Schottky-bonded to the plurality of semiconductor films.
[0072]
(Supplementary Note 3) The semiconductor device according to supplementary note 2, wherein the channel includes a SiGe film and a Si film formed on the SiGe film.
[0073]
(Supplementary Note 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the resistance of the second film is lower than the resistance of the first film.
[0074]
(Supplementary Note 5) The semiconductor according to any one of Supplementary Notes 1 to 4, wherein the second film contains at least one metal element selected from the group consisting of Ni, Co, and Ti. apparatus.
[0075]
(Supplementary Note 6) A semiconductor substrate;
An insulating layer formed on the semiconductor substrate,
Has,
6. The semiconductor device according to claim 1, wherein the channel is formed on the insulating layer.
[0076]
(Supplementary note 7) The semiconductor device according to supplementary note 6, further comprising a back gate formed on a surface of the semiconductor substrate so as to match the channel.
[0077]
(Supplementary Note 8) The semiconductor device according to supplementary note 6 or 7, wherein the first film is in contact with the insulating layer.
[0078]
(Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the channel is completely depleted.
[0079]
(Supplementary Note 10) a step of forming a gate insulating film, a gate electrode, and a sidewall on a substrate having a semiconductor region on a surface;
Forming a source and a drain in contact with the semiconductor region;
Forming a source wiring and a drain wiring connected to the source and the drain, respectively;
A method for manufacturing a semiconductor device having
The step of forming the source and the drain includes, in at least one of the source and the drain, a first film made of a metal or a compound of a metal and a semiconductor, and a Schottky junction with the semiconductor region; A method of manufacturing a semiconductor device, comprising a step of forming a second film made of a metal different from the above or a compound of a metal and a semiconductor and in contact with the source wiring or the drain wiring.
[0080]
(Supplementary Note 11) The semiconductor region includes a plurality of semiconductor films that are heterojunction with each other,
11. The semiconductor device according to claim 10, wherein, in the step of forming the first film, a plurality of metal films or a compound film of a metal and a semiconductor are formed by Schottky bonding to the plurality of semiconductor films, respectively. Manufacturing method.
[0081]
(Supplementary Note 12) The method for manufacturing a semiconductor device according to Supplementary Note 11, wherein the semiconductor region includes a SiGe film and a Si film formed on the SiGe film.
[0082]
(Supplementary Note 13) In the step of forming the second film, a film having a resistance lower than the resistance of the first film is formed as the second film. 9. The method for manufacturing a semiconductor device according to claim 1.
[0083]
(Supplementary Note 14) In the step of forming the second film, a film containing at least one metal element selected from the group consisting of Ni, Co, and Ti is formed as the second film. 14. The method of manufacturing a semiconductor device according to any one of supplementary notes 10 to 13.
[0084]
(Supplementary Note 15) As the substrate, a substrate including a semiconductor substrate, an insulating layer formed over the semiconductor substrate, and a semiconductor layer formed over the insulating layer is used. 15. The method for manufacturing a semiconductor device according to any one of 14.
[0085]
(Supplementary Note 16) A substrate having a back gate formed on a surface of the semiconductor substrate is used as the substrate,
The method of manufacturing a semiconductor device according to claim 15, wherein in the step of forming the gate insulating film, the gate electrode, and the sidewall, the gate electrode is formed so as to match the back gate.
[0086]
(Supplementary note 17) The method for manufacturing a semiconductor device according to supplementary note 15 or 16, wherein in the step of forming the source and the drain, the first film is formed so as to be in contact with the insulating layer.
[0087]
(Supplementary Note 18) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 10 to 17, wherein a substrate in which the semiconductor region is completely depleted is used as the substrate.
[0088]
(Supplementary Note 19) The step of forming the first film and the second film includes:
Sequentially forming first and second metal films in the semiconductor region;
By reacting the semiconductor region and the first metal film to form a first compound film as the first film, and by reacting the semiconductor region and the second metal film, Forming a second compound film as the second film;
19. The method of manufacturing a semiconductor device according to any one of supplementary notes 10 to 18, further comprising:
[0089]
(Supplementary Note 20) The step of forming the first film and the second film includes:
Forming a depression in the semiconductor region using the sidewall as a mask;
Forming a first metal film in the depression;
Forming a first compound film as the first film by reacting the semiconductor region with the first metal film;
Removing a portion of the first metal film that has not reacted with the semiconductor region;
Forming a second metal film in the depression;
Forming a second compound film as the second film by reacting the semiconductor region with the second metal film;
Removing a portion of the second metal film that has not reacted with the semiconductor region;
19. The method of manufacturing a semiconductor device according to any one of supplementary notes 10 to 18, further comprising:
[0090]
(Supplementary Note 21) The step of forming the first film and the second film includes:
Exposing the insulating layer by etching the semiconductor region using the sidewall as a mask,
Forming a first metal film so as to contact a remaining portion of the semiconductor region;
Forming a first compound film as the first film by reacting the remaining portion with the first metal film;
Removing a portion of the first metal film that has not reacted with the remaining portion;
Forming a second metal film in contact with the remaining portion of the semiconductor region;
Forming a second compound film as the second film by reacting the remaining portion with the second metal film;
19. The method of manufacturing a semiconductor device according to claim 15, further comprising: removing a portion of the second metal film that has not reacted with the remaining portion.
[0091]
【The invention's effect】
As described in detail above, according to the present invention, the resistance of the second film can be controlled independently of the resistance of the first film, so that the parasitic resistance can be reduced. As a result, it is possible to improve DC characteristics and high frequency characteristics, and to avoid an increase in resistance value due to an area reduction effect even when miniaturization is performed to improve the performance of CMOS and the like and to improve the degree of integration. Can be.
[Brief description of the drawings]
FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.
FIG. 2 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment in the order of steps, illustrating a step subsequent to the step illustrated in FIG. 1;
3 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment, illustrating a step subsequent to the step illustrated in FIG. 2;
FIG. 4 is a sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.
FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps, and is a view showing a step subsequent to the step shown in FIG. 4;
FIG. 6 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the second embodiment in the order of steps, and is a view illustrating a step subsequent to the step illustrated in FIG. 5;
FIG. 7 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the second embodiment, illustrating a step subsequent to the step illustrated in FIG. 4;
FIG. 8 is a sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.
FIG. 9 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the third embodiment in the order of steps, and is a view illustrating a step subsequent to the step illustrated in FIG. 8;
FIG. 10 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the third embodiment in the order of steps, and is a view illustrating a step subsequent to the step illustrated in FIG. 9;
FIG. 11 is a sectional view illustrating a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention in the order of steps.
FIG. 12 is a cross-sectional view showing a method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps, and is a view showing a step subsequent to the step shown in FIG. 11;
FIG. 13 is a cross-sectional view showing a manufacturing method of the semiconductor device according to the fourth embodiment in the order of steps, and is a view showing a step subsequent to the step shown in FIG. 12;
FIG. 14 is a sectional view showing a structure of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 15 is a sectional view illustrating a structure of a semiconductor device according to a sixth embodiment of the present invention.
FIG. 16 is a sectional view illustrating a structure of a semiconductor device according to a seventh embodiment of the present invention.
FIG. 17 is a sectional view illustrating a structure of a semiconductor device according to an eighth embodiment of the present invention.
[Explanation of symbols]
1; semiconductor substrate
2: Element isolation insulating film
3: Gate insulating film
4: Gate electrode
5; sidewall
6, 7; metal film
8, 9; compound film
10G; gate wiring
10S; source wiring
10D; drain wiring
11; interlayer insulating film
12; SOI substrate
13; semiconductor substrate
14; insulating layer
15; silicon layer
16; back gate
17; SiGe film
18; Si film

Claims (10)

A semiconductor channel;
A source and a drain in contact with the channel;
A source wiring and a drain wiring connected to the source and the drain, respectively;
Has,
At least one of the source and the drain is at least
A first film made of a metal or a compound of a metal and a semiconductor and Schottky-joined to the channel;
A second film made of a metal different from the first film or a compound of a metal and a semiconductor, and in contact with the source wiring or the drain wiring;
A semiconductor device comprising: The channel has a plurality of semiconductor films heterojunction with each other,
2. The semiconductor device according to claim 1, wherein the first film is composed of a plurality of metal films or a compound film of a metal and a semiconductor, each of which is Schottky-bonded to the plurality of semiconductor films. 3. The semiconductor device according to claim 2, wherein the channel has a SiGe film and a Si film formed on the SiGe film. 4. The semiconductor device according to claim 1, wherein the resistance of the second film is lower than the resistance of the first film. 5. A semiconductor substrate;
An insulating layer formed on the semiconductor substrate,
Has,
The semiconductor device according to claim 1, wherein the channel is formed on the insulating layer. Forming a gate insulating film, a gate electrode, and a sidewall on a substrate having a semiconductor region on a surface thereof;
Forming a source and a drain in contact with the semiconductor region;
Forming a source wiring and a drain wiring connected to the source and the drain, respectively;
A method for manufacturing a semiconductor device having
The step of forming the source and the drain includes, in at least one of the source and the drain, a first film made of a metal or a compound of a metal and a semiconductor, and a Schottky junction with the semiconductor region; A method of manufacturing a semiconductor device, comprising a step of forming a second film made of a metal different from the above or a compound of a metal and a semiconductor and in contact with the source wiring or the drain wiring. The semiconductor region has a plurality of semiconductor films heterojunction with each other,
7. The semiconductor according to claim 6, wherein, in the step of forming the first film, a plurality of metal films or a compound film of a metal and a semiconductor are formed by Schottky junction with the plurality of semiconductor films, respectively. Device manufacturing method. The method according to claim 7, wherein the semiconductor region includes a SiGe film and a Si film formed on the SiGe film. 9. The method according to claim 6, wherein in the step of forming the second film, a film having a lower resistance than the resistance of the first film is formed as the second film. 13. The method for manufacturing a semiconductor device according to item 5. 10. The substrate according to claim 6, wherein a substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer is used. 9. The method for manufacturing a semiconductor device according to claim 1.

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