JP2006237512A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To particularly improve the controllability of a gate electrode to a channel region in the vicinity of a source, and to enhance the current driving capacity of an element in a Schottky type field-effect transistor. <P>SOLUTION: A thickness in the geometric meaning of a gate insulating film can be made thinner than a semiconductor device formed only of a material having a high dielectric constant, by laminating a film having the dielectric constant different from the gate insulating film. The deterioration of the controllability of the gate electrode can be inhibited to the potential of the channel region in the vicinity of the source region particularly, resulting from a leakage to the outside from the side face of the gate insulating film of an electric-force line emitted from the gate electrode. The electric-force line emitted from the gate electrode can be collected in the channel region in the vicinity of the source region by the bending of the electric-force line on the interface of a substance having the different dielectric constant, by forming a gate side-wall insulating film 12 composed of the material having the high dielectric constant. A Schottky barrier formed between the source region and the channel region is thinned, and the resistance of the Schottky barrier is reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a Schottky field effect transistor.

  FIG. 25 is a cross-sectional view of a conventional Schottky field effect transistor. Here, an N channel field effect transistor is taken as an example. As shown in FIG. 25, in a conventional field effect transistor, an element isolation region 2 is formed on a semiconductor substrate 1 by a trench element isolation method. An N channel region 3 is formed in the semiconductor substrate 1 by B (boron) ion implantation. A gate insulating film 4 is formed on the N channel region 3 by an insulating film such as a metal oxide having a dielectric constant higher than that of silicon oxide. A thickness of 100 nm is formed on the gate insulating film 4 by sputtering. A refractory metal is deposited to form the gate electrode 5. A source / drain region 6 is formed by forming a silicide layer so as to sandwich the gate electrode 5. In this figure, interlayer insulating films, wirings, etc. are omitted.

As a specific example of the basic configuration of the Schottky field effect transistor, for example, a semiconductor device in which an HfO ₂ film is applied to the gate insulating film 4 and a TaN / HfN laminated film is applied to the gate electrode 5 is described below. This is shown in Fig.2. Incidentally, the TaN / HfN multilayer film has the purpose of adjusting the threshold voltage by forming the vicinity of the gate insulating film with HfN, and reducing the gate resistance by providing the TaN layer on top of it. The means and purpose are different.
S.Zhu et al. Solid-State Electronics 48 (2004) p.1987-p.1992

  In the above-described conventional field effect transistor, the gate electrode is formed of a refractory metal in order to reduce the resistance for the purpose of increasing the operation speed of the element, and the gate insulating film does not increase the current driving force. In order to improve the controllability of the gate electrode with respect to the potential of the channel region and to suppress the gate current by forming it thickly, it is made of a material having a higher dielectric constant than silicon oxide such as metal oxide, that is, a high dielectric material. Has been. The strength of capacitive coupling between the channel region and the gate electrode is determined by dividing the product of the dielectric film thickness and the dielectric constant of silicon oxide (3.9) by the dielectric constant of the film. When the insulating film is formed of a high dielectric material, the gate insulating film can be formed thick while maintaining the controllability of the gate electrode with respect to the potential of the channel region.

However, as shown in FIG. 26 showing the simulation result of the dependence of the drain current on the gate voltage, increasing the dielectric constant of the gate insulating film while keeping the equivalent oxide thickness of the gate insulating film constant reduces the current value. This has hindered high current driving capability. This simulation is based on the value per unit width (1 micron) of the drain current when the channel length is 35 nm and the equivalent oxide thickness of the gate insulating film is 1 nm, and the drain voltage (V _D ) is 1 V. is there. It can be seen that the drain current decreases as the dielectric constant of the gate insulating film increases to 3.9, 10, and 20.

  The decrease in the drain current accompanying the increase in the dielectric constant of the gate insulating film is due to the following two reasons. One is that the gate insulating film has a geometrical thickness that increases as the dielectric constant is increased by keeping the equivalent oxide thickness of the gate insulating film constant. The electric lines of force leak from the side surface of the gate insulating film to the outside, and the electric lines of force reaching the channel region are reduced. In this example, an n-type field effect transistor has been described as an example, so the term “electric field lines come out of the gate electrode” is used. However, as in the case of a p-type field effect transistor, the gate electrode When the potential is lower than the channel region, the electric lines of force are “toward the gate electrode”. However, the phrase “electric field lines coming out of the gate electrode” including this case is used in this specification. The other is that the capacitive coupling between the source region and the channel region due to the electric lines of force penetrating the gate insulating film is strengthened as the dielectric constant of the gate insulating film is increased. Since the potential of the nearby channel region is brought close to the potential of the source region, the Schottky barrier formed between the source region and the channel region becomes thick, and as a result, the Schottky barrier resistance increases. Both of these phenomena exist even in a field effect transistor having a source / drain region of a normal pn junction, but in a Schottky field effect transistor, it is formed between a source region and a channel region. Since the Schottky barrier resistance is important in determining the current, the effects of these phenomena are particularly pronounced. Therefore, increasing the dielectric constant of the gate insulating film has been an obstacle to high driving force.

  Further, in the conventional field effect transistor shown in FIG. 25 and FIG. 2 of the non-patent document, the side wall is not formed on the gate electrode. For this reason, when silicidation for forming the source / drain regions is performed, there is a problem of causing so-called bridging in which the source / drain regions and the gate electrode are short-circuited. This is a fatal problem because normal operation of the device becomes impossible if bridging occurs.

  One possible solution to this problem is to provide a side wall on the gate electrode. In this case, the source / drain region is located farther from the center of the channel by the width of the side wall than when there is no side wall. Therefore, there is no overlap between the gate electrode and the source / drain region, and an offset is formed. When the offset is formed, the current value decreases as shown in the simulation result of the dependence of the drain current on the gate voltage as shown in FIG. 27, which also hinders the high current driving capability. In this simulation, the unit width of the drain current (1 micron) at the drain voltage (VD) = 1 V of the element of silicon oxide (dielectric constant = 3.9) with a channel length of 35 nm and a gate insulating film of 1 nm thickness. ) Value. There is almost no difference between the case where the overlap length of the source / drain region and the gate electrode is 0 nm and 2 nm, but when there is an offset of 2 nm, the drain current value is greatly reduced. I understand. This decrease in drain current is due to the following reason. When the offset occurs, the Schottky barrier formed between the source region and the channel region becomes thick because the controllability of the gate electrode with respect to the potential of the channel region in the vicinity of the source / drain region is lowered. The resistance of the key barrier increases. This phenomenon exists even in a field effect transistor having a source / drain region of a normal pn junction, but in a Schottky field effect transistor, a Schottky barrier is formed between the source region and the channel region. The effect of this phenomenon is particularly noticeable because the resistance of the current is important in determining the current. In order to prevent bridging between the source / drain regions and the gate electrode, in addition to providing a gate side wall insulating film, a high dielectric material is used for the gate insulating film in the geometrical meaning of the gate insulating film. It is also possible to increase the thickness and to keep the source / drain regions and the gate electrode away from each other. However, there is a problem as described above with reference to FIG. 26 in forming a thick gate insulating film using a high dielectric material. These phenomena are obstacles to realizing high-speed operation of the element.

  The present invention has been made to solve the above problems, and its purpose is to improve the controllability of the gate electrode with respect to the potential of the channel region and to prevent bridging between the source / drain region and the gate electrode. An object of the present invention is to provide a high-performance fine semiconductor device capable of sufficiently high-speed operation.

  In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor substrate having a semiconductor layer, a first insulating film formed on the semiconductor layer, the first insulating film formed on the first insulating film, and the A second insulating film having a dielectric constant different from that of the first insulating film, a gate electrode formed on the second insulating film, and a surface portion of the semiconductor substrate so as to sandwich the gate electrode And a source region and a drain region made of metal or metal silicide.

  The semiconductor device of the present invention is a Schottky field effect transistor, and the gate insulating film is a stack of films having different dielectric constants. As a result, the gate insulating film can be formed thicker in terms of the geometrical meaning compared to the conventional case where the gate insulating film is formed only from silicon oxide. It is possible to suppress the current flowing through the gate insulating film while maintaining high controllability of the gate insulating film. On the other hand, compared to the case where the gate insulating film is formed only of a material having a high dielectric constant, It is possible to reduce the thickness of the gate region, and the electric field lines from the gate electrode leak out from the side surface of the gate insulating film. It is possible to suppress a decrease in the controllability of the gate electrode. The problem of leakage of electric lines of force from the side surface of the gate insulating film is that resistance in a Schottky field effect transistor is due to the thick Schottky barrier formed between the source region and the channel region. Increase, which greatly hinders the realization of a high current driving force. This problem is suppressed in the semiconductor device of the present invention.

  Hereinafter, details of the present invention will be described with reference to the illustrated embodiments.

In order to achieve the above object, the present invention relates to a Schottky field effect transistor composed of a stack of films having different dielectric constants in a gate insulating film, and a gate insulating film that is such a device and includes a stack. And a device having a gate sidewall insulating film having a dielectric constant higher than that of the lower dielectric constant.

In the field effect transistor of the present invention, since the gate insulating film is a laminate of a material having a high dielectric constant and a low material, it is geometrical compared to the case where the entire gate insulating film is formed of silicon oxide as usual. It is possible to increase the thickness of the film in a scientific sense, and it is possible to suppress the gate leakage current while maintaining the controllability of the gate electrode with respect to the potential of the channel region. In addition, since it is possible to reduce the geometrically meaning film thickness compared to the case where the entire gate insulating film is formed of a high dielectric material, the electric lines of force from the gate electrode as described above are not generated. The effect of leaking from the side surface of the gate insulating film is suppressed. Therefore, a high current driving force can be obtained. Furthermore, if the dielectric constant of the film closer to the substrate in the laminated gate insulating film is set lower than the dielectric constant of the film far from the substrate, the source region and the channel depend on the lines of electric force penetrating the gate insulating film laterally. Since the capacitive coupling with the region is weakened, the shot formed between the source region and the channel region due to the fact that this capacitive coupling is larger than when the gate insulating film is formed of conventional silicon oxide. The increase in resistance and the resulting decrease in current driving force due to the thicker key barrier are suppressed. Assuming that the gate insulating film is a laminate of a film having a dielectric constant of 3.9 (e.g., silicon oxide) and a film having a dielectric constant of 20 (e.g., hafnium dioxide film), the total equivalent oxide thickness of the gate insulating film is maintained at a constant value of 1 nm. FIG. 1 shows a simulation result of the dependence of the drain current on the geometric thickness of the gate insulating film when the thickness of each film is changed. The simulation result shows that the channel length is 35 nm, the total oxide equivalent film thickness of the gate insulating film = 1 nm, the overlap length of the gate electrode and the source / drain region = 2 nm, the drain voltage (V _D ) = gate voltage ( V _G ) = A value per unit width (1 micron) of drain current at 1 V. In Case 1, the dielectric constant of the film closer to the substrate of the gate insulating film is low and the dielectric constant of the film far from the substrate is high. In Case 2, the dielectric constant of the film closer to the substrate of the gate insulating film is If the dielectric constant of the film that is high and far from the substrate is low, Case 3 is a single layer of a film with a dielectric constant = 3.9, and Case 4 is a single layer of a film with a dielectric constant = 20 If the result is. Further, the horizontal axis of this figure is the film thickness in the geometric sense of the entire gate insulating film. In this simulation, the total oxide equivalent film thickness of the gate insulating film is kept constant, and the thickness of each film in the stack is changed. Therefore, the geometrically meaning film thickness of the gate insulating film varies. Value. Looking at this figure, it is effective to improve the current driving force by reducing the gate thickness from a single layer of a high dielectric constant material film to a laminated film and reducing the geometric thickness. Of the films that form the gate insulating film, the film closer to the substrate is formed of a material having a low dielectric constant, and the film far from the substrate is formed of a material having a high dielectric constant. It turns out that it is the target.

Next, a case where a gate sidewall insulating film made of a high dielectric material is provided in addition to such a laminated gate insulating film structure will be considered. FIG. 2 shows a simulation result of the drain current value of the two-layer laminated gate insulating film element having the gate sidewall insulating film. This simulation result shows that the device drain voltage (V _D ) = gate voltage (V _G ) with a channel length of 35 nm, gate oxide equivalent oxide thickness = 1 nm, gate sidewall insulation thickness = 10 nm = Value per unit width (1 micron) of drain current at 1 V, and it is assumed that there is an offset of 2 nm between the gate electrode and the source / drain region because the gate sidewall insulating film is provided . Case 5 in the figure shows that the dielectric constant of the film closer to the substrate of the laminated gate insulating film is 3.9 and the dielectric constant of the film far from the substrate is 20, and Case 6 is the one closer to the substrate of the laminated gate insulating film. When the dielectric constant of the film is 20 and the dielectric constant of the film far from the substrate is 3.9, and the dielectric constant of the gate sidewall insulating film = 3.9, the dielectric constant of the gate sidewall insulating film = 20 The conditions are as described in the figure. Further, the horizontal axis of this figure is the film thickness in the geometric sense of the entire gate insulating film. In this simulation, the total oxide equivalent film thickness of the gate insulating film is kept constant, and the thickness of each film in the stack is changed. Therefore, the geometrically meaning film thickness of the gate insulating film varies. Value. As shown in this figure, when the gate insulating film has a geometric thickness of less than about 4 nm, the dielectric constant of the gate insulating film closer to the substrate is increased by increasing the dielectric constant of the gate sidewall insulating film. In the device whose dielectric constant is lower than the dielectric constant of the gate insulating film far from the gate, the current driving force is increased, and when the gate insulating film is thinner than 3 nm to 3.5 nm, the gate sidewall insulating film It can be seen that by increasing the dielectric constant, the current driving force increases regardless of the dielectric constant of each layer constituting the laminated gate insulating film. Therefore, it can be seen that increasing the dielectric constant of the gate sidewall insulating film is effective in improving the current driving capability. The reason for this is the refraction of electric lines of force at the interface of materials with different dielectric constants, as described below. FIG. 3 schematically shows the state of lines of electric force in the very vicinity of the interface of substances having different dielectric constants. As is well known in electrostatics, normal lines (indicated by arrows in the figure) and normal lines (indicated by solid lines) at the interface of materials with different dielectric constants (in the figure) The ratio of the tangent of the angle between the tangent of the electric force line and the angle of the interface normal at that point is the ratio of the dielectric constant of both substances. Will be equal. Therefore, it can be seen that the electric lines of force are close to the interface perpendicular to the low dielectric constant of both materials, and parallel to the interface of the high dielectric constant, and intersect the interface. This is the essence.

  First, consider the case where the dielectric constant of the film farther from the substrate in the stacked gate insulating film is lower than the dielectric constant of the film closer to the substrate. An enlarged view of the vicinity of the source region is schematically shown in FIG. Electric field lines at the interface between the upper and lower gate insulating films (denoted as interface A in the figure) and the interface between the gate insulating film and the gate sidewall insulating film far from the substrate (denoted as interface B in the figure) Depending on the refraction, the lines of electric force emitted from the gate electrode gather near the boundary between the source region and the channel region. This means that the capacitive coupling formed between the region and the gate electrode is strengthened, that is, the controllability of the gate electrode with respect to the potential of the channel region near the source is enhanced. As a result, the resistance decreases as the thickness of the Schottky barrier formed between the source region and the channel region decreases, and as a result, the current driving capability increases. Here, assuming that the dielectric constant of the gate insulating film closer to the substrate and the dielectric constant of the gate sidewall insulating film are substantially equal, the refraction of the electric field lines at their interface (denoted as interface C in the figure) is This is not the essence though I drew it as if it were not. Even if refraction occurs at the interface because the dielectric constants of the two are different, the same effect can be obtained.

  Next, consider the case where the dielectric constant of the film closer to the substrate in the stacked gate insulating film is lower than the dielectric constant of the film far from the substrate. An enlarged view of the vicinity of the source region is schematically shown in FIG. Electric field lines at the interface between the upper and lower gate insulating films (denoted as interface A in the figure) and the interface between the gate insulating film and the gate sidewall insulating film closer to the substrate (denoted as interface B in the figure) Depending on the refraction, the lines of electric force emitted from the gate electrode gather near the boundary between the source region and the channel region. This means that the capacitive coupling formed between the region and the gate electrode is strengthened, that is, the controllability of the gate electrode with respect to the potential of the channel region near the source is enhanced. As a result, the resistance decreases as the thickness of the Schottky barrier formed between the source region and the channel region decreases, and as a result, the current driving capability increases. Here, assuming that the dielectric constant of the gate insulating film far from the substrate and the dielectric constant of the gate sidewall insulating film are substantially equal, the refraction of the electric field lines at their interface (denoted as interface C in the figure) is This is not the essence though I drew it as if it were not. Even if refraction occurs at the interface because the dielectric constants of the two are different, the same effect can be obtained.

  In these two cases, if the dielectric constant of the gate sidewall insulating film is set higher than the dielectric constant of any of the films constituting the laminated gate insulating film, the interface indicated as interface C in FIGS. However, the electric lines of force are refracted downward when entering the gate side wall insulating film, and the refraction at the interface indicated as interface B becomes significant. Will be collected more effectively. Therefore, it is preferable to set the dielectric constant of the gate sidewall insulating film to be higher than the dielectric constant of any film constituting the laminated gate insulating film.

  Referring to FIG. 2, as the gate insulating film has a larger geometric thickness, the current is smaller when the gate sidewall insulating film has a higher dielectric constant. The reason for this is as follows. In the simulation whose result is shown in FIG. 2, since the total equivalent oxide thickness of the gate insulating film is constant, the geometrical thickness of the gate insulating film is large. This means that the thickness of the lower dielectric constant film is extremely thin. In FIG. 4 to FIG. 5, the two layers of the laminated gate insulating film are drawn to substantially the same thickness, but when one of the two is extremely thin, as long as attention is paid to the shape of the lines of electric force, The thin film is the same as it does not exist. That is, the gate insulating film is the same as that of a single-layer gate insulating film made only of a film having a higher dielectric constant. In this case, the effect of collecting the electric lines of force described above in the vicinity of the source region and the channel region due to refraction becomes extremely weak. On the other hand, when the dielectric constant of the gate sidewall insulating film is increased, capacitive coupling formed between the source region and the channel region in the vicinity thereof by the lines of electric force penetrating the gate sidewall insulating film (schematically shown in FIG. 6). Show) is strengthened. This means that the potential of the channel region in the vicinity of the source region is brought close to the potential of the source region as well as the problem of increasing the dielectric constant of the gate insulating film described above. The Schottky barrier formed between the channel region and the channel region is made thick, and as a result, the current driving force is reduced. As a result of this and the effect of reducing the lines of electric force described above, the dielectric constant of the gate sidewall insulating film is increased when the gate insulating film is thick in the geometrical sense. As a result, the current driving force decreases. In this way, when the lower dielectric constant of the laminated gate insulating film is extremely thin, the current driving force is reduced by increasing the dielectric constant of the gate sidewall insulating film, but in other cases It is preferable to increase the dielectric constant of the gate sidewall insulating film because it leads to an improvement in current driving capability.

  In addition, as shown in FIG. 2, when a high dielectric material is used for the gate sidewall insulating film, the dielectric constant of the film closer to the substrate in the laminated gate insulating film is lower than the dielectric constant of the film far from the substrate. It can be seen that the current is larger in the case than in the reverse case. The reason for this is as follows. When the dielectric constant of the film closer to the substrate in the laminated gate insulating film is lower than the dielectric constant of the film far from the substrate (the electric lines of force in the vicinity of the source region are schematically shown in FIG. 5) Compared with the case where the dielectric constant is reversed (the electric lines of force in the vicinity of the source region are schematically shown in FIG. 4), the shape of the electric lines of force emerging from the lower surface of the gate electrode slightly away from the gate end. Is different. In particular, when looking at the electric lines of force in the upper film in the laminated gate insulating film, the dielectric constant of the film closer to the substrate in the laminated gate insulating film is accompanied by the refraction of the electric lines of force described above. When the dielectric constant is lower than the dielectric constant of the film far from the substrate (FIG. 5), it can be seen that the electric field lines in a wider range converge than when the dielectric constant is reversed (FIG. 4). Therefore, when the dielectric constant of the film closer to the substrate in the laminated gate insulating film is lower than the dielectric constant of the film far from the substrate (FIG. 5), the dielectric constant is reversed. As shown in FIG. 4, many electric lines of force gather in the channel region near the source region. Accordingly, the Schottky barrier formed between the source region and the channel region becomes thin, and as a result, the current driving capability is improved. As described above, regardless of the presence or absence of the gate sidewall insulating film and the dielectric constant, the laminated gate insulating film preferably has a higher dielectric constant for the film farther from the substrate than the dielectric constant for the film closer to the substrate.

Note that the boundary between the source / drain region and the channel region is at the edge of the gate insulating film in order for the electric force lines to be collected on the channel region near the source end according to the discussion of the refraction of the electric force lines described above. It is important to be located further away from the center of the channel. That is, it is preferable that a part of the gate sidewall insulating film exists on a region between the source region and the drain region. In addition, the refraction of the electric lines of force at the interface between the gate insulating film and the gate sidewall insulating film (interface B between FIGS. 4 and 5) is also essential to the convergence of the electric lines of force to the channel region near the source. Therefore, as schematically shown in FIG. 7, the gate insulating film is contained under the gate electrode, and the gate side wall insulating film is in contact with the side surface of the gate insulating film as schematically shown in FIG. As shown in the structure, the gate insulating film is also present under the gate sidewall insulating film, and the gate sidewall insulating film is more preferably in contact with the upper surface of the gate insulating film. However, even if the gate insulating film is also present under the gate sidewall insulating film as schematically shown in FIG. 8, if the gate insulating film is laminated, the entire structure is made of a high dielectric material. Since the gate insulating film thickness having a geometrical meaning can be reduced as compared with the case of using a material, leakage of electric lines of force from the side surface of the gate insulating film is suppressed, leading to improvement in current driving force. Also in this case, considering the suppression of the capacitive coupling formed between the source region and the channel region due to the electric field lines penetrating the gate insulating film, the dielectric of the film farthest from the substrate in the stacked gate insulating film The rate is preferably higher than the dielectric constant of the film closer to the substrate. In addition, when the gate insulating film is also present under the gate sidewall insulating film in this way, the effect of collecting the electric lines of force described above in the channel region near the source end is weakened. It is not preferable that an offset exists between the drain region and the gate electrode, and it is preferable that an overlap exists between the two.

  As described above, in the Schottky field effect transistor of the present invention, the gate insulating film is formed by stacking a film made of a material having a high dielectric constant and a film made of a material having a low dielectric constant. Compared to the case where the gate insulating film is a single layer of a high dielectric material, the gate insulating film has a smaller geometric thickness and suppresses the leakage of electric lines of force from the side surface of the gate insulating film. By setting the dielectric constant of the insulating film closer to the substrate to a low value, the capacitive coupling formed between the source region and the channel region can be suppressed, and a gate sidewall insulating film having a high dielectric constant can be provided. Thus, by collecting the lines of electric force emitted from the gate electrode on the channel region in the vicinity of the source region by refraction of the electric field lines, and improving the controllability of the gate electrode with respect to the potential of the region, the source region and the channel region are Formed between Reduce the thinned by resistance hotkey barrier, high current driving capability is achieved as a result. Therefore, a high-performance fine element capable of high-speed operation is provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following embodiment, A various change can be used.

(Embodiment 1)
FIG. 9 is a cross-sectional view of the field effect transistor of the present invention. In this embodiment, an N-channel field effect transistor is taken as an example. If the conductivity type of the impurity is reversed, the same applies to the case of a P-channel field effect transistor, and a method such as injecting impurities only into a specific region in the substrate using a method such as photo-etching is used. In the case of a complementary field effect transistor, the same effect can be obtained.

This field effect transistor is a Schottky field effect transistor, and is characterized in that the gate insulating film 9 is a laminate of a film 7 made of silicon oxide and a film 8 made of a high dielectric material such as a metal oxide. . Here, an HfO ₂ (hafnium dioxide) film is used as the film 8 made of a high dielectric material such as a metal oxide. However, an oxide of different valence of Hf (hafnium) or Zr (zirconium), Ti (titanium) , Sc (scandium), Y (yttrium), Ta (tantalum), Al (aluminum), La (lanthanum), Ce (cerium), Pr (praseodymium), or oxides of other metals such as lanthanoid series elements Or other silicate materials containing various elements including these elements, or other high dielectric films such as insulating films containing nitrogen in them, or other insulating films such as laminates thereof. Also good. When nitrogen is present in the insulating film, it is preferable that only a specific element is crystallized and precipitated. In addition, the presence of nitrogen in the insulating film is preferable because it has another advantage of suppressing the diffusion of impurities into the substrate when a semiconductor containing impurities is used as the gate electrode.

  In this way, compared to the case where the gate insulating film is entirely formed of conventional silicon oxide, the gate insulating film can be formed to have a thicker geometric thickness under the same equivalent oxide thickness. In order to be possible, the current flowing through the gate insulating film is suppressed. Further, in this way, the gate insulating film has a geometrical meaning of the gate insulating film under the same equivalent oxide film thickness as compared with the case where the gate insulating film is entirely formed of a high dielectric material such as a metal oxide. Since it is possible to reduce the thickness, it is possible to prevent the electric lines of force from the gate electrode from leaking out of the side surface of the gate insulating film and reducing the controllability of the gate electrode with respect to the channel region potential. The In this case, the gate insulating film in the vicinity of the substrate is made of a material having a low dielectric constant, so that the capacitive coupling formed between the source region and the channel region in the vicinity thereof is weakened. Thus, the thick Schottky barrier formed between the source region and the channel region is suppressed, and as a result, the resistance is reduced and a high current driving force is realized.

  In the field effect transistor, an element isolation region 2 is formed on a semiconductor substrate 1 by, for example, a trench element isolation method. An N channel region 3 is formed in the semiconductor substrate 1 by, for example, B ion implantation. A laminated gate insulating film 9 is formed on the N channel region 3 by, for example, a silicon oxide film 7 and a hafnium dioxide film 8, for example. On the laminated gate insulating film 9, for example, a polycrystalline film having a thickness of 100 nm, for example. Silicon is deposited to form the gate electrode 5. Further, the source / drain regions 6 are formed so as to sandwich the gate electrode 5 by forming a silicide layer, for example. In this figure, interlayer insulating films, wirings, etc. are omitted.

  Next, a method for manufacturing this field effect transistor will be described below.

First, as shown in FIG. 10, an element isolation region 2 is formed in a semiconductor substrate 1 by, for example, a trench element isolation method. Subsequently, for example, B ions are implanted into the P well formation region at 100 keV and 2.0 × 10 ¹² cm ⁻² , and then a thermal process is performed at 1050 ° C. for 30 seconds, for example. Subsequently, in order to obtain a desired threshold voltage in the P well region, for example, B ions are implanted at 30 keV and 1.0 × 10 ¹² cm ⁻² to adjust the concentration of the N channel 3 surface.

  Next, as shown in FIG. 11, for example, the silicon oxide film 10 having a thickness of 1 nm, for example, is formed by exposing the semiconductor substrate 1 to an oxidizing atmosphere in a temperature-raised state.

Next, as shown in FIG. 12, for example, by using a method such as a CVD method (chemical vapor deposition method), an HfO ₂ (hafnium dioxide) film 11 having a thickness of, for example, 5 nm is formed on the silicon oxide film 10. Form.

Next, as shown in FIG. 13, a polycrystalline silicon film containing, for example, P (phosphorus) having a thickness of, for example, 100 nm is deposited on the HfO ₂ film 11 by, for example, CVD, for example, RIE (reactive ion etching). The gate electrode 5 is formed by processing the polycrystalline silicon film by performing anisotropic etching such as (method). Subsequently, the laminated gate insulating film 9 is formed by processing the HfO ₂ film 11 and the silicon oxide film 10 by performing anisotropic etching such as RIE.

  Next, for example, Er (erbium) is deposited on the entire surface of the semiconductor substrate 1 by a method such as sputtering, and a source / drain region 6 made of erbium silicide is formed on the surface of the semiconductor substrate 1 by applying a thermal process. To do. Subsequently, unreacted erbium is removed by a method such as immersing the semiconductor substrate 1 in a chemical solution. Thereafter, the field effect transistor of the present invention shown in FIG. 9 is formed through an interlayer insulating film forming process, a wiring process, and the like as in the prior art.

  In the present embodiment, an N-type field effect transistor is shown as an example. However, if the conductivity type of the impurity is reversed, a P-type field effect transistor can be used, and a method such as a photo-etching method can be used. The same applies to complementary field effect transistors if impurities are introduced only into specific regions within the substrate. Further, it can be used for a semiconductor device including them as a part.

  In addition to field effect transistors, other active elements such as bipolar transistors and single electron transistors, passive elements such as resistors, diodes, inductors and capacitors, or elements using, for example, ferroelectrics, magnetic elements, etc. It can also be used when a field effect transistor is formed as part of a semiconductor device including an element using a body. The same is true when field effect transistors are formed as part of OEIC (Optoelectric Integrated Circuit) or MEMS (Micro Electro Mechanical System). Further, it can be used in the same manner for a FIN type element, a pi gate element, a trigate element, a gate all-around element, a columnar structure element, and the like, and the same effect can be obtained.

  In this embodiment, a so-called bulk element formed on a normal semiconductor substrate has been described as an example. However, an SOI type element, a double gate SOI type element having gate electrodes on both sides of a channel region, etc. Are used in the same manner, and the same effect can be obtained.

  In this embodiment, P is used as an impurity for forming an N-type semiconductor layer, and B is used as an impurity for forming a P-type semiconductor layer. However, an N-type or P-type semiconductor layer is formed. Other group V or group III impurities may be used as impurities for this purpose. The introduction of impurities may be performed in the form of a compound containing them.

  In this embodiment, the introduction of impurities into the channel region is performed using ion implantation. However, for example, a method other than ion implantation such as solid phase diffusion or vapor phase diffusion may be used. Alternatively, a method of depositing or growing a semiconductor containing impurities may be used. Further, although a method of depositing a semiconductor containing an impurity is used for the gate electrode, the introduction of the impurity may be performed using a method such as ion implantation, solid phase diffusion, or vapor phase diffusion. If a semiconductor containing impurities is deposited, it is possible to introduce impurities at a high concentration, and as a result, there is an advantage that resistance is reduced. If the ion implantation method is used, there is an advantage that the process is simplified when a complementary element having an N-type element and a P-type element is formed.

  In this embodiment, Er is used to form the silicide layer for forming the source / drain regions, but other metals may be used. However, the Fermi level of the source / drain region of the N-type field effect transistor is preferably a value close to the lower end of the conduction band of the semiconductor used for the substrate. In view of this point of view, it is preferable to use Er when using a silicon substrate. preferable. In addition, the Fermi level of the source / drain region of the P-type field effect transistor is preferably close to the upper end of the valence band of the semiconductor used for the substrate, and in view of this point of view, when using a silicon substrate, Pt (platinum) Is preferably used. However, in the case of forming complementary elements including both N-type and P-type elements, the material whose Fermi level is in the vicinity of the forbidden band center of the semiconductor used for the substrate is both N-type and P-type. When used, there is an advantage that the process is simplified. In view of this point of view, Ni (nickel) or Co (cobalt) is preferable when a complementary element using silicon is formed on the substrate. The source / drain regions may be formed using metal instead of silicide. In that case, there is an advantage that the resistance of the source / drain region is further reduced. However, if the source / drain regions are formed of silicide as shown in this embodiment, the source / drain regions can be formed in a self-aligned manner with respect to the gate electrode or the element isolation region, thereby simplifying the process. There is an advantage to say.

  In this embodiment, the introduction of impurities into the source / drain formation regions is not mentioned, but impurities may be introduced into the source / drain formation regions. In particular, introducing a high concentration of an impurity having a conductivity type opposite to that of the channel region into the source / drain formation region reduces the Schottky barrier formed between the source / drain region and the channel region. Therefore, it is preferable because the resistance is lowered.

  In this embodiment, the source / drain regions are formed after the processing of the gate electrode or the gate insulating film. However, the order is not essential, and the order may be reversed. However, when the source / drain region is formed of a silicide layer as in this embodiment, the source / drain region is formed after the gate electrode or gate insulating film is processed. Since it can be formed in a self-aligned manner with respect to the isolation region, there is an advantage that the process is simplified.

  In addition, the impurity concentration of the channel region in forming the SOI element may be set to be a fully depleted element or a partially depleted element. Setting the device to be a fully depleted device reduces the impurity concentration in the channel region, which improves the mobility and further improves the current drive capability, and suppresses the parasitic bipolar effect. This is also preferable because the advantages of

  In this embodiment, polycrystalline silicon is used for the gate electrode, but a semiconductor such as single crystal silicon or amorphous silicon, a refractory metal or a metal not necessarily having a high melting point, a compound containing a metal, or the like, or You may form by lamination | stacking etc. of those. When the gate electrode is formed of a metal or a compound containing a metal, gate resistance is suppressed, so that high-speed operation of the device can be obtained, which is preferable. In addition, when the gate is formed of a metal, the oxidation reaction does not proceed easily, so that there is an advantage that the controllability of the interface between the gate insulating film and the gate electrode is good. Further, when a semiconductor such as polycrystalline silicon is used for at least a part of the gate electrode, there is another advantage that the control of the threshold voltage of the element is facilitated because the work function can be easily controlled.

  In this embodiment, the upper portion of the gate electrode has a structure in which the electrode is exposed, but an insulator such as silicon oxide, silicon nitride, or silicon oxynitride may be provided on the upper portion. Especially when it is necessary to protect the gate electrode during the manufacturing process, such as when the gate electrode is formed of a material containing metal, silicon oxide, silicon nitride, silicon oxynitride, etc. It is important to provide protective materials.

  In this embodiment, the gate electrode is formed by a method in which anisotropic etching is performed after the gate electrode material is deposited. However, the gate electrode is formed by using a method such as embedding such as a damascene process. An electrode may be formed. In the case where the source / drain regions are formed prior to the formation of the gate electrode, it is preferable to use a damascene process because the source / drain regions and the gate electrode are formed in a self-aligned manner.

  In this embodiment, the length of the gate electrode measured in the main direction of the current flowing through the element is the same for both the upper and lower portions of the gate electrode, but this is not essential. For example, the length of the upper portion of the gate electrode measured in the upper part of the gate electrode may be longer than the length measured in the lower portion of the letter “T”. In this case, there is another advantage that the gate resistance can be reduced.

In this embodiment, the upper surface of the gate electrode is a plane parallel to the substrate surface. However, this is not inevitable, and the upper surface of the gate electrode is inclined with respect to the substrate surface, or the upper surface is a curved surface. The same effect can be obtained even if the upper surface has corners.
In the present embodiment, the film closer to the substrate in the laminated gate insulating film is made of silicon oxide. However, this is not inevitable, and silicon nitride, silicon oxynitride, or the like may be used. However, when this film is formed of silicon oxide, the mobility of carriers is improved, so that there is an advantage that the current driving capability is further improved. In addition, since it is desirable that there are few charges, levels, and the like existing in the insulating film and at the interface with the semiconductor substrate, in view of this, it is preferable to use silicon oxide for the film in contact with the semiconductor substrate. On the other hand, from the viewpoint of preventing impurities in the gate electrode from diffusing into the channel region when a semiconductor containing impurities is used for the gate electrode, diffusion of impurities is suppressed by the presence of nitrogen. Since it is known, it is preferable to use silicon nitride or silicon oxynitride. Further, these films can be formed by, for example, exposing to a heated oxygen gas or using a method such as deposition, or may be exposed to an excited oxygen gas without necessarily raising the temperature. It is preferable to form it by a method in which it is exposed to an excited oxygen gas that is not accompanied by an increase in temperature, because the impurity in the channel region is suppressed from changing its concentration distribution due to diffusion. Further, in the case of using silicon oxynitride, nitrogen may be introduced into the insulating film by first forming a silicon oxide film and then exposing it to a gas containing nitrogen in a heated state or excited state. In this case, it is preferable to form it by a method of exposing to an excited nitrogen gas that is not accompanied by an increase in temperature, because impurities in the channel region can be prevented from changing the concentration distribution due to diffusion.

  Further, the method for forming the insulating film is not limited to the CVD method, and other methods such as a vapor deposition method, a sputtering method, and an epitaxial growth method may be used. When an oxide of a certain material is used as the insulating film, a method of first forming a film of the material and oxidizing it may be used. In the method of the present invention, the gate insulating film is formed by stacking a material having a high dielectric constant and a material having a low dielectric constant, so that the geometry of the gate insulating film is made as compared with the case where the gate insulating film is formed only from a material having a high dielectric constant. By reducing the thickness of the film, the electric lines of force from the gate are prevented from leaking out from the side surface of the gate insulating film. Therefore, the effect of the film having a high dielectric constant is particularly remarkable when a material such as a metal oxide having a sufficiently high dielectric constant is used as compared with silicon oxide used for the gate insulating film of the conventional device.

  In this embodiment, the dielectric constant of the film far from the semiconductor substrate in the stacked gate insulating film is higher than the dielectric constant of the film closer to the semiconductor substrate, but this magnitude relationship may be reversed. However, in view of the point of weakening the capacitive coupling formed between the source region and the channel region due to the lines of electric force penetrating the gate insulating film, the dielectric of the film farther from the semiconductor substrate as in this embodiment is used. A higher rate is preferred.

  In this embodiment, the gate insulating film is a two-layered stack, but may be formed to be a stack of three or more layers.

  Further, the thickness of the insulating film or the like forming the gate insulating film is not limited to the value of this embodiment. Further, although the gate insulating film has a uniform thickness, this is not essential.

  In this embodiment, the element isolation is performed using the trench element isolation method. However, the element isolation may be performed using another method such as a local oxidation method or a mesa element isolation method.

  In this embodiment, post-oxidation after the formation of the gate electrode is not mentioned, but a post-oxidation step may be performed if possible in view of materials such as the gate electrode and the gate insulating film. Further, the process is not necessarily limited to post-oxidation, and a process of rounding the corner of the lower end of the gate electrode may be performed by a method such as chemical treatment or exposure to a reactive gas. If these steps are possible, it is preferable because the electric field at the lower corner of the gate electrode is relaxed.

  In the present embodiment, the interlayer insulating film is not mentioned, but a substance other than silicon oxide such as a low dielectric constant material may be used for the interlayer insulating film. If the dielectric constant of the interlayer insulating film is lowered, the parasitic capacitance of the element is reduced, so that there is an advantage that high-speed operation of the element can be obtained.

Although no mention is made of contact holes, self-aligned contacts can be formed. The use of the self-aligned contact is preferable because the area of the element can be reduced, and the degree of integration can be improved.

  In the present embodiment, the formation of a metal layer for wiring is not mentioned, but a metal such as Cu (copper) can be used. In particular, Cu is preferable because of its low efficiency.

  In this embodiment or modification, the structure of only a single transistor is shown. However, the embodiment shown here is not limited to the case of a single transistor, and the same effect can be obtained. Of course, you can get it.

(Embodiment 2)
Next, another embodiment of the semiconductor device of the present invention will be described.

  The semiconductor device of this embodiment is shown in FIG. This field effect transistor is a Schottky field effect transistor, in which a gate insulating film 9 is a laminate of a film 7 made of silicon oxide and a film 8 made of a high dielectric constant material such as a metal oxide. It is characterized by having a gate sidewall insulating film 12 made of a high dielectric constant material. This has the advantage that so-called bridging in which the source / drain regions and the gate electrode are short-circuited during the silicidation reaction for forming the source / drain regions is prevented. In addition, as described above, the electric field lines emitted from the gate electrode due to the refraction of the electric field lines are collected in the channel region near the source region, and the controllability of the gate electrode with respect to the potential of the region is improved. Therefore, there is an advantage that a Schottky barrier formed between the source region and the channel region is thinned to reduce the resistance, and as a result, a high current driving force can be obtained.

  In the field effect transistor, an element isolation region 2 is formed on a semiconductor substrate 1 by, for example, a trench element isolation method. An N channel region 3 is formed in the semiconductor substrate 1 by, for example, B ion implantation. A stacked gate insulating film 9 is formed on the N channel region 3 by, for example, a silicon oxide film 7 and, for example, a hafnium dioxide film 8, and the laminated gate insulating film 9 has a thickness of, for example, 100 nm. A gate electrode 5 is formed by depositing a refractory metal such as (tungsten). Further, a gate sidewall insulating film 12 of, for example, hafnium dioxide is formed so as to sandwich the gate electrode 5, and a source / drain region 6 is formed by forming a silicide layer so as to sandwich the gate sidewall insulating film 12. In this figure, interlayer insulating films, wirings, etc. are omitted.

  Next, a method for manufacturing this field effect transistor will be described below.

For example, a W (tungsten) film 14 having a thickness of, for example, 100 nm is deposited on the HfO ₂ film 11 by, eg, CVD, as shown in FIG. For example, a silicon nitride film 13 having a thickness of 10 nm, for example, is deposited on the W film 14 by a method such as CVD.

Next, as shown in FIG. 16, the silicon nitride film 13 and the W film 14 are processed to form the gate electrode 5 by performing anisotropic etching such as RIE. Subsequently, the laminated gate insulating film 9 is formed by processing the HfO ₂ film 11 and the silicon oxide film 10 by performing anisotropic etching such as RIE.

Next, as shown in FIG. 17, for example, an HfO ₂ film having a thickness of 10 nm, for example, is deposited by a method such as CVD. Then, the gate sidewall insulating film 12 is formed by processing the HfO ₂ film by performing anisotropic etching such as RIE.

  Next, for example, Er is deposited on the entire surface of the semiconductor substrate 1 by a method such as sputtering, and a source / drain region 6 made of erbium silicide is formed on the surface of the semiconductor substrate 1 by applying a thermal process. Subsequently, unreacted erbium is removed by a method such as immersing the semiconductor substrate 1 in a chemical solution. Thereafter, the field effect transistor of the present invention shown in FIG. 14 is formed through an interlayer insulating film forming process, a wiring process, and the like as in the prior art.

  In the present embodiment, the gate sidewall insulating film is formed using the same material as that of the film having the higher dielectric constant of the laminated gate insulating film, but this is not essential and is a different material. May be used. However, in view of the above discussion of the refraction of the lines of electric force, the dielectric constant of the material forming the side wall is the dielectric constant between the film closest to the substrate and the film closest to the substrate that forms the stacked gate insulating film. The dielectric constant needs to be equal to or higher than the dielectric constant of the material having the lower rate, and as described above, it is preferably higher than the dielectric constant of any of these two layers. Further, specific values such as the thickness of the gate sidewall insulating film are not limited to the values in the present embodiment.

  In the present embodiment, the dielectric constant of the film farther from the semiconductor substrate in the stacked gate insulating film is higher than the dielectric constant of the film closer to the semiconductor substrate, but this magnitude relationship may be reversed. Good. However, as described above, in view of the fact that the lines of electric force emitted from the gate electrode are effectively collected in the channel region in the vicinity of the source region due to the refraction of the lines of electric force, the semiconductor as in this embodiment It is preferable that the dielectric constant of the film farther from the substrate is higher.

  In this embodiment, silicon nitride is used as an insulating film formed on the gate electrode in order to protect the gate electrode during the silicide process for forming the source / drain regions. However, this material is limited to silicon nitride. Instead, other materials may be used. However, it is preferable to remove the natural silicon oxide film formed on the surface by subjecting the substrate to a treatment such as dilute hydrofluoric acid treatment before the silicide process. In view of this, it is preferable to use a material such as silicon nitride having a low reactivity with hydrofluoric acid for the film formed on the gate electrode.

  In the present embodiment, various modifications as described in the first embodiment are possible, and similar effects can be obtained.

(Embodiment 3)
Next, still another embodiment of the semiconductor device of the present invention will be described.

  The semiconductor device of this embodiment is shown in FIG. This field effect transistor is a Schottky field effect transistor, in which a gate insulating film 9 is a laminate of a film 7 made of silicon oxide and a film 8 made of a high dielectric constant material such as a metal oxide. It is characterized in that it has a gate sidewall insulating film 12 made of a high dielectric constant material and a gap 15 at the gate end portion of the film 7 made of silicon oxide in the laminated gate insulating film. This has the advantage that so-called bridging in which the source / drain regions and the gate electrode are short-circuited during the silicidation reaction for forming the source / drain regions is prevented. Further, as described above, when the electric force lines coming out from the gate electrode are collected in the channel region near the source region due to the refraction of the electric force lines, the voids are collected more effectively because the dielectric constant is extremely low. Further, the controllability of the gate electrode with respect to the potential of the region is further improved. For this reason, the Schottky barrier formed between the source region and the channel region is further thinned to further reduce the resistance, and as a result, the resistance is further increased. There is an advantage that current driving force can be obtained. In this figure, interlayer insulating films, wirings, etc. are omitted.

  Next, a method for manufacturing this field effect transistor will be described below.

  Subsequent to the step shown in FIG. 16 of the second embodiment, as shown in FIG. 19, the silicon oxide film 10 is removed only in the vicinity of the gate end by a method such as immersion in a chemical solution.

  The subsequent steps are the same as those shown in FIG.

  In the present embodiment, the dielectric constant of the film farther from the semiconductor substrate in the stacked gate insulating film is higher than the dielectric constant of the film closer to the semiconductor substrate, but this magnitude relationship may be reversed. In that case, as shown in FIG. 20, a gap 15 is formed in the vicinity of the gate end of the film far from the semiconductor substrate in the laminated gate insulating film. In any case, if a gap is provided in the vicinity of the gate end of the film having the lower dielectric constant among the film closest to the semiconductor substrate in the stacked gate insulating film and the film closest to the next, as described above, In addition, when the electric field lines coming out of the gate electrode are collected in the channel region near the source region due to the refraction of the electric field lines, the voids are collected more effectively because the dielectric constant is extremely low, and the potential relative to the potential of the region is reduced. The controllability of the gate electrode is further improved. For this reason, the Schottky barrier formed between the source region and the channel region is further thinned to further reduce the resistance. As a result, a higher current driving force can be obtained. There is an advantage to say.

  Also in this embodiment, various modifications as described in the above embodiment are possible, and the same effect can be obtained.

(Embodiment 4)
Next, still another embodiment of the semiconductor device of the present invention will be described.

  The semiconductor device of this embodiment is shown in FIG. This field effect transistor is a Schottky field effect transistor, in which a gate insulating film 9 is a laminate of a film 7 made of silicon oxide and a film 8 made of a high dielectric constant material such as a metal oxide. The gate sidewall insulating film 12 made of a high dielectric constant material is included, and the film 7 made of silicon oxide in the laminated gate insulating film extends to the bottom of the gate sidewall insulating film 12. This has the advantage that so-called bridging in which the source / drain regions and the gate electrode are short-circuited during the silicidation reaction for forming the source / drain regions is prevented. In addition, since the capacitive coupling formed between the source region and the channel region is weakened by the electric lines of force penetrating the gate sidewall insulating film, the Schottky barrier formed between the source region and the channel region is thin. Thus, there is an advantage that the resistance is reduced, and as a result, a high current driving force can be obtained. In this figure, interlayer insulating films, wirings, etc. are omitted.

  Next, a method for manufacturing this field effect transistor will be described below.

As shown in FIG. 22 following the step shown in FIG. 15 of the second embodiment, the silicon nitride film 13 and the W film 14 are processed by performing anisotropic etching such as RIE, for example, to process the gate electrode 5. Form. Subsequently, the HfO ₂ film 11 is processed by performing anisotropic etching such as RIE.

Next, as shown in FIG. 23, for example, an HfO ₂ film having a thickness of 10 nm, for example, is deposited by a method such as CVD. Then, the gate sidewall insulating film 12 is formed by processing the HfO ₂ film by performing anisotropic etching such as RIE.

  Next, as shown in FIG. 24, the silicon oxide film 10 is processed by performing anisotropic etching such as RIE, for example, to form a laminated gate insulating film 9.

  Next, for example, Er is deposited on the entire surface of the semiconductor substrate 1 by a method such as sputtering, and a source / drain region 6 made of erbium silicide is formed on the surface of the semiconductor substrate 1 by applying a thermal process. Subsequently, unreacted erbium is removed by a method such as immersing the semiconductor substrate 1 in a chemical solution. Thereafter, the field effect transistor of the present invention shown in FIG. 21 is formed through an interlayer insulating film forming process, a wiring process, and the like as in the prior art.

  Also in this embodiment, various modifications as described in the above embodiment are possible, and the same effect can be obtained.

Characteristics diagram for explaining a semiconductor device of the present invention Characteristics diagram for explaining a semiconductor device of the present invention Schematic diagram for explaining a semiconductor device of the present invention Schematic diagram for explaining a semiconductor device of the present invention Schematic diagram for explaining a semiconductor device of the present invention Schematic diagram for explaining a semiconductor device of the present invention Schematic diagram for explaining a semiconductor device of the present invention Schematic diagram for explaining a semiconductor device of the present invention Sectional drawing for demonstrating the structure of the field effect transistor concerning Embodiment 1 of this invention Sectional drawing for demonstrating the manufacturing process of the field effect transistor concerning Embodiment 1 of this invention. Sectional drawing for demonstrating the manufacturing process of the field effect transistor concerning Embodiment 1 of this invention. Sectional drawing for demonstrating the manufacturing process of the field effect transistor concerning Embodiment 1 of this invention. Sectional drawing for demonstrating the manufacturing process of the field effect transistor concerning Embodiment 1 of this invention. Sectional drawing for demonstrating the structure of the field effect transistor concerning Embodiment 2 of this invention Sectional drawing for demonstrating the manufacturing process of the field effect transistor concerning Embodiment 2 of this invention. Sectional drawing for demonstrating the manufacturing process of the field effect transistor concerning Embodiment 2 of this invention. Sectional drawing for demonstrating the manufacturing process of the field effect transistor concerning Embodiment 2 of this invention. Sectional drawing for demonstrating the semiconductor device concerning Embodiment 3 of this invention. Sectional drawing for demonstrating the manufacturing process of the field effect transistor concerning Embodiment 3 of this invention. Sectional drawing for demonstrating the modification of the semiconductor device concerning Embodiment 3 of this invention. Sectional drawing for demonstrating the structure of the field effect transistor concerning Embodiment 4 of this invention Sectional drawing for demonstrating the manufacturing process of the field effect transistor concerning Embodiment 4 of this invention. Sectional drawing for demonstrating the manufacturing process of the field effect transistor concerning Embodiment 4 of this invention. Sectional drawing for demonstrating the manufacturing process of the field effect transistor concerning Embodiment 4 of this invention. Cross-sectional view of a conventional field effect transistor Characteristics diagram for explaining the problems of conventional field effect transistors Characteristics diagram for explaining the problems of conventional field effect transistors

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Element isolation region 3 ... Channel region 4 ... Gate insulating film 5 which consists of metal oxides ... Gate electrode 6 ... Source / drain region 7 ... Silicon oxide film 8 ... Metal oxide film 9 ... Laminated gate insulating film DESCRIPTION OF SYMBOLS 10 ... Silicon oxide film 11 ... Hafnium dioxide film 12 ... Gate side wall insulating film 13 ... Silicon nitride film 14 ... Tungsten film 15 ... Air gap

Claims (7)

  A semiconductor substrate having a semiconductor layer, a first insulating film formed on the semiconductor layer, and a second insulating film formed on the first insulating film and having a dielectric constant different from that of the first insulating film A film, a gate electrode formed on the second insulating film, and a source region and a drain region made of metal or metal silicide formed on a surface portion of the semiconductor substrate so as to sandwich the gate electrode. A semiconductor device characterized by including.   The semiconductor device according to claim 1, wherein a dielectric constant of the second insulating film is higher than a dielectric constant of the first insulating film.   The gate sidewall insulating film having a dielectric constant equal to or higher than a lower one of a dielectric constant of the first insulating film and a dielectric constant of the second insulating film on the sidewall of the gate electrode. A semiconductor device according to 1.   The gate sidewall insulating film having a dielectric constant higher than both of the dielectric constant of the first insulating film and the dielectric constant of the second insulating film is provided on the sidewall of the gate electrode. A semiconductor device according to claim 1.   5. The semiconductor device according to claim 3, wherein the gate side wall is in contact with any side surface of the first insulating film and the second insulating film.   6. The semiconductor device according to claim 3, wherein at least a part of the gate sidewall insulating film exists on a region between the source region and the drain region. 7. The semiconductor device according to claim 1, wherein at least one of the first insulating film and the second insulating film contains a metal or oxygen.

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