JP2006278369A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for obtaining an optimum Vth for each transistor of the semiconductor device having a plurality of transistors for controlling the threshold voltage of the semiconductor device. <P>SOLUTION: After a mask 9 is formed at an nMOS formation region and a pMOS formation region, the mask 9 at the pMOS formation region is removed, and a prescribed amount of metal 11 is deposited at the nMOS formation region and the pMOS formation region, thus silicifying a gate electrode 3b at the pMOS formation region fully. In the same manner, a gate electrode 3a at the nMOS formation region is silicified fully by a prescribed amount of metal. The silicide composition of respective gate electrodes 3a, 3b can be controlled each according to the amount of metal to be deposited, thus obtaining an optimum threshold voltage for each transistor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a salicide structure.

  In recent semiconductor devices, a silicide structure has been widely used in order to keep the sheet resistance and contact resistance of the source / drain region in the transistor structure low with the increase in speed, miniaturization, and high integration. Yes.

  In general, the silicide layer is formed by depositing metal on the entire surface and then performing heat treatment, so that the metal is deposited on the source / drain region with a substantially uniform film thickness and is almost the same as the source / drain region. Formed in depth. In the source / drain region, the junction leakage often becomes a problem, but due to the difference in tolerance for junction leakage between the source side and the drain side in the transistor, the source side and the drain side have recently become different. A method of forming silicide layers having different depths has also been proposed (see Patent Document 1).

  In this proposal, a gate electrode is formed on a silicon substrate through a gate insulating film, an LDD region, a sidewall, a source region, and a drain region are formed, and then a metal such as tungsten (W) is first deposited on the entire surface. Next, a method is disclosed in which a silicidation reaction suppression layer is formed only on the drain region side with metal nitride or the like, and metal is deposited again on the entire surface and then annealed. By such a method, a silicide layer is formed on the surface of the gate electrode, and the metal deposited for the first time on the drain region side and the metal deposited for the first and second times on the source region side are each contributed to silicidation. Attempts have been made to form a shallow silicide layer on the drain region side and a deep silicide layer on the source region side.

In addition, polysilicon is often used as the material for the gate electrode, but recently, the gate electrode (FUSI gate) which is silicided not only to the surface but also to the inside (referred to as “full silicidation”) is used. Reports have also been made. When full silicidation is performed, there is a problem that the threshold voltage (V _th ) shifts. Such a V _th shift causes a composition of silicon and metal in the gate electrode (referred to as “silicide composition”). It has also been found that it can be suppressed by changing the value.
JP-A-9-153557

By the way, for example, when a plurality of transistors such as an n-type MOS transistor (referred to as “nMOS”) and a p-type MOS transistor (referred to as “pMOS”) are formed on a silicon substrate, it is very important to obtain a desired V _th for each transistor. Become important. However, when the conventional method of performing silicidation for each transistor at once is used, a substantially uniform silicide layer is formed on the gate electrode of each transistor, so that accurate V _th control is performed for each transistor. Difficult to do.

Conventionally, the control of V _th has been performed by optimizing the ion implantation conditions for each transistor. However, as the performance of semiconductor devices improves, it is difficult to control by such ion implantation.

The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor device manufacturing method for obtaining an optimum V _th for each transistor of a semiconductor device having a plurality of transistors.

  In the present invention, in order to solve the above problem, in a method of manufacturing a semiconductor device including a plurality of transistors, a step of forming a plurality of gate electrodes on a semiconductor substrate, and a gate electrode on one of the plurality of gate electrodes, And a step of depositing a predetermined amount of metal on each of the other gate electrodes for silicidation.

  According to such a method of manufacturing a semiconductor device, after forming a plurality of gate electrodes, a predetermined amount of metal is deposited on one gate electrode and the other gate electrode, and the gate electrode is formed using the metal. Silicidize. Thereby, the silicide composition of each gate electrode can be controlled.

In the present invention, when forming a semiconductor device including a plurality of transistors, a predetermined amount of metal is deposited on each of one gate electrode and another gate electrode, and each gate electrode is silicided using the metal. I tried to do it. This makes it possible to control the silicide composition of each gate electrode, thereby controlling the V _th of each transistor and obtaining the optimum V _th for each transistor. As a result, the performance of a semiconductor device including a plurality of transistors can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, taking as an example the formation of a semiconductor device having pMOS and nMOS.
First, the first embodiment will be described.

  1 to 8 are explanatory views of a method of forming a semiconductor device according to the first embodiment. FIG. 1 is a schematic cross-sectional view of an essential part of a gate electrode processing step according to the first embodiment. FIG. FIG. 3 is a schematic cross-sectional view of an essential part of a sidewall forming process of the first embodiment, FIG. 3 is a schematic cross-sectional view of an essential part of a selective epitaxial growth process of the first embodiment, and FIG. 4 is a mask forming process of the first embodiment. FIG. 5 is a schematic cross-sectional view of the main part of the resist patterning process of the first embodiment, FIG. 6 is a schematic cross-sectional view of the main part of the metal deposition process of the first embodiment, and FIG. FIG. 8 is a schematic cross-sectional view of an essential part of the silicidation process of the first embodiment. Hereinafter, a method for forming a semiconductor device according to the first embodiment will be described in order with reference to FIGS.

  In the method of forming a semiconductor device according to the first embodiment, first, as shown in FIG. 1, for example, a silicon substrate 1 is used, and a LOCOS (Local Oxidation of Silicon) method or STI (Shallow Trench Isolation) is applied to a predetermined region. An element isolation region (not shown) is formed using a method. Subsequently, the surface of the silicon substrate 1 is thermally oxidized, and a polysilicon and silicon nitride (SiN) film is formed thereon using a CVD (Chemical Vapor Deposition) method or the like. Then, the three layers of the silicon nitride film, the polysilicon, and the thermal oxide film are etched using the photolithography technique while leaving the gate electrodes of the nMOS and pMOS. As a result, the gate electrodes 3a made of polysilicon are formed on the silicon substrate 1 in the regions where the nMOS and pMOS are formed (referred to as “nMOS formation region” and “pMOS formation region”, respectively) via the gate insulating films 2a and 2b. 3b is formed, and a stacked structure in which silicon nitride hard masks 4a and 4b are formed thereon is obtained.

In addition to the thermal oxide film, a high-k insulating film or the like can be used for the gate insulating films 2a and 2b.
Next, one of the nMOS formation region and the pMOS formation region, for example, the pMOS formation region is covered with a resist or the like, and ion implantation is performed on the nMOS formation region under a predetermined condition using the stacked structure as a mask. Then, the other region, i.e., the nMOS formation region in this case is covered with a resist or the like, and ion implantation is performed on the pMOS formation region under a predetermined condition using the stacked structure as a mask. Thereafter, annealing is performed under predetermined conditions. Thereby, extension regions 5a and 5b are formed in the nMOS formation region and the pMOS formation region, respectively.

  When the extension regions 5a and 5b are formed, ion implantation and annealing may be performed after forming a thin sidewall (not shown) on the side wall of the laminated structure serving as an ion implantation mask. In addition to the extension regions 5a and 5b, a pocket region of a predetermined conductivity type adjacent to them may be formed.

  Thereafter, a silicon nitride film is formed on the entire surface by CVD or the like, and anisotropic etching is performed. As shown in FIG. 2, the gate insulating films 2a and 2b, the gate electrodes 3a and 3b, and the hard masks 4a and 4b are formed. Side walls 6a and 6b are formed on the side walls.

The sidewalls 6a and 6b may be formed using other insulating materials such as silicon oxide (SiO ₂ ). Also, for example, a thin silicon oxide film is first formed on the entire surface, and then a thick silicon nitride film is formed thereon. Thereafter, anisotropic etching is performed to form silicon oxide on the inside and silicon nitride on the outside. You may make it comprise the double-structured side wall provided.

  Next, as shown in FIG. 3, selective epitaxial layers 7 a and 7 b are formed in the nMOS formation region and the pMOS formation region by selectively performing epitaxial growth of silicon on the exposed surface of the silicon substrate 1. For example, after removing the hard masks 4a and 4b with phosphoric acid or the like, first, the pMOS formation region is covered with a resist or the like, and ion implantation is performed on the nMOS formation region with the gate electrode 3a and the sidewall 6a as a mask under predetermined conditions. Next, the nMOS formation region is covered with a resist or the like, and ion implantation is performed on the pMOS formation region using the gate electrode 3b and the side wall 6b as a mask, followed by annealing under the predetermined condition. Thus, source / drain regions 8a and 8b are formed in the nMOS formation region and the pMOS formation region, respectively.

  In the figure, the selective epitaxial layers 7a and 7b and the source / drain regions 8a and 8b are shown separately. However, ion implantation and annealing are also performed on the selective epitaxial layers 7a and 7b. The selective epitaxial layers 7a and 7b together with the source / drain regions 8a and 8b also function as the source / drain of the nMOS and pMOS.

  Further, the gate electrodes 3a and 3b are thin, and when the gate electrodes 3a and 3b are fully silicided by silicidation described later, the silicide layers formed in the source / drain regions 8a and 8b simultaneously break the pn junction. In the case where there is a very low possibility that the layer will be formed to such a depth, the selective epitaxial layers 7a and 7b may not be formed. In this case, the hard masks 4a and 4b may be removed after the sidewalls 6a and 6b are formed, and ion implantation and annealing may be performed to form the source / drain regions 8a and 8b.

  Next, as shown in FIG. 4, a silicon nitride film is formed on the entire surface by CVD or the like to form a mask 9, and patterning is performed to cover the nMOS formation region with a resist 10 as shown in FIG.

  Then, after removing the silicon nitride mask 9 exposed in the pMOS formation region using phosphoric acid or the like, the resist 10 in the nMOS formation region is removed, and as shown in FIG. 6, a metal 11 for silicidation is formed on the entire surface. accumulate. As the metal 11, for example, cobalt (Co), nickel (Ni), platinum (Pt), titanium (Ti), tungsten, molybdenum (Mo), or the like can be used.

  At this time, since the metal 11 is deposited on the mask 9 in the nMOS formation region, the metal 11 does not contact the gate electrode 3a and the selective epitaxial layer 7a. On the other hand, in the pMOS formation region, since the mask 9 is removed before the metal 11 is deposited, the metal 11 contacts the gate electrode 3b and the selective epitaxial layer 7b. Therefore, when annealing is performed under such conditions that the gate electrode 3b in the pMOS formation region can be fully silicided, the gate electrode 3b is fully silicided as shown in FIG. 7b and the underlying source / drain region 8b are silicided to form a silicide layer 12b. Unreacted metal 11 is removed using sulfuric acid or the like.

  After full silicidation of the pMOS formation region, processing similar to the processing shown in FIGS. 4 to 7 is performed on the nMOS formation region. That is, first, a mask is formed on the entire surface using silicon nitride. Then, resist patterning is performed to form a resist covering the pMOS formation region, and the mask exposed to the nMOS formation region is removed. Thereafter, the resist is peeled off, a predetermined metal is deposited on the entire surface, and annealing for full silicidation of the gate electrode 3a in the nMOS formation region is performed, so that the pMOS formation region is formed with a mask 13 as shown in FIG. In the covered state, the gate electrode 3a is fully silicided, and the selective epitaxial layer 7a and the source / drain region 8a are silicided to form a silicide layer 12a. Unreacted metal is removed using sulfuric acid or the like.

Thereafter, the semiconductor device may be completed by forming interlayer insulating films, contacts, wirings and the like according to a conventionally known method.
In this way, if the silicidation of the gate electrodes 3a and 3b in the nMOS formation region and the pMOS formation region is performed separately, the silicide composition of the gate electrodes 3a and 3b can be controlled independently. . In order to change the silicide composition, the pMOS formation region and the nMOS formation region are made different from the film thickness of the metal 11 deposited in the pMOS formation region shown in FIG. And the like, different metal types, different metal film thicknesses and types, and different annealing conditions can be used. By controlling the composition ratio of silicon and metal in the gate electrodes 3a and 3b when the gate electrodes 3a and 3b are fully silicided in this way, the V _th shift generated by the full silicidation is caused in each of the nMOS and the pMOS. It becomes possible to control about.

Here, FIG. 9 is a diagram showing the relationship between the metal content in the gate electrode and the flat band voltage. FIG. 9 shows the relationship between the nickel content and the flat band voltage (V _FB ) when nickel is used as the silicide metal as an example. In FIG. 9, the horizontal axis represents Ni content (%), and the vertical axis represents V _FB (V).

As shown in FIG. 9, on the basis of the case of NiSi, that is, the case where the ratio of Ni: Si is 1: 1, V _FB is changed in the p direction (valence band side) by changing the Ni content. Can be shifted up to about 0.41V and up to about 0.12V in the n direction (conduction band side). For example, with NiSi (Ni content 50%) as a reference, if the p direction is plus (+) and the n direction is minus (−), Ni ₂ Si (Ni content 67%) is about +0.1 V, Ni ₃ V _FB can be shifted by about +0.15 V for Si (Ni content 75%) and by about −0.1 V for NiSi ₂ (Ni content 33%).

V _FB and V _th are closely related, and the control of V _FB leads to the control of V _th . Therefore, according to the method for forming the semiconductor device of the first embodiment, the silicide composition of each of the gate electrodes 3a and 3b can be controlled by performing full silicidation of the nMOS formation region and the pMOS formation region separately. , _{Vth of} nMOS and pMOS can be optimally controlled. As a result, it is possible to realize a high-performance semiconductor device in which each of the nMOS and pMOS transistors has an optimum _Vth .

  In the first embodiment, full silicidation is performed in the order of the pMOS formation region and the nMOS formation region, but conversely, full silicidation may be performed in the order of the nMOS formation region and the pMOS formation region. I do not care.

Next, a second embodiment will be described.
10 to 13 are explanatory views of a method of forming a semiconductor device according to the second embodiment. FIG. 10 is a schematic cross-sectional view of a main part of a metal deposition process according to the second embodiment. FIG. FIG. 12 is a schematic cross-sectional view of the relevant part of the resist stripping process of the second embodiment, and FIG. 13 is a schematic view of the silicidation process of the second embodiment. FIG. Hereinafter, a method for forming a semiconductor device according to the second embodiment will be described in order with reference to FIGS. 1 to 3 and FIGS. 10 to 13, the same elements as those shown in FIGS. 1 to 8 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the method of forming the semiconductor device according to the second embodiment, the processes up to the steps shown in FIGS. 1 to 3 of the first embodiment are the same. Thereafter, in the second embodiment, first, the hard masks 4a and 4b are removed with phosphoric acid or the like, and then a metal 20 for silicidation is deposited on the entire surface as shown in FIG. As will be described later, the metal 20 deposited here is deposited in an amount (film thickness) in consideration of the silicide composition of the gate electrode 3a in the nMOS formation region.

  Next, as shown in FIG. 11, patterning is performed to cover the nMOS formation region with a resist 21, and the metal 20 exposed in the pMOS formation region is etched to reduce its thickness. Etching of the metal 20 may be performed by dry etching or wet etching. By this etching, the metal 20 is left thick in the nMOS formation region and thin in the pMOS formation region. The etching amount of the metal 20 in the pMOS formation region is set in consideration of the required characteristics of the semiconductor device to be formed, particularly the pMOS, specifically, the silicide composition of the gate electrode 3b in the pMOS formation region. After the etching of the metal 20 in the pMOS formation region, the resist 21 is removed by stripping as shown in FIG.

  Then, when annealing for full silicidation of the gate electrodes 3a and 3b is performed in such a state, as shown in FIG. 13, the gate electrodes 3a and 3b are full silicidized and the selective epitaxial layers 7a and 7b. The source / drain regions 8a and 8b are silicided to form silicide layers 12a and 12b.

  As shown in FIG. 12, since the film thickness of the metal 20 is thick in the nMOS formation region and thin in the pMOS formation region before full silicidation, when the full silicidation is performed, the gate electrodes 3a and 3b are formed. The silicide composition is different. That is, the gate electrode 3a having a silicide composition corresponding to the amount of the first deposited metal 20 can be obtained in the nMOS formation region, and the silicide composition corresponding to the amount remaining after etching of the first deposited metal 20 in the pMOS formation region. The gate electrode 3b is obtained. Thereafter, unreacted metal 20 is removed using sulfuric acid or the like.

As described above, even when full silicidation of the nMOS formation region and the pMOS formation region is performed at once, by controlling the film thickness of the metal 20 in the nMOS formation region and the pMOS formation region before full silicidation, It becomes possible to independently control the silicide compositions of 3a and 3b. This makes it possible to realize a high-performance semiconductor device in which each of the nMOS and pMOS transistors has an optimum _Vth .

  In the second embodiment, the thickness of the metal 20 in the pMOS formation region is reduced. On the contrary, the thickness of the metal 20 in the nMOS formation region is reduced to perform silicidation. It doesn't matter.

Next, a third embodiment will be described.
14 to 16 are explanatory views of the method of forming the semiconductor device according to the third embodiment. FIG. 14 is a schematic cross-sectional view of the main part of the first metal deposition step according to the third embodiment. FIG. 16 is a schematic cross-sectional view of an essential part of a reaction suppression layer forming step of the third embodiment, and FIG. 16 is a schematic cross-sectional view of an essential part of a second metal deposition step of the third embodiment. Hereinafter, a method for forming a semiconductor device according to the third embodiment will be described in order with reference to FIGS. 1 to 3 and FIGS. 14 to 16. 14 to 16, the same elements as those shown in FIGS. 1 to 8 are given the same reference numerals, and detailed description thereof is omitted.

  In the method of forming the semiconductor device according to the third embodiment, the processes up to the steps shown in FIGS. 1 to 3 of the first embodiment are the same. Thereafter, in the third embodiment, first, the hard masks 4a and 4b are removed with phosphoric acid or the like, and then a metal 30 for silicidation is deposited on the entire surface as shown in FIG. The metal 30 deposited here is deposited with a film thickness in consideration of the silicide composition of the gate electrode 3a in the nMOS formation region, as will be described later.

  Next, as shown in FIG. 15, a film made of a material which does not react with the metal 30 such as silicon oxide or silicon nitride or does not react so much is formed on the entire surface, and is left only in the nMOS formation region, for example, to form the pMOS. By removing from the formation region, the reaction suppression layer 31 is formed as a mask in the nMOS formation region.

  Next, as shown in FIG. 16, a metal 32 for silicidation is deposited again on the entire surface. At this time, the metal 32 is deposited on the reaction suppression layer 31 in the nMOS formation region, and is deposited on the metal 30 previously formed in the pMOS formation region. The metal 32 deposited here is deposited with a film thickness that takes into account the silicide composition of the gate electrode 3b in the pMOS formation region when added to the previously formed metal 30.

  Then, if annealing for full silicidation of the gate electrodes 3a and 3b is performed in such a state, the gate electrodes 3a and 3b in the nMOS formation region and the pMOS formation region are fully silicided and the selective epitaxial layer 7a, 7b and source / drain regions 8a and 8b are silicided.

  As shown in FIG. 16, before full silicidation, a metal 30, a reaction suppression layer 31, and a metal 32 are sequentially deposited on the gate electrode 3a in the nMOS formation region, and two layers are deposited on the gate electrode 3b in the pMOS formation region. Metals 30 and 32 are sequentially deposited. In the nMOS formation region, the metal 32 deposited on the reaction suppression layer 31 does not contribute to silicidation, but only the metal 30 contributes to silicidation. In the pMOS formation region, both the two layers of metals 30 and 32 are silicidated. Contribute to. As a result, different silicide compositions can be obtained for the gate electrodes 3a and 3b. That is, when full silicidation is performed, a gate electrode 3a having a silicide composition corresponding to the amount (film thickness) of one layer of metal 30 is obtained in the nMOS formation region, and two layers of metal 30, A gate electrode 3b having a silicide composition corresponding to the amount (film thickness) of 32 can be obtained.

  After full silicidation, first, the unreacted metal 32 is removed with sulfuric acid or the like, then the reaction suppression layer 31 is removed with phosphoric acid or the like, and finally the unreacted metal 30 is removed again with sulfuric acid or the like. A structure similar to that shown in FIG. 13 is obtained.

By using the reaction suppression layer 31 in this way, it becomes possible to independently control the silicide compositions of the gate electrodes 3a and 3b in the nMOS formation region and the pMOS formation region. This makes it possible to realize a high-performance semiconductor device in which each of the nMOS and pMOS transistors has an optimum _Vth .

  In the third embodiment, the reaction suppression layer 31 is left in the nMOS formation region. Conversely, the reaction suppression layer 31 may be left in the pMOS formation region to perform silicidation. .

Next, a fourth embodiment will be described.
17 to 20 are explanatory views of a method of forming a semiconductor device according to the fourth embodiment. FIG. 17 is a schematic cross-sectional view of a main part of a resist patterning process according to the fourth embodiment. FIG. FIG. 19 is a schematic cross-sectional view of an essential part of a metal deposition process according to the fourth embodiment, and FIG. 20 is an illustration of a silicidation process according to the fourth embodiment. It is a principal part cross-sectional schematic diagram. Hereinafter, a method for forming a semiconductor device according to the fourth embodiment will be described in order with reference to FIGS. 1 to 3 and FIGS. 17 to 20. In FIGS. 17 to 20, the same elements as those shown in FIGS. 1 to 8 are given the same reference numerals, and detailed descriptions thereof are omitted.

  In the method of forming the semiconductor device according to the fourth embodiment, the processes up to the steps shown in FIGS. 1 to 3 of the first embodiment are the same. Thereafter, in the fourth embodiment, first, after removing the hard masks 4a and 4b with phosphoric acid or the like, as shown in FIG. 17, for example, there is an opening 40a through which the gate electrode 3a in the nMOS formation region is exposed. The resist 40 is patterned.

  Then, using the resist 40 as a mask, the polysilicon of the gate electrode 3a is etched to reduce its thickness, as shown in FIG. At this time, the etching amount of the gate electrode 3a is set in consideration of the silicide composition of the gate electrode 3a when a metal 41 described later is deposited to be fully silicided. After the etching, the resist 40 is peeled off and removed.

  Thereafter, as shown in FIG. 19, a metal 41 for silicidation is deposited on the entire surface. The metal 41 deposited here is deposited in an amount (film thickness) in consideration of the silicide composition of the gate electrodes 3a and 3b in the nMOS formation region and the pMOS formation region.

  When annealing for full silicidation of the gate electrodes 3a and 3b is performed in such a state, the gate electrodes 3a and 3b in the nMOS formation region and the pMOS formation region are fully silicided as shown in FIG. At the same time, the selective epitaxial layers 7a and 7b and the source / drain regions 8a and 8b are silicided to form silicide layers 12a and 12b.

  As shown in FIG. 19, before full silicidation, a metal 41 is deposited with an equivalent film thickness on the gate electrodes 3a and 3b in the nMOS formation region and the pMOS formation region, but the gate electrodes 3a and 3b themselves The film thickness is different. In other words, a predetermined amount of metal 41 is deposited on each of the gate electrodes 3a and 3b in accordance with their film thickness. That is, when full silicidation is performed, the gate electrode 3a having a higher composition ratio of the metal 41 than the gate electrode 3b in the pMOS formation region is obtained in the nMOS formation region, and the gate electrode 3a in the nMOS formation region in the pMOS formation region. A gate electrode 3b having a small composition ratio of the metal 41 can be obtained. After full silicidation, unreacted metal 41 is removed with sulfuric acid or the like.

Thus, by controlling the film thickness of each gate electrode 3a, 3b in the nMOS formation region and the pMOS formation region before depositing the metal 41 on the entire surface, the silicide composition of each gate electrode 3a, 3b is independently controlled. It becomes possible to do. This makes it possible to realize a high-performance semiconductor device in which each of the nMOS and pMOS transistors has an optimum _Vth .

  In the fourth embodiment, in order to control the film thicknesses of the gate electrodes 3a and 3b in the nMOS formation region and the pMOS formation region before the deposition of the metal 41 for silicidation, in addition to the above method, The following method shown in FIGS. 21 to 26 can also be used.

  Here, FIG. 21 is a schematic cross-sectional view of the main part of the polysilicon forming process, FIG. 22 is a schematic cross-sectional view of the main part of the resist patterning process, FIG. 23 is a schematic cross-sectional view of the main part of the polysilicon etching process, and FIG. FIG. 25 is a schematic cross-sectional view of the relevant part of the step, FIG. 25 is a schematic cross-sectional view of the relevant part of the planarization process, and FIG. 26 is a schematic cross-sectional view of the relevant part of the gate electrode processing step. In FIG. 21 to FIG. 26, the same reference numerals are given to the same elements as those shown in FIG. 1, and the detailed description thereof is omitted.

  First, after element isolation regions (not shown) are formed at appropriate positions, as shown in FIG. 21, a thermal oxide film 50 is formed on the surface of the silicon substrate 1, and polysilicon is formed thereon using a CVD method or the like. 51 is formed. Next, as shown in FIG. 22, for example, the pMOS formation region is covered with a resist 52, and further, as shown in FIG. 23, the polysilicon 51 exposed in the nMOS formation region is etched using the resist 52 as a mask. The resist 52 is removed and removed. Next, as shown in FIG. 24, a silicon nitride film 53 is formed on the entire surface by CVD or the like, and further, as shown in FIG. 25, silicon nitride films in the nMOS formation region and the pMOS formation region by CMP (Chemical Mechanical Polishing). 53 is flattened. Such a planarization step may be omitted depending on circumstances.

  Finally, as shown in FIG. 26, the three layers of the silicon nitride film 53, the polysilicon 51, and the thermal oxide film 50 are etched using the photolithography technique while leaving the gate electrodes of the nMOS and pMOS. As a result, the gate electrodes 3a and 3b and the hard masks 4a and 4b are formed on the silicon substrate 1 in the nMOS formation region and the pMOS formation region via the gate insulating films 2a and 2b. Thereby, the gate electrode 3a is formed relatively thin in the nMOS formation region, and the gate electrode 3b is formed relatively thick in the pMOS formation region.

  After the formation of the gate electrodes 3a and 3b, the processes shown in FIG. 17 and subsequent steps may be performed through the steps shown in FIGS. Also by such a method, it becomes possible to control the silicide composition independently by controlling the film thickness of each gate electrode 3a, 3b.

  In the fourth embodiment, the thickness of the gate electrode 3a in the nMOS formation region is reduced. Conversely, the thickness of the gate electrode 3b in the pMOS formation region is reduced to perform silicidation. It doesn't matter if you do.

  In the first to third embodiments, the nMOS formation region and the pMOS formation region are formed using the method shown in FIG. 17 of the fourth embodiment and the method shown in FIGS. The gate electrodes 3a and 3b may be formed so as to have different film thicknesses.

As described above, according to the method for forming the semiconductor device of the first to fourth embodiments, the silicide compositions of the gate electrodes 3a and 3b in the nMOS formation region and the pMOS formation region are controlled independently. Therefore, it is possible to realize a high-performance semiconductor device in which each transistor of the pMOS has an optimum _Vth .

  The device formation conditions such as the size (film thickness, length, etc.) of each part (including those in the formation process) and ion implantation conditions of the semiconductor device in the first to fourth embodiments are formed. It can be set according to the required characteristics of nMOS and pMOS.

  In the first to fourth embodiments, each gate electrode is fully silicided. However, it is not always necessary to fully silicide. For example, in an element region that does not require full silicidation, the metal for silicidation is formed thinner on the gate electrode, or the gate electrode thickness (polysilicon film thickness) before silicidation is increased. That's fine. In addition, silicidation can be performed on all the gate electrodes or only on a part of the gate electrodes.

  In the first to fourth embodiments, an SOI (Silicon On Insulator) substrate can be used instead of the silicon substrate 1, and in that case, the first to fourth embodiments are also used. A semiconductor device can be formed by a method similar to that described above.

In addition, here, a method for forming a semiconductor device including two types of transistors, nMOS and pMOS, has been described as an example. However, the above-described formation method can also be applied to the case of forming other types of semiconductor devices. . For example, a semiconductor device in which a low V _th transistor and a high V _th transistor are mixedly mounted.

Usually, when a high V _th transistor is formed, a method of increasing the channel concentration by increasing the amount of ion implantation into the silicon substrate is employed in order to increase V _th . However, in this case, there is a possibility that the carrier mobility is lowered and a desired on-current cannot be obtained. Therefore, by utilizing the phenomenon that V _th is shifted by a full silicidation, when appropriately setting the silicide composition of the gate electrode of the high V _th transistor, it is possible to increase the V _th without increasing the channel concentration .

Therefore, even when a semiconductor device in which a low V _th transistor and a high V _th transistor are mixedly formed is used, the silicide composition of each transistor, in other words, the V _th of each transistor is controlled by using the above formation method. Therefore, a higher-performance semiconductor device can be realized.

(Supplementary Note 1) In a method for manufacturing a semiconductor device including a plurality of transistors,
Forming a plurality of gate electrodes on a semiconductor substrate;
Depositing a predetermined amount of metal on each of the gate electrode and the other gate electrode of the plurality of gate electrodes to form a silicide;
A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 2) In the step of silicidizing by depositing a predetermined amount of metal on each of the one gate electrode and the other gate electrode of the plurality of gate electrodes,
2. The method of manufacturing a semiconductor device according to claim 1, wherein an amount of metal corresponding to the silicide composition of each of the one gate electrode and the other gate electrode is deposited and silicided.

(Supplementary Note 3) In the step of silicidizing by depositing a predetermined amount of metal on each of the one gate electrode and the other gate electrode of the plurality of gate electrodes,
Forming a first mask on the other gate electrode, depositing metal in a region including the first mask and the one gate electrode, and silicidating the one gate electrode;
A second mask is formed on the silicided one gate electrode, and a metal is deposited in a region including the second mask and the other gate electrode to silicide the other gate electrode. To
The method of manufacturing a semiconductor device according to appendix 1, wherein:

(Supplementary Note 4) In the step of depositing a predetermined amount of metal on each of the one gate electrode and the other gate electrode among the plurality of gate electrodes to form a silicide,
Depositing a metal in a region including the one gate electrode and the other gate electrode;
Removing a portion of the metal deposited on the one gate electrode to reduce the amount of metal deposited on the one gate electrode;
Siliciding the one gate electrode and the other gate electrode;
The method of manufacturing a semiconductor device according to appendix 1, wherein:

(Supplementary Note 5) In the step of silicidizing by depositing a predetermined amount of metal on each of the one gate electrode and the other gate electrode of the plurality of gate electrodes,
Depositing a metal in a region including the one gate electrode and the other gate electrode;
Forming a mask on the metal deposited on the one gate electrode;
Further depositing metal in a region including on the mask and on the metal deposited on the other gate electrode;
Siliciding the one gate electrode and the other gate electrode;
The method of manufacturing a semiconductor device according to appendix 1, wherein:

(Supplementary Note 6) In the step of forming the plurality of gate electrodes on the semiconductor substrate,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the one gate electrode and the other gate electrode of the plurality of gate electrodes are formed to have different thicknesses.

(Supplementary Note 7) In the step of silicidizing by depositing a predetermined amount of metal on each of the one gate electrode and the other gate electrode of the plurality of gate electrodes,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the one gate electrode or the other gate electrode is fully silicided.

(Appendix 8) In the step of depositing a predetermined amount of metal on each of the one gate electrode and the other gate electrode among the plurality of gate electrodes to form a silicide,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the type of metal deposited on the one gate electrode is different from the type of metal deposited on the other gate electrode.

  (Appendix 9) One of the one gate electrode and the other gate electrode is a gate electrode of an n-type MOS transistor, and the other is a gate electrode of a p-type MOS transistor. A method for manufacturing a semiconductor device.

  (Supplementary note 10) The supplementary note 1, wherein one of the one gate electrode and the other gate electrode is a gate electrode of a high threshold voltage transistor, and the other is a gate electrode of a low threshold voltage transistor. A method for manufacturing a semiconductor device.

It is a principal part cross-sectional schematic diagram of the gate electrode processing process of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the side wall formation process of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the selective epitaxial growth process of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the mask formation process of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the resist patterning process of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the metal deposition process of 1st Embodiment. It is a principal part cross-sectional schematic diagram (the 1) of the silicidation process of 1st Embodiment. FIG. 6 is a schematic cross-sectional view (No. 2) of relevant parts of the silicidation process of the first embodiment. It is a figure which shows the relationship between the metal content in a gate electrode, and a flat band voltage. It is a principal part cross-sectional schematic diagram of the metal deposition process of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the resist patterning process of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the resist peeling process of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the silicidation process of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the 1st metal deposition process of 3rd Embodiment. It is a principal part cross-sectional schematic diagram of the reaction suppression layer formation process of 3rd Embodiment. It is a principal part cross-sectional schematic diagram of the 2nd metal deposition process of 3rd Embodiment. It is a principal part cross-sectional schematic diagram of the resist patterning process of 4th Embodiment. It is a principal part cross-sectional view of the polysilicon etching process of 4th Embodiment. It is a principal part cross-sectional schematic diagram of the metal deposition process of 4th Embodiment. It is a principal part cross-sectional schematic diagram of the silicidation process of 4th Embodiment. It is a principal part cross-sectional schematic diagram of a polysilicon formation process. It is a principal part cross-sectional schematic diagram of a resist patterning process. It is a principal part cross-sectional schematic diagram of a polysilicon etching process. It is a principal part cross-sectional schematic diagram of a hard mask formation process. It is a principal part cross-sectional schematic diagram of a planarization process. It is a principal part cross-sectional schematic diagram of a gate electrode processing process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2a, 2b Gate insulating film 3a, 3b Gate electrode 4a, 4b Hard mask 5a, 5b Extension area | region 6a, 6b Side wall 7a, 7b Selective epitaxial layer 8a, 8b Source / drain area | region 9,13 Mask 10,21, 40, 52 Resist 11, 20, 30, 32, 41 Metal 12a, 12b Silicide layer 31 Reaction suppression layer 40a Opening 50 Thermal oxide film 51 Polysilicon 53 Silicon nitride film

Claims (5)

In a method for manufacturing a semiconductor device including a plurality of transistors,
Forming a plurality of gate electrodes on a semiconductor substrate;
Depositing a predetermined amount of metal on each of the gate electrode and the other gate electrode of the plurality of gate electrodes to form a silicide;
A method for manufacturing a semiconductor device, comprising: In the step of silicidizing by depositing a predetermined amount of metal on each of the one gate electrode and the other gate electrode of the plurality of gate electrodes,
Forming a first mask on the other gate electrode, depositing metal in a region including the first mask and the one gate electrode, and silicidating the one gate electrode;
A second mask is formed on the silicided one gate electrode, and a metal is deposited in a region including the second mask and the other gate electrode to silicide the other gate electrode. To
The method of manufacturing a semiconductor device according to claim 1. In the step of silicidizing by depositing a predetermined amount of metal on each of the one gate electrode and the other gate electrode of the plurality of gate electrodes,
Depositing a metal in a region including the one gate electrode and the other gate electrode;
Removing a portion of the metal deposited on the one gate electrode to reduce the amount of metal deposited on the one gate electrode;
Siliciding the one gate electrode and the other gate electrode;
The method of manufacturing a semiconductor device according to claim 1. In the step of silicidizing by depositing a predetermined amount of metal on each of the one gate electrode and the other gate electrode of the plurality of gate electrodes,
Depositing a metal in a region including the one gate electrode and the other gate electrode;
Forming a mask on the metal deposited on the one gate electrode;
Further depositing metal in a region including on the mask and on the metal deposited on the other gate electrode;
Siliciding the one gate electrode and the other gate electrode;
The method of manufacturing a semiconductor device according to claim 1. In the step of forming the plurality of gate electrodes on the semiconductor substrate,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the first gate electrode and the other gate electrode of the plurality of gate electrodes are formed to have different film thicknesses.

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