JP2010272596A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technique for suitably setting respective threshold voltages of an n-channel field-effect transistor and a p-channel field-effect transistor, in a semiconductor device having a CMIS device of ≤32 nm in half-pitch size. <P>SOLUTION: In a pMIS formation region, a pMIS 100p is formed which has a gate insulating film 5 consisting of a high dielectric film 5h (for example, an HfO<SB>2</SB>film) in which principally Al is diffused, and a metal gate electrode 6 comprising a laminate film of a lower-layer metal gate electrode 6D and an upper-layer metal gate electrode 6U. In an nMIS formation region, an nMIS 100n is formed which has a gate insulating film 11 consisting of a high dielectric film 5h (for example, an HfO<SB>2</SB>film) in which principally La (lanthanum) is diffused, and a metal gate electrode 12 comprising the upper-layer metal gate electrode 6U. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to the manufacture of a field effect transistor having a gate electrode made of metal and a gate insulating film made of a high dielectric film.

  For example, Japanese Unexamined Patent Application Publication No. 2007-110091 (Patent Document 1) discloses a PMOS transistor including a first gate electrode having a first thickness and a second gate having a second thickness smaller than the first thickness. And a NMOS transistor including an electrode, and the work function of the PMOS transistor and the NMOS transistor is set by the thicknesses of the first gate electrode and the second gate electrode.

  Japanese Patent Laid-Open No. 2007-243209 (Patent Document 2) discloses a gate insulating film made of a hafnium oxide film, a metal oxide film made of an aluminum oxide film formed on the gate insulating film, and a metal oxide film. A p-channel MISFET is disclosed which includes a gate electrode made of a tantalum nitride film formed thereon, and the metal oxide film has a function of shifting the work function value of the gate electrode.

  Japanese Patent Laid-Open No. 2007-19400 (Patent Document 3) discloses a PMOS transistor gate electrode having a first metal layer / polycrystalline silicon layer stacked structure and an NMOS transistor gate electrode having a second metal layer / polycrystalline structure. A technique is disclosed in which a laminated structure of silicon layers is formed, the thickness of the second metal layer is formed to be thinner than the thickness of the first metal layer, and the respective threshold values are controlled.

  Also, S. Kubicek et al., International Electron Devices Meeting 2008 Technical Digest, 2007, p. 49-52 (Non-patent Document 1) uses a high-k insulating film whose main electrode is made of a metal whose main material is TaC, and whose main material is Hf containing La for the gate insulating film of the nMOS. A CMOS device using a high-k insulating film mainly containing Hf containing Al as a gate insulating film is described.

  In addition, H. Rusty Harris et al., 2007 Symposium on VLSI Technology Digest of Technical Papers, 2007, p. In 154 to 155 (Non-patent Document 2), the NMOS gate insulating film (high-k insulating film) and the metal gate electrode are different from the PMOS gate insulating film (high-k insulating film) and the metal gate electrode, respectively. There is described a CMOS device provided in SiGe formed by a process and further having a PMOS channel formed by epitaxial growth.

JP 2007-110091 A JP 2007-243209 A JP 2007-19400 A

S. Kubicek et al., International Electron Devices Meeting 2008 Technical Digest, 2007, p. 49-52 H. Rusty Harris et al., 2007 Symposium on VLSI Technology Digest of Technical Papers, 2007, p. 154-155

In a planar type field effect transistor having an hp (half pitch size) of 32 nm or less used in SoC (System on a Chip), it is necessary to reduce not only the planar dimension but also the dimension in the height direction according to the reduction proportional law. However, since it is necessary to suppress the leakage current between the gate electrode and the silicon substrate or the leakage current between the gate electrode and the source / drain through the gate insulating film, the physical thickness of the gate insulating film is reduced. It can't be too much. When a gate electrode made of polycrystalline silicon is used, the gate depletion typically observed is about 0.3 nm in terms of an oxide film, so that an equivalent oxide film required for an hp32 nm planar field effect transistor is used. When the thickness (the film thickness converted to an electrical film thickness equivalent to the SiO ₂ film in consideration of the dielectric constant) is about 1 nm, the influence of the gate depletion becomes relatively large, and the improvement of the gate capacitance is limited.

Therefore, as means for solving these problems, for example, an insulating material generally called a High-k insulating film having a dielectric constant larger than that of SiO ₂ is used for the gate insulating film, and polycrystalline Si is used for the gate electrode. Therefore, methods using metal have been studied. The former method can prevent the physical film thickness from becoming too thin while ensuring an equivalent oxide film thickness of 1 nm. Further, gate depletion can be suppressed by the latter method.

  When the gate electrode is made of metal, the work function of the metal used for the gate electrode is one of the major factors that determine the threshold voltage of the field effect transistor. There are various metal materials such as TiN, TiSiN, TaSiN, TaC, W, and Mo as candidates for the metal material to be used, and each metal material basically has a specific work function. However, the work function of each metal material greatly depends on film formation conditions and process conditions before and after film formation (see, for example, Patent Document 1 described above). In other words, not only the selection of the metal material but also the setting of the film formation conditions and the process conditions before and after the film formation are the first means for adjusting the threshold voltage.

  However, it is difficult to set the threshold voltage of the n-channel field effect transistor and the threshold voltage of the p-channel field effect transistor in a well-balanced manner by simply forming the gate electrode from the same metal and changing the film thickness. For example, a threshold voltage of +0.4 V is obtained for an n-channel field effect transistor for LSTP (Low Standby Power) and −0.4 V for a p-channel field effect transistor, and an n-channel electric field is used for LOP (Low Operation Power). A threshold voltage of +0.3 V is obtained with an effect transistor and −0.3 V is obtained with a p-channel field effect transistor, and +0.2 V with an n-channel field effect transistor and a p-channel field effect transistor for HP (High Performance). It is difficult to obtain a threshold voltage of −0.2V.

Therefore, in recent years, it has been studied to reduce the threshold voltage by forming a metal oxide on the upper or lower side of the high-k insulating film. For example, a technique is disclosed in which a metal oxide, for example, an Al ₂ O ₃ film is inserted between a high-k insulating film and a metal gate electrode in a p-channel field effect transistor (see, for example, Patent Document 2 described above). A technique of inserting a metal oxide has been studied as a second means for adjusting the threshold voltage of a field effect transistor.

  Further, for the purpose of reducing and setting the threshold voltage as well as reducing the threshold voltage of one of the field effect transistors, metal oxides of different materials are used for each of the n-channel field effect transistor and the p-channel field effect transistor. (See, for example, the aforementioned non-patent documents 1 and 2).

  By the way, when a high-k insulating film and a metal oxide are employed, in the process of manufacturing an n-channel field effect transistor and a p-channel field effect transistor, the process is complicated and difficult to process, and the number of processes is large. There's a problem. For example, when a p-channel field effect transistor is manufactured first, a high-k insulating film is formed, a metal oxide for a p-channel field effect transistor is formed, and a p-channel type only in an n-channel field effect transistor region is formed. Removal of metal oxide for field effect transistor, formation of metal oxide for n channel field effect transistor, and removal of metal oxide for n channel field effect transistor only in p channel field effect transistor region A first process flow is possible. However, in this first process flow, in order to separate the n-channel field effect transistor region and the p-channel field effect transistor region, two lithography / etching steps are required. When miniaturization progresses like a planar field effect transistor of hp 32 nm or less, the gate electrode of an n-channel type field effect transistor such as SRAM (Static Random Access Memory) and the gate electrode of a p-channel type field effect transistor approach each other. In a region where accurate overlay is required, there is a concern that variations in transistor characteristics of the n-channel field effect transistor and the p-channel field effect transistor may increase. In an SRAM, the smaller the area, the greater the risk that normal transistor operation will be hindered due to increased variations in transistor characteristics of the n-channel field effect transistor and the p-channel field effect transistor. Therefore, the importance of accurate overlay increases as the miniaturization progresses.

  Therefore, for example, in the first process flow described above, after the metal oxide for the n-channel field effect transistor is formed, the metal oxide for the n-channel field effect transistor only in the p-channel field effect transistor region is formed. A second process flow without removal is proposed. By adopting this second process flow, the lithography and etching process for separating the n-channel field effect transistor region and the p-channel field effect transistor region can be stopped at one time, thereby reducing the overlay problem. can do.

  Further, by adopting this second process flow, the following advantages can be obtained. (1) Considering the work function or mobility, the thickness of the metal gate electrode of the n-channel field effect transistor and the thickness of the metal gate electrode of the p-channel field effect transistor can be determined respectively. Optimal setting is possible. (2) Since the high-k insulating film of the n-channel field effect transistor and the high-k insulating film of the p-channel field effect transistor can be formed of different metal oxides, the threshold voltage can be reduced for each of them. Optimal setting is possible. (3) Overlay deviation can be suppressed by performing separate formation of the metal oxide for the n-channel field effect transistor and the metal oxide for the p-channel field effect transistor in one lithography / etching step, As a result, variations in transistor characteristics can be reduced.

  However, in the second process flow, the metal oxide for the n-channel field effect transistor is in contact with the metal oxide for the p-channel field effect transistor in the p-channel field effect transistor region. As a result, it is conceivable that the mutual effects are offset and the effect of lowering the threshold voltage of the p-channel field effect transistor is reduced. This problem is that the high-k insulating film of the p-channel field effect transistor is in contact with the metal oxide for the p-channel field effect transistor, and the high-k insulating film of the n-channel field effect transistor is in contact with the high-k insulating film. This can be solved by bringing the metal oxide for the n-channel field effect transistor into contact. However, as described above, two lithography / etching steps are required to make each of them in this way, which causes a problem of overlay.

  An object of the present invention is to provide a technique capable of appropriately setting respective threshold voltages of an n-channel field effect transistor and a p-channel field effect transistor in a semiconductor device having a CMIS device having an hp of 32 nm or less. .

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, an embodiment of a representative one will be briefly described as follows.

In this embodiment, a p-channel field effect transistor is formed in a first region of a semiconductor substrate, and an n-channel field effect transistor is formed in a second region of the semiconductor substrate. An HfO ₂ film, an Al ₂ O ₃ film having a dielectric constant higher than that of SiO ₂ , and a first TiN film having a first thickness are formed on the main surface of the semiconductor substrate. Subsequently, after removing the first TiN film and the Al ₂ O ₃ film in the second region, a La ₂ O ₃ film and a second TiN film having a second thickness smaller than the first thickness are formed on the main surface of the semiconductor substrate. Form. Subsequently, heat treatment is performed on the semiconductor substrate, Al is diffused in the HfO ₂ film in the first region, La is diffused in the HfO ₂ film in the second region, and then the polycrystalline Si film is formed on the main surface of the semiconductor substrate. Form. Subsequently, a multilayer film composed of the polycrystalline Si film, the second TiN film, the first TiN film, the Al ₂ O ₃ film, and the HfO ₂ film in which Al is diffused in the first region is processed to obtain a p-channel field effect transistor. Forming a gate electrode made of a polycrystalline Si film, a second TiN film, and a first TiN film, and a gate insulating film made of an Al ₂ O ₃ film and an HfO ₂ film in which Al is diffused; A laminated film composed of the second TiN film, La ₂ O ₃ film, and La diffused HfO ₂ film is processed to form a gate electrode composed of the polycrystalline Si film and the second TiN film of the n-channel field effect transistor, and La ₂ O _A gate insulating film composed of _three films and an HfO ₂ film in which La is diffused is formed.

Further, this embodiment is a method for manufacturing a semiconductor device in which a p-channel field effect transistor is formed in a first region of a semiconductor substrate and an n-channel field effect transistor is formed in a second region of the semiconductor substrate. An HfO ₂ film, an Al ₂ O ₃ film having a dielectric constant higher than that of SiO ₂ , and a first TiN film having a first thickness are formed on the main surface of the semiconductor substrate. Subsequently, after removing the first TiN film and the Al ₂ O ₃ film in the second region, a La ₂ O ₃ film and a second TiN film having a second thickness smaller than the first thickness are formed on the main surface of the semiconductor substrate. Form. Subsequently, after forming the first polycrystalline Si film on the La ₂ O ₃ film, the first polycrystalline Si film is ground until the upper surface of the first TiN film in the first region is exposed. Subsequently, after forming a second polycrystalline Si film on the main surface of the semiconductor substrate, heat treatment is performed to the semiconductor substrate, the HfO ₂ film in the first region by diffusing the Al, the HfO ₂ film of the second region La diffuses. Subsequently, a laminated film composed of the second polycrystalline Si film, the first TiN film, the Al ₂ O ₃ film, and the HfO ₂ film in which Al is diffused in the first region is processed to obtain the second p-channel field effect transistor. A gate electrode composed of a polycrystalline Si film and a first TiN film, an Al ₂ O ₃ film, and a gate insulating film composed of an HfO ₂ film in which Al is diffused are formed, and the second polycrystalline Si film in the second region, A laminated film composed of the crystalline Si film, the second TiN film, the La ₂ O ₃ film, and the HfO ₂ film in which La is diffused is processed to obtain the second polycrystalline Si film and the first polycrystalline Si film of the n-channel field effect transistor. A gate electrode made of a film, a second TiN film, a La ₂ O ₃ film, and a gate insulating film made of an HfO ₂ film in which La is diffused are formed.

  Among the inventions disclosed in the present application, effects obtained by one embodiment of a representative one will be briefly described as follows.

  In a semiconductor device having a CMIS device with an hp of 32 nm or less, the threshold voltages of the n-channel field effect transistor and the p-channel field effect transistor can be set appropriately.

It is principal part sectional drawing which shows the CMIS device by Embodiment 1 of this invention. It is principal part sectional drawing which shows the manufacturing process of the CMIS device by Embodiment 1 of this invention. FIG. 3 is a cross-sectional view of an essential part of the same place in FIG. 2 during a manufacturing step for the CMIS device continued from FIG. 2. FIG. 4 is a fragmentary cross-sectional view of the same portion as that in FIG. 2 during a manufacturing step of the CMIS device subsequent to FIG. 3. FIG. 5 is a fragmentary cross-sectional view of the same portion as that in FIG. 2 during a manufacturing step of the CMIS device continued from FIG. 4. FIG. 6 is a fragmentary cross-sectional view of the same portion as that in FIG. 2 during a manufacturing step of the CMIS device continued from FIG. 5. FIG. 7 is a fragmentary cross-sectional view of the same portion as that of FIG. 2 during a manufacturing step of the CMIS device continued from FIG. 6. FIG. 8 is a cross-sectional view of the principal part of the same portion as FIG. 2 in the manufacturing step for the CMIS device continued from FIG. 7. FIG. 9 is an essential part cross-sectional view of the same portion as that of FIG. 2 of the CMIS device during a manufacturing step following that of FIG. 8; FIG. 10 is a fragmentary cross-sectional view of the same portion as that of FIG. 2 of the CMIS device during a manufacturing step following that of FIG. 9; It is principal part sectional drawing of the same location as FIG. 2 in the manufacturing process of the CMIS device following FIG. FIG. 12 is a fragmentary cross-sectional view of the same portion as that in FIG. 2 of the CMIS device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the same place as that in FIG. 2 during a manufacturing step of the CMIS device continued from FIG. 12. It is principal part sectional drawing which shows the CMIS device by Embodiment 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the CMIS device by Embodiment 2 of this invention. FIG. 16 is a cross-sectional view of the principal part of the same portion as FIG. 15 in the manufacturing step for the CMIS device continued from FIG. 15; FIG. 17 is an essential part cross-sectional view of the same portion as that of FIG. 15 of the CMIS device during a manufacturing step following that of FIG. 16; FIG. 18 is a cross-sectional view of the principal part of the same portion as FIG. 15 in the manufacturing step for the CMIS device continued from FIG. FIG. 19 is a cross-sectional view of the principal part of the same portion as FIG. 15 in the manufacturing step for the CMIS device continued from FIG. FIG. 20 is a cross-sectional view of the principal part of the same portion as FIG. 15 in the manufacturing step for the CMIS device continued from FIG. 19;

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In the following embodiments, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a p-channel type MISFET is abbreviated as pMIS, and an n-channel type MISFET is abbreviated as nMIS. In the following embodiments, the term “wafer” is mainly a Si (Silicon) single crystal wafer. However, not only that, but also an SOI (Silicon On Insulator) wafer and an integrated circuit are formed thereon. Insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
A CMIS (Complementary Metal Insulator Semiconductor) device according to the first embodiment will be described with reference to FIG.

  An element isolation 2 is formed on the main surface of the semiconductor substrate 1. The element isolation 2 has a function of preventing interference between elements formed on the semiconductor substrate 1, and is formed by, for example, an STI (Shallow Trench Isolation) method in which a groove is formed in the semiconductor substrate 1 and an insulating film is embedded in the groove. Is done. The active region isolated by the element isolation 2 is a pMIS formation region (first region) or an nMIS formation region (second region).

  An n-type well 3 that is a semiconductor region is formed on the main surface of the semiconductor substrate 1 in the pMIS formation region, and a p-type well 4 that is a semiconductor region is formed on the main surface of the semiconductor substrate 1 in the nMIS formation region. Yes. An n-type impurity such as P (phosphorus) or As (arsenic) is introduced into the n-type well 3, and a p-type impurity such as B (boron) is introduced into the p-type well 4.

  Next, the configuration of the pMIS 100p formed in the pMIS formation region will be described. As shown in FIG. 1, a gate insulating film 5 is formed on the n-type well 3 formed on the main surface of the semiconductor substrate 1 in the pMIS formation region.

The gate insulating film 5 is mainly formed of a high dielectric film 5h having a dielectric constant higher than that of, for example, SiO ₂ (silicon oxide). Examples of the high dielectric film 5h include a hafnium-based insulating film such as an HfO ₂ (hafnium oxide) film, an HfON (hafnium oxynitride) film, an HfSiO (hafnium silicate) film, or an HfSiON (hafnium silicon oxynitride) film. Is used. A metal oxide film (first metal oxide film) 5m1, for example, an Al ₂ O ₃ (aluminum oxide) film, is formed on the upper surface of the high dielectric film 5h, and a metal (first metal) contained in the metal oxide film 5m1. For example, Al (aluminum) is diffused in the high dielectric film 5h. An oxide film 5s, for example, a SiO ₂ film is formed between the semiconductor substrate 1 and the high dielectric film 5h.

A metal gate electrode 6 is formed on the gate insulating film 5. The metal gate electrode 6 has a structure in which a lower metal gate electrode 6D made of a first metal gate electrode material and an upper metal gate electrode 6U made of a second metal gate electrode material are laminated. The lower metal gate electrode 6D and the upper metal gate electrode 6U are made of, for example, a TiN (titanium nitride) film, but are not limited thereto. For example, TaN film, TaSiN film, TiAlN film, HfN film, Ni _x Si _1-x film, PtSi film, Ni _x Ta _1-x Si film, Ni _x Pt _1-x Si film, HfSi film, WSi film, Ir _x The metal gate electrode 6 may be composed of any one of a Si _1-x film, a TaGe film, a TaCx film, a Mo film, and a W film. Furthermore, a silicon gate electrode 7 is formed on the metal gate electrode 6. The silicon gate electrode 7 is composed of a polycrystalline Si film (silicon gate electrode material) into which an impurity of about 1 × 10 ²⁰ cm ⁻³ is introduced, for example. Therefore, the gate electrode Gp1 of the pMIS 100p has a structure in which the metal gate electrode 6 and the silicon gate electrode 7 are stacked.

  On the side walls on both sides of the gate electrode Gp1, side walls 8 made of, for example, an insulating film are formed. A p-type extension region 9 which is a semiconductor region is formed in the semiconductor substrate 1 (n-type well 3) immediately below the sidewall 8, and a p-type diffusion region 10 is formed outside the p-type extension region 9. ing. A p-type impurity such as B is introduced into the p-type extension region 9 and the p-type diffusion region 10, and the p-type impurity is introduced into the p-type diffusion region 10 at a higher concentration than the p-type extension region 9. Yes. The p-type extension region 9 and the p-type diffusion region 10 form a source / drain region SD of the pMIS 100p having an extension or LDD (Lightly Doped Drain) structure.

  Next, the configuration of the nMIS 100n formed in the nMIS formation region will be described. As shown in FIG. 1, a gate insulating film 11 is formed on the p-type well 4 formed on the main surface of the semiconductor substrate 1 in the nMIS formation region.

The gate insulating film 11 is formed mainly from, for example, having a dielectric constant higher than that of SiO ₂ high dielectric film 5h. As the high dielectric film 5h, for example, a hafnium-based insulating film such as an HfO ₂ film, an HfON film, an HfSiO film, or an HfSiON film is used. On the upper surface of the high dielectric film 5h, a metal oxide film (second metal oxide film) 5m2, for example, a La ₂ O ₃ (lanthanum oxide) film, a Y ₂ O ₃ (yttrium oxide) film, an MgO (magnesium oxide) film, or A Sc ₂ O ₃ (scandium oxide) film is formed, and a metal (second metal) contained in the metal oxide film 5m2, such as La (lanthanum), Y (yttrium), Mg (magnesium), or Sc (scandium) Is diffused in the high dielectric film 5h. An oxide film 5s, for example, a SiO ₂ film is formed between the semiconductor substrate 1 and the high dielectric film 5h.

  A metal gate electrode 12 is formed on the gate insulating film 11. The metal gate electrode 12 is made of the same electrode material (second metal gate electrode material) as the upper metal gate electrode 6U located above the metal gate electrode 6 constituting a part of the gate electrode Gp1 of the pMIS 100p described above. Yes. Furthermore, a silicon gate electrode 13 is formed on the metal gate electrode 12. The silicon gate electrode 13 is made of the same silicon gate electrode material as that of the silicon gate electrode 7 constituting the other part of the gate electrode Gp1 of the pMIS 100p described above. Therefore, although the gate electrode Gn1 of the nMIS 100n has a structure in which the metal gate electrode 12 and the silicon gate electrode 13 are stacked, the thickness of the gate electrode Gn1 of the nMIS 100n is larger than the thickness of the gate electrode Gp1 of the pMIS 100p. The lower metal gate electrode 6D positioned below the metal gate electrode 6 constituting a part of the gate electrode Gp1 of the pMIS 100p is thinned by the thickness.

  On the side walls on both sides of the gate electrode Gn1, side walls 8 made of, for example, an insulating film are formed. An n-type extension region 14 which is a semiconductor region is formed in the semiconductor substrate 1 (p-type well 4) immediately below the sidewall 8, and an n-type diffusion region 15 is formed outside the n-type extension region 14. ing. An n-type impurity such as P or As is introduced into the n-type extension region 14 and the n-type diffusion region 15, and the n-type impurity is introduced into the n-type diffusion region 15 at a higher concentration than the n-type extension region 14. Has been. The n-type extension region 14 and the n-type diffusion region 15 form the source / drain region SD of the nMIS 100n having the LDD structure.

As described above, the gate insulating film 5 of the pMIS 100p is composed of a high dielectric film (for example, HfO ₂ film) 5h in which Al is diffused, and the gate insulating film 11 of the nMIS 100n is a high dielectric in which La, Y, Mg, or Sc is diffused. The body film (for example, HfO ₂ film) 5h, the thickness (first thickness) of the metal gate electrode 6 constituting a part of the gate electrode Gp1 of the pMIS 100p, and the part of the gate electrode Gn1 of the nMIS 100n The thickness (second thickness) of the metal gate electrode 12 is changed (the thickness of the metal gate electrode 6 constituting a part of the gate electrode Gp1 of the pMIS 100p is changed to the metal constituting the part of the gate electrode Gn1 of the nMIS 100n) And the work function of each of the pMIS 100p and the nMIS 100n is controlled. And it makes it possible to set the threshold voltage of each of pMIS100p and nMIS100n to appropriate values.

  Next, the manufacturing method of the CMIS device according to the first embodiment will be described in the order of steps with reference to FIGS. 2 to 13 are cross-sectional views of the main part of the CMIS device.

First, as shown in FIG. 2, for example, a semiconductor substrate (in this stage, a substantially circular semiconductor thin plate called a semiconductor wafer) 1 in which a p-type impurity such as B is introduced into single crystal Si is prepared. Next, element isolation 2 is formed on the main surface of the semiconductor substrate 1. The element isolation 2 is made of, for example, SiO ₂ and is formed by an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. FIG. 2 shows an element isolation 2 formed by the STI method of embedding a SiO ₂ film in a groove formed in the semiconductor substrate 1. The active region is isolated by the element isolation 2 to form a pMIS formation region and an nMIS formation region.

  Next, the n-type well 3 is formed in the pMIS formation region using photolithography and ion implantation. The n-type well 3 is a semiconductor region, and an n-type impurity such as P or As is introduced. Similarly, the p-type well 4 is formed in the nMIS formation region using photolithography and ion implantation. The p-type well 4 is a semiconductor region, and a p-type impurity such as B is introduced.

Next, the SiO ₂ film 16 is formed on the main surface of the semiconductor substrate 1 by using, for example, a thermal oxidation method. The thickness of the SiO ₂ film 16 is, for example, 1 nm or less, and a typical thickness is, for example, about 0.7 nm. Subsequently, a high dielectric film, for example, an HfO ₂ film 17 is formed on the SiO ₂ film 16 by using, for example, a CVD (Chemical Vapor Deposition) method or an ALD (Atomic Layer Deposition) method. The thickness of the HfO ₂ film 17 is, for example, 5 nm or less, and a typical thickness is, for example, about 2.0 to 2.5 nm. Instead of the HfO ₂ film 17, for example, another hafnium-based insulating film such as an HfON film, an HfSiO film, or an HfSiON film can be used.

Next, heat treatment is performed on the semiconductor substrate 1. The heat treatment is performed, for example, at 850 ° C. for about 5 seconds in an N ₂ atmosphere. This heat treatment can improve the crystallinity of the HfO ₂ film 17.

Next, as shown in FIG. 3, an Al ₂ O ₃ film 18 is formed on the HfO ₂ film 17 by using, for example, an ALD method. The thickness of the Al ₂ O ₃ film 18 is about 0.5 nm, for example.

Next, as shown in FIG. 4, a first metal gate electrode material, for example, a TiN film 19 is formed on the Al ₂ O ₃ film 18 by using, for example, a sputtering method. The thickness of the TiN film 19 is about 10 nm, for example. Subsequently, a SiN (silicon nitride) film 20 is formed on the TiN film 19 by using, for example, a CVD method. The thickness of the SiN film 20 is, for example, about 30 nm.

  Next, as shown in FIG. 5, a resist pattern 21 covering the pMIS formation region is formed by photolithography, and the SiN film in the nMIS formation region exposed from the resist pattern 21 is formed using the resist pattern 21 as a mask. 20 is removed using, for example, a dry etching method.

Next, as shown in FIG. 6, after removing the resist pattern 21, the TiN film 19 in the nMIS formation region exposed from the SiN film 20 is removed by using, for example, a wet etching method. In this wet etching method, for example, a solution containing hydrogen peroxide (H ₂ O ₂ ) is used.

  Next, as shown in FIG. 7, the SiN film 20 is removed by using, for example, a wet etching method. In this wet etching method, for example, a solution containing hydrofluoric acid (HF) is used.

Next, as shown in FIG. 8, the exposed Al ₂ O ₃ film 18 in the nMIS formation region is removed by using, for example, a wet etching method to expose the underlying HfO ₂ film 17. Here, since the wet etching method is used to remove the Al ₂ O ₃ film 18, the HfO ₂ film 17 is not easily damaged by etching, and lattice defects or oxygen depletion is hardly formed.

Next, as shown in FIG. 9, a La ₂ O ₃ film 22 is formed on the TiN film 19 in the pMIS formation region and on the HfO ₂ film 17 in the nMIS formation region, for example, using an ALD method. The thickness of the La ₂ O ₃ film 22 is, for example, about 0.1 to 0.3 nm. Subsequently, a second metal gate electrode material, for example, a TiN film 23 is formed on the La ₂ O ₃ film 22 by using, for example, a sputtering method. The thickness of the TiN film 23 is, for example, about 5 nm. Instead of the La ₂ O ₃ film 22, a Y ₂ O ₃ film, a MgO film, or a Sc ₂ O ₃ film can also be used.

Next, as shown in FIG. 10, a heat treatment is performed on the semiconductor substrate 1. The heat treatment is performed at a temperature of 1000 ° C., for example. This heat treatment diffuses Al in _{the Al} 2 _{O 3} film 18 is pMIS formation region on the HfO ₂ film 17, in the nMIS formation region La in _La 2 _{O 3} film 22 is diffused into the HfO ₂ film 17.

Here, in the pMIS formation region, the La ₂ O ₃ film 22 is sandwiched between the TiN film 19 and the TiN film 23, and La in the La ₂ O ₃ film 22 is also diffused into the TiN film 19 and the TiN film 23. To do. However, most of the La diffused into the lower TiN film 19 remains in the TiN film 19 and very little La diffuses into the HfO ₂ film 17 in the pMIS formation region. Therefore, in the pMIS formation region, there is a low risk that the effect of diffusion of Al into the HfO ₂ film 17 is offset by the diffusion of La.

Further, by reducing the thickness of the La ₂ O ₃ film 22 to about 0.1 to 0.3 nm, most of La and O (oxygen) is diffused into the TiN film 19 or the TiN film 23 by the heat treatment. The La and O concentrations at the interface between the TiN film 19 and the TiN film 23 decrease. Therefore, when the TiN film 19 and the TiN film 23 are processed in a later process, an etching defect (for example, a change in etching rate) due to La and O remaining at the interface between the TiN film 19 and the TiN film 23. Is unlikely to occur.

When it is desired to improve the etching processability, the steps described with reference to FIGS. 9 and 10 are changed as follows. That is, after the La ₂ O ₃ film 22 is formed, heat treatment is performed, and subsequently, La remaining on the TiN film 19 in the pMIS formation region is removed with a nitric acid / aqueous hydrochloric acid solution or the like. Al is diffused in the HfO ₂ film 17 in the pMIS formation region by the heat treatment, and the crystallized HfO ₂ film 17 is hardly etched even if a treatment with a nitric acid aqueous solution or a hydrochloric acid aqueous solution is performed. For two reasons, Al is present in the HfO ₂ film 17 in the pMIS formation region even if the treatment is performed with a nitric acid / aqueous solution or a hydrochloric acid / aqueous solution. Thereafter, a TiN film 23 is formed.

  Next, as shown in FIG. 11, a polycrystalline Si film 24 is formed on the TiN film 23 by using, for example, a CVD method. The thickness of the polycrystalline Si film 24 is, for example, about 50 nm. The polycrystalline Si film 24 in the pMIS formation region and the nMIS formation region may be composed of polycrystalline Si having the same conductivity by introducing an n-type impurity or a p-type impurity. The Si film 24 may be composed of polycrystalline Si exhibiting p-type conductivity, and the polycrystalline Si film 24 in the nMIS formation region may be composed of polycrystalline Si exhibiting n-type conductivity.

  Next, as shown in FIG. 12, the gate insulating film 5 and the gate electrode Gp1 are formed in the pMIS formation region using the photolithography method and the dry etching method, and the gate insulating film 11 and the gate electrode Gn1 are formed in the nMIS formation region. Form.

The gate insulating film 5 formed in the pMIS formation region includes an SiO ₂ film 16 (oxide film 5s), an Al diffused HfO ₂ film 17 (high dielectric film 5h), and an Al ₂ O ₃ film 18 (metal oxide film 5m1). The gate electrode Gp1 is composed of the metal gate electrode 6 and the silicon gate electrode 7. Further, the metal gate electrode 6 is constituted by a TiN film 19 (lower metal gate electrode 6D) and a TiN film 23 (upper metal gate electrode 6U), and the silicon gate electrode 7 is constituted by a polycrystalline Si film 24.

The gate insulating film 11 formed in the nMIS formation region includes a SiO ₂ film 16 (oxide film 5s), a La diffused HfO ₂ film 17 (high dielectric film 5h), and a La ₂ O ₃ film 22 (metal oxide film 5m2). The gate electrode Gn1 is composed of a metal gate electrode 12 and a silicon gate electrode 13. Further, the metal gate electrode 12 is composed of a TiN film 23 (upper layer metal gate electrode 6U), and the silicon gate electrode 13 is composed of a polycrystalline Si film 24.

  The metal gate electrode 6 constituting a part of the gate electrode Gp1 formed in the pMIS formation region is composed of the TiN film 19 and the TiN film 23, and the metal gate constituting a part of the gate electrode Gn1 formed in the nMIS formation region. The electrode 12 is made of a TiN film 23. Therefore, the thickness of the metal gate electrode 6 constituting a part of the gate electrode Gp1 formed in the pMIS formation region and the thickness of the metal gate electrode 12 constituting a part of the gate electrode Gn1 formed in the nMIS formation region are determined. , Each can be set to an optimum value considering the work function. In the first embodiment, the thickness of the metal gate electrode 6 constituting a part of the gate electrode Gp1 formed in the pMIS formation region is set to about 15 nm, and a part of the gate electrode Gn1 formed in the nMIS formation region is constituted. The thickness of the metal gate electrode 12 to be set is about 5 nm, and the thicknesses of the metal gate electrodes 12 are set to be different from each other by about 10 nm.

  Next, as shown in FIG. 13, the p-type extension region 9 is formed in the pMIS formation region in a self-aligned manner with respect to the gate electrode Gp1 by using a photolithography method and an ion implantation method. The p-type extension region 9 is a semiconductor region and can be formed by introducing a p-type impurity such as B into the semiconductor substrate 1. Similarly, the n-type extension region 14 is formed in the nMIS formation region in a self-aligned manner with respect to the gate electrode Gn1 using photolithography and ion implantation. The n-type extension region 14 is a semiconductor region and can be formed by introducing an n-type impurity such as P or As into the semiconductor substrate 1.

  Next, after an insulating film is formed on the main surface of the semiconductor substrate 1, the gate electrode Gp1 in the pMIS formation region and the gate in the nMIS formation region are anisotropically etched using a dry etching method. Sidewalls 8 are formed on the respective side walls of the electrode Gn1.

  Next, a p-type diffusion region 10 is formed in the pMIS formation region in a self-aligned manner with respect to the gate electrode Gp1 and the sidewall 8 by using a photolithography method and an ion implantation method. The p-type diffusion region 10 is a semiconductor region and can be formed by introducing a p-type impurity such as B into the semiconductor substrate 1. Similarly, an n-type diffusion region 15 is formed in the nMIS formation region in a self-aligned manner with respect to the gate electrode Gn1 and the sidewall 8 by using a photolithography method and an ion implantation method. The n-type diffusion region 15 is a semiconductor region and can be formed by introducing an n-type impurity such as P or As into the semiconductor substrate 1.

Next, heat treatment is performed on the semiconductor substrate 1. The heat treatment is performed at a temperature of 1000 ° C., for example. By this heat treatment, the p-type impurity introduced into the p-type extension region 9 and the p-type diffusion region 10 in the pMIS formation region is activated, and the n-type extension region 14 and the n-type diffusion region 15 in the nMIS formation region are introduced. Activate type impurities. Al in _{the Al} 2 _{O 3} film 18 is also pMIS formation region in the heat treatment are diffused into the HfO ₂ film 17, in the nMIS formation region La in _La 2 _{O 3} film 22 is diffused into the HfO ₂ film 17.

Next, after an interlayer insulating film 25, for example, a TEOS (tetraethoxysilane (Si (OC ₂ H ₅ ) ₄ )) film is formed on the main surface of the semiconductor substrate 1 by using, for example, a CVD method, this interlayer insulating film The surface of 25 is ground by using, for example, a CMP (Chemical Mechanical Polishing) method, so that the surface is processed to be flat. Subsequently, a connection hole 26 is formed in the interlayer insulating film 25 by using a photolithography method and a dry etching method.

  Next, a Ti / TiN film is formed by sequentially depositing a Ti (titanium) / TiN (titanium nitride) film on the interlayer insulating film 25 including the bottom surface and inner wall of the connection hole 26 by using, for example, a sputtering method. The Ti / TiN film has a so-called barrier function that prevents, for example, a material embedded in the connection hole 26 from diffusing in a later step. Subsequently, a W (tungsten) film is formed on the main surface of the semiconductor substrate 1 so as to bury the inside of the connection hole 26 by using, for example, a CVD method. Subsequently, the plug 27 is formed inside the connection hole 26 by grinding the W film and the Ti / TiN film using, for example, a CMP method.

  Subsequently, a Ti / TiN film, an Al film, and a Ti / TiN film are sequentially formed on the main surface of the semiconductor substrate 1 by using, for example, a sputtering method. Subsequently, these films are processed using a photolithography method and a dry etching method to form the wiring 28. Thereafter, an upper layer wiring is formed, but the description thereof is omitted here. Through the above steps, a CMIS device composed of pMIS 100p and nMIS 100n is substantially completed.

Thus, the metal oxide (Al ₂ O ₃ film 18) in contact with the HfO ₂ film 17 constituting the gate insulating film 5 of the pMIS 100p and the metal oxide (in contact with the HfO ₂ film 17 constituting the gate insulating film 11 of the nMIS 100n). In the process of separately forming the La ₂ O ₃ film 22), since the process using the photolithography method and the dry etching method is performed once, the transistor characteristics of the pMIS 100p or the nMIS 100n due to misalignment in the photolithography process Can be reduced.

Thus, according to the first embodiment, (1) the thickness of the metal gate electrode 6 constituting a part of the gate electrode Gp1 of the pMIS 100p and the metal gate electrode 12 constituting a part of the gate electrode Gn1 of the nMIS 100n. Since the thickness can be determined separately, the threshold voltage can be optimally set. (2) The gate insulating film 5 of the pMIS 100p is composed of a high dielectric film 5h (for example, an HfO ₂ film 17) in which Al is diffused, and the gate insulating film 11 of the nMIS 100n is a high dielectric in which La, Y, Mg, or Sc is diffused. Since the body film 5h (for example, the HfO ₂ film 17) can be used, the threshold voltage can be reduced and optimally set for each. (3) The metal oxide film 5m1 (for example, Al ₂ O ₃ film 18) in contact with the high dielectric film 5h (for example, the HfO ₂ film 17) constituting the gate insulating film 5 of the pMIS 100p and the high that forms the gate insulating film 11 of the nMIS 100n. By performing the separate formation with the metal oxide film 5m2 (for example, the La ₂ O ₃ film 22) in contact with the dielectric film 5h (for example, the HfO ₂ film 17) in one lithography / etching process, overlay deviation can be suppressed, As a result, variations in transistor characteristics can be reduced. A high dielectric film 5h constituting the high dielectric film 5h (e.g. HfO ₂ film 17) and the gate insulating film 11 of nMIS100n constituting the gate insulating film 5 (4) pMIS100p (e.g. HfO ₂ film 17), each suitable for In addition, a process flow in which only the metal oxide films 5m1 and 5m2 are in contact with each other can be provided.

(Embodiment 2)
A CMIS device according to the second embodiment will be described with reference to FIG. The difference from the first embodiment described above is the structure of the gate electrodes of pMIS and nMIS.

  That is, in the first embodiment described above, the metal gate electrode 6 that constitutes a part of the gate electrode Gp1 of the pMIS 100p is composed of two layers of metal films (upper layer metal gate electrode 6U and lower layer metal gate electrode 6D), and the nMIS 100n By forming the metal gate electrode 12 constituting a part of the gate electrode Gn1 with a single layer metal film (upper layer metal gate electrode 6U), the thickness of the metal gate electrode 6 of the pMIS 100p is set to the thickness of the metal gate electrode 12 of the nMIS 100n. It is thicker than the thickness.

  On the other hand, in the second embodiment, as shown in FIG. 14, the metal gate electrode 30 that constitutes a part of the gate electrode Gp2 of the pMIS 200p is constituted by a relatively thick single layer metal film, and the nMIS 200n By forming the metal gate electrode 31 constituting a part of the gate electrode Gn2 from a relatively thin metal film, the thickness of the metal gate electrode 30 of the pMIS 200p is thicker than the thickness of the metal gate electrode 31 of the nMIS 200n. Forming.

  In the first embodiment described above, the thickness of the silicon gate electrode 7 constituting another part of the gate electrode Gp1 of the pMIS 100p and the thickness of the silicon gate electrode 13 constituting another part of the gate electrode Gn1 of the nMIS 100n Are the same thickness, and the height from the main surface of the semiconductor substrate 1 to the upper surface of the gate electrode Gp1 of the pMIS 100p is higher than the height from the main surface of the semiconductor substrate 1 to the upper surface of the gate electrode Gn1 of the nMIS 100n.

  On the other hand, in the second embodiment, as shown in FIG. 14, the thickness of the silicon gate electrode 32 constituting the other part of the gate electrode Gp2 of the pMIS 200p is set to the other part of the gate electrode Gn2 of the nMIS 200n. Is formed to be thinner than the thickness of the silicon gate electrode 33 constituting the height from the main surface of the semiconductor substrate 1 to the upper surface of the gate electrode Gp2 of the pMIS 200p and from the main surface of the semiconductor substrate 1 to the upper surface of the gate electrode Gn2 of the nMIS 200n. The height is the same.

Next, a method for manufacturing a CMIS device according to the second embodiment will be described in the order of steps with reference to FIGS. 15 to 20 are cross-sectional views of main parts of the CMIS device. An SiO ₂ film 16, an HfO ₂ film 17, an Al ₂ O ₃ film 18, a TiN film 19, a La ₂ O ₃ film 22, and a TiN film 23 are formed on the main surface of the semiconductor substrate 1 in the pMIS formation region, A manufacturing process until the SiO ₂ film 16, the HfO ₂ film 17, the La ₂ O ₃ film 22, and the TiN film 23 are formed on the main surface of the semiconductor substrate 1 in the nMIS formation region (FIG. 2 in the first embodiment described above). Since the steps described with reference to FIG. 9 are the same as those in the first embodiment, the description thereof is omitted.

  Following the manufacturing process described with reference to FIG. 9 in the first embodiment, as shown in FIG. 15, a polycrystalline Si film (first silicon gate electrode material) is formed on the TiN film 23 by using, for example, the CVD method. ) 34 is formed. The thickness of the polycrystalline Si film 34 is, for example, about 100 nm.

Next, as shown in FIG. 16, until the TiN film 19 in the pMIS formation region is exposed, the polycrystalline Si film 34, the TiN film 23, and the La ₂ O ₃ film 22 are ground using, for example, the CMP method. Thus, the SiO ₂ film 16, the HfO ₂ film 17, the Al ₂ O ₃ film 18, and the TiN film 19 are left on the main surface of the semiconductor substrate 1 in the pMIS formation region, and on the main surface of the semiconductor substrate 1 in the nMIS formation region. The SiO ₂ film 16, the HfO ₂ film 17, the La ₂ O ₃ film 22, the TiN film 23, and the polycrystalline Si film 34 are left. Here, the height from the main surface of the semiconductor substrate 1 in the pMIS formation region to the upper surface of the TiN film 19 is the same as the height from the main surface of the semiconductor substrate 1 in the nMIS formation region to the upper surface of the polycrystalline Si film 34.

  Next, as shown in FIG. 17, a polycrystalline Si film (second silicon gate electrode material) 35 is formed on the main surface of the semiconductor substrate 1 by using, for example, a CVD method. The thickness of the polycrystalline Si film 35 is, for example, about 50 nm. The polycrystalline Si film 35 in the pMIS formation region and the polycrystalline Si films 34 and 35 in the nMIS formation region are made of polycrystalline Si showing the same conductivity by introducing n-type impurities or p-type impurities. However, the polycrystalline Si film 35 in the pMIS formation region is made of polycrystalline Si showing p-type conductivity, and the polycrystalline Si films 34 and 35 in the nMIS formation region are made of polycrystalline Si showing n-type conductivity. You may comprise by.

Next, heat treatment is performed on the semiconductor substrate 1. The heat treatment is performed at a temperature of 1000 ° C., for example. This heat treatment diffuses Al in _{the Al} 2 _{O 3} film 18 is pMIS formation region on the HfO ₂ film 17, in the nMIS formation region La in _La 2 _{O 3} film 22 is diffused into the HfO ₂ film 17.

Here, in the first embodiment described above, _La 2 _{O 3} film 22 in the pMIS formation region is sandwiched between the TiN film 19 and the TiN film 23, and La in _La 2 _{O 3} film 22 by heat treatment It diffuses into the TiN film 19 and the TiN film 23. However, in the second embodiment, since the La ₂ O ₃ film 22 is not formed in the pMIS formation region, there is no concern about diffusion of La due to the heat treatment in the pMIS formation region as in the first embodiment.

In the first embodiment, the heat treatment for diffusing Al or La into the HfO ₂ film 17 is performed after the TiN film (upper TiN film) 23 is formed on the main surface (entire surface) of the semiconductor substrate 1. Although performed (the process described with reference to FIG. 10 described above), in the second embodiment, the heat treatment is performed on the main surface (entire surface) of the semiconductor substrate 1 with a polycrystalline Si film (upper polycrystalline Si film). After forming 35. In the second embodiment, the TiN film 23 is formed on the main surface (entire surface) of the semiconductor substrate 1, and the polycrystalline Si film 34 is further formed thereon (described with reference to FIG. 15 described above). Step) Thereafter, until the TiN film 19 in the pMIS formation region is exposed, the polycrystalline Si film 34, the TiN film 23, and the La ₂ O ₃ film 22 are ground by, eg, CMP (described with reference to FIG. 16 described above). Process). If the heat treatment is performed before this grinding step, the La ₂ O ₃ film 22 cannot be completely removed, and the La ₂ O ₃ film 22 remains in part. If the La ₂ O ₃ film 22 remains in part, etching defects (for example, changes in the etching rate) due to the remaining La and O described in the first embodiment will occur. Therefore, in order to completely remove the La ₂ O ₃ film 22, the heat treatment is performed after the step of grinding the polycrystalline Si film 34, the TiN film 23, and the La ₂ O ₃ film 22.

  Next, as shown in FIG. 18, the gate insulating film 5 and the gate electrode Gp2 are formed in the pMIS formation region by using the photolithography method and the dry etching method, and the gate insulating film 11 and the gate electrode Gn2 are formed in the nMIS formation region. Form.

The gate insulating film 5 formed in the pMIS formation region includes an SiO ₂ film 16 (oxide film 5s), an Al diffused HfO ₂ film 17 (high dielectric film 5h), and an Al ₂ O ₃ film 18 (metal oxide film 5m1). The gate electrode Gp2 is composed of the metal gate electrode 30 and the silicon gate electrode 32. Further, the metal gate electrode 30 is composed of the TiN film 19, and the silicon gate electrode 32 is composed of the polycrystalline Si film 35.

The gate insulating film 11 formed in the nMIS formation region includes a SiO ₂ film 16 (oxide film 5s), a La diffused HfO ₂ film 17 (high dielectric film 5h), and a La ₂ O ₃ film 22 (metal oxide film 5m2). The gate electrode Gn2 is composed of a metal gate electrode 31 and a silicon gate electrode 33. Further, the metal gate electrode 31 is composed of a TiN film 23, and the silicon gate electrode 33 is composed of polycrystalline Si films 34 and 35.

  The metal gate electrode 30 constituting a part of the gate electrode Gp2 formed in the pMIS formation region is formed by the TiN film 19, and the metal gate electrode 31 constituting a part of the gate electrode Gn2 formed in the nMIS formation region is The TiN film 19 is formed by a TiN film 23 formed in a different process. Therefore, since the thicknesses of the TiN film 19 and the TiN film 23 can be set different from each other, the thickness of the metal gate electrode 30 constituting a part of the gate electrode Gp2 formed in the pMIS formation region and The thickness of the metal gate electrode 31 constituting a part of the gate electrode Gn1 formed in the nMIS formation region can be set to an optimum value in consideration of the work function. In the second embodiment, the thickness of the metal gate electrode 30 constituting a part of the gate electrode Gp2 formed in the pMIS formation region is about 15 to 20 nm and a part of the gate electrode Gn2 formed in the nMIS formation region. The thickness of the metal gate electrode 31 that constitutes is set to about 2 to 5 nm, and the thicknesses of the metal gate electrodes 31 are set to different values by about 10 to 18 nm.

In the photolithography method, a laminated film composed of the polycrystalline Si film 35, the TiN film 19, the Al ₂ O ₃ film 18, the HfO ₂ film 17, and the SiO ₂ film 16 is formed in the pMIS formation region, and the polycrystalline silicon film is formed in the nMIS formation region. Thus, a resist pattern is formed when a laminated film composed of the films 34 and 35, the TiN film 23, the La ₂ O ₃ film 22, the HfO ₂ film 17, and the SiO ₂ film 16 is sequentially processed by dry etching. This resist pattern is formed by first applying a photoresist film on the main surface of the semiconductor substrate 1 and then exposing and developing the photoresist film. If there is a difference in level between the upper surface of the stacked film in the pMIS formation region and the upper surface of the stacked film in the nMIS formation region, a resolution failure or the like due to a difference in focal length occurs. In the second embodiment, the pMIS formation region Since there is no difference in level between the upper surface of the laminated film and the upper surface of the laminated film in the nMIS formation region, a fine resist pattern with good resolution can be formed. Therefore, the gate electrode Gp2 of the pMIS 200p and the gate electrode Gn2 of the nMIS 200n can be finely processed with good reproducibility.

  Next, as shown in FIG. 19, using the photolithography method and the ion implantation method, the p-type extension region 9 is formed in the pMIS formation region in a self-aligned manner with respect to the gate electrode Gp2. The p-type extension region 9 is a semiconductor region and can be formed by introducing a p-type impurity such as B into the semiconductor substrate 1. Similarly, the n-type extension region 14 is formed in the nMIS formation region in a self-aligned manner with respect to the gate electrode Gn2 by using a photolithography method and an ion implantation method. The n-type extension region 14 is a semiconductor region and can be formed by introducing an n-type impurity such as P or As into the semiconductor substrate 1.

  Next, after forming an insulating film on the main surface of the semiconductor substrate 1, the insulating film is anisotropically etched using a dry etching method, whereby the gate electrode Gp2 in the pMIS forming region and the gate in the nMIS forming region are formed. Sidewalls 8 are formed on the respective side walls of the electrode Gn2.

  Next, a p-type diffusion region 10 is formed in the pMIS formation region in a self-aligned manner with respect to the gate electrode Gp2 and the sidewall 8 by using a photolithography method and an ion implantation method. The p-type diffusion region 10 is a semiconductor region and can be formed by introducing a p-type impurity such as B into the semiconductor substrate 1. Similarly, an n-type diffusion region 15 is formed in the nMIS formation region in a self-aligned manner with respect to the gate electrode Gn2 and the sidewall 8 by using a photolithography method and an ion implantation method. The n-type diffusion region 15 is a semiconductor region and can be formed by introducing an n-type impurity such as P or As into the semiconductor substrate 1.

Next, heat treatment is performed on the semiconductor substrate 1. The heat treatment is performed at a temperature of 1000 ° C., for example. By this heat treatment, the p-type impurity introduced into the p-type extension region 9 and the p-type diffusion region 10 in the pMIS formation region is activated, and the n-type extension region 14 and the n-type diffusion region 15 in the nMIS formation region are introduced. Activate type impurities. Al in _{the Al} 2 _{O 3} film 18 is also pMIS formation region in the heat treatment are diffused into the HfO ₂ film 17, in the nMIS formation region La in _La 2 _{O 3} film 22 is diffused into the HfO ₂ film 17.

  Next, after an interlayer insulating film 25 is formed on the main surface of the semiconductor substrate 1 by using, for example, a CVD method, the surface of the interlayer insulating film 25 is processed to be flat by grinding, for example, by using the CMP method. .

  Next, a connection hole 26 is formed in the interlayer insulating film 25 by using a photolithography method and a dry etching method. In the photolithography method, a resist pattern is formed when the interlayer insulating film 25 is processed by dry etching. Similar to the formation of the gate electrode Gp2 of the pMIS 200p and the gate electrode Gn2 of the nMIS 200n described above, if there is a difference in height on the surface of the interlayer insulating film 25, a resolution failure due to a difference in focal length occurs. Then, since the surface of the interlayer insulating film 25 is flat and has no height difference, a fine resist pattern with good resolution can be formed.

  Further, the height from the main surface of the semiconductor substrate 1 in the pMIS formation region to the upper surface of the gate electrode Gp2 (upper surface of the silicon gate electrode 32) and the upper surface of the gate electrode Gn2 from the main surface of the semiconductor substrate 1 in the nMIS formation region (silicon gate electrode). Therefore, the thickness of the interlayer insulating film 25 on the gate electrode Gp2 of the pMIS 200p is the same as the thickness of the interlayer insulating film 25 on the gate electrode Gn2 of the nMIS 200n. Therefore, the connection hole 26 reaching the gate electrode Gp2 of the pMIS 200p and the connection hole 26 reaching the gate electrode Gn2 of the nMIS 200n can be formed in the same shape, and the fine connection hole 26 is formed in the pMIS formation region and the nMIS formation region. It can be formed with good reproducibility.

  Thereafter, as shown in FIG. 20, the CMIS device is substantially completed by forming the plug 27, the wiring 28, and the like in the same manner as in the first embodiment.

As described above, according to the second embodiment, the metal gate electrode 30 constituting a part of the gate electrode Gp2 in the pMIS formation region is formed of the single layer TiN film 19, and as in the first embodiment described above, The influence of La diffusion, which is a concern due to the insertion of the La ₂ O ₃ film 22 between the metal gate electrodes 6, can be completely eliminated. Therefore, in the pMIS formation region, there is no risk that the effect of diffusion of Al into the HfO ₂ film 17 is offset by the diffusion of La.

  Further, since the height from the main surface of the semiconductor substrate 1 to the upper surface of the gate electrode Gp2 of the pMIS 200p is the same as the height from the main surface of the semiconductor substrate 1 to the upper surface of the gate electrode Gn2 of the nMIS 200n, the gate electrode Gp2 of the pMIS 200p. When the gate electrode Gn2 of the nMIS 200n is formed by a photolithography method and a dry etching method, a fine resist pattern with high resolution can be formed in the photolithography process, so that the gate electrode Gp2 of the fine pMIS 200p with good reproducibility and The gate electrode Gn2 of the nMIS 200n can be formed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  INDUSTRIAL APPLICABILITY The present invention can be widely used in manufacturing industries for manufacturing semiconductor devices, particularly semiconductor devices having an hp of 32 nm or less.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation | separation 3 N-type well 4 P-type well 5 Gate insulating film 5h High dielectric film 5m1, 5m2 Metal oxide film 5s Oxide film 6 Metal gate electrode 6D Lower metal gate electrode 6U Upper metal gate electrode 7 Silicon gate electrode 8 Sidewall 9 p-type extension region 10 p-type diffusion region 11 gate insulating film 12 metal gate electrode 13 silicon gate electrode 14 n-type extension region 15 n-type diffusion region 16 SiO ₂ (silicon oxide) film 17 HfO ₂ (hafnium oxide) Film 18 Al ₂ O ₃ (aluminum oxide) film 19 TiN (titanium nitride) film 20 SiN (silicon nitride) film 21 Resist pattern 22 La ₂ O ₃ (lanthanum oxide) film 23 TiN (titanium nitride) film 24 Polycrystalline Si ( Silicon) film 25 interlayer insulating film 26 connection hole 27 plug 28 wiring 30 1 metal gate electrodes 32 and 33 a silicon gate electrodes 34, 35 of polycrystalline Si (silicon) film 100n, 200n n-channel type MISFET
100p, 200p p-channel MISFET
Gn1, Gn2, Gp1, Gp2 Gate electrode SD Source / drain region

Claims (20)

A method for manufacturing a semiconductor device, comprising forming a p-channel field effect transistor in a first region of a semiconductor substrate and forming an n-channel field effect transistor in a second region of the semiconductor substrate,
(A) forming a high dielectric film having a dielectric constant higher than that of SiO ₂ on the main surface of the semiconductor substrate;
(B) forming a first metal oxide film containing a first metal on the high dielectric film;
(C) forming a first metal gate electrode material having a first thickness on the first metal oxide film;
(D) removing the first metal gate electrode material and the first metal oxide film in the second region;
(E) after the step (d), forming a second metal oxide film containing a second metal on the main surface of the semiconductor substrate;
(F) forming a second metal gate electrode material having a second thickness on the second metal oxide film;
(G) After the step (f), the semiconductor substrate is subjected to a heat treatment to diffuse the first metal into the high dielectric film in the first region, and to the high dielectric film in the second region. Diffusing the second metal;
(H) After the step (g), a step of forming a silicon gate electrode material on the main surface of the semiconductor substrate;
(I) The silicon gate electrode material, the second metal gate electrode material, the first metal gate electrode material, the first metal oxide film, and the high dielectric film in which the first metal is diffused in the first region A gate electrode made of the silicon gate electrode material, the second metal gate electrode material, and the first metal gate electrode material of the p-channel field effect transistor, and the first metal oxide film. And forming a gate insulating film made of the high dielectric film in which the first metal is diffused,
Processing the laminated film composed of the silicon gate electrode material, the second metal gate electrode material, the second metal oxide film, and the high dielectric film in which the second metal is diffused in the second region; A gate electrode made of the silicon gate electrode material and the second metal gate electrode material of the channel type field effect transistor, the second metal oxide film, and a gate insulating film made of the high dielectric film in which the second metal is diffused. Forming, and
Including
The method of manufacturing a semiconductor device, wherein the second thickness of the second metal gate electrode material is thinner than the first thickness of the first metal gate electrode material. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the high dielectric film is an HfO ₂ film, an HfON film, an HfSiO film, or an HfSiOn film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal is Al.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second metal is La, Y, Mg, or Sc. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second metal gate electrode _{material, TiN, TaN, TaSiN, TiAlN} , HfN, Ni x Si 1-x, PtSi, Ni x Ta 1-x Si , Ni _x Pt _1-x Si, HfSi, WSi, Ir _x Si _1-x , TaGe, TaCx, Mo, or W.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second metal is diffused in the first and second metal gate electrode materials.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal oxide film has a thickness of 0.5 nm.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second metal oxide film has a thickness of 0.1 nm to 0.3 nm. 2. The method of manufacturing a semiconductor device according to claim 1, wherein before the step (a),
(J) forming a SiO ₂ film on the main surface of the semiconductor substrate;
A method for manufacturing a semiconductor device, further comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (d) includes:
(D1) forming an insulating film on the first metal gate electrode material;
(D2) removing the insulating film in the second region using a photolithography method and a dry etching method;
(D3) removing the first metal gate electrode material in the second region using a wet etching method;
(D4) removing the insulating film in the first region using a wet etching method;
(D5) removing the first metal oxide film in the second region using a wet etching method;
A method for manufacturing a semiconductor device, further comprising: A method for manufacturing a semiconductor device, comprising forming a p-channel field effect transistor in a first region of a semiconductor substrate and forming an n-channel field effect transistor in a second region of the semiconductor substrate,
(A) forming a high dielectric film having a dielectric constant higher than that of SiO ₂ on the main surface of the semiconductor substrate;
(B) forming a first metal oxide film containing a first metal on the high dielectric film;
(C) forming a first metal gate electrode material having a first thickness on the first metal oxide film;
(D) removing the first metal gate electrode material and the first metal oxide film in the second region;
(E) after the step (d), forming a second metal oxide film containing a second metal on the main surface of the semiconductor substrate;
(F) forming a second metal gate electrode material having a second thickness on the second metal oxide film;
(G) forming a first silicon gate electrode material on the second metal gate electrode material;
(H) grinding the first silicon gate electrode material until an upper surface of the first metal gate electrode material in the first region is exposed;
(I) After the step (h), forming a second silicon gate electrode material on the main surface of the semiconductor substrate;
(J) After the step (i), the semiconductor substrate is subjected to a heat treatment to diffuse the first metal into the high dielectric film in the first region, and to the high dielectric film in the second region. Diffusing the second metal;
(K) Processing a laminated film including the second silicon gate electrode material, the first metal gate electrode material, the first metal oxide film, and the high dielectric film in which the first metal is diffused in the first region. The gate electrode made of the second silicon gate electrode material and the first metal gate electrode material of the p-channel field effect transistor, and the high dielectric material in which the first metal oxide film and the first metal are diffused Forming a gate insulating film made of a film,
From the second silicon gate electrode material, the first silicon gate electrode material, the second metal gate electrode material, the second metal oxide film, and the high dielectric film in which the second metal is diffused in the second region The laminated film is processed to form the second silicon gate electrode material of the n-channel field effect transistor, the gate electrode made of the first silicon gate electrode material and the second metal gate electrode material, and the second metal oxide. Forming a gate insulating film made of the high dielectric film in which the film and the second metal are diffused;
Including
The method of manufacturing a semiconductor device, wherein the second thickness of the second metal gate electrode material is thinner than the first thickness of the first metal gate electrode material. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the high dielectric film is an HfO ₂ film, an HfON film, an HfSiO film, or an HfSiOn film.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the first metal is Al.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the second metal is La, Y, Mg, or Sc. The method of manufacturing a semiconductor device according to claim 11, wherein the first and second metal gate electrode _{material, TiN, TaN, TaSiN, TiAlN} , HfN, Ni x Si 1-x, PtSi, Ni x Ta 1-x Si , Ni _x Pt _1-x Si, HfSi, WSi, Ir _x Si _1-x , TaGe, TaCx, Mo, or W.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the first metal oxide film has a thickness of 0.5 nm.   12. The method of manufacturing a semiconductor device according to claim 11, wherein a thickness of the second metal oxide film is 0.1 nm to 0.3 nm.   12. The method of manufacturing a semiconductor device according to claim 11, wherein a height from a main surface of the semiconductor substrate in the first region to an upper surface of a gate electrode of the p-channel field effect transistor, and a height of the semiconductor substrate in the second region. A method of manufacturing a semiconductor device, wherein a height from a main surface to an upper surface of a gate electrode of the n-channel field effect transistor is the same. 12. The method for manufacturing a semiconductor device according to claim 11, wherein before the step (a),
(K) forming a SiO ₂ film on the main surface of the semiconductor substrate;
A method for manufacturing a semiconductor device, further comprising: 12. The method of manufacturing a semiconductor device according to claim 11, wherein the step (d) includes:
(D1) forming an insulating film on the first metal gate electrode material;
(D2) removing the insulating film in the second region using a photolithography method and a dry etching method;
(D3) removing the first metal gate electrode material in the second region using a wet etching method;
(D4) removing the insulating film in the first region using a wet etching method;
(D5) removing the first metal oxide film in the second region using a wet etching method;
A method for manufacturing a semiconductor device, further comprising:

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