JP2009194352A - Semiconductor device fabrication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify a fabrication method of a metal gate CMOS using a high-dielectric gate insulating film and a metal gate electrode. <P>SOLUTION: A silicon film 7 is formed on a high-dielectric gate insulating film 6, and only a silicon film 7 of PMOS region is nitrided to substitute an SiN film 9. After La(O) film 11 as a cap film and a W film 12 of a metal electrode are formed on a silicon film 7 on an NMOS region and on a SiN film 9 on a PMOS region; and then heat treated to diffuse La elements of the La(O) film 11 into high-dielectric gate insulating film in NMOS region. Here, in the PMOS region, diffusion of the La elemensts is blocked by the SiN film 9. As a result, the NMOSFET and the PMOSFET are formed to be readily separated. Furthermore, if it the high-dielectric gate insulating film 6 tends to be nitrided, the silicon film 7 is discarded, and only the high-dielectric gate insulating film 6 in the PMOS region may be selectively nitrided by nitriding treatment. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, in particular, a CMOS (Complementary Metal Oxide Semiconductor) transistor and a manufacturing method thereof.

  With the recent miniaturization of large-scale integrated circuits, thinning of the gate insulating film is also required for CMOS transistors. However, when the gate insulating film is made thinner, depletion of the gate electrode cannot be ignored when a polysilicon film is used for the gate electrode. Therefore, in recent years, it has been studied to use a metal electrode as the gate electrode. In order to realize a low threshold voltage in both the NMOS transistor and the PMOS transistor, gates using materials having different work functions are used. So-called dual gate formation for forming electrodes has been studied.

  In addition, a proposal has been made to promote electrical thinning while using a high dielectric constant insulating film such as Hf oxide as a gate insulating film to increase the physical film thickness and suppress leakage current. ing. However, even when a high dielectric constant insulating film is used for the gate insulating film, when polysilicon is used for the gate electrode, there is a problem that the polysilicon gate electrode is depleted and the electrical film thickness increases. Therefore, attempts have been made to use a combination of a high dielectric constant gate insulating film and a metal gate.

An insulating film containing hafnium (Hf) or zirconium (Zr) is promising as a high dielectric constant gate insulating film of a next-generation MOSFET. For example, a hafnium silicate nitride film (HfSiON) film is used as a high dielectric constant gate insulating film. In a CMOS transistor using a TFT, because of a phenomenon called pinning, even if materials having different work functions are used, the flat band voltage (Vfb) cannot be adjusted to the band edge and becomes near the mid gap, resulting in a low threshold. There is a problem that the value voltage cannot be realized. Therefore, in order to bring Vfb of the NMOSFET to the band edge, it is effective to use a cap film such as a lanthanoid (see, for example, Patent Document 1). However, in order to create a cap film separately in the NMOS region and the PMOS region, there has been a problem that complicated and many steps are required, such as repeating steps such as film formation, patterning, and etching a plurality of times.
JP 2002-270821

The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a metal gate CMOS using a high dielectric constant gate insulating film and a metal gate electrode that can simplify the manufacturing process.

  In order to achieve the above object, a method for manufacturing a semiconductor device according to an aspect of the present invention includes a step of forming an N-type semiconductor region and a P-type semiconductor region on a main surface of a substrate, and the N-type semiconductor region and the P-type semiconductor. Forming a high dielectric constant gate insulating film on the region; forming a silicon film on the high dielectric constant gate insulating film; and nitriding the silicon film on the N-type semiconductor region to form a silicon nitride film A step of replacing, a step of forming a metal gate electrode on the silicon film of the P-type semiconductor region and the silicon nitride film of the N-type semiconductor region via a cap film, and the constituent elements of the cap film And a heating step of introducing into the high dielectric constant gate insulating film in the N-type semiconductor region.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming an N-type semiconductor region and a P-type semiconductor region on a main surface of a substrate; and a high dielectric constant on the N-type semiconductor region and the P-type semiconductor region. Forming a gate insulating film; nitriding the high dielectric constant gate insulating film on the N-type semiconductor region and replacing it with a nitrided high dielectric constant gate insulating film; and the high dielectric constant of the P-type semiconductor region Forming a metal gate electrode on the gate insulating film and on the nitrided high dielectric constant gate insulating film of the N-type semiconductor region through a cap film; and forming a constituent element of the cap film in the high-level of the P-type semiconductor region And a heating step for introducing the dielectric constant into the gate insulating film.

  Furthermore, a method for manufacturing a semiconductor device according to another aspect of the present invention includes a step of forming an N-type semiconductor region and a P-type semiconductor region on a main surface of a substrate, and a high dielectric constant on the N-type semiconductor region and the P-type semiconductor region. Forming a gate insulating film; forming a silicon nitride film on the high dielectric constant gate insulating film on the N-type semiconductor region; on the high dielectric constant gate insulating film in the P-type semiconductor region; and Forming a metal gate electrode on the silicon nitride film in the N-type semiconductor region via a cap film, and heating for introducing the constituent elements of the cap film into the high-dielectric-constant gate insulating film in the P-type semiconductor region And a process.

  According to the present invention, a metal gate CMOS manufacturing method using a high dielectric constant gate insulating film and a metal gate electrode can be simplified.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1 and 2 are cross-sectional views showing a manufacturing process of the CMOSFET according to the first embodiment of the present invention.

  First, as shown in FIG. 1A, a PMOSFET formation region (hereinafter simply referred to as a PMOS region) and an NMOSFET formation region (hereinafter simply referred to as an NMOS) are formed on a main surface of a silicon (Si) substrate 1 by a known method. An element isolation region 2 having an STI (Shallow Trench Isolation) structure for defining a region is formed. The element isolation region 2 is formed using, for example, the following method. First, a silicon nitride film serving as a mask is deposited on the main surface of the silicon substrate 1 via a buffer film. Next, the silicon nitride film and the buffer film are patterned using a resist pattern transfer method to form a mask, and the silicon substrate 1 is etched to a predetermined depth using this mask to form a trench. Next, after removing the resist, a silicon oxide film is deposited on the entire main surface of the silicon substrate 1, and then planarized by CMP (Chemical Mechanical Polishing) or the like, and the silicon oxide film is buried in the trench, and then used as a mask. The element isolation region 2 is formed by removing the used silicon nitride film and buffer film.

Thereafter, a P well diffusion layer 3 as an NMOS region and an N well diffusion layer 4 as a PMOS region are formed by a known method. Next, as shown in FIG. 1B, the main surface of the silicon substrate 1 is oxidized by a heat treatment or the like in an oxygen atmosphere to form a silicon oxide (SiO ₂ ) film 5 in the PMOS region and the NMOS region.

As shown in FIG. 1 (c), following the formation of the SiO ₂ film 5, MOCVD method using tetradimethylamino silicon and tetra diethylamino hafnium HfSiO film on the SiO ₂ film 5 as the high dielectric constant gate insulating film 6 Further, a very thin silicon film 7 is formed on the HfSiO film 6 by using, for example, an ALD method or a sputtering method.

  The thickness of the silicon film 7 may be a thickness that can prevent diffusion of a lanthanum element, which will be described later, when it is nitrided, specifically about 0.5 nm to 1.0 nm. Further, if the thickness does not affect the characteristics of the device, it may be formed thicker than that. Note that in the case where film formation is performed by a sputtering method, it is desirable to perform film formation after sufficient conditions are set.

  Thereafter, as shown in FIG. 1D, the NMOS region is masked with a resist 8 using a photolithography method or the like, and as shown in FIG. 1E, the HfSiO film in the PMOS region is formed by, for example, plasma nitriding. 6 and the silicon film 7 are nitrided and replaced with a silicon nitride (SiN) film. In this embodiment, since the silicon film 7 in the NMOS region is masked by the resist 8, the HfSiO film 6 and the silicon film 7 in the PMOS region can be plasma-nitrided at a low temperature at which the resist does not deteriorate. As a result, the SiN film 9 and the HfSiON film 10 are formed in the PMOS region, and the NMOS region is covered with the resist 8, so that the silicon film 7 remains as it is. Note that the resist 8 is an organic substance, and it is considered that the characteristics do not change so much by performing plasma nitriding, so that the resist 8 is hardly adversely affected.

  Next, as shown in FIG. 2A, the resist 8 is removed with an organic solvent or the like, and a lanthanum (La) film as a cap film is formed on the silicon film 7 in the NMOS region and the SiN film 9 in the PMOS region. . This La film is formed to lower the threshold Vth of the NMOSFET. As the cap film, any one of yttrium, terbium, erbium, ytterbium, magnesium, yttrium, scandium, other lanthanoids, actinoids, alkaline earth metals, and rare earth metals may be used instead of lanthanum. Usually, the La film is slightly oxidized during the process, and exists in a state of becoming a La (O) film 11 containing a small amount of oxygen. Similarly, when magnesium is used instead of lanthanum, it is considered that it is present in a slightly oxidized state.

Subsequently, as shown in FIG. 2B, a W film 12 as a metal electrode is formed on the La (O) film 11, and a TiN film 13 as a barrier film is formed on the W film 12. In the NMOS region, the La element contained in the La (O) film 11 diffuses to the vicinity of the interface between the silicon substrate 1 and the SiO ₂ film 5 by performing a heating process after the TiN film 13 is formed. Since the SiN film 9 blocks the diffusion of the La element, the La element does not diffuse in the interface direction between the silicon substrate 1 and the SiO ₂ film 5. In this heating step, as shown in FIG. 2C, in the NMOS region, the W film 12 and the silicon film 7 react and the W film 12 and the silicon film 7 are replaced with the WSi film 14. In the PMOS region, the W film 12, the La (O) film 11, the SiN film 9, and the HfSiON film 10 exist as they are.

  Here, the reason why the SiN film 9 blocks the diffusion of the La element will be described below. For example, when the La (O) film 11 is brought into contact with the SiN film 9, a reaction as shown in the following formula (1) occurs in terms of thermodynamics. Whether this reaction proceeds depends on whether the Gibbs free energy difference (ΔG) is negative.

SiN + La (O) = La (O) N + Si + ΔG Equation (1)
As shown in FIG. 3, ΔG in the reaction of the formula (1) becomes a positive value at the temperature of the heating process performed in normal semiconductor device manufacturing, and therefore the reaction of the formula (1) does not proceed to the right side. Accordingly, since the La element of the La (O) film 11 cannot pass through the SiN film 9, the diffusion of the La element toward the interface of the silicon substrate 1 in the PMOS region is suppressed.

  Thereafter, as shown in FIG. 2 (d), a polycrystalline silicon film 15 is deposited as a gate material on the TiN film as the barrier metal 13, and after ion implantation is performed on the polycrystalline silicon film 15, photolithography is performed. The polycrystalline silicon film 15, the TiN film 13, the WSi film 14, or the W film 12 are etched in order to form the gate electrode 16. Further, using the gate electrode 16 as a mask, the La (O) film 11, the HfSiON film 10, the SiN film 9, the HfSiO film 6, and the SiO2 film 5 are sequentially etched to form the gate insulating film 17. At this time, extension ion implantation and crystal recovery annealing may be performed as necessary.

  Here, the La (O) film 11 in the PMOS region is present as it is as a part of the gate structure, but may be present because it does not adversely affect the device characteristics.

  Next, as shown in FIG. 2E, after a liner film made of SiN is deposited on the entire upper surface of the silicon substrate 1, TEOS (Tetraethoxysilane) is deposited on the SiN film, and anisotropic etching is performed. The TEOS and SiN films are etched to form a SiN film 18 and a TEOS film 19 that become gate sidewalls. Subsequently, ion implantation of conductive impurities and activation annealing are performed on the silicon substrate 1 using the gate electrode 16 as a mask to form a source / drain diffusion layer 20.

According to the above-described embodiment, the following effects can be obtained. That is, after the silicon film 7 is formed on the high dielectric constant gate insulating film 6, nitriding is performed to replace the silicon film on the PMOS region with the SiN film 9 while leaving the silicon film 7 on the NMOS region as it is. Thereby, in the NMOS region, the La element contained in the La (O) film 11 diffuses to near the interface between the silicon substrate 1 and the SiO ₂ film 5, but in the PMOS region, the SiN film 9 diffuses the La element. Therefore, the La element does not diffuse up to the interface between the silicon substrate 1 and the SiO ₂ film 5. Therefore, an increase in the number of manufacturing steps can be suppressed and the flat band voltage suitable for each of the NMOSFET and the PMOSFET can be adjusted.

  In the present embodiment, the W film 12 is used as the metal electrode, and a TiN film is formed as the barrier metal 13 in order to prevent the reaction between the polycrystalline silicon film 15 formed on the metal electrode and the W film 12. The metal electrode may use transition metals such as Ta, their silicides, nitrides, carbides, etc., and the barrier metal 13 need not be formed as long as it does not react with the polycrystalline silicon film 15. The barrier metal 13 is not limited to TiN, and any other metal may be used as long as it can prevent a reaction between a metal electrode such as TaC or Ru and polycrystalline silicon.

  In this embodiment, in order to diffuse the La element to the vicinity of the interface between the silicon substrate and the gate insulating film, the heat treatment is performed in the process shown in FIG. 2B. However, the heating during the formation of the source and drain diffusion layers is performed. Since the phase separation and diffusion occur sufficiently even in the processing step, they may be omitted.

  In addition, in this embodiment, a high dielectric constant insulating film having a dielectric constant higher than that of a silicon oxide film or a silicon oxynitride film is used as the high dielectric constant gate insulating film, and hafnium silicidation containing a metal element (for example, Hf) is used. Although a film is used, a hafnium silicate nitride film, a zirconium oxide film, a hafnium oxide film, a hafnium zirconium oxide film, a hafnium zirconium oxide film, or the like that is difficult to be nitrided or other nitrided or low nitrogen concentration may be used. Good.

  The substrate used in this embodiment may be an SOI (Silicon On Insulator) substrate in addition to a normal silicon substrate.

(Second Embodiment)
In the second embodiment, prior to forming the SiO ₂ film 5 in the first embodiment, a silicon germanium (SiGe) layer is formed in the PMOS region by epitaxial growth or the like. Since the present embodiment is the same as the first embodiment except that a SiGe layer is formed, the same reference numerals are given to the same parts as those in the first embodiment, and the description thereof is omitted. .

As shown in FIG. 4A, the SiGe layer 21 is formed before the SiO ₂ film 5 is formed. The subsequent steps are the same as those in the first embodiment. As shown in FIG. 4B, after forming the gate electrode 16, ions of conductive impurities are formed on the silicon substrate 1 using the gate electrode 16 as a mask. Implantation and activation annealing are performed to form the source / drain diffusion layer 20.

By forming the SiGe layer 21, a lower threshold voltage (Vth) than that of a normal silicon channel transistor can be realized. Instead of the SiGe layer 21, an Al ₂ O ₃ layer or an AlN layer may be formed by using MOCVD (Metal Organic Chemical Vapor Deposition) method or ALD (Atomic Layer Deposition) method. Alternatively, an Al ₂ O ₃ layer or an AlN layer may be formed after the SiGe layer is formed.

  According to the present embodiment described above, the following effects are obtained in addition to the effects of the first embodiment described above. That is, by forming the SiGe layer in the PMOS region, it becomes possible to realize a CMOSFET having a lower threshold value as compared with the first embodiment.

(Third embodiment)
FIG. 5 and FIG. 6 are cross-sectional views showing a manufacturing process of a semiconductor device having a CMOSFET according to the third embodiment of the present invention.

  First, as shown in FIG. 5A, an element isolation region 23 having an STI structure for partitioning a PMOS region and an NMOS region is formed on the main surface of the silicon substrate 22 by a known method. Thereafter, a P well diffusion layer 24 which is an NMOS region and an N well diffusion layer 25 which is a PMOS region are formed by a known method.

Next, as shown in FIG. 5B, the main surface of the silicon substrate 22 is oxidized by a heat treatment or the like in an oxygen atmosphere to form a silicon oxide (SiO ₂ ) film 26 in the PMOS region and the NMOS region.

As shown in FIG. 5 (c), following the formation of the SiO ₂ film 26, a HfSiON film is deposited by MOCVD or the like as the high dielectric constant gate insulating film 27 on the SiO ₂ film 26. The nitrogen concentration of the HfSiON film 27 can be changed as desired within a range that does not completely block La element diffusion described later.

  Thereafter, as shown in FIG. 5D, the NMOS region is masked with a resist 28 using a photolithography method or the like, and as shown in FIG. 5E, the HfSiON film in the PMOS region is formed by plasma nitridation, for example. 27 is nitrided. As a result, the HfSiON film 27 in the PMOS region is replaced with the nitrided HfSiON film 29, and the NMOS region is covered with the resist 28, so that the HfSiON film 27 remains as it is. The nitrided HfSiON film 29 has a higher nitrogen concentration than the HfSiON film 27.

  Note that the resist 28 is an organic substance, and it is considered that the characteristics do not change so much by performing plasma nitriding, and therefore, the resist 28 is hardly adversely affected.

  Next, as shown in FIG. 6A, the resist 28 is removed with an organic solvent or the like, and a La film as a cap film is formed on the HfSiON film 27 in the NMOS region and the nitrided HfSiON film 29 in the PMOS region. This La film is formed to lower the threshold Vth of the NMOSFET. As the cap film, any one of yttrium, terbium, erbium, ytterbium, magnesium, yttrium, scandium, other lanthanoids, actinoids, alkaline earth metals, and rare earth metals may be used instead of lanthanum. Usually, the La film is slightly oxidized during the process, and exists in a state of becoming a La (O) film 30 containing a small amount of oxygen. Similarly, when magnesium is used instead of lanthanum, it is considered that it is present in a slightly oxidized state.

Subsequently, as shown in FIG. 6B, a W film 31 as a metal electrode is formed on the La (O) film 30, and a TiN film as a barrier metal 32 is formed on the W film 31. In the NMOS region, the La element contained in the La (O) film 30 diffuses to the vicinity of the interface between the silicon substrate 22 and the SiO ₂ film 26 by performing a heating process after the TiN film 32 is formed. Since the nitrided HfSiON film 29 blocks the diffusion of the La element, the La element does not diffuse in the interface direction of the silicon substrate 22.

Thereafter, as shown in FIG. 6C, a polycrystalline silicon film 33 is deposited on the TiN film 32 as a gate material, and after ion implantation is performed on the polycrystalline silicon film 33, the polycrystalline silicon film is formed by photolithography. The gate electrode 34 is formed by etching the film 33, the TiN film 32, and the W film 31 in order. Further, using the gate electrode 34 as a mask, the La (O) film 30, the nitrided HfSiON film 29 or the HfSiON film 27, and the SiO ₂ film 26 are sequentially etched to form a gate insulating film 35. At this time, extension ion implantation and crystal recovery annealing may be performed as necessary.

  Here, the La (O) film 30 in the PMOS region exists as it is as a part of the gate structure, but may not exist because it does not adversely affect the device characteristics.

  Next, as shown in FIG. 6D, after a liner film made of SiN is deposited on the entire upper surface of the silicon substrate 22, TEOS (Tetraethoxysilane) is deposited on the SiN film, and anisotropic etching is performed. The TEOS and SiN films are etched to form a SiN film 36 and a TEOS film 37 serving as gate sidewalls. Subsequently, ion implantation and activation annealing are performed using the gate electrode 34 as a mask to form a source / drain diffusion layer 38.

According to the above-described embodiment, the following effects can be obtained. That is, after the HfSiON film 27 is formed on the PMOS region and the NMOS region, nitriding is performed to replace the HfSiON film on the PMOS region with the nitrided HfSiON film 29 having a high nitrogen concentration while leaving the HfSiON 27 on the NMOS region as it is. Thereby, in the NMOS region, the La element contained in the La (O) film 30 diffuses to the vicinity of the interface between the silicon substrate 22 and the SiO ₂ film 26. However, in the PMOS region, the nitrided HfSiON film 29 is composed of the La element. In order to block the diffusion, La element does not diffuse in the interface direction between the silicon substrate 22 and the SiO ₂ film 26. Therefore, an increase in the number of manufacturing steps can be suppressed, and metal electrodes suitable for the NMOSFET and the PMOSFET can be formed.

  In the present embodiment, since the HfSiO film, which is a high dielectric constant gate insulating film on the PMOS region, is directly and selectively nitrided, the diffusion of La element is blocked in the PMOS region. Compared to the embodiment, the number of manufacturing steps can be further reduced.

  In this embodiment, the W film 31 is used as a metal electrode, and a TiN film is formed as the barrier metal 32 in order to prevent the reaction between the polycrystalline silicon film 33 formed on the metal electrode and the W film 31. The metal electrode may use transition metals such as Ta, their silicides, nitrides, carbides, etc., and the barrier metal 32 may not be formed as long as it does not react with the polycrystalline silicon film 33. Further, the barrier metal 32 is not limited to TiN, and any other metal may be used as long as it can prevent a reaction between a metal electrode such as TaC or Ru and polycrystalline silicon.

  In this embodiment, in order to diffuse the La element to the vicinity of the interface between the silicon substrate and the gate insulating film, the heat treatment is performed in the process shown in FIG. 6B. However, the heating at the time of forming the source and drain diffusion layers is performed. Since the phase separation and diffusion occur sufficiently even in the processing step, they may be omitted.

  In addition, in the present embodiment, a hafnium silicate nitride film is used for the high dielectric constant gate insulating film 27. However, a hafnium silicate film, a zirconium silicate film, a zirconium silicate nitride film, a hafnium zirconium silicate film, and a hafnium zirconium silicate nitride are used. Other materials may be used as long as the nitrogen concentration capable of preventing the diffusion of the cap film can be realized by nitriding the film or the like.

  The substrate used in this embodiment may be an SOI (Silicon On Insulator) substrate in addition to a normal silicon substrate.

(Fourth embodiment)
In the fourth embodiment, prior to the formation of the SiO ₂ film 26 in the third embodiment, a SiGe layer is formed in the PMOS region by epitaxial growth or the like. Since this embodiment is the same as the third embodiment except that a SiGe layer is formed, the same parts as those in the third embodiment are denoted by the same reference numerals, and the description thereof is omitted. .

As shown in FIG. 7A, the SiGe layer 39 is formed before the SiO ₂ film 26 is formed. The subsequent steps are the same as in the third embodiment. As shown in FIG. 7B, after forming the gate electrode 34, ions of conductive impurities are formed on the silicon substrate 22 using the gate electrode 34 as a mask. Implantation and activation annealing are performed to form a source / drain diffusion layer 38.

By forming the SiGe layer 39, a threshold voltage (Vth) lower than that of a normal silicon channel transistor can be realized. Instead of the SiGe layer, an Al ₂ O ₃ layer or an AlN layer may be formed by using MOCVD (Metal Organic Chemical Vapor Deposition) method or ALD (Atomic Layer Deposition) method. Alternatively, an Al ₂ O ₃ layer or an AlN layer may be formed after the SiGe layer is formed.

  According to the present embodiment described above, the following effects can be obtained in addition to the effects of the third embodiment described above. That is, by forming the SiGe layer in the PMOS region, it becomes possible to realize a CMOSFET having a lower threshold value as compared with the third embodiment.

(Fifth embodiment)
Then, the manufacturing method of the semiconductor device concerning the 5th Embodiment of this invention is demonstrated. 8 and 9 are sectional views showing a method for manufacturing a semiconductor device according to the fifth embodiment of the present invention. The manufacturing process will be described below with reference to FIGS.

  First, as shown in FIG. 8A, an element isolation region 41 having an STI structure for partitioning a PMOS region and an NMOS region is formed on the main surface of the silicon substrate 40 by a known method. Thereafter, a P well diffusion layer 42 as an NMOS region and an N well diffusion layer 43 as a PMOS region are formed by a known method.

Next, as shown in FIG. 8B, the main surface of the silicon substrate 40 is oxidized by heat treatment or the like in an oxygen atmosphere to form a silicon oxide (SiO ₂ ) film 44 in the PMOS region and the NMOS region.

Following the formation of the SiO ₂ film 44, as shown in FIG. 8C, a hafnium silicate film (HfSiO) film is deposited on the SiO ₂ film 44 as a high dielectric constant gate insulating film by MOCVD or the like. A hafnium silicate nitriding (HfSiON) film 45 is formed through nitriding and annealing processes on the HfSiO film deposited on the SiO ₂ film 44. The nitrogen concentration of the HfSiON film 45 can be arbitrarily changed within a range that does not completely block the diffusion of La element described later. Further, instead of nitriding the HfSiO film, an HfSiON film may be deposited directly on the SiO ₂ film 44 by MOCVD or the like.

  Subsequently, a very thin silicon nitride (SiN) film 46 is formed on the HfSiON film 45 by using an ALD method, a CVD method or the like. The thickness of the SiN film 46 may be a thickness that can prevent the diffusion of a lanthanum element to be described later, specifically about 0.5 nm to 1.0 nm. Further, if the thickness does not affect the characteristics of the device, it may be formed thicker than that.

  Thereafter, as shown in FIG. 8D, the PMOS region is masked with a resist 47 by using a photolithography method or the like, and as shown in FIG. 8E, for example, the NMOS is formed by selective etching using phosphoric acid. The SiN film 46 in the region is removed.

Next, as shown in FIG. 9A, the resist 47 is removed with an organic solvent or the like, and lanthanum oxidation (La ₂ O ₃ ) as a cap film is formed on the HfSiON film 45 in the NMOS region and the SiN film 46 in the PMOS region. A film 48 is formed. This La ₂ O ₃ film is formed to lower the threshold Vth of the NMOSFET. A lanthanum film may be formed instead of the La ₂ O ₃ film. Instead of the lanthanum film, any one of yttrium, terbium, erbium, ytterbium, magnesium, yttrium, scandium, other lanthanoids, actinoids, alkaline earth metals, and rare earth metals may be used. In that case, usually, the La film is slightly oxidized during the process, and exists in a state of becoming a La (O) film containing a small amount of oxygen. Similarly, when magnesium is used instead of lanthanum, it is considered that it is present in a slightly oxidized state.

Subsequently, as shown in FIG. 9B, a W film 49 as a metal electrode is formed on the La ₂ O ₃ film 48, and a TiN film as a barrier metal 50 is formed on the W film 49. In the NMOS region, the La element contained in the La ₂ O ₃ film 48 diffuses to the vicinity of the interface between the silicon substrate 40 and the SiO ₂ film 44 by performing a heating process after the TiN film 50 is formed. Since the SiN film 46 blocks the diffusion of the La element, the La element does not diffuse in the interface direction of the silicon substrate 40.

Thereafter, as shown in FIG. 9C, a polycrystalline silicon film 51 is deposited on the TiN film 50 as a gate material, and after ion implantation is performed on the polycrystalline silicon film 51, the polycrystalline silicon film is formed by photolithography. The gate electrode 52 is formed by sequentially etching the film 51, the TiN film 50, and the W film 49. Further, using the gate electrode 52 as a mask, the La ₂ O ₃ film 48, the SiN film 46, the HfSiON film 45, and the SiO ₂ film 44 are sequentially etched to form a gate insulating film 53. At this time, extension ion implantation and crystal recovery annealing may be performed as necessary.

  Next, as shown in FIG. 9D, after a liner film made of SiN is deposited on the entire upper surface of the silicon substrate 40, TEOS (Tetraethoxysilane) is deposited on the SiN film, and anisotropic etching is performed. The TEOS and SiN films are etched to form a SiN film 54 and a TEOS film 55 that become gate sidewalls. Subsequently, ion implantation and activation annealing are performed using the gate electrode 52 as a mask to form a source / drain diffusion layer 56.

According to the above-described embodiment, the following effects can be obtained. That is, the SiN film 46 is formed on the PMOS region. Thereby, in the NMOS region, the La element contained in the La ₂ O ₃ film 48 diffuses to the vicinity of the interface between the silicon substrate 40 and the SiO ₂ film 44, but in the PMOS region, the SiN film 46 diffuses the La element. Therefore, the La element does not diffuse in the interface direction between the silicon substrate 40 and the SiO ₂ film 44. Therefore, an increase in the number of manufacturing steps can be suppressed, and metal electrodes suitable for the NMOSFET and the PMOSFET can be formed.

  In the first embodiment described above, since the silicon film 7 remains on the NMOS region, the silicide electrode 14 is formed by reacting with the W film 12, but in this embodiment, the W film is not silicided. Since it can be used as an electrode, a higher speed operation can be realized. In addition, since there is no step of nitriding the resist film as compared with the first to fourth embodiments, it is considered that the resist film can be easily peeled off as compared with the nitrided resist film.

  In this embodiment, the W film 49 is used as a metal electrode, and a TiN film is formed as the barrier metal 50 in order to prevent the reaction between the polycrystalline silicon film 51 formed on the metal electrode and the W film 49. The metal electrode may use transition metals such as Ta, their silicides, nitrides, carbides, etc., and the barrier metal 50 may not be formed as long as it does not react with the polycrystalline silicon film 51. The barrier metal 50 is not limited to TiN, and any other metal may be used as long as it can prevent the reaction between a metal electrode such as TaC or Ru and polycrystalline silicon.

  In this embodiment, in order to diffuse the La element to the vicinity of the interface between the silicon substrate and the gate insulating film, the heat treatment is performed in the process shown in FIG. 9B. However, the heating at the time of forming the source and drain diffusion layers is performed. Since the phase separation and diffusion occur sufficiently even in the processing step, they may be omitted.

  In addition, in the present embodiment, a hafnium silicate nitride film is used for the high dielectric constant gate insulating film 45. However, a hafnium silicate film, a zirconium silicate film, a zirconium silicate nitride film, a hafnium zirconium silicate film, and a hafnium zirconium silicate nitride are used. Other materials may be used as long as the nitrogen concentration capable of preventing the diffusion of the cap film can be realized by nitriding the film or the like.

  The substrate used in this embodiment may be an SOI (Silicon On Insulator) substrate in addition to a normal silicon substrate.

(Sixth embodiment)
In the sixth embodiment, prior to forming the SiO ₂ film 44 in the fifth embodiment, a SiGe layer is formed in the PMOS region by epitaxial growth or the like. Since this embodiment is the same as the fifth embodiment except that a SiGe layer is formed, the same parts as those in the fifth embodiment are denoted by the same reference numerals, and description thereof is omitted. .

As shown in FIG. 10A, the SiGe layer 57 is formed before the SiO ₂ film 44 is formed. The subsequent steps are the same as in the fifth embodiment. As shown in FIG. 10B, after forming the gate electrode 52, ions of conductive impurities are formed on the silicon substrate 40 using the gate electrode 52 as a mask. Implantation and activation annealing are performed to form the source / drain diffusion layer 56.

By forming the SiGe layer 57, a lower threshold voltage (Vth) than that of a normal silicon channel transistor can be realized. Instead of the SiGe layer, an Al ₂ O ₃ layer or an AlN layer may be formed using MOCVD or ALD. Alternatively, an Al ₂ O ₃ layer or an AlN layer may be formed after the SiGe layer is formed.

  According to the present embodiment described above, the following effects can be obtained in addition to the effects of the fifth embodiment described above. That is, by forming the SiGe layer in the PMOS region, it becomes possible to realize a CMOSFET having a lower threshold value as compared with the fifth embodiment.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which showed the difference characteristic of the Gibbs free energy in reaction which concerns on the 1st Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 5th Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 5th Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 6th Embodiment of this invention.

Explanation of symbols

1, 22, 40 Silicon substrate 2, 23, 41 Element isolation region (STI)
3, 24, 42 P well diffusion layer 4, 25, 43 N well diffusion layer 5, 26, 44 Silicon oxide film 6, 27, 45 High dielectric constant gate insulating film 7 Silicon film 8, 28, 47 Resist 9, 18, 36, 46, 54 SiN film 10, 23 HfSiON film 11, 30 La (O) film 12, 31, 49 W film 13, 32, 50 Barrier metal 14 WSi film 15, 33, 51 Doped polycrystalline silicon film 16, 34 , 52 Gate electrodes 17, 35, 53 Gate insulating films 19, 37, 55 TEOS films 20, 38, 56 Source / drain diffusion layers 21, 39, 57 SiGe layer 29 Nitride HfSiON film 48 La ₂ O ₃ film

Claims (6)

Forming an N-type semiconductor region and a P-type semiconductor region on the main surface of the substrate;
Forming a high dielectric constant gate insulating film on the N-type semiconductor region and the P-type semiconductor region;
Forming a silicon film on the high dielectric constant gate insulating film;
Nitriding the silicon film on the N-type semiconductor region and replacing it with a silicon nitride film;
Forming a metal gate electrode on the silicon film in the P-type semiconductor region and on the silicon nitride film in the N-type semiconductor region via a cap film;
Introducing a constituent element of the cap film into the high dielectric constant gate insulating film of the N-type semiconductor region;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the high dielectric constant gate insulating film contains at least one of hafnium and zirconium. The method further includes the step of forming a single layer of SiGe, Al ₂ O ₃ , or AlN, or a stacked layer thereof under the high dielectric constant gate insulating film on the N-type semiconductor region. A method for manufacturing a semiconductor device according to claim 2. Forming an N-type semiconductor region and a P-type semiconductor region on the main surface of the substrate;
Forming a high dielectric constant gate insulating film on the N-type semiconductor region and the P-type semiconductor region;
Nitriding the high dielectric constant gate insulating film on the N-type semiconductor region and replacing it with a nitrided high dielectric constant gate insulating film;
Forming a metal gate electrode on the high dielectric constant gate insulating film in the P-type semiconductor region and on the nitrided high dielectric constant gate insulating film in the N-type semiconductor region via a cap film;
Introducing a constituent element of the cap film into the high dielectric constant gate insulating film of the P-type semiconductor region;
A method for manufacturing a semiconductor device, comprising:   5. The method of manufacturing a semiconductor device according to claim 4, wherein the high dielectric constant gate insulating film contains at least one of hafnium and zirconium. Forming an N-type semiconductor region and a P-type semiconductor region on the main surface of the substrate;
Forming a high dielectric constant gate insulating film on the N-type semiconductor region and the P-type semiconductor region;
Forming a silicon nitride film on the high dielectric constant gate insulating film on the N-type semiconductor region;
Forming a metal gate electrode on the high dielectric constant gate insulating film in the P-type semiconductor region and on the silicon nitride film in the N-type semiconductor region via a cap film;
Introducing a constituent element of the cap film into the high dielectric constant gate insulating film of the P-type semiconductor region;
A method for manufacturing a semiconductor device, comprising:

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