WO2011104788A1 - Method for manufacturing a semiconductor device - Google Patents

Method for manufacturing a semiconductor device Download PDF

Info

Publication number
WO2011104788A1
WO2011104788A1 PCT/JP2010/006228 JP2010006228W WO2011104788A1 WO 2011104788 A1 WO2011104788 A1 WO 2011104788A1 JP 2010006228 W JP2010006228 W JP 2010006228W WO 2011104788 A1 WO2011104788 A1 WO 2011104788A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
semiconductor device
manufacturing
formation region
high dielectric
Prior art date
Application number
PCT/JP2010/006228
Other languages
French (fr)
Japanese (ja)
Inventor
成田賢治
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2011104788A1 publication Critical patent/WO2011104788A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Definitions

  • the present disclosure relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a gate insulating film including a high dielectric material and a gate electrode including a metal film.
  • CMOS Complementary metal-oxide semiconductor
  • CMOS Complementary metal-oxide semiconductor
  • a conventional gate insulating film made of a silicon oxide film is made thinner, an increase in leakage current may be induced, and the standby current of an LSI (Large Scale Integration) circuit may increase. For this reason, the thinning of the gate insulating film made of a silicon oxide film has reached its limit.
  • a CMIS (Complementary Metal-Insulator Semiconductor) device that uses an insulating film made of a high dielectric material as a gate insulating film instead of a silicon oxide film has been attracting attention.
  • An insulating film made of a high-dielectric material is expected to be able to further reduce the thickness of the gate insulating film because the electrical film thickness can be reduced even if the physical film thickness is increased. ing.
  • the most promising high dielectric material for gate insulating films is hafnium nitride silicate (HfSiON).
  • HfSiON hafnium nitride silicate
  • an n-type N-MISFET N-metal-insulator semiconductor field effect transistor
  • a p-type P-MISFET P-metal-insulator semiconductor field effect transistor
  • the characteristics required for the gate insulating film and the gate electrode are different between the N-MISFET and the P-MISFET. Specifically, it is preferable to lower the effective work function in the N-MISFET, and it is preferable to increase the effective work function in the P-MISFET.
  • the conventional method of making a separate N-MISFET and P-MISFET has the following problems.
  • a method of selectively forming a cap film a method of selectively forming a cap film in one region using a resist film as a mask is known.
  • the cap film when the cap film is selectively formed using the resist film as a mask, the resist film is scattered when the cap film is formed, which may cause generation of particles or abnormal growth. Further, the cap film formed on the resist film may be scattered when the resist film is removed, and the cap film may be reattached to the lower layer of the resist film. For this reason, there exists a problem that the characteristic of a semiconductor device is not stabilized.
  • the lower layer of the cap film may be etched.
  • a necessary cap film may be thinned.
  • An object of the present disclosure is to solve the above-described problem and to easily realize a semiconductor device including an N-MISFET and a P-MISFET having predetermined stable characteristics.
  • the exemplary semiconductor device manufacturing method has a configuration in which a cap film is selectively formed using a sacrificial conductive film as a hard mask.
  • the method for manufacturing a semiconductor device includes a step (a) of forming a first element formation region and a second element formation region on a semiconductor substrate, and a high dielectric film on the entire surface of the semiconductor substrate.
  • the portions are selectively removed using the second chemical solution and the third chemical solution, respectively, and high dielectrics are formed in the first element formation region.
  • the step (f) of forming the third film having the third metal element on the entire surface of the semiconductor substrate after the step (e), and the step (f) Later, the step (g) of diffusing the third metal element into the high dielectric film and the remaining portions of the third film and the sacrificial conductive film are removed using the fourth chemical solution and the fifth chemical solution, respectively.
  • a first gate insulating film containing a third metal element and a first gate electrode made of an electrode film are formed in the element forming region, and the first metal element is contained in the second element forming region.
  • the method for manufacturing a semiconductor device selectively forms a third film, which is a cap film for the first element, using a hard mask made of a sacrificial conductive film. For this reason, when the third film is formed, the resist film does not scatter and become particles or cause abnormal growth. Further, the first film which is the cap film for the second element is removed by wet etching. For this reason, when removing the first film in the first element formation region, the high dielectric film is hardly etched. Therefore, a highly reliable semiconductor device can be easily manufactured.
  • the sacrificial conductive film may be titanium nitride, tungsten, or tungsten nitride, and the second film may be lanthanum oxide.
  • a neutral solution containing an oxidizing agent and having a pH adjusted to 6 or more and 8 or less may be used as the second chemical solution.
  • the neutral solution containing the oxidizing agent may be hydrogen peroxide solution having a concentration of 5% by mass or more and 30% by mass or less.
  • an acidic solution that does not contain an oxidant and that has a pH adjusted to 1 or less may be used as the third chemical solution.
  • step (h) an acidic solution that does not include an oxidant and is adjusted to pH 2 or more and 4 or less is used as the fourth chemical solution, and the pH is 2 as the fifth chemical solution.
  • An acidic solution containing an oxidizing agent adjusted to 4 or less may be used.
  • the pH of the portion remaining on the sacrificial conductive film of the second film is adjusted to 1 or less after the step (d) and before the step (e).
  • the step (k) of removing using an acidic solution containing no oxidizing agent may be further provided.
  • an acidic solution that does not contain an oxidizing agent having a pH adjusted to 4.0 or more and 4.9 or less may be used as the first chemical solution.
  • the high dielectric film may be a metal oxide, metal oxynitride, nitride, or nitrogen-containing nitride having a relative dielectric constant of 8 or more.
  • the second metal element may be aluminum or tantalum.
  • the third metal element may be lanthanum or a lanthanoid other than lanthanum, scandium, strontium, or magnesium.
  • the electrode film may be a laminated film of a titanium nitride film and a silicon film.
  • a semiconductor device including an N-MISFET and a P-MISFET having predetermined stable characteristics can be easily realized.
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12.
  • an N-MISFET formation region 101N and a P-MISFET formation region 101P are formed on a semiconductor substrate 101 which is a p-type silicon substrate.
  • a first active region 101 a and a second active region 101 b separated from each other by the element isolation region 111 are formed on the semiconductor substrate 101.
  • a p-type well 102a is formed in the first active region 101a
  • an n-type well 102b is formed in the second active region 101b.
  • the element isolation region 111 may be formed by an STI (Shallow Trench Isolation) method in which an insulating film is embedded in a trench formed in the semiconductor substrate 101.
  • a base film (not shown), a high dielectric film 121, a first film 122, a sacrificial conductive film 123 and a second film 124 are sequentially formed on the entire surface of the semiconductor substrate 101.
  • the base film may be a silicon oxide film (SiO 2 ) film having a thickness of about 1.1 nm.
  • the high dielectric film 121 may be a nitrogen-containing hafnium silicate (HfSiON) film having a thickness of about 1.7 nm.
  • the high dielectric film 121 may be formed by an atomic layer deposition (ALD) method.
  • the high dielectric film 121 may be a hafnium oxide (HfO 2 ) film or a hafnium silicate (HfSiO x ) film instead of the HfSiON film.
  • a high dielectric material such as a metal oxide, metal oxynitride, nitride or nitrogen-containing nitride having a relative dielectric constant of 8 or more may be used.
  • the first film 122 may be an aluminum oxide (Al 2 O 3 ) film having a thickness of about 0.5 nm.
  • the first film 122 is not limited to the Al 2 O 2 film, and may be formed of a material containing a first metal that increases the effective work function of the transistor when diffused into the high dielectric film 121.
  • the sacrificial conductive film 123 may be a titanium nitride (TiN) film having a thickness of about 10 nm.
  • the sacrificial conductive film 123 may be formed by an ALD method.
  • the sacrificial conductive film 123 is not limited to a TiN film, and may be a tungsten (W) film, a tungsten nitride (WN) film, or the like.
  • the second film 124 may be a lanthanum oxide (La 2 O 3 ) film having a thickness of 5 nm, for example.
  • the second film 124 may be formed by a physical vapor deposition (PVD) method.
  • the second film 124 may be formed of a material containing a second metal that can change the etching characteristics of the sacrificial conductive film 123 when diffused into the sacrificial conductive film 123.
  • the portion of the second film 124 formed in the N-MISFET formation region 101N is selectively removed. Specifically, first, a resist pattern 151 that exposes the N-MISFET formation region 101N and covers the P-MISFET formation region 101P is formed on the sacrificial conductive film 123 by photolithography. Subsequently, using the resist pattern 151 as a mask, the portion formed in the N-MISFET formation region 101N in the second film 124 is removed by wet etching using the first chemical solution.
  • the first chemical solution may be a weakly acidic chemical solution that does not contain an oxidant and has a pH adjusted to about 4.0 to 4.9.
  • a hydrochloric acid aqueous solution in which 36% by mass of hydrochloric acid and water are mixed at a volume ratio of 1: 500000 may be used. In this case, the pH is about 4.6.
  • La contained in the second film 124 is removed from the sacrificial conductive film 123.
  • a sacrificial conductive film 123a containing La is formed above the portion of the sacrificial conductive film 123 formed in the P-MISFET formation region 101P.
  • the undiffused second film 124 is removed.
  • La may be diffused by heat treatment, the heat treatment temperature may be about 600 ° C., and the treatment time may be about 10 minutes. The heat treatment temperature may be about 500 ° C.
  • the undiffused second film 124 may be removed by wet etching.
  • the etching solution may be a strongly acidic chemical solution that does not contain an oxidizing agent whose pH is adjusted to 1 or less.
  • a hydrochloric acid aqueous solution in which 36% by mass of hydrochloric acid and water are mixed at a volume ratio of 1:50 may be used.
  • the second film 124 may be completely diffused and may not remain. In this case, the undiffused second film 124 may not be removed.
  • the second chemical solution may be a neutral solution containing an oxidizing agent whose pH is adjusted to about 6-8.
  • hydrogen peroxide having a concentration of 5% by mass to 30% by mass may be used.
  • the sacrificial conductive film 123a containing La is resistant to a neutral solution containing an oxidizing agent whose pH is adjusted to 6-8.
  • the third chemical solution may be a strongly acidic solution that does not contain an oxidizing agent whose pH is adjusted to 1 or less.
  • a hydrochloric acid aqueous solution in which 36% by mass of hydrochloric acid and water are mixed at a volume ratio of 1:50 may be used.
  • the ratio of the etching rate of Al 2 O 3 to the etching rate of HfSiON is 10,000 or more. Therefore, it is possible to easily remove the first film 122 without etching the high dielectric film 121. Note that when Al diffuses in the upper portion of the high dielectric film 121, the diffused Al is also removed to the extent that does not cause a problem.
  • a third film 125 is formed on the entire surface of the semiconductor substrate 101.
  • the third film 125 may be a La 2 O 3 film having a thickness of about 2 nm.
  • the third film 125 is not limited to La 2 O 3 and may be formed of a material containing a metal that lowers the effective function of the transistor when diffused into the high dielectric film 121.
  • the third film may be formed by a PVD method.
  • the semiconductor substrate 101 is heat-treated at, for example, 650 ° C. for 10 minutes.
  • the N-MISFET formation region 101N La contained in the third film diffuses into the high dielectric film, and a high dielectric film 121a containing La is formed.
  • the P-MISFET formation region 101P Al contained in the first film diffuses into the high dielectric film, and a high dielectric film 121b containing Al is formed.
  • FIG. 7 shows a state in which the first film 122 is completely diffused and disappeared, the unreacted first film 122 may remain depending on heat treatment conditions.
  • La contained in the third film diffuses into the sacrificial conductive film 123, and the La concentration of the sacrificial conductive film 123a containing La increases.
  • the heat treatment may be performed at a temperature of 600 ° C. to 700 ° C. for about 5 minutes to 10 minutes.
  • the undiffused third film and the sacrificial conductive film 123a and sacrificial conductive film 123 in which La is diffused are wet-etched using the fourth chemical solution and the fifth chemical solution, respectively.
  • the fourth chemical solution may be an acidic solution that does not contain an oxidant having a pH adjusted to about 2 to 4.
  • an oxidant having a pH adjusted to about 2 to 4.
  • a hydrochloric acid aqueous solution in which 36% by mass of hydrochloric acid and water are mixed at a volume ratio of 1: 2000 may be used.
  • the fifth chemical solution may be an acidic solution containing an oxidizing agent whose pH is adjusted to about 2 to 4.
  • a solution in which 36% by mass hydrochloric acid and 31% by mass hydrogen peroxide water are mixed at a deposition ratio of 1: 2000 may be used.
  • the concentration of hydrogen peroxide as the oxidizing agent is preferably 1% by mass or more.
  • a TiN film 128 having a thickness of 15 nm and a silicon film 129 having a thickness of 90 nm are formed on the entire surface of the semiconductor substrate 101 by an ALD method or the like.
  • the silicon film 129 may be a polysilicon film or an amorphous silicon film.
  • the silicon film 129, the TiN film 128, the high dielectric film 121a containing La, the high dielectric film 121b containing Al, and the base film are patterned by dry etching using a resist pattern.
  • the first gate electrode 130a in which the TiN film 128 and the silicon film 129 are stacked in the N-MISFET formation region 101N, the high dielectric film 121a containing La, and the base film (FIG. A first gate insulating film is formed.
  • the gate etching time in the N-MISFET formation region 101N is a time required to etch the silicon film 129, the TiN film 128, and the high dielectric film 121a if the base film can be ignored.
  • the gate etching time in the P-MISFET formation region 101P is the time required to etch the silicon film 129, the TiN film 128, and the high dielectric film 121b.
  • the height from the surface of the p-type well 102a and the n-type well 102b to the surface of the silicon film 129 in the semiconductor substrate 101 is such that the N-MISFET formation region 101N and the P-MISFET It becomes substantially equal in the formation region 101P.
  • the gate etching time is N ⁇
  • the MISFET formation region 101N and the P-MISFET formation region 101P are substantially equal.
  • the region where the etching to the gate insulating film has been completed first is the well until the other gate etching is completed.
  • the surface of the film continues to be etched. As a result, the characteristics of the transistor may be deteriorated.
  • the semiconductor device manufacturing method of this embodiment has an advantage that such a problem can be solved.
  • the first offset spacer 131a is formed on the side surface of the first gate electrode 130a
  • the second offset spacer 131b is formed on the side surface of the second gate electrode 130b.
  • Impurities are implanted into the first active region 101a using the first gate electrode 130a and the first offset spacer 131a as a mask to form an n-type extension region 141a.
  • an impurity is implanted into the second active region 101b using the second gate electrode 130b and the second offset spacer 131b as a mask to form a p-type extension region 141b.
  • first sidewall 133a and the second sidewall 133b are formed on the side surface of the first offset spacer 131a and the side surface of the second offset spacer 131b, respectively.
  • the first side wall 133a has an L-shaped first inner side wall 134a and a first outer side wall 135a
  • the second side wall 133b has an L-shaped second inner side wall 134b and a first outer side wall 134b. 2 outer sidewalls 135b.
  • an impurity is implanted into the first active region 101a using the first gate electrode 130a, the first offset spacer 131a, and the first sidewall 133a as a mask to form an n-type source / drain region 142a.
  • an impurity is implanted into the second active region 101b using the second gate electrode 130b, the second offset spacer 131b, and the second sidewall 133b as a mask to form a p-type source / drain region 142b.
  • silicide layers 138 made of nickel silicide or the like are formed on the first gate electrode 130a, the second gate electrode 130b, the n-type source / drain region 142a, and the p-type source / drain region 142b, respectively.
  • a semiconductor device having an N-MISFET and a P-MISFET can be obtained.
  • FIG. 12 shows a planar configuration of the semiconductor device obtained by the semiconductor device manufacturing method of the present embodiment.
  • FIG. 13 shows a cross-sectional structure taken along line XIII-XIII in FIG. Note that FIG. 11 corresponds to a cross-sectional configuration taken along line XI-XI in FIG.
  • the method for manufacturing a semiconductor device uses the sacrificial conductive film 123 as a mask covering the P-MISFET formation region. For this reason, the resist film does not exist when the third film is formed, and generation of particles and abnormal growth due to the resist film do not occur. Further, a sacrificial conductive film 123a in which La diffuses is formed on the sacrificial conductive film 123 in the PMISFET formation region, and the sacrificial conductive film 123 can be removed with very high selectivity in the N-MISFET formation region. Therefore, there is almost no possibility that the high dielectric film is etched in the N-MISFET formation region. Therefore, it is possible to form a gate insulating film having optimum characteristics with good reproducibility in each of the N-MISFET formation region and the PMISFET formation region.
  • FIG. 7 shows an example in which La is uniformly diffused in the high dielectric film 121 and the high dielectric film 121a containing La is formed.
  • the La concentration in the high dielectric film 121a may not be uniform, and the upper portion may have a higher La concentration than the lower portion, or the lower portion may have a higher La concentration than the upper portion.
  • a plurality of layers having different La concentrations may be formed.
  • FIG. 7 shows an example in which the third film 125 remains after the heat treatment, but the third film 125 disappears after the heat treatment depending on the thickness of the third film 125, heat treatment conditions, and the like. Also occurs.
  • the Al concentration is not uniform, and the upper portion has a higher Al concentration than the lower portion, or the lower portion has a higher Al concentration than the upper portion.
  • a plurality of layers having different concentrations may be formed.
  • FIG. 7 shows an example in which the first film 122 disappears after the heat treatment. However, depending on the film thickness of the first film 122, heat treatment conditions, and the like, the gap between the high dielectric film 121b and the sacrificial conductive film 123 is increased. In some cases, the first film 122 may remain. In the case where the first film 122 remains, the remaining portion of the first film 122 may be removed when the sacrificial conductive film 123 is removed.
  • the remaining portion of the first film 122 may not be removed.
  • the remaining portion of the first film 122 is diffused into the high dielectric film 121 by heat treatment performed in the process of forming the extension region, the source / drain region, and the silicide layer.
  • the undiffused third film 125 in the N-MISFET formation region 101N may not be completely removed.
  • the remaining portion of the third film 125 is diffused into the high dielectric film 121 by the subsequent heat treatment process.
  • a base film (not shown) is formed between the high dielectric film 121 and the semiconductor substrate 101 is shown, but the base film may not be formed.
  • a base film may be provided between at least one of the first gate insulating film having the high dielectric film 121 a and the second gate insulating film having the high dielectric film 121 b and the semiconductor substrate 101.
  • the third film 125 may be a film containing a lanthanoid other than La, scandium (Sc), strontium (Sr), magnesium (Mg), or the like instead of La 2 O 3 .
  • the third film 125 is not limited to an oxide film, and may be any film containing these metal elements. Moreover, the metal film which is not a compound may be sufficient.
  • the first film 122 may be Ta 2 O 3 instead of Al 2 O 3 .
  • the film is not limited to an oxide film, and may be a film containing Al or Ta, and may be an Al film or a Ta film.
  • the first film 122 and the third film 125 do not need to be insulating films themselves, and the high dielectric film in which the metal element contained in the first film 122 and the third film 125 diffuses has an insulating property. Show it.
  • the method of selectively wet-etching the hard mask by combining the sacrificial conductive film and the second film is a process for forming a Cu wiring using a low dielectric constant film as an interlayer insulating film. It can be used for a non-silicide formation process, an implantation resist substitute mask formation process and the like.
  • the method for manufacturing a semiconductor device according to the present disclosure can easily realize a semiconductor device including an N-MISFET and a P-MISFET having predetermined stable characteristics, and particularly includes a gate insulating film and a metal film including a high dielectric material. This is useful as a method for manufacturing a semiconductor device including a gate electrode.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Weting (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Disclosed is a method for manufacturing a semiconductor device in which a high dielectric film (121), a first film (122), a sacrificial conductive film (123), and a second film (124) are successively formed on a semiconductor substrate (101), and then the portion formed in an N-MISFET forming region (101N) in the second film (124) is selectively removed by using a first chemical solution. A second metal element contained in the second film (124) is then diffused into the portion formed in a P-MISFET forming region (101P) in the sacrificial conductive film (123). Next, the portions formed in N-MISFET forming regions (101N) in the sacrificial conductive film (123) and the first film (122) are selectively removed by using a second chemical solution and a third chemical solution, respectively. After a third film (125) is formed, a third metal element contained in the third film (125) is diffused into the high dielectric film (121).

Description

半導体装置の製造方法Manufacturing method of semiconductor device
　本開示は、半導体装置の製造方法に関し、特に高誘電体材料を含むゲート絶縁膜及び金属膜を含むゲート電極を備えた半導体装置の製造方法に関する。 The present disclosure relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a gate insulating film including a high dielectric material and a gate electrode including a metal film.
　ＣＭＯＳ（Complementary metal-oxide semiconductor）デバイスは、さらなる微細化が要求されている。ＣＭＯＳデバイスをさらに微細化するためには、ゲート絶縁膜のさらなる薄膜化が必要となる。しかし、従来のシリコン酸化膜からなるゲート絶縁膜をさらに薄くすると、リーク電流の増大を誘発し、ＬＳＩ（Large scale integration）回路の待機時電流が増大するおそれがある。このため、シリコン酸化膜からなるゲート絶縁膜の薄膜化は、限界を迎えている。そこで、シリコン酸化膜に代えて高誘電体材料からなる絶縁膜をゲート絶縁膜とする、ＣＭＩＳ（Complementary metal-insulator semiconductor）デバイスが注目されている。高誘電体材料からなる絶縁膜は、物理的な膜厚を厚くしても電気的な膜厚を薄くすることが可能であるため、ゲート絶縁膜の薄膜化をさらに進めることができると期待されている。現在、ゲート絶縁膜用の高誘電体材料として最も有望視されているのは、窒化ハフニウムシリケート（ＨｆＳｉＯＮ）である。また、ゲート電極についても、従来のポリシリコンからなる電極ではその空乏化が無視できなくなってきており、空乏化が生じないメタルゲート電極の開発が盛んに行われている。 CMOS (Complementary metal-oxide semiconductor) devices are required to be further miniaturized. In order to further miniaturize the CMOS device, it is necessary to further reduce the thickness of the gate insulating film. However, if a conventional gate insulating film made of a silicon oxide film is made thinner, an increase in leakage current may be induced, and the standby current of an LSI (Large Scale Integration) circuit may increase. For this reason, the thinning of the gate insulating film made of a silicon oxide film has reached its limit. Therefore, a CMIS (Complementary Metal-Insulator Semiconductor) device that uses an insulating film made of a high dielectric material as a gate insulating film instead of a silicon oxide film has been attracting attention. An insulating film made of a high-dielectric material is expected to be able to further reduce the thickness of the gate insulating film because the electrical film thickness can be reduced even if the physical film thickness is increased. ing. At present, the most promising high dielectric material for gate insulating films is hafnium nitride silicate (HfSiON). As for the gate electrode, depletion cannot be ignored in conventional polysilicon electrodes, and development of metal gate electrodes that do not cause depletion has been actively conducted.
　一方、ＣＭＩＳデバイスを形成する場合には、ｎ型のＮ－ＭＩＳＦＥＴ（Ｎ－metal-insulator semiconductor field effect transistor）とｐ型のＰ－ＭＩＳＦＥＴ（Ｐ－metal-insulator semiconductor field effect transistor）とが必要である。しかし、Ｎ－ＭＩＳＦＥＴとＰ－ＭＩＳＦＥＴとでは、ゲート絶縁膜及びゲート電極に求められる特性が互いに異なっている。具体的には、Ｎ－ＭＩＳＦＥＴでは実効仕事関数を低くすることが好ましく、Ｐ－ＭＩＳＦＥＴでは実効仕事関数を高くすることが好ましい。このため、実効仕事関数が低いＮ－ＭＩＳＦＥＴ用のゲート絶縁膜及びゲート電極と、実効仕事関数が高いＰ－ＭＩＳＦＥＴ用のゲート絶縁膜及びゲート電極とを作り別けるプロセスが提案されている（例えば特許文献１参照）。 On the other hand, when forming a CMIS device, an n-type N-MISFET (N-metal-insulator semiconductor field effect transistor) and a p-type P-MISFET (P-metal-insulator semiconductor field effect transistor) are required. is there. However, the characteristics required for the gate insulating film and the gate electrode are different between the N-MISFET and the P-MISFET. Specifically, it is preferable to lower the effective work function in the N-MISFET, and it is preferable to increase the effective work function in the P-MISFET. For this reason, a process has been proposed in which a gate insulating film and gate electrode for N-MISFET having a low effective work function and a gate insulating film and gate electrode for P-MISFET having a high effective work function are separated (for example, patents). Reference 1).
特開２００９－２６７３４２号公報JP 2009-267342 A
　しかしながら、前記従来のＮ－ＭＩＳＦＥＴとＰ－ＭＩＳＦＥＴとを作り別ける方法は、以下のような問題を有している。Ｎ－ＭＩＳＦＥＴとＰ－ＭＩＳＦＥＴとを作り別けるためには、Ｎ－ＭＩＳＦＥＴを形成する領域又はＰ－ＭＩＳＦＥＴを形成する領域の一方だけにキャップ膜を選択的に形成する必要がある。キャップ膜を選択的に形成する方法として、レジスト膜をマスクとして一方の領域に選択的にキャップ膜を形成する方法が知られている。 However, the conventional method of making a separate N-MISFET and P-MISFET has the following problems. In order to separate the N-MISFET and the P-MISFET, it is necessary to selectively form a cap film only in one of the region for forming the N-MISFET and the region for forming the P-MISFET. As a method of selectively forming a cap film, a method of selectively forming a cap film in one region using a resist film as a mask is known.
　しかし、レジスト膜をマスクとしてキャップ膜を選択的に形成する場合には、キャップ膜を成膜する際にレジスト膜が飛散して、パーティクルが発生したり、異常成長を引き起こしたりする原因となる。また、レジスト膜の上に形成されたキャップ膜がレジスト膜を除去する際に飛散し、レジスト膜の下側の層にキャップ膜が再付着するおそれがある。このため、半導体装置の特性が安定しないという問題がある。 However, when the cap film is selectively formed using the resist film as a mask, the resist film is scattered when the cap film is formed, which may cause generation of particles or abnormal growth. Further, the cap film formed on the resist film may be scattered when the resist film is removed, and the cap film may be reattached to the lower layer of the resist film. For this reason, there exists a problem that the characteristic of a semiconductor device is not stabilized.
　キャップ膜を形成した後、一方の領域を覆うレジスト膜を形成し、レジスト膜をマスクとしてドライエッチングを行うことにより、不要なキャップ膜を除去する方法も知られている。しかし、ドライエッチングによりキャップ膜の不要な部分を除去する方法の場合には、キャップ膜の下側の層もエッチングされてしまうおそれがある。また、ドライエッチング後の、残渣洗浄工程において、必要とするキャップ膜が薄くなるおそれがある。 Also known is a method of removing an unnecessary cap film by forming a resist film covering one region after forming the cap film and performing dry etching using the resist film as a mask. However, in the case of a method of removing an unnecessary portion of the cap film by dry etching, the lower layer of the cap film may be etched. In addition, in the residue cleaning process after dry etching, a necessary cap film may be thinned.
　このように、従来のＮ－ＭＩＳＦＥＴとＰ－ＭＩＳＦＥＴとを作り別ける方法には種々の問題があり、半導体装置の特性を安定させることができず、信頼性が高い半導体装置を実現することが困難であるということを本願発明者らは見出した。 As described above, there are various problems in the conventional method for separately forming the N-MISFET and the P-MISFET, the characteristics of the semiconductor device cannot be stabilized, and it is difficult to realize a highly reliable semiconductor device. The inventors of the present application have found that
　本開示は、前記の問題を解決し、所定の安定した特性を有するＮ－ＭＩＳＦＥＴとＰ－ＭＩＳＦＥＴとを備えた半導体装置を容易に実現できるようにすることを目的とする。 An object of the present disclosure is to solve the above-described problem and to easily realize a semiconductor device including an N-MISFET and a P-MISFET having predetermined stable characteristics.
　前記の目的を達成するため、例示の半導体装置の製造方法は、犠牲導電膜をハードマスクとして、キャップ膜を選択的に形成する構成とする。 To achieve the above object, the exemplary semiconductor device manufacturing method has a configuration in which a cap film is selectively formed using a sacrificial conductive film as a hard mask.
　具体的に、本開示の半導体装置の製造方法は、半導体基板に、第１の素子形成領域及び第２の素子形成領域を形成する工程（ａ）と、半導体基板上の全面に高誘電体膜と、第１の金属元素を含む第１の膜と、犠牲導電膜と、第２の金属元素を含む第２の膜とを順次形成する工程（ｂ）と、第２の膜における第１の素子形成領域の上に形成された部分を第１の薬液を用いて選択的に除去する工程（ｃ）と、工程（ｃ）よりも後で、第２の金属元素を犠牲導電膜における第２の素子形成領域の上に形成された部分に拡散させる工程（ｄ）と、工程（ｄ）よりも後で、犠牲導電膜及び第１の膜における第１の素子形成領域の上に形成された部分を、それぞれ第２の薬液及び第３の薬液を用いて選択的に除去し、第１の素子形成領域において高誘電体膜を露出させる工程（ｅ）と、工程（ｅ）よりも後で、半導体基板上の全面に第３の金属元素を有する第３の膜を形成する工程（ｆ）と、工程（ｆ）よりも後で、第３の金属元素を高誘電体膜中に拡散させる工程（ｇ）と、第３の膜及び犠牲導電膜の残存部分をそれぞれ第４の薬液及び第５の薬液を用いて除去する工程（ｈ）と、（ｈ）よりも後で、半導体基板上の全面に電極膜を形成する工程（ｉ）と、電極膜及び高誘電体膜を選択的に除去することにより、第１の素子形成領域に、第３の金属元素を含む第１のゲート絶縁膜と、電極膜からなる第１のゲート電極とを形成し、第２の素子形成領域に、第１の金属元素を含む第２のゲート絶縁膜と、電極膜からなる第２のゲート電極とを形成する工程（ｊ）とを備えている。 Specifically, the method for manufacturing a semiconductor device according to the present disclosure includes a step (a) of forming a first element formation region and a second element formation region on a semiconductor substrate, and a high dielectric film on the entire surface of the semiconductor substrate. A step (b) of sequentially forming a first film containing the first metal element, a sacrificial conductive film, and a second film containing the second metal element, and the first film in the second film A step (c) of selectively removing a portion formed on the element formation region using the first chemical solution, and a second metal element in the sacrificial conductive film after the step (c). A step (d) of diffusing into a portion formed on the element formation region of the first layer, and a step formed after the step (d) on the first element formation region in the sacrificial conductive film and the first film. The portions are selectively removed using the second chemical solution and the third chemical solution, respectively, and high dielectrics are formed in the first element formation region. From the step (e) of exposing the film, the step (f) of forming the third film having the third metal element on the entire surface of the semiconductor substrate after the step (e), and the step (f) Later, the step (g) of diffusing the third metal element into the high dielectric film and the remaining portions of the third film and the sacrificial conductive film are removed using the fourth chemical solution and the fifth chemical solution, respectively. The step (h), the step (i) of forming an electrode film on the entire surface of the semiconductor substrate after the step (h), and the first film by selectively removing the electrode film and the high dielectric film. A first gate insulating film containing a third metal element and a first gate electrode made of an electrode film are formed in the element forming region, and the first metal element is contained in the second element forming region. A step (j) of forming a second gate insulating film and a second gate electrode made of an electrode film.
　本開示の半導体装置の製造方法は、犠牲導電膜からなるハードマスクを用いて、第１の素子用のキャップ膜である第３の膜を選択的に形成する。このため、第３の膜を成膜する際にレジスト膜が飛散してパーティクルとなったり、異常成長の原因となったりすることがない。また、第２の素子用のキャップ膜である第１の膜を、ウェットエッチングにより除去している。このため、第１の素子形成領域において第１の膜を除去する際に、高誘電体膜はほとんどエッチングされない。従って、信頼性が高い半導体装置を容易に製造することが可能となる。 The method for manufacturing a semiconductor device according to the present disclosure selectively forms a third film, which is a cap film for the first element, using a hard mask made of a sacrificial conductive film. For this reason, when the third film is formed, the resist film does not scatter and become particles or cause abnormal growth. Further, the first film which is the cap film for the second element is removed by wet etching. For this reason, when removing the first film in the first element formation region, the high dielectric film is hardly etched. Therefore, a highly reliable semiconductor device can be easily manufactured.
　本開示の半導体装置の製造方法において、犠牲導電膜は、窒化チタン、タングステン又は窒化タングステンとし、第２の膜は、酸化ランタンとすればよい。 In the method for manufacturing a semiconductor device according to the present disclosure, the sacrificial conductive film may be titanium nitride, tungsten, or tungsten nitride, and the second film may be lanthanum oxide.
　本開示の半導体装置の製造方法において、工程（ｅ）では、第２の薬液としてｐＨを６以上且つ８以下に調整した、酸化剤を含む中性溶液を用いればよい。 In the method for manufacturing a semiconductor device according to the present disclosure, in the step (e), a neutral solution containing an oxidizing agent and having a pH adjusted to 6 or more and 8 or less may be used as the second chemical solution.
　本開示の半導体装置の製造方において、酸化剤を含む中性溶液は、５質量％以上且つ３０質量％以下の濃度の過酸化水素水とすればよい。 In the method of manufacturing a semiconductor device according to the present disclosure, the neutral solution containing the oxidizing agent may be hydrogen peroxide solution having a concentration of 5% by mass or more and 30% by mass or less.
　本開示の半導体装置の製造方法において、工程（ｅ）では、第３の薬液としてｐＨを１以下に調整した、酸化剤を含まない酸性溶液を用いればよい。 In the method for manufacturing a semiconductor device of the present disclosure, in the step (e), an acidic solution that does not contain an oxidant and that has a pH adjusted to 1 or less may be used as the third chemical solution.
　本開示の半導体装置の製造方法において、工程（ｈ）では、第４の薬液としてｐＨを２以上且つ４以下に調整した、酸化剤を含まない酸性溶液を用い、第５の薬液としてｐＨを２以上且つ４以下に調整した酸化剤を含む酸性溶液を用いればよい。 In the method for manufacturing a semiconductor device according to the present disclosure, in step (h), an acidic solution that does not include an oxidant and is adjusted to pH 2 or more and 4 or less is used as the fourth chemical solution, and the pH is 2 as the fifth chemical solution. An acidic solution containing an oxidizing agent adjusted to 4 or less may be used.
　本開示の半導体装置の製造方法は、工程（ｄ）よりも後で且つ工程（ｅ）よりも前に、第２の膜の犠牲導電膜の上に残存した部分を、ｐＨを１以下に調整した、酸化剤を含まない酸性溶液を用いて除去する工程（ｋ）をさらに備えていてもよい。 In the method of manufacturing a semiconductor device according to the present disclosure, the pH of the portion remaining on the sacrificial conductive film of the second film is adjusted to 1 or less after the step (d) and before the step (e). The step (k) of removing using an acidic solution containing no oxidizing agent may be further provided.
　本開示の半導体装置の製造方法において、工程（ｃ）では、第１の薬液としてｐＨを４．０以上且つ４．９以下に調整した酸化剤を含まない酸性溶液を用いればよい。 In the method for manufacturing a semiconductor device according to the present disclosure, in the step (c), an acidic solution that does not contain an oxidizing agent having a pH adjusted to 4.0 or more and 4.9 or less may be used as the first chemical solution.
　本開示の半導体装置の製造方法において、高誘電体膜は、比誘電率が８以上の金属酸化物、金属酸窒化物、硅化物又は窒素含有硅化物とすればよい。 In the method for manufacturing a semiconductor device according to the present disclosure, the high dielectric film may be a metal oxide, metal oxynitride, nitride, or nitrogen-containing nitride having a relative dielectric constant of 8 or more.
　本開示の半導体装置の製造方法において、第２の金属元素は、アルミニウム又はタンタルとすればよい。 In the method for manufacturing a semiconductor device according to the present disclosure, the second metal element may be aluminum or tantalum.
　本開示の半導体装置の製造方法において、第３の金属元素は、ランタン若しくはランタン以外のランタノイド、スカンジウム、ストロンチウム又はマグネシウムとすればよい。 In the method for manufacturing a semiconductor device of the present disclosure, the third metal element may be lanthanum or a lanthanoid other than lanthanum, scandium, strontium, or magnesium.
　本開示の半導体装置の製造方法において、電極膜は、窒化チタン膜とシリコン膜との積層膜とすればよい。 In the method for manufacturing a semiconductor device of the present disclosure, the electrode film may be a laminated film of a titanium nitride film and a silicon film.
　本開示の半導体装置の製造方法によれば、所定の安定した特性を有するＮ－ＭＩＳＦＥＴとＰ－ＭＩＳＦＥＴとを備えた半導体装置を容易に実現できる。 According to the method for manufacturing a semiconductor device of the present disclosure, a semiconductor device including an N-MISFET and a P-MISFET having predetermined stable characteristics can be easily realized.
一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の製造方法により得られた半導体装置を示す平面図である。It is a top view which shows the semiconductor device obtained by the manufacturing method of the semiconductor device which concerns on one Embodiment. 図１２のXIII－XIII線における断面図である。FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12.
　図１～図１１は、一実施形態に係る半導体装置の製造方法を工程順に示している。まず、図１に示すように、ｐ型のシリコン基板である半導体基板１０１に、Ｎ－ＭＩＳＦＥＴ形成領域１０１Ｎ及びＰ－ＭＩＳＦＥＴ形成領域１０１Ｐを形成する。具体的には、まず、素子分離領域１１１により互いに分離された第１の活性領域１０１ａ及び第２の活性領域１０１ｂを半導体基板１０１に形成する。続いて、第１の活性領域１０１ａにｐ型ウェル１０２ａを形成し、第２の活性領域１０１ｂにｎ型ウェル１０２ｂを形成する。素子分離領域１１１は、半導体基板１０１に形成されたトレンチに絶縁膜を埋め込む、ＳＴＩ（Shallow Trench Isolation）法により形成すればよい。 1 to 11 show a semiconductor device manufacturing method according to an embodiment in the order of steps. First, as shown in FIG. 1, an N-MISFET formation region 101N and a P-MISFET formation region 101P are formed on a semiconductor substrate 101 which is a p-type silicon substrate. Specifically, first, a first active region 101 a and a second active region 101 b separated from each other by the element isolation region 111 are formed on the semiconductor substrate 101. Subsequently, a p-type well 102a is formed in the first active region 101a, and an n-type well 102b is formed in the second active region 101b. The element isolation region 111 may be formed by an STI (Shallow Trench Isolation) method in which an insulating film is embedded in a trench formed in the semiconductor substrate 101.
　次に、図２に示すように、下地膜（図示せず）、高誘電体膜１２１、第１の膜１２２、犠牲導電膜１２３及び第２の膜１２４を半導体基板１０１上の全面に順次形成する。下地膜は、膜厚が１．１ｎｍ程度のシリコン酸化膜（ＳｉＯ2）膜とすればよい。高誘電体膜１２１は、膜厚が１．７ｎｍ程度の窒素含有ハフニウムシリケート（ＨｆＳｉＯＮ）膜とすればよい。高誘電体膜１２１は、原子層堆積（Atomic Layer Deposition:ＡＬＤ）法により形成すればよい。高誘電体膜１２１は、ＨｆＳｉＯＮ膜に代えて酸化ハフニウム（ＨｆＯ2）膜又はハフニウムシリケート（ＨｆＳｉＯx）膜等としてもよい。また、この他にも比誘電率が８以上の金属酸化物、金属酸窒化物、硅化物又は窒素含有硅化物等の高誘電体材料により形成すればよい。第１の膜１２２は、膜厚が０．５ｎｍ程度の酸化アルミニウム（Ａｌ2Ｏ3）膜とすればよい。第１の膜１２２は、Ａｌ2Ｏ2膜に限らず、高誘電体膜１２１へ拡散させた場合にトランジスタの実効仕事関数を高くする第１の金属を含む材料により形成すればよい。犠牲導電膜１２３は、膜厚が１０ｎｍ程度の窒化チタン（ＴｉＮ）膜とすればよい。犠牲導電膜１２３は、ＡＬＤ法により形成すればよい。犠牲導電膜１２３は、ＴｉＮ膜に限らず、タングステン（Ｗ）膜又は窒化タングステン（ＷＮ）膜等であってもよい。第２の膜１２４は、例えば膜厚が５ｎｍの酸化ランタン（Ｌａ2Ｏ3）膜とすればよい。第２の膜１２４は、物理気相成長（ＰＶＤ）法により形成すればよい。第２の膜１２４は、犠牲導電膜１２３へ拡散させた場合に、犠牲導電膜１２３のエッチング特性を変化させることができる第２の金属を含む材料により形成すればよい。 Next, as shown in FIG. 2, a base film (not shown), a high dielectric film 121, a first film 122, a sacrificial conductive film 123 and a second film 124 are sequentially formed on the entire surface of the semiconductor substrate 101. To do. The base film may be a silicon oxide film (SiO 2 ) film having a thickness of about 1.1 nm. The high dielectric film 121 may be a nitrogen-containing hafnium silicate (HfSiON) film having a thickness of about 1.7 nm. The high dielectric film 121 may be formed by an atomic layer deposition (ALD) method. The high dielectric film 121 may be a hafnium oxide (HfO 2 ) film or a hafnium silicate (HfSiO x ) film instead of the HfSiON film. In addition to this, a high dielectric material such as a metal oxide, metal oxynitride, nitride or nitrogen-containing nitride having a relative dielectric constant of 8 or more may be used. The first film 122 may be an aluminum oxide (Al 2 O 3 ) film having a thickness of about 0.5 nm. The first film 122 is not limited to the Al 2 O 2 film, and may be formed of a material containing a first metal that increases the effective work function of the transistor when diffused into the high dielectric film 121. The sacrificial conductive film 123 may be a titanium nitride (TiN) film having a thickness of about 10 nm. The sacrificial conductive film 123 may be formed by an ALD method. The sacrificial conductive film 123 is not limited to a TiN film, and may be a tungsten (W) film, a tungsten nitride (WN) film, or the like. The second film 124 may be a lanthanum oxide (La 2 O 3 ) film having a thickness of 5 nm, for example. The second film 124 may be formed by a physical vapor deposition (PVD) method. The second film 124 may be formed of a material containing a second metal that can change the etching characteristics of the sacrificial conductive film 123 when diffused into the sacrificial conductive film 123.
　次に、図３に示すように、第２の膜１２４におけるＮ－ＭＩＳＦＥＴ形成領域１０１Ｎに形成された部分を選択的に除去する。具体的には、まず犠牲導電膜１２３の上に、Ｎ－ＭＩＳＦＥＴ形成領域１０１Ｎを露出し、Ｐ－ＭＩＳＦＥＴ形成領域１０１Ｐを覆うレジストパターン１５１をフォトリソグラフィ法により形成する。続いて、レジストパターン１５１をマスクとして、第１の薬液を用いたウェットエッチングにより、第２の膜１２４におけるＮ－ＭＩＳＦＥＴ形成領域１０１Ｎに形成された部分を除去する。第１の薬液はｐＨをｐＨ４．０～４．９程度に調整した酸化剤を含まない弱酸性薬液とすればよい。例えば、３６質量％の塩酸と水とを１対５０００００の体積比率で混合した塩酸水溶液を用いればよい。この場合ｐＨは４．６程度となる。 Next, as shown in FIG. 3, the portion of the second film 124 formed in the N-MISFET formation region 101N is selectively removed. Specifically, first, a resist pattern 151 that exposes the N-MISFET formation region 101N and covers the P-MISFET formation region 101P is formed on the sacrificial conductive film 123 by photolithography. Subsequently, using the resist pattern 151 as a mask, the portion formed in the N-MISFET formation region 101N in the second film 124 is removed by wet etching using the first chemical solution. The first chemical solution may be a weakly acidic chemical solution that does not contain an oxidant and has a pH adjusted to about 4.0 to 4.9. For example, a hydrochloric acid aqueous solution in which 36% by mass of hydrochloric acid and water are mixed at a volume ratio of 1: 500000 may be used. In this case, the pH is about 4.6.
　次に、図４に示すように、シンナー及び水酸化テトラメチルアンモニウム（ＴＭＡＨ）からなる現像液を用いてレジストパターン１５１を除去した後、第２の膜１２４に含まれるＬａを犠牲導電膜１２３の上部に拡散させる。これにより、犠牲導電膜１２３におけるＰ－ＭＩＳＦＥＴ形成領域１０１Ｐに形成された部分の上部にＬａを含む犠牲導電膜１２３ａが形成される。その後、未拡散の第２の膜１２４を除去する。Ｌａの拡散は熱処理により行えばよく、熱処理温度は６００℃程度とし、処理時間は１０分程度とすればよい。なお、熱処理温度は、５００℃～７００℃程度であればよく、処理時間は５分～１０分程度であればよい。なお、熱処理の条件によっては第１の膜１２２に含まれるＡｌが高誘電体膜１２１の上部に拡散するが問題ない。未拡散の第２の膜１２４の除去は、ウェットエッチングにより行えばよい。エッチング溶液は、ｐＨを１以下に調整した酸化剤を含まない強酸性薬液とすればよい。例えば、３６質量％の塩酸と水とを１対５０の体積比で混合した塩酸水溶液とすればよい。第２の膜１２４の膜厚及び熱処理条件等によっては、第２の膜１２４が全て拡散し、残存しない場合もある。この場合には未拡散の第２の膜１２４の除去を行わなくてもよい。 Next, as shown in FIG. 4, after removing the resist pattern 151 using a developer composed of thinner and tetramethylammonium hydroxide (TMAH), La contained in the second film 124 is removed from the sacrificial conductive film 123. Spread on top. As a result, a sacrificial conductive film 123a containing La is formed above the portion of the sacrificial conductive film 123 formed in the P-MISFET formation region 101P. Thereafter, the undiffused second film 124 is removed. La may be diffused by heat treatment, the heat treatment temperature may be about 600 ° C., and the treatment time may be about 10 minutes. The heat treatment temperature may be about 500 ° C. to 700 ° C., and the treatment time may be about 5 minutes to 10 minutes. Note that although Al contained in the first film 122 diffuses into the upper portion of the high dielectric film 121 depending on the heat treatment conditions, there is no problem. The undiffused second film 124 may be removed by wet etching. The etching solution may be a strongly acidic chemical solution that does not contain an oxidizing agent whose pH is adjusted to 1 or less. For example, a hydrochloric acid aqueous solution in which 36% by mass of hydrochloric acid and water are mixed at a volume ratio of 1:50 may be used. Depending on the thickness of the second film 124, the heat treatment conditions, and the like, the second film 124 may be completely diffused and may not remain. In this case, the undiffused second film 124 may not be removed.
　次に、図５に示すように、犠牲導電膜１２３及び第１の膜１２２におけるＮ－ＭＩＳＦＥＴ形成領域１０１Ｎに形成された部分をそれぞれ第２の薬液及び第３の薬液を用いたウェットエッチングにより除去する。第２の薬液は、ｐＨを６～８程度に調整した酸化剤を含む中性溶液とすればよい。例えば、５質量％～３０質量％の濃度の過酸化水素水を用いればよい。Ｌａを含む犠牲導電膜１２３ａは、ｐＨを６～８に調整した酸化剤を含む中性溶液に耐性を有する。このため、Ｌａを含む犠牲導電膜１２３ａがハードマスクとなり、犠牲導電膜１２３におけるＮ－ＭＩＳＦＥＴ形成領域１０１Ｎに形成された部分を選択的に除去することができる。第３の薬液は、ｐＨを１以下に調整した酸化剤を含まない強酸性溶液とすればよい。例えば、３６質量％の塩酸と水とを１対５０の体積比で混合した塩酸水溶液を用いればよい。ｐＨを１以下に調整した酸化剤を含まない強酸性溶液を用いたウェットエッチングの場合、ＨｆＳｉＯＮのエッチングレートに対するＡｌ2Ｏ3のエッチングレートの比は１００００以上となる。このため、高誘電体膜１２１をエッチングすることなく、第１の膜１２２を選択的に除去することが容易にできる。なお、高誘電体膜１２１の上部にＡｌが拡散している場合には、拡散したＡｌも問題にならない程度まで除去される。 Next, as shown in FIG. 5, portions of the sacrificial conductive film 123 and the first film 122 formed in the N-MISFET formation region 101N are removed by wet etching using the second chemical solution and the third chemical solution, respectively. To do. The second chemical solution may be a neutral solution containing an oxidizing agent whose pH is adjusted to about 6-8. For example, hydrogen peroxide having a concentration of 5% by mass to 30% by mass may be used. The sacrificial conductive film 123a containing La is resistant to a neutral solution containing an oxidizing agent whose pH is adjusted to 6-8. For this reason, the sacrificial conductive film 123a containing La serves as a hard mask, and a portion of the sacrificial conductive film 123 formed in the N-MISFET formation region 101N can be selectively removed. The third chemical solution may be a strongly acidic solution that does not contain an oxidizing agent whose pH is adjusted to 1 or less. For example, a hydrochloric acid aqueous solution in which 36% by mass of hydrochloric acid and water are mixed at a volume ratio of 1:50 may be used. In the case of wet etching using a strongly acidic solution that does not contain an oxidant whose pH is adjusted to 1 or less, the ratio of the etching rate of Al 2 O 3 to the etching rate of HfSiON is 10,000 or more. Therefore, it is possible to easily remove the first film 122 without etching the high dielectric film 121. Note that when Al diffuses in the upper portion of the high dielectric film 121, the diffused Al is also removed to the extent that does not cause a problem.
　次に、図６に示すように、半導体基板１０１上の全面に第３の膜１２５を形成する。第３の膜１２５は、膜厚が２ｎｍ程度のＬａ2Ｏ3膜とすればよい。第３の膜１２５は、Ｌａ2Ｏ3に限らず、高誘電体膜１２１へ拡散させた場合に、トランジスタの実効関数を低くする金属を含む材料により形成すればよい。第３の膜は、ＰＶＤ法により形成すればよい。 Next, as shown in FIG. 6, a third film 125 is formed on the entire surface of the semiconductor substrate 101. The third film 125 may be a La 2 O 3 film having a thickness of about 2 nm. The third film 125 is not limited to La 2 O 3 and may be formed of a material containing a metal that lowers the effective function of the transistor when diffused into the high dielectric film 121. The third film may be formed by a PVD method.
　次に、図７に示すように、半導体基板１０１に対して例えば６５０℃で１０分間の熱処理を行う。これにより、Ｎ－ＭＩＳＦＥＴ形成領域１０１Ｎにおいては第３の膜に含まれるＬａが高誘電体膜へ拡散し、Ｌａを含む高誘電体膜１２１ａが形成される。一方、Ｐ－ＭＩＳＦＥＴ形成領域１０１Ｐにおいては、第１の膜に含まれるＡｌが高誘電体膜へ拡散し、Ａｌを含む高誘電体膜１２１ｂが形成される。図７においては、第１の膜１２２が完全に拡散して消滅した状態を示しているが、熱処理条件によっては未反応の第１の膜１２２が残存することもある。また、第３の膜に含まれるＬａが犠牲導電膜１２３へ拡散し、Ｌａを含む犠牲導電膜１２３ａのＬａ濃度が上昇する。なお、熱処理は６００℃～７００℃の温度で５分～１０分程度行えばよい。 Next, as shown in FIG. 7, the semiconductor substrate 101 is heat-treated at, for example, 650 ° C. for 10 minutes. Thereby, in the N-MISFET formation region 101N, La contained in the third film diffuses into the high dielectric film, and a high dielectric film 121a containing La is formed. On the other hand, in the P-MISFET formation region 101P, Al contained in the first film diffuses into the high dielectric film, and a high dielectric film 121b containing Al is formed. Although FIG. 7 shows a state in which the first film 122 is completely diffused and disappeared, the unreacted first film 122 may remain depending on heat treatment conditions. Further, La contained in the third film diffuses into the sacrificial conductive film 123, and the La concentration of the sacrificial conductive film 123a containing La increases. Note that the heat treatment may be performed at a temperature of 600 ° C. to 700 ° C. for about 5 minutes to 10 minutes.
　次に、図８に示すように、未拡散の第３の膜と、Ｌａが拡散した犠牲導電膜１２３ａ及び犠牲導電膜１２３とをそれぞれ第４の薬液及び第５の薬液を用いたウェットエッチングにより除去する。第４の薬液は、ｐＨを２～４程度に調整した酸化剤を含まない酸性溶液とすればよい。例えば、３６質量％の塩酸と水とを１対２０００の体積比率で混合した塩酸水溶液とすればよい。第５の薬液は、ｐＨを２～４程度に調整した酸化剤を含む酸性溶液とすればよい。例えば、３６質量％の塩酸と３１質量％の過酸化水素水とを１対２０００の堆積比率で混合した溶液を用いればよい。酸化剤である過酸化水素の濃度は、１質量％以上であることが好ましい。 Next, as shown in FIG. 8, the undiffused third film and the sacrificial conductive film 123a and sacrificial conductive film 123 in which La is diffused are wet-etched using the fourth chemical solution and the fifth chemical solution, respectively. Remove. The fourth chemical solution may be an acidic solution that does not contain an oxidant having a pH adjusted to about 2 to 4. For example, a hydrochloric acid aqueous solution in which 36% by mass of hydrochloric acid and water are mixed at a volume ratio of 1: 2000 may be used. The fifth chemical solution may be an acidic solution containing an oxidizing agent whose pH is adjusted to about 2 to 4. For example, a solution in which 36% by mass hydrochloric acid and 31% by mass hydrogen peroxide water are mixed at a deposition ratio of 1: 2000 may be used. The concentration of hydrogen peroxide as the oxidizing agent is preferably 1% by mass or more.
　次に、図９に示すように、半導体基板１０１上の全面に、膜厚が１５ｎｍのＴｉＮ膜１２８と膜厚が９０ｎｍのシリコン膜１２９とをＡＬＤ法等により形成する。シリコン膜１２９は、ポリシリコン膜であってもアモルファスシリコン膜であってもよい。 Next, as shown in FIG. 9, a TiN film 128 having a thickness of 15 nm and a silicon film 129 having a thickness of 90 nm are formed on the entire surface of the semiconductor substrate 101 by an ALD method or the like. The silicon film 129 may be a polysilicon film or an amorphous silicon film.
　次に、レジストパターンを用いたドライエッチングにより、シリコン膜１２９、ＴｉＮ膜１２８、Ｌａを含む高誘電体膜１２１ａ、Ａｌを含む高誘電体膜１２１ｂ及び下地膜（図示せず）をパターニングする。これにより、図１０に示すように、Ｎ－ＭＩＳＦＥＴ形成領域１０１Ｎに、ＴｉＮ膜１２８及びシリコン膜１２９が積層された第１のゲート電極１３０ａと、Ｌａを含む高誘電体膜１２１ａと下地膜（図示せず）とを有する第１のゲート絶縁膜が形成される。Ｐ－ＭＩＳＦＥＴ形成領域１０１Ｐに、ＴｉＮ膜１２８及びシリコン膜１２９が積層された第２のゲート電極１３０ｂと、Ａｌを含む高誘電体膜１２１ｂと下地膜（図示せず）とを有する第２のゲート絶縁膜が形成される。 Next, the silicon film 129, the TiN film 128, the high dielectric film 121a containing La, the high dielectric film 121b containing Al, and the base film (not shown) are patterned by dry etching using a resist pattern. As a result, as shown in FIG. 10, the first gate electrode 130a in which the TiN film 128 and the silicon film 129 are stacked in the N-MISFET formation region 101N, the high dielectric film 121a containing La, and the base film (FIG. A first gate insulating film is formed. A second gate electrode 130b in which a TiN film 128 and a silicon film 129 are stacked in a P-MISFET formation region 101P, a high dielectric film 121b containing Al, and a base film (not shown). An insulating film is formed.
　Ｎ－ＭＩＳＦＥＴ形成領域１０１Ｎにおけるゲートエッチング時間は、下地膜は無視できるとするとシリコン膜１２９、ＴｉＮ膜１２８及び高誘電体膜１２１ａをエッチングするのに要する時間である。同様に、Ｐ－ＭＩＳＦＥＴ形成領域１０１Ｐにおけるゲートエッチング時間は、シリコン膜１２９、ＴｉＮ膜１２８及び高誘電体膜１２１ｂをエッチングするのに要する時間である。本実施形態の半導体装置の製造方法によれば、半導体基板１０１におけるｐ型ウェル１０２ａ及びｎ型ウェル１０２ｂの表面からシリコン膜１２９の表面までの高さは、Ｎ－ＭＩＳＦＥＴ形成領域１０１ＮとＰ－ＭＩＳＦＥＴ形成領域１０１Ｐとにおいてほぼ等しくなる。このため、シリコン膜１２９の上にゲート電極を形成するためのレジストパターンを形成し、Ｎ－ＭＩＳＦＥＴ形成領域１０１ＮとＰ－ＭＩＳＦＥＴ形成領域１０１Ｐとにおいてゲートエッチングを同時に行う場合、ゲートエッチング時間はＮ－ＭＩＳＦＥＴ形成領域１０１ＮとＰ－ＭＩＳＦＥＴ形成領域１０１Ｐとでほぼ等しくなる。 The gate etching time in the N-MISFET formation region 101N is a time required to etch the silicon film 129, the TiN film 128, and the high dielectric film 121a if the base film can be ignored. Similarly, the gate etching time in the P-MISFET formation region 101P is the time required to etch the silicon film 129, the TiN film 128, and the high dielectric film 121b. According to the semiconductor device manufacturing method of the present embodiment, the height from the surface of the p-type well 102a and the n-type well 102b to the surface of the silicon film 129 in the semiconductor substrate 101 is such that the N-MISFET formation region 101N and the P-MISFET It becomes substantially equal in the formation region 101P. Therefore, when a resist pattern for forming a gate electrode is formed on the silicon film 129 and gate etching is simultaneously performed in the N-MISFET formation region 101N and the P-MISFET formation region 101P, the gate etching time is N− The MISFET formation region 101N and the P-MISFET formation region 101P are substantially equal.
　Ｎ－ＭＩＳＦＥＴ形成領域１０１ＮとＰ－ＭＩＳＦＥＴ形成領域１０１Ｐとにおいてゲートエッチング時間が異なる場合には、先にゲート絶縁膜までのエッチングが終了した方の領域は、もう一方のゲートエッチングが終了するまでウェルの表面がエッチングされ続ける。これにより、トランジスタの特性劣化が生じるおそれがある。本実施形態の半導体装置の製造方法においては、このような問題についても解決できるという利点がある。 When the gate etching time differs between the N-MISFET formation region 101N and the P-MISFET formation region 101P, the region where the etching to the gate insulating film has been completed first is the well until the other gate etching is completed. The surface of the film continues to be etched. As a result, the characteristics of the transistor may be deteriorated. The semiconductor device manufacturing method of this embodiment has an advantage that such a problem can be solved.
　次に、第１のゲート電極１３０ａの側面上に第１のオフセットスペーサ１３１ａを形成し、第２のゲート電極１３０ｂの側面上に第２のオフセットスペーサ１３１ｂを形成する。第１のゲート電極１３０ａ及び第１のオフセットスペーサ１３１ａをマスクとして第１の活性領域１０１ａに不純物を注入しｎ型エクステンション領域１４１ａを形成する。また、第２のゲート電極１３０ｂ及び第２のオフセットスペーサ１３１ｂをマスクとして第２の活性領域１０１ｂに不純物を注入しｐ型エクステンション領域１４１ｂを形成する。その後、第１のオフセットスペーサ１３１ａの側面上及び第２のオフセットスペーサ１３１ｂの側面上に、それぞれ第１のサイドウォール１３３ａ及び第２のサイドウォール１３３ｂを形成する。第１のサイドウォール１３３ａはＬ字状の第１の内側サイドウォール１３４ａ及び第１の外側サイドウォール１３５ａを有し、第２のサイドウォール１３３ｂはＬ字状の第２の内側サイドウォール１３４ｂ及び第２の外側サイドウォール１３５ｂを有する。続いて、第１のゲート電極１３０ａ、第１のオフセットスペーサ１３１ａ及び第１のサイドウォール１３３ａをマスクとして第１の活性領域１０１ａに不純物を注入し、ｎ型ソースドレイン領域１４２ａを形成する。また、第２のゲート電極１３０ｂ、第２のオフセットスペーサ１３１ｂ及び第２のサイドウォール１３３ｂをマスクとして第２の活性領域１０１ｂに不純物を注入し、ｐ型ソースドレイン領域１４２ｂを形成する。続いて、第１のゲート電極１３０ａ、第２のゲート電極１３０ｂ、ｎ型ソースドレイン領域１４２ａ及びｐ型ソースドレイン領域１４２ｂの上部に、それぞれニッケルシリサイド等からなるシリサイド層１３８を形成する。これにより、図１１に示すように、Ｎ－ＭＩＳＦＥＴとＰ－ＭＩＳＦＥＴとを有する半導体装置が得られる。 Next, the first offset spacer 131a is formed on the side surface of the first gate electrode 130a, and the second offset spacer 131b is formed on the side surface of the second gate electrode 130b. Impurities are implanted into the first active region 101a using the first gate electrode 130a and the first offset spacer 131a as a mask to form an n-type extension region 141a. Further, an impurity is implanted into the second active region 101b using the second gate electrode 130b and the second offset spacer 131b as a mask to form a p-type extension region 141b. After that, the first sidewall 133a and the second sidewall 133b are formed on the side surface of the first offset spacer 131a and the side surface of the second offset spacer 131b, respectively. The first side wall 133a has an L-shaped first inner side wall 134a and a first outer side wall 135a, and the second side wall 133b has an L-shaped second inner side wall 134b and a first outer side wall 134b. 2 outer sidewalls 135b. Subsequently, an impurity is implanted into the first active region 101a using the first gate electrode 130a, the first offset spacer 131a, and the first sidewall 133a as a mask to form an n-type source / drain region 142a. Further, an impurity is implanted into the second active region 101b using the second gate electrode 130b, the second offset spacer 131b, and the second sidewall 133b as a mask to form a p-type source / drain region 142b. Subsequently, silicide layers 138 made of nickel silicide or the like are formed on the first gate electrode 130a, the second gate electrode 130b, the n-type source / drain region 142a, and the p-type source / drain region 142b, respectively. As a result, as shown in FIG. 11, a semiconductor device having an N-MISFET and a P-MISFET can be obtained.
　図１２は、本実施形態の半導体装置の製造方法により得られた半導体装置の平面構成を示している。図１３は図１２のXIII－XIII線における断面構成を示している。なお、図１１は、図１２のXI－XI線における断面構成に相当する。 FIG. 12 shows a planar configuration of the semiconductor device obtained by the semiconductor device manufacturing method of the present embodiment. FIG. 13 shows a cross-sectional structure taken along line XIII-XIII in FIG. Note that FIG. 11 corresponds to a cross-sectional configuration taken along line XI-XI in FIG.
　本実施形態の半導体装置の製造方法は、図１１及び図１３に示すように、Ｎ－ＭＩＳＦＥＴとＰ－ＭＩＳＦＥＴとの高さを同じにすることができるため、ドライエッチングを用いたゲート電極のパターニングにおいて、パターン寸法制御が容易であるという利点を有している。また、Ｎ－ＭＩＳＦＥＴ形成領域１０１ＮとＰ－ＭＩＳＦＥＴ形成領域１０１Ｐとの両方において、ゲート電極及びサイドウォール形成時のオーバーエッチングにかかる時間を等しくすることができる。このため、基板及び素子分離領域に段差が形成されにくいという利点も有している。 In the method of manufacturing the semiconductor device of this embodiment, as shown in FIGS. 11 and 13, since the height of the N-MISFET and the P-MISFET can be made the same, patterning of the gate electrode using dry etching is performed. However, it has the advantage that pattern dimension control is easy. Further, in both the N-MISFET formation region 101N and the P-MISFET formation region 101P, the time required for overetching when forming the gate electrode and the sidewall can be made equal. For this reason, there is an advantage that a step is hardly formed in the substrate and the element isolation region.
　本実施形態に係る半導体装置の製造方法は、Ｐ－ＭＩＳＦＥＴ形成領域を覆うマスクとして犠牲導電膜１２３を用いている。このため、第３の膜を形成する際にレジスト膜が存在せず、レジスト膜によるパーティクルの発生及び異常成長は生じない。また、ＰＭＩＳＦＥＴ形成領域において犠牲導電膜１２３の上部にＬａが拡散した犠牲導電膜１２３ａを形成しており、Ｎ－ＭＩＳＦＥＴ形成領域において非常に選択性良く犠牲導電膜１２３を除去することができる。このため、Ｎ－ＭＩＳＦＥＴ形成領域において高誘電体膜がエッチングされるおそれがほとんどない。従って、Ｎ－ＭＩＳＦＥＴ形成領域及びＰＭＩＳＦＥＴ形成領域のそれぞれに、最適な特性を有するゲート絶縁膜を再現性良く形成することが可能となる。 The method for manufacturing a semiconductor device according to the present embodiment uses the sacrificial conductive film 123 as a mask covering the P-MISFET formation region. For this reason, the resist film does not exist when the third film is formed, and generation of particles and abnormal growth due to the resist film do not occur. Further, a sacrificial conductive film 123a in which La diffuses is formed on the sacrificial conductive film 123 in the PMISFET formation region, and the sacrificial conductive film 123 can be removed with very high selectivity in the N-MISFET formation region. Therefore, there is almost no possibility that the high dielectric film is etched in the N-MISFET formation region. Therefore, it is possible to form a gate insulating film having optimum characteristics with good reproducibility in each of the N-MISFET formation region and the PMISFET formation region.
　図７において、高誘電体膜１２１中にＬａが均一に拡散してＬａを含む高誘電体膜１２１ａが形成される例を示した。しかし、熱処理条件によっては、高誘電体膜１２１ａ中においてＬａ濃度が均一とならず、上部において下部よりもＬａ濃度が高い状態が生じたり、下部において上部よりもＬａ濃度が高い状態が生じたりする。また、Ｌａ濃度が異なる複数の層が形成される場合もある。また、図７では、熱処理後に第３の膜１２５が残存している例を示したが、第３の膜１２５の膜厚及び熱処理条件等によっては、熱処理後に第３の膜１２５が消失する場合も生じる。 FIG. 7 shows an example in which La is uniformly diffused in the high dielectric film 121 and the high dielectric film 121a containing La is formed. However, depending on the heat treatment conditions, the La concentration in the high dielectric film 121a may not be uniform, and the upper portion may have a higher La concentration than the lower portion, or the lower portion may have a higher La concentration than the upper portion. . In addition, a plurality of layers having different La concentrations may be formed. FIG. 7 shows an example in which the third film 125 remains after the heat treatment, but the third film 125 disappears after the heat treatment depending on the thickness of the third film 125, heat treatment conditions, and the like. Also occurs.
　同様に、Ａｌを含む高誘電体膜１２１ｂ中においてＡｌ濃度が均一とならず、上部において下部よりもＡｌ濃度が高い状態が生じたり、下部において上部よりもＡｌ濃度が高い状態が生じたり、Ａｌ濃度が異なる複数の層が形成されたりする。また、図７では、熱処理後に第１の膜１２２が消失する例を示したが、第１の膜１２２の膜厚及び熱処理条件等によっては、高誘電体膜１２１ｂと犠牲導電膜１２３との間に第１の膜１２２が残存する場合も生じる。第１の膜１２２が残存する場合には、犠牲導電膜１２３を除去する際に第１の膜１２２の残存する部分も除去すればよい。また、第１の膜１２２の残存する部分を除去しなくてもよい。この場合、エクステンション領域、ソースドレイン領域及びシリサイド層の形成工程等において行う熱処理によって、第１の膜１２２の残存する部分は高誘電体膜１２１中に拡散する。さらに、Ｎ－ＭＩＳＦＥＴ形成領域１０１Ｎにおいて未拡散の第３の膜１２５は、完全に除去できなくてもよい。この場合にも、後の熱処理工程により第３の膜１２５の残存する部分は高誘電体膜１２１中に拡散する。但し、高誘電体膜１２１中へＬａの拡散を正確に制御するという観点からは、第３の膜１２５の除去を十分に行うことが好ましい。 Similarly, in the high dielectric film 121b containing Al, the Al concentration is not uniform, and the upper portion has a higher Al concentration than the lower portion, or the lower portion has a higher Al concentration than the upper portion. A plurality of layers having different concentrations may be formed. FIG. 7 shows an example in which the first film 122 disappears after the heat treatment. However, depending on the film thickness of the first film 122, heat treatment conditions, and the like, the gap between the high dielectric film 121b and the sacrificial conductive film 123 is increased. In some cases, the first film 122 may remain. In the case where the first film 122 remains, the remaining portion of the first film 122 may be removed when the sacrificial conductive film 123 is removed. Further, the remaining portion of the first film 122 may not be removed. In this case, the remaining portion of the first film 122 is diffused into the high dielectric film 121 by heat treatment performed in the process of forming the extension region, the source / drain region, and the silicide layer. Further, the undiffused third film 125 in the N-MISFET formation region 101N may not be completely removed. Also in this case, the remaining portion of the third film 125 is diffused into the high dielectric film 121 by the subsequent heat treatment process. However, from the viewpoint of accurately controlling the diffusion of La into the high dielectric film 121, it is preferable to sufficiently remove the third film 125.
　本実施形態は、高誘電体膜１２１と半導体基板１０１との間に下地膜（図示せず）を形成する例を示したが、下地膜は形成しなくてもよい。また、高誘電体膜１２１ａを有する第１のゲート絶縁膜及び高誘電体膜１２１ｂを有する第２のゲート絶縁膜の少なくとも一方と半導体基板１０１との間に下地膜が存在する構成としてもよい。 In the present embodiment, an example in which a base film (not shown) is formed between the high dielectric film 121 and the semiconductor substrate 101 is shown, but the base film may not be formed. Alternatively, a base film may be provided between at least one of the first gate insulating film having the high dielectric film 121 a and the second gate insulating film having the high dielectric film 121 b and the semiconductor substrate 101.
　第３の膜１２５は、Ｌａ2Ｏ3に代えて、Ｌａ以外のランタノイド、スカンジウム（Ｓｃ）、ストロンチウム（Ｓｒ）又はマグネシウム（Ｍｇ）等を含む膜としてもよい。第３の膜１２５は酸化膜に限らず、これらの金属元素を含む膜であればよい。また、化合物となっていない金属膜であってもよい。同様に第１の膜１２２は、Ａｌ2Ｏ3に代えて、Ｔａ2Ｏ3としてもよい。また、酸化膜に限らずＡｌ又はＴａを含む膜であればよく、Ａｌ膜又はＴａ膜であってもよい。第１の膜１２２及び第３の膜１２５はそれ自身が絶縁膜である必要はなく、第１の膜１２２及び第３の膜１２５に含まれる金属元素が拡散した高誘電体膜が絶縁性を示せばよい。 The third film 125 may be a film containing a lanthanoid other than La, scandium (Sc), strontium (Sr), magnesium (Mg), or the like instead of La 2 O 3 . The third film 125 is not limited to an oxide film, and may be any film containing these metal elements. Moreover, the metal film which is not a compound may be sufficient. Similarly, the first film 122 may be Ta 2 O 3 instead of Al 2 O 3 . Further, the film is not limited to an oxide film, and may be a film containing Al or Ta, and may be an Al film or a Ta film. The first film 122 and the third film 125 do not need to be insulating films themselves, and the high dielectric film in which the metal element contained in the first film 122 and the third film 125 diffuses has an insulating property. Show it.
　なお、メタルゲートの形成について説明したが、犠牲導電膜と第２の膜とを組み合わせてハードマスクを選択的にウェットエッチングする方法は、低誘電率膜を層間絶縁膜とするＣｕ配線の形成工程、非シリサイド形成工程及び注入レジスト代替マスクの形成工程等に用いることができる。 Although the formation of the metal gate has been described, the method of selectively wet-etching the hard mask by combining the sacrificial conductive film and the second film is a process for forming a Cu wiring using a low dielectric constant film as an interlayer insulating film. It can be used for a non-silicide formation process, an implantation resist substitute mask formation process and the like.
　本開示の半導体装置の製造方法は、所定の安定した特性を有するＮ－ＭＩＳＦＥＴとＰ－ＭＩＳＦＥＴとを備えた半導体装置を容易に実現でき、特に高誘電体材料を含むゲート絶縁膜及び金属膜を含むゲート電極を備えた半導体装置の製造方法等として有用である。 The method for manufacturing a semiconductor device according to the present disclosure can easily realize a semiconductor device including an N-MISFET and a P-MISFET having predetermined stable characteristics, and particularly includes a gate insulating film and a metal film including a high dielectric material. This is useful as a method for manufacturing a semiconductor device including a gate electrode.
１０１　　　半導体基板
１０１Ｎ　　Ｎ－ＭＩＳＦＥＴ形成領域
１０１Ｐ　　Ｐ－ＭＩＳＦＥＴ形成領域
１０１ａ　　第１の活性領域
１０１ｂ　　第２の活性領域
１０２ａ　　ｐ型ウェル
１０２ｂ　　ｎ型ウェル
１１１　　　素子分離領域
１２１　　　高誘電体膜
１２１ａ　　第１のゲート絶縁膜
１２１ｂ　　第２のゲート絶縁膜
１２２　　　第１の膜
１２３　　　犠牲導電膜
１２３ａ　　犠牲導電膜
１２４　　　第２の膜
１２５　　　第３の膜
１２８　　　ＴｉＮ膜
１２９　　　シリコン膜
１３０ａ　　第１のゲート電極
１３０ｂ　　第２のゲート電極
１３１ａ　　第１のオフセットスペーサ
１３１ｂ　　第２のオフセットスペーサ
１３３ａ　　第１のサイドウォール
１３３ｂ　　第２のサイドウォール
１３４ａ　　第１の内側サイドウォール
１３４ｂ　　第２の内側サイドウォール
１３５ａ　　第１の外側サイドウォール
１３５ｂ　　第２の外側サイドウォール
１３８　　　シリサイド層
１４１ａ　　ｎ型エクステンション領域
１４１ｂ　　ｐ型エクステンション領域
１４２ａ　　ｎ型ソースドレイン領域
１４２ｂ　　ｐ型ソースドレイン領域
１５１　　　レジストパターン 101 semiconductor substrate 101N N-MISFET formation region 101P P-MISFET formation region 101a first active region 101b second active region 102a p-type well 102b n-type well 111 element isolation region 121 high dielectric film 121a first gate insulation Film 121b second gate insulating film 122 first film 123 sacrificial conductive film 123a sacrificial conductive film 124 second film 125 third film 128 TiN film 129 silicon film 130a first gate electrode 130b second gate electrode 131a First offset spacer 131b Second offset spacer 133a First sidewall 133b Second sidewall 134a First inner sidewall 134b Second inner sidewall 135a First outer sidewall 135b Second outer side wall 138 Silicide layer 141a n-type extension region 141b p-type extension region 142a n-type source / drain region 142b p-type source / drain region 151 resist pattern

Claims (12)

  1. 　半導体基板に、第１の素子形成領域及び第２の素子形成領域を形成する工程（ａ）と、
    　半導体基板上の全面に高誘電体膜と、第１の金属元素を含む第１の膜と、犠牲導電膜と、第２の金属元素を含む第２の膜とを順次形成する工程（ｂ）と、
    　前記第２の膜における前記第１の素子形成領域の上に形成された部分を第１の薬液を用いて選択的に除去する工程（ｃ）と、
    　前記工程（ｃ）よりも後で、前記第２の金属元素を前記犠牲導電膜における前記第２の素子形成領域の上に形成された部分に拡散させる工程（ｄ）と、
    　前記工程（ｄ）よりも後で、前記犠牲導電膜及び第１の膜における前記第１の素子形成領域の上に形成された部分を、それぞれ第２の薬液及び第３の薬液を用いて選択的に除去し、前記第１の素子形成領域において前記高誘電体膜を露出させる工程（ｅ）と、
    　前記工程（ｅ）よりも後で、前記半導体基板上の全面に第３の金属元素を有する第３の膜を形成する工程（ｆ）と、
    　前記工程（ｆ）よりも後で、前記第３の金属元素を前記高誘電体膜中に拡散させる工程（ｇ）と、
    　前記第３の膜及び前記犠牲導電膜の残存部分をそれぞれ第４の薬液及び第５の薬液を用いて除去する工程（ｈ）と、
    　前記（ｈ）よりも後で、前記半導体基板上の全面に電極膜を形成する工程（ｉ）と、
    　前記電極膜及び前記高誘電体膜を選択的に除去することにより、前記第１の素子形成領域に、前記第３の金属元素を含む第１のゲート絶縁膜と、前記電極膜からなる第１のゲート電極とを形成し、前記第２の素子形成領域に、前記第１の金属元素を含む第２のゲート絶縁膜と、前記電極膜からなる第２のゲート電極とを形成する工程（ｊ）とを備えていることを特徴とする半導体装置の製造方法。     A step (a) of forming a first element formation region and a second element formation region on a semiconductor substrate;
    (B) sequentially forming a high dielectric film, a first film containing a first metal element, a sacrificial conductive film, and a second film containing a second metal element on the entire surface of the semiconductor substrate. When,
    A step (c) of selectively removing a portion of the second film formed on the first element formation region using a first chemical solution;
    A step (d) of diffusing the second metal element into a portion of the sacrificial conductive film formed on the second element formation region after the step (c);
    After the step (d), the portions formed on the first element formation region in the sacrificial conductive film and the first film are selected using the second chemical liquid and the third chemical liquid, respectively. Removing the high dielectric film in the first element formation region (e),
    After the step (e), a step (f) of forming a third film having a third metal element on the entire surface of the semiconductor substrate;
    A step (g) of diffusing the third metal element into the high dielectric film after the step (f);
    Removing the remaining portions of the third film and the sacrificial conductive film using a fourth chemical solution and a fifth chemical solution, respectively (h);
    A step (i) of forming an electrode film on the entire surface of the semiconductor substrate after (h);
    By selectively removing the electrode film and the high dielectric film, a first gate insulating film containing the third metal element in the first element formation region and a first electrode comprising the electrode film. Forming a second gate insulating film containing the first metal element and a second gate electrode comprising the electrode film in the second element formation region (j A method for manufacturing a semiconductor device.
  2. 　前記犠牲導電膜は、窒化チタン、タングステン又は窒化タングステンからなり、
    　前記第２の膜は、酸化ランタンからなることを特徴とする請求項１に記載の半導体装置の製造方法。     The sacrificial conductive film is made of titanium nitride, tungsten or tungsten nitride,
    The method for manufacturing a semiconductor device according to claim 1, wherein the second film is made of lanthanum oxide.
  3. 　前記工程（ｅ）では、前記第２の薬液としてｐＨを６以上且つ８以下に調整した、酸化剤を含む中性溶液を用いることを特徴とする請求項２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 2, wherein, in the step (e), a neutral solution containing an oxidizing agent having a pH adjusted to 6 or more and 8 or less is used as the second chemical solution.
  4. 　前記酸化剤を含む中性溶液は、５質量％以上且つ３０質量％以下の濃度の過酸化水素水であることを特徴とする請求項３に記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 3, wherein the neutral solution containing the oxidizing agent is hydrogen peroxide having a concentration of 5% by mass or more and 30% by mass or less.
  5. 　前記工程（ｅ）では、前記第３の薬液としてｐＨを１以下に調整した、酸化剤を含まない酸性溶液を用いることを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein, in the step (e), an acidic solution containing no oxidant and having a pH adjusted to 1 or less is used as the third chemical solution.
  6. 　前記工程（ｈ）では、
    　前記第４の薬液としてｐＨを２以上且つ４以下に調整した、酸化剤を含まない酸性溶液を用い、
    　前記第５の薬液としてｐＨを２以上且つ４以下に調整した酸化剤を含む酸性溶液を用いることを特徴とする請求項５に記載の半導体装置の製造方法。     In the step (h),
    As the fourth chemical solution, an acidic solution that is adjusted to pH 2 to 4 and does not contain an oxidizing agent is used.
    6. The method of manufacturing a semiconductor device according to claim 5, wherein an acidic solution containing an oxidizing agent whose pH is adjusted to 2 or more and 4 or less is used as the fifth chemical solution.
  7. 　前記工程（ｄ）よりも後で且つ前記工程（ｅ）よりも前に、前記第２の膜における前記犠牲導電膜の上に残存した部分を、ｐＨを１以下に調整した、酸化剤を含まない酸性溶液を用いて除去する工程（ｋ）をさらに備えていることを特徴とする請求項６に記載の半導体装置の製造方法。 The part which remained on the said sacrificial conductive film in the said 2nd film | membrane after the said process (d) and before the said process (e) contains the oxidizing agent which adjusted pH to 1 or less The method of manufacturing a semiconductor device according to claim 6, further comprising a step (k) of removing using a non-acidic solution.
  8. 　前記工程（ｃ）では、前記第１の薬液としてｐＨを４．０以上且つ４．９以下に調整した酸化剤を含まない酸性溶液を用いることを特徴とする請求項７に記載の半導体装置の製造方法。 8. The semiconductor device according to claim 7, wherein in the step (c), an acidic solution that does not contain an oxidant having a pH adjusted to 4.0 or more and 4.9 or less is used as the first chemical solution. 9. Production method.
  9. 　前記高誘電体膜は、比誘電率が８以上の金属酸化物、金属酸窒化物、硅化物又は窒素含有硅化物からなることを特徴とする請求項８に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 8, wherein the high dielectric film is made of a metal oxide, metal oxynitride, nitride, or nitrogen-containing nitride having a relative dielectric constant of 8 or more.
  10. 　前記第２の金属元素は、アルミニウム又はタンタルであることを特徴とする請求項９に記載の半導体装置の製造方法。 10. The method of manufacturing a semiconductor device according to claim 9, wherein the second metal element is aluminum or tantalum.
  11. 　前記第３の金属元素は、ランタン若しくはランタン以外のランタノイド、スカンジウム、ストロンチウム又はマグネシウムであることを特徴とする請求項１０に記載の半導体装置の製造方法。 11. The method of manufacturing a semiconductor device according to claim 10, wherein the third metal element is lanthanum or a lanthanoid other than lanthanum, scandium, strontium, or magnesium.
  12. 　前記電極膜は、窒化チタン膜とシリコン膜との積層膜であることを特徴とする請求項１１に記載の半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 11, wherein the electrode film is a laminated film of a titanium nitride film and a silicon film.
PCT/JP2010/006228 2010-02-23 2010-10-20 Method for manufacturing a semiconductor device WO2011104788A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010036978A JP2013084637A (en) 2010-02-23 2010-02-23 Manufacturing method of semiconductor device
JP2010-036978 2010-02-23

Publications (1)

Publication Number Publication Date
WO2011104788A1 true WO2011104788A1 (en) 2011-09-01

Family

ID=44506236

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/006228 WO2011104788A1 (en) 2010-02-23 2010-10-20 Method for manufacturing a semiconductor device

Country Status (2)

Country Link
JP (1) JP2013084637A (en)
WO (1) WO2011104788A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5548550B2 (en) * 2010-07-30 2014-07-16 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008166713A (en) * 2006-10-20 2008-07-17 Interuniv Micro Electronica Centrum Vzw Manufacturing method of semiconductor device with a plurality of dielectrics
JP2009194352A (en) * 2008-01-17 2009-08-27 Toshiba Corp Semiconductor device fabrication method
JP2009302260A (en) * 2008-06-12 2009-12-24 Panasonic Corp Semiconductor device and method for manufacturing the same
JP2010010199A (en) * 2008-06-24 2010-01-14 Panasonic Corp Semiconductor device and method of manufacturing the same
JP2010040710A (en) * 2008-08-04 2010-02-18 Panasonic Corp Semiconductor device and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008166713A (en) * 2006-10-20 2008-07-17 Interuniv Micro Electronica Centrum Vzw Manufacturing method of semiconductor device with a plurality of dielectrics
JP2009194352A (en) * 2008-01-17 2009-08-27 Toshiba Corp Semiconductor device fabrication method
JP2009302260A (en) * 2008-06-12 2009-12-24 Panasonic Corp Semiconductor device and method for manufacturing the same
JP2010010199A (en) * 2008-06-24 2010-01-14 Panasonic Corp Semiconductor device and method of manufacturing the same
JP2010040710A (en) * 2008-08-04 2010-02-18 Panasonic Corp Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JP2013084637A (en) 2013-05-09

Similar Documents

Publication Publication Date Title
JP4602440B2 (en) Semiconductor device and manufacturing method thereof
US8143676B2 (en) Semiconductor device having a high-dielectric-constant gate insulating film
US20070082445A1 (en) Metal-gate cmos device and fabrication method of making same
JP2009141168A (en) Semiconductor device and method of manufacturing the same
TW200820435A (en) Semiconductor devices with dual-metal gate structures and fabrication methods thereof
JP2009194352A (en) Semiconductor device fabrication method
JP2009224386A (en) Semiconductor device and method for manufacturing the same
JP2007251030A (en) Semiconductor device and method of manufacturing the same
KR20180059649A (en) Method of fabricating a semiconductor device
JP2013165191A (en) Semiconductor device and manufacturing method of the same
US20050285206A1 (en) Semiconductor device and manufacturing method thereof
JP2011029483A (en) Semiconductor device and method for manufacturing the same
JP2007036116A (en) Semiconductor device manufacturing method
JP5436362B2 (en) Semiconductor device
JP2010272596A (en) Method of manufacturing semiconductor device
US8471341B2 (en) Semiconductor device and method for fabricating the same
JP2006108355A (en) Semiconductor device and manufacturing method thereof
US20100133622A1 (en) Semiconductor device including MOSFET with controlled threshold voltage, and manufacturing method of the same
JP2007318015A (en) Semiconductor device and method of manufacturing the same
US8558321B2 (en) Semiconductor device having gate insulating film including high dielectric material
WO2011104788A1 (en) Method for manufacturing a semiconductor device
JP2008117842A (en) Semiconductor device, and method for manufacturing the same
JP4589219B2 (en) Manufacturing method of semiconductor device
JP2010010199A (en) Semiconductor device and method of manufacturing the same
JP2007287793A (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10846456

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10846456

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP