JP5684371B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a technology effective when applied to a semiconductor integrated circuit device and a threshold voltage control technology in a method of manufacturing a semiconductor integrated circuit device (or a semiconductor device).

  V. Narayanan other 25 people, "Band-Edge High-Performance high-k / Metal Gate n-MOSFETs using Cap Layers Containing Group IIA and IIIB Elemens with Gate-First Processing for 45nm and Beyond", 2006 Symposium on VLSI Technology Digest of Technical Papers (Non-Patent Document 1) includes an n-MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a High-k gate insulating film and a threshold voltage (more accurately, a p-MISFET). In order to reduce both of the absolute values in a balanced manner at the same time, a different kind of metal or metal oxide is formed on the High-k gate insulating film in each region, and the components are contained in the High-k gate insulating film. A technique to be introduced in is disclosed.

  T. T. et al. Morooka and 13 other people, "Suppression of Anomalous Threshold Voltage Increase with Area Scaling for Mg- or La-incorporated High-k / Metal Gate nMOSFETs in Deep Scaled Region", 2010 Symposium on VLSI Technology Digest of Technical Papers (Non-Patent Document 2) In order to control the threshold voltage of the n-MISFET and the p-MISFET, the concentration of the additive component introduced into the High-k gate insulating film is not lowered due to diffusion caused by subsequent high-temperature heat treatment or the like. −k Offset the gate insulating film processing edge. Technology to extend to the sidewall end portion is disclosed.

V. Narayanan other 25 people, "Band-Edge High-Performance high-k / Metal Gate n-MOSFETs using Cap Layers Containing Group IIA and IIIB Elemens with Gate-First Processing for 45nm and Beyond", 2006 Symposium on VLSI Technology Digest of Technical Papers T. T. et al. Morooka and 13 other people, "Suppression of Anomalous Threshold Voltage Increase with Area Scaling for Mg- or La-incorporated High-k / Metal Gate nMOSFETs in Deep Scaled Region", 2010 Symposium on VLSI Technology Digest of Technical Papers

  High-k gate insulating films and metal gate electrodes are introduced in MISFETs used for SOC (System on Chip) and the like after the 32 nm technology node. In this case, there is a problem that the absolute value of the threshold voltage of the n-MISFET and the p-MISFET is increased by the subsequent high-temperature heat treatment. Therefore, by forming various threshold voltage adjusting metal films or threshold voltage adjusting metal oxide films on the High-k gate insulating film and introducing these film components into the High-k gate insulating film therefrom. The threshold voltage is controlled. However, the inventors of the present application have a problem that lanthanum or the like introduced into the high-k gate insulating film of the n-MISFET is likely to move to a STI (Shallow Trench Isolation) region or the like by a subsequent heat treatment. It was revealed.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a highly reliable semiconductor integrated circuit device or a manufacturing process of a semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to one aspect of the present invention, in the semiconductor integrated circuit device, an N-channel threshold adjustment element outward diffusion prevention region is provided on the lower part of the gate stack of the n-MISFET and on the surface of the element isolation region around the gate stack.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in the semiconductor integrated circuit device, since the N-channel threshold adjustment element outward diffusion prevention region is provided in the lower part of the gate stack of the n-MISFET and in the surface of the element isolation region around the gate stack, the high-k gate insulation of the n-MISFET is provided. Lanthanum or the like introduced into the film can be prevented from moving to an STI region (element isolation region) or the like by a subsequent heat treatment.

It is a device principal part top view for demonstrating the device structure (N channel threshold value adjustment element dope STI structure) etc. of the semiconductor integrated circuit device of one embodiment of this application. FIG. 2 is a device cross-sectional view corresponding to the X-X ′ cross section of FIG. 1. FIG. 2 is a device cross-sectional view corresponding to the Y-Y ′ cross section of FIG. 1. Device sectional view (STI) corresponding to the XX ′ section of FIG. 1 for explaining a main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). The region is being formed). 1 is a device cross-sectional view corresponding to the XX ′ cross section of FIG. 1 for explaining a main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Channel threshold adjustment element ion implantation step). Device sectional view (STI) corresponding to the XX ′ section of FIG. 1 for explaining a main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Forming silicon nitride film removal step). Device sectional view corresponding to the XX ′ section of FIG. 1 for explaining the main process in the manufacturing method (N channel threshold adjustment element ion implantation method) of the semiconductor integrated circuit device of the one embodiment of the present application (well) Region forming step). Device sectional view (P) corresponding to the XX ′ section of FIG. 1 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device of the embodiment of the present application (N-channel threshold adjustment element ion implantation method). This is a resist film forming step for hard mask for channel threshold adjustment film processing). Device sectional view (P) corresponding to the XX ′ section of FIG. 1 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device of the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Channel threshold adjustment film processing hard mask film processing step). Device sectional view (P) corresponding to the XX ′ section of FIG. 1 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device of the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Channel threshold adjustment film processing step). 1 is a device cross-sectional view corresponding to the XX ′ cross section of FIG. 1 for explaining a main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Channel threshold adjustment film forming step). 1 is a device cross-sectional view corresponding to the XX ′ cross section of FIG. 1 for explaining a main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Channel threshold adjustment film removal process). Device sectional view (P) corresponding to the XX ′ section of FIG. 1 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device of the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Channel threshold adjustment film processing hard mask film removal step). Device sectional view (metal) corresponding to the XX ′ section of FIG. 1 for explaining a main process in the method for manufacturing a semiconductor integrated circuit device of the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Gate electrode film and polysilicon gate electrode film forming step). Device sectional view (gate) corresponding to the XX ′ section of FIG. 1 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device (N channel threshold adjustment element ion implantation method) of the one embodiment of the present application Patterning step). 1 is a device cross-sectional view corresponding to the XX ′ cross section of FIG. 1 for explaining a main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Channel threshold value adjusting element-containing film forming step). 1 is a device cross-sectional view corresponding to the XX ′ cross section of FIG. 1 for explaining a main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Channel threshold adjustment element-containing film patterning step). 1 is a device cross-sectional view corresponding to the XX ′ cross section of FIG. 1 for explaining a main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Channel threshold adjustment element-containing film patterning heat treatment step). 1 is a device cross-sectional view corresponding to the XX ′ cross section of FIG. 1 for explaining a main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Channel threshold adjustment element-containing film removal step). 1 is a device cross-sectional view corresponding to the XX ′ cross section of FIG. 1 for explaining a main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Channel threshold value adjusting element-containing film sidewall forming step). 1 is a device cross-sectional view corresponding to the XX ′ cross section of FIG. 1 for explaining a main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Channel threshold adjustment element-containing film sidewall removal step). Device sectional view (STI) corresponding to the XX ′ section of FIG. 1 for explaining a main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). Forming silicon nitride film removal step). 1 corresponds to the XX ′ cross section of FIG. 1 for explaining the third modification (the N channel threshold adjustment element-containing film formation & hard mask method) of the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing (P channel device area | region covering hard mask film | membrane film-forming process). 1 corresponds to the XX ′ cross section of FIG. 1 for explaining the third modification (the N channel threshold adjustment element-containing film formation & hard mask method) of the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing (P channel device area | region covering hard mask film | membrane patterning process). 1 corresponds to the XX ′ cross section of FIG. 1 for explaining the third modification (the N channel threshold adjustment element-containing film formation & hard mask method) of the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing (N channel threshold value adjustment element containing film | membrane film-forming process). 1 corresponds to the XX ′ cross section of FIG. 1 for explaining the third modification (the N channel threshold adjustment element-containing film formation & hard mask method) of the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing (N channel threshold value adjustment element containing film | membrane post-heat-treatment process). It is a device principal part top view (corresponding to Drawing 1) for explaining a modification (nitrogen dope STI structure) etc. of a device structure of a semiconductor integrated circuit device of one embodiment of the present application. It is device sectional drawing corresponding to the X-X 'cross section of FIG. FIG. 28 is a device cross-sectional view corresponding to the Y-Y ′ cross section of FIG. 27. XX in FIG. 27 for explaining a main process in a manufacturing method (nitrogen ion implantation method) corresponding to a modified example (nitrogen-doped STI structure) of the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. 'Is a device cross-sectional view (nitrogen ion implantation step) corresponding to the cross-section. XX in FIG. 27 for explaining a main process in a manufacturing method (nitrogen ion implantation method) corresponding to a modified example (nitrogen-doped STI structure) of the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. It is a device sectional view corresponding to a section (step of removing silicon nitride film for forming STI).

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. Semiconductor integrated circuit devices including:
(A) an element isolation region provided on the surface of the first main surface of the semiconductor substrate;
(B) an N channel active region and a P channel active region provided on the surface of the first main surface of the semiconductor substrate and separated from each other by the element isolation region;
(C) an N-channel gate stack which is provided on the first main surface of the semiconductor substrate and traverses the N-channel active region and constitutes an N-channel MISFET;
(D) a P-channel gate stack which is provided on the first main surface of the semiconductor substrate and traverses the P-channel active region and constitutes a P-channel MISFET;
(E) An N channel threshold adjustment element outward diffusion prevention region provided in a surface region of the element isolation region under and around the N channel gate stack.

  2. In the semiconductor integrated circuit device according to the item 1, the N channel threshold adjustment element outward diffusion prevention region is doped with an N channel threshold adjustment element.

  3. In the semiconductor integrated circuit device according to the item 2, the N channel threshold value adjusting element is La, Y, Mg, or Sc.

  4). 4. In the semiconductor integrated circuit device according to any one of items 1 to 3, the N channel threshold adjustment element outward diffusion prevention region is doped with nitrogen.

  5. 5. In the semiconductor integrated circuit device according to any one of 1 to 4, the N channel threshold adjustment element outward diffusion prevention region is provided in a surface region of the element isolation region below and around the P channel gate stack. Not.

6). A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) By forming an element isolation region on the surface of the first main surface of the semiconductor wafer, an N channel active region and a P channel active region are partitioned on the surface of the first main surface of the semiconductor substrate. Process;
(B) On the first main surface of the semiconductor substrate, an N channel gate stack (including an intrinsic gate stack and a dummy gate stack) that forms an N channel MISFET is formed across the N channel active region. Process;
(C) forming a P-channel gate stack that forms a P-channel MISFET across the P-channel active region on the first main surface of the semiconductor substrate;
(D) Before the steps (b) and (c) and after the step (a), an N channel threshold adjustment element is formed in the surface region of the element isolation region below and around the N channel gate stack. Forming an outward diffusion prevention region;

  7). In the method of manufacturing a semiconductor integrated circuit device according to the item 6, the N channel threshold adjustment element outward diffusion prevention region is formed by ion implantation of the N channel threshold adjustment element.

  8). In the method of manufacturing a semiconductor integrated circuit device according to 6 or 7, the N channel threshold value adjusting element outward diffusion preventing region is formed by ion implantation of nitrogen.

  9. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the N channel threshold adjustment element outward diffusion prevention region is formed by forming a surface of the element isolation region in a portion to be the N channel threshold adjustment element outward diffusion prevention region. In addition, an N channel threshold adjusting element or an oxide thereof is formed and heat-treated.

  10. 10. The method of manufacturing a semiconductor integrated circuit device according to any one of 6 to 9, wherein the N channel threshold value adjusting element outward diffusion prevention region is formed under the P channel gate stack and in the vicinity of the surface of the element isolation region. In the region, the N channel threshold adjustment element outward diffusion prevention region is not formed.

  11. In the method for manufacturing a semiconductor integrated circuit device according to 6, 9, or 10, the N channel threshold value adjusting element is La, Y, Mg, or Sc.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” or “semiconductor integrated circuit device” mainly refers to various types of transistors (active elements) alone, and resistors, capacitors, etc. as semiconductor chips (eg, single crystal). The one integrated on the silicon substrate). Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, as a typical integrated circuit configuration, a CMIS (Complementary Metal Insulator Semiconductor) integrated circuit represented by a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit combining an N-channel MISFET and a P-channel MISFET. Can be illustrated.

  A semiconductor process of today's semiconductor integrated circuit device, that is, a LSI (Large Scale Integration) wafer process, is usually performed by carrying a silicon wafer as a raw material to a premetal process (an interlayer insulating film between the lower end of the M1 wiring layer and the gate electrode structure). Etc., contact hole formation, tungsten plug, embedding, etc.) (FEOL (Front End of Line) process) and M1 wiring layer formation, pad opening to the final passivation film on the aluminum-based pad electrode Can be roughly divided into BEOL (Back End of Line) processes up to the formation of the wafer (including the process in the wafer level package process). Among the FEOL processes, the gate electrode patterning process, the contact hole forming process, and the like are microfabrication processes that require particularly fine processing. On the other hand, in the BEOL process, a via and trench formation process, in particular, a relatively lower local wiring (for example, M1 to M3 in a buried wiring having a structure of about four layers, M1 in a buried wiring having a structure of about 10 layers. In particular, fine processing is required for fine embedded wiring from M to around M5. Note that “MN (usually N = 1 to 15)” represents the N-th layer wiring from the bottom. M1 is a first layer wiring, and M3 is a third layer wiring.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide, SiOC (Silicon Oxicarbide) or carbon-doped silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS) coated silicon oxide, silica-based low-k insulating film (porous insulating) Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Note that SiC has similar properties to SiN, but SiON is often rather classified as a silicon oxide insulating film.

  The silicon nitride film is frequently used as an etch stop film or CESL (Contact Etch Stop Layer) in SAC (Self-Aligned Contact) technology, and also as a stress applying film (stressor film) in SMT (Stress Memory Technique). used.

  Similarly, the term “nickel silicide” usually refers to nickel monosilicide, but includes not only relatively pure ones but also alloys, mixed crystals, and the like whose main components are nickel monosilicide. Further, the silicide is not limited to nickel silicide, but may be cobalt silicide, titanium silicide, tungsten silicide, or the like that has been proven in the past. In addition to the Ni (nickel) film, for example, a Ni-Pt alloy film (Ni and Pt alloy film), a Ni-V alloy film (Ni and V alloy film), A nickel alloy film such as a Ni—Pd alloy film (Ni—Pd alloy film), a Ni—Yb alloy film (Ni—Yb alloy film) or a Ni—Er alloy film (Ni—Er alloy film) is used. be able to. These silicides having nickel as a main metal element are collectively referred to as “nickel-based silicide”.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). In the present application, the term “gate” includes “real gate”, that is, what is actually a gate, and so-called “dummy gate” and “replacement gate” that are removed later. The “gate stack” refers to a stacked body mainly composed of a gate insulating film and a gate electrode (referred to as an “actual gate stack” when it is particularly necessary to distinguish from a “dummy gate stack”). The term “High-k gate stack” refers to a gate insulating film having a High-k gate insulating layer.

  The “gate side structure” refers to a gate peripheral structure such as an offset spacer or a side wall spacer formed on the side wall of the gate stack. Further, the gate peripheral structure including the gate stack and the gate side surface structure is referred to as a “gate structure”.

  In the present application, the “gate first method” refers to a method in which the formation of the actual gate stack is performed before the activation heat treatment of the source / drain in the manufacturing method of the integrated circuit device in which the MISFETs are integrated. On the other hand, the “gate last method” refers to a method in which the main elements of the actual gate stack are formed after the activation heat treatment of the source and drain. In the gate-last method, the interface gate insulating film (interface actual gate insulating film) and the high-k gate insulating film (actual gate insulating film) are executed before the activation heat treatment of the source / drain, A method of forming the main elements of the gate stack after the activation heat treatment of the source / drain is referred to as a “High-k first-metal gate last method”.

  In the high-k first-metal gate last method, the interface gate insulating film (so-called IL) and the high-k gate insulating film are elements constituting the dummy gate stack, but are also elements constituting the actual gate stack. Therefore, the name at that time may be used in the description of the process.

  7). In the present application, an “active region” is a region surrounded by an element isolation region on the device surface of a semiconductor substrate, and refers to a portion to be a channel region or a source / drain region of a MISFET or the like.

  Further, the “N-channel threshold adjustment element outward diffusion prevention region” means N-channel threshold adjustment of La, Y, Mg, Sc, etc. for adjusting the threshold voltage of an N-channel MISFET having a High-k gate insulating film. This is a region for preventing elements from diffusing outwardly from the gate insulating film to the element isolation region (eg, STI region). Specifically, an N channel threshold adjustment element introduction region, a nitrogen introduction region, and the like.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

1. Description of Device Structure (N-Channel Threshold Adjusting Element Doped STI Structure) of Semiconductor Integrated Circuit Device of One Embodiment of the Present Application (Mainly FIGS. 1 to 3)
In the following example, a CMIS semiconductor integrated circuit device having a 32 nm technology node will be specifically described as an example.
Needless to say, the present invention can be applied to products smaller than this and products having dimensions larger than this.

  Hereinafter, for convenience of explanation, the gate first method will be mainly described. However, it is needless to say that the present invention can also be applied to a gate last method including an intermediate form such as a High-k first-metal gate last method.

  FIG. 1 is a top view of an essential part of a device for explaining a device structure (N-channel threshold adjustment element doped STI structure) and the like of a semiconductor integrated circuit device according to an embodiment of the present application. FIG. 2 is a device sectional view corresponding to the X-X ′ section of FIG. 1. FIG. 3 is a device sectional view corresponding to the Y-Y ′ section of FIG. 1. Based on these, the device structure (N-channel threshold adjustment element doped STI structure) of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  As shown in FIG. 1, on the device surface 1a of the semiconductor chip 2, the active regions of the N-channel MISFET (Qn) and the P-channel MISFET (Qp) constituting the CMIS, that is, the N-channel active region 4n and the P-channel Each of the active regions 4p is surrounded by an STI (Shallow Trench Isolation) region 3 (element isolation region). The surface region of the element isolation region 3 includes an N channel threshold adjustment element introduction region 3d (N channel threshold adjustment element outward diffusion prevention region) around the N channel active region 4n and an N channel threshold around the P channel active region 4p. It is divided into non-introducing regions 3u such as adjusting elements. An N-channel gate stack 5n and a P-channel gate stack 5p cross or cross each other at the center of the N-channel active region 4n and the P-channel active region 4p.

  Next, as shown in FIG. 2, the semiconductor chip 2 is divided into a substrate portion 1s (P-type single crystal silicon substrate portion) and a well portion thereon, and the well portion corresponds to the N channel device region Rn. It is divided into an N-type well region 6n and a P-type well region 6p corresponding to the P-channel device region Rp. An N-type source / drain region 20n and a P-type source / drain region 20p are provided in the surface regions of the N-channel gate stack 5n and the P-channel gate stack 5p, respectively. The N-channel gate stack 5n includes, from below, an IL (Interfacial Layer), that is, an interfacial oxide insulating film 7, an N-channel High-k gate insulating film 8n (High-k gate insulating film 8), a metal gate electrode film 9m, a poly It is composed of a silicon gate electrode film 9s and the like. On the other hand, the P-channel gate stack 5p includes an IL, that is, an interfacial silicon oxide insulating film 7, a P-channel High-k gate insulating film 8p (High-k gate insulating film 8), a metal gate electrode film 9m, a polysilicon gate from the bottom. The electrode film is composed of 9s and the like.

  Next, as shown in FIG. 3, an N-channel threshold adjustment element introduction region 3d is provided on the surface of the STI region 3 (element isolation region) below or around the N-channel gate stack 5n. On the other hand, the N channel threshold adjustment element introduction region 3d is not provided on the surface of the STI region 3 (element isolation region) below or around the P channel gate stack 5p. This is because the threshold voltage control of the P channel MISFET (Qp) is adversely affected.

  As shown in FIG. 1, the N-channel threshold adjustment element introduction region 3d is generally almost the entire surface region of the STI region 3 (element isolation region) corresponding to the N-channel device region Rn because of ease of manufacturing. However, it may be formed only on the surface region of the STI region 3 (element isolation region) below or around the N-channel gate stack 5n.

  The N channel threshold adjustment element introduction region 3d (N channel threshold adjustment element outward diffusion prevention region) is basically the same N channel as the N channel threshold adjustment element doped in the N channel High-k gate insulating film 8n. It is preferable from the viewpoint of the process that the threshold adjusting element is doped. Note that different N-channel threshold adjustment elements may be doped. As an N channel threshold value adjusting element, for example, La, Y, Sc (hereinafter, a rare earth element), Mg (Group 2 of the periodic table) and the like can be exemplified as suitable ones.

2. Description of principal processes in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method) (mainly FIGS. 4 to 15)
In this section, the main processes for realizing the device structure described in Section 1 will be described. In the following description, the process up to the patterning of the gate stack will be mainly described. This is because the formation of the gate structure including the gate side structure after patterning of the gate stack and the introduction of the source / drain region are necessary depending on the process method employed, including the selection of the gate first method or the gate last method. This is because various selections can be made according to the above.

  4 is a device cross-section corresponding to the XX ′ cross-section of FIG. 1 for explaining the main process in the method for manufacturing a semiconductor integrated circuit device (N-channel threshold adjustment element ion implantation method) according to the embodiment of the present application. It is a figure (in the middle of STI region formation). FIG. 5 is a device cross-section corresponding to the XX ′ cross-section of FIG. 1 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). It is a figure (N channel threshold value adjustment element ion implantation process). 6 is a device cross-section corresponding to the XX ′ cross-section of FIG. 1 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). It is a figure (STI formation silicon nitride film etc. removal process). 7 is a device cross-section corresponding to the XX ′ cross-section of FIG. 1 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). It is a figure (well area | region formation process). FIG. 8 is a device cross-section corresponding to the XX ′ cross-section of FIG. 1 for explaining the main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). It is a figure (P channel threshold value adjustment film processing hard mask resist film forming step). FIG. 9 is a device cross section corresponding to the XX ′ cross section of FIG. 1 for explaining the main process in the method for manufacturing a semiconductor integrated circuit device (N channel threshold adjustment element ion implantation method) of the embodiment of the present application. It is a figure (P channel threshold value adjustment film processing hard mask film processing step). 10 is a device cross-section corresponding to the XX ′ cross-section of FIG. 1 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). It is a figure (P channel threshold value adjustment film processing process). FIG. 11 is a device cross section corresponding to the XX ′ cross section of FIG. 1 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N channel threshold adjustment element ion implantation method). It is a figure (N channel threshold value adjustment film | membrane film-forming process). FIG. 12 is a device cross section corresponding to the XX ′ cross section of FIG. 1 for describing the main process in the method for manufacturing a semiconductor integrated circuit device (N channel threshold adjustment element ion implantation method) of the embodiment of the present application. It is a figure (N channel threshold value adjustment film etc. removal process). FIG. 13 is a device cross section corresponding to the XX ′ cross section of FIG. 1 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N channel threshold adjustment element ion implantation method). It is a figure (P channel threshold value adjustment film processing hard mask film removal step). FIG. 14 is a device cross section corresponding to the XX ′ cross section of FIG. 1 for describing the main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N channel threshold adjustment element ion implantation method). It is a figure (a metal gate electrode film and a polysilicon gate electrode film film-forming process). 15 is a device cross-section corresponding to the XX ′ cross-section of FIG. 1 for explaining the main process in the method for manufacturing a semiconductor integrated circuit device (N-channel threshold adjustment element ion implantation method) according to the embodiment of the present application. It is a figure (gate patterning process). Based on these, the main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method) will be described.

  First, the STI process leading to FIG. 4 will be briefly described with reference to FIG. As a wafer 1 (substrate portion 1s), for example, a P-type single crystal silicon wafer (for example, having a specific resistance of about 1 to 10 Ωcm) is prepared, and on the device surface (first main surface) 1a side (opposite the back surface 1b). A pad silicon oxide film 12 (for example, about 10 nm thick) is formed on almost the entire surface, for example, by thermal oxidation. Subsequently, an STI-forming silicon nitride film 11 (for example, about 20 nm thick) is formed on almost the entire surface of the pad silicon oxide film 12 by, eg, CVD (Chemical Vapor Deposition). Next, the silicon nitride film 11 for STI formation and the pad silicon oxide film 12 are patterned by normal lithography (for example, ArF lithography) to form a trench formation opening (for example, a width of about 70 nm). Next, a trench (for example, a depth of about 300 nm) is formed by anisotropic dry etching using a halogen-based etching gas, for example, using the patterned silicon nitride film 11 for forming STI as a mask. Next, a liner silicon oxide film (for example, about 3 nm thick) is formed in the trench by, for example, thermal oxidation. Subsequently, an embedded silicon oxide film is formed on almost the entire device surface 1a side of the wafer 1 and in the trench by, for example, HDP (High Density Plasma) -CVD. Next, the surface is planarized by, for example, CMP (Chemical Mechanical Polishing), and stopped on the STI forming silicon nitride film 11. Subsequently, when the buried silicon oxide film on the trench is removed using, for example, a hydrofluoric acid-based etching solution, the STI region 3 (element isolation region) remains in the trench as shown in FIG.

Next, as shown in FIG. 5, the N-channel threshold adjustment element introduction resist film 14 (for example, about 300 nm thick) is patterned by normal lithography (for example, ArF lithography). For example, lanthanum is ion-implanted into the surface of the STI region 3 corresponding to the N-channel device region Rn by using the patterned resist film 14 for introducing the N-channel threshold adjustment element as an ion implantation mask. Region 3d (N-channel threshold adjustment element outward diffusion prevention region) is formed. Here, as ion implantation conditions, for example, ion species: lanthanum, implantation energy: about 150 KeV, dose amount: 5 × 10 ¹⁴ / cm ² or the like (for example, implantation energy: about 50 to 300 KeV, dose amount: 5 × 10 ¹³ / Cm ² to 5 × 10 ¹⁵ / cm ² etc.) can be exemplified as a suitable one. As described above, since ion implantation of lanthanum or the like is performed in the state where the silicon nitride film 11 for forming the STI and the pad silicon oxide film 12 are present, it is possible to prevent undesired introduction of lanthanum or the like into the N channel active region 4n. There is a merit that can be.

  Thereafter, the resist film 14 for introducing the N-channel threshold adjustment element that has become unnecessary is removed by, for example, ashing. Subsequently, the silicon nitride film 11 for forming the STI is removed by, for example, hot phosphoric acid, and the device surface 1a of the wafer 1 is etched back by using, for example, a hydrofluoric acid-based etchant, whereby the pad silicon oxide film 12 is obtained. When these are removed, the result is as shown in FIG.

  Next, as shown in FIG. 7, by ion implantation from the device surface 1a side of the wafer 1, a portion corresponding to the N channel device region Rn on the device surface 1a side of the semiconductor substrate portion 1s and the P channel device region Rp are formed. N-type well region 6n and P-type well region 6p are formed in the corresponding portions, respectively.

  Next, as shown in FIG. 8, a silicon oxide insulating film 7 (for example, a thickness) is formed on almost the entire semiconductor surface of the device surface 1a of the wafer 1 as an IL (interfacial oxide insulating film) by, for example, thermal oxidation. A silicon oxynitride film of about 1 nm is formed. Subsequently, a non-doped High-k gate insulating film 8 (for example, a hafnium oxide High-k gate insulating film having a thickness of about 2 nm) is formed on almost the entire surface of the interfacial silicon oxide insulating film 7 by, for example, ALD (Atomic Layer deposition). ). Subsequently, a P-channel threshold adjustment film 10p (for example, an alumina film having a thickness of about 1 nm) is formed on almost the entire surface of the non-doped High-k gate insulating film 8 by sputtering, for example. Next, a metal cap film or a hard mask film 15 for processing the P channel threshold adjustment film (for example, a TiN film having a thickness of about 10 nm) is formed on almost the entire surface of the P channel threshold adjustment film 10p by, for example, reactive sputtering. Form a film. Subsequently, a P-channel threshold adjustment film processing hard mask resist film 16 (for example, a thickness of about 300 nm) is formed on the P-channel threshold adjustment film processing hard mask film 15, and this is applied to normal lithography (for example, ArF Patterning is performed by lithography.

  Next, as shown in FIG. 9, the P channel threshold adjustment film processing hard mask film 15 is patterned by, for example, wet etching using the P channel threshold adjustment film processing hard mask resist film 16 as a mask. Thereafter, the P-channel threshold adjustment film processing hard mask resist film 16 that has become unnecessary is removed.

  Next, as shown in FIG. 10, the P-channel threshold adjustment film 10p on the N-channel device region Rn side is removed by, for example, wet etching using the hard mask film 15 for processing the P-channel threshold adjustment film as a mask. Here, as a wet etching solution, for example, SPM (Sulfur Acid Hydrogen Peroxide Mixture) or the like can be exemplified as a suitable one.

  Next, as shown in FIG. 11, an N-channel threshold adjustment film 10n (for example, a lanthanum oxide film having a thickness of about 1 nm) is formed on almost the entire surface of the wafer 1 on the device surface 1a side by, for example, sputtering film formation. To do. Thereafter, by performing a heat treatment (for example, an RTA treatment of about 850 degrees Celsius), as shown in FIG. 12, the non-doped High-k gate insulating film 8 in the N-channel device region Rn becomes an N-channel High-k gate insulating. The film 8n (lanthanum-added hafnium oxide-based High-k gate insulating film) is formed. On the other hand, the non-doped High-k gate insulating film 8 in the P-channel device region Rp becomes a P-channel High-k gate insulating film 8p (aluminum-added hafnium oxide-based High-k gate insulating film). Next, when the P-channel threshold adjustment film processing hard mask film 15 that is no longer needed is removed by, for example, wet etching or the like, the result is as shown in FIG. Here, as a wet etching liquid, SPM etc. can be illustrated as a suitable thing, for example.

  Next, as shown in FIG. 14, for example, reactive sputtering film formation is performed on the N-channel High-k gate insulating film 8n and the P-channel High-k gate insulating film 8p on almost the entire surface of the wafer 1 on the device surface 1a side. Thus, a metal gate electrode film 9m (for example, a TiN film having a thickness of about 10 nm) is formed. Subsequently, a polysilicon gate electrode film 9s (for example, a polysilicon film or an amorphous silicon film having a thickness of about 10 nm) is formed on almost the entire surface of the metal gate electrode film 9m by, for example, CVD.

Next, as shown in FIG. 15, the N-channel gate stack 5n and the P-channel gate stack 5p are patterned by a combination of normal lithography (for example, ArF lithography) and anisotropic dry etching, for example. Here, as the etching gas for the polysilicon gate electrode film 9s, for example, a halogen-based etching gas such as HBr is used, and as the etching gas for the metal gate electrode film 9m, for example, a halogen-based etching gas such as Cl ₂ / HBr is used. As an etching gas for the −k gate insulating film 8 (8n, 8p), for example, a halogen-based etching gas such as BCl ₃ / Cl ₂ can be exemplified as a preferable one.

  After that, through formation of a gate structure including a gate side structure and introduction of a source / drain region, etc., in the case of a gate first method, formation of a pre-metal insulating film, formation of a contact hole, tungsten plug, etc. After embedding, for example, the process shifts to a copper-based buried wiring process such as a damascene method.

3. Description of Modified Example 1 (Basic Channel Formation Method of N-Channel Threshold Adjusting Element-Containing Film) of Manufacturing Method of Semiconductor Integrated Circuit Device According to One Embodiment of the Present Application (Mainly FIGS. 16 to 19)
In section 2, a method of ion-implanting an N-channel threshold adjusting element such as lanthanum has been described as a device manufacturing method for realizing the device structure of section 1, but in this section, an N-channel threshold adjusting element-containing method is included as a modification. A method of introducing an N channel threshold adjustment element from the film will be described. Needless to say, using the method of section 2 together is not excluded.

  FIG. 16 is a device cross section corresponding to the XX ′ cross section of FIG. 1 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N channel threshold adjustment element ion implantation method). It is a figure (N channel threshold value adjustment element containing film | membrane film-forming process). FIG. 17 is a device cross section corresponding to the XX ′ cross section of FIG. 1 for explaining the main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N channel threshold adjustment element ion implantation method). It is a figure (N channel threshold value adjustment element containing film | membrane patterning process). FIG. 18 is a device cross section corresponding to the XX ′ cross section of FIG. 1 for explaining the main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). It is a figure (N channel threshold value adjustment element containing film | membrane post-patterning heat processing process). 19 is a device cross-section corresponding to the XX ′ cross-section of FIG. 1 for explaining the main process in the method for manufacturing a semiconductor integrated circuit device (N-channel threshold adjustment element ion implantation method) according to the embodiment of the present application. It is a figure (N channel threshold value adjustment element containing film | membrane removal process).

  From the state of FIG. 4, as shown in FIG. 16, an N channel threshold adjustment element-containing film 17 (for example, a lanthanum oxide film having a thickness of about 1 nm is formed on the entire surface of the wafer 1 on the device surface 1 a side by, for example, sputtering film formation. ).

  Next, as shown in FIG. 17, the N-channel threshold adjustment element-containing film processing resist film 17 (for example, a thickness of about 300 nm) is patterned by, for example, normal lithography (for example, ArF lithography). Using this patterned N channel threshold adjustment element-containing film processing resist film 17 as a mask, the N channel threshold adjustment element containing film 17 on the P channel device region Rp is removed, for example, by wet etching or the like. Here, as a wet etching liquid, SPM etc. can be illustrated as a suitable thing, for example. Thereafter, the N-channel threshold adjustment element-containing film processing resist film 17 that is no longer needed is removed by, for example, ashing, as shown in FIG.

  Further, when heat treatment (for example, an RTA treatment of about 850 degrees Celsius) is performed in this state, as shown in FIG. 19, an N channel threshold adjustment element introduction region 3d (on the surface region of the STI region 3 (element isolation region)) N-channel threshold adjustment element outward diffusion prevention region) is formed, and the element isolation region 3 is divided into this region and the original N-channel threshold adjustment element non-introduction region 3u. Thereafter, the process proceeds to the step of FIG.

  As described above, in the method of introducing the N channel threshold adjustment element from the N channel threshold adjustment element containing film (N channel threshold adjustment element containing film deposition basic method), a method by ion implantation (N channel threshold adjustment element ion implantation method). As compared with the above, there is an advantage that the high concentration N-channel threshold adjustment element-containing region 3d can be formed relatively easily.

4). Description of Modification 2 (N Channel Threshold Adjusting Element-Containing Film Containing & Sidewall Method) of Manufacturing Method of Semiconductor Integrated Circuit Device According to One Embodiment of the Present Application (Mainly FIGS. 20 to 22)
In this section, as in section 3, the N-channel threshold adjustment element-containing film formation method is used, but the N-channel threshold adjustment element introduction region 3d is used as the element isolation region 3 corresponding to the N-channel device region Rn. An N channel threshold adjustment element-containing film formation & sidewall method that can be limited to only the region close to the N channel active region 4n in the surface will be described.

  FIG. 20 is a device cross section corresponding to the XX ′ cross section of FIG. 1 for explaining the main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N channel threshold adjustment element ion implantation method). It is a figure (N channel threshold value adjustment element containing film | membrane sidewall formation process). FIG. 21 is a device cross section corresponding to the XX ′ cross section of FIG. 1 for describing the main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N channel threshold adjusting element ion implantation method). It is a figure (N channel threshold value adjustment element containing film | membrane sidewall removal process). 22 is a device cross-section corresponding to the XX ′ cross-section of FIG. 1 for explaining the main process in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element ion implantation method). It is a figure (STI formation silicon nitride film etc. removal process). Based on these, a second modification of the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element-containing film formation & sidewall method) will be described.

  From the state of FIG. 18, by performing anisotropic dry etching on the N-channel threshold adjustment element-containing film 17 (lanthanum oxide film) as shown in FIG. 20, the N-channel threshold adjustment element-containing film sidewall 17s. Form.

  Next, as shown in FIG. 21, by performing a heat treatment (for example, an RTA process of about 850 degrees Celsius), an N channel threshold adjustment element introduction region 3d (N A channel threshold adjustment element outward diffusion prevention region) is formed, and the element isolation region 3 is divided into this region and the original N-channel threshold adjustment element non-introduction region 3u as before.

  Next, as shown in FIG. 22, the silicon nitride film 11 for forming the STI is removed by, for example, hot phosphoric acid, and the device surface 1a of the wafer 1 is etched back using, for example, a hydrofluoric acid etching solution. Thus, the pad silicon oxide film 12 and the like are removed.

  By adopting such a structure, the N-channel threshold adjustment element introduction region 3d is limited to only the region close to the N-channel active region 4n in the surface of the element isolation region 3 corresponding to the N-channel device region Rn. Therefore, the adverse effect of the N channel threshold adjustment element on the P channel device region Rp can be reduced.

5. Description of Modification 3 (N Channel Threshold Adjusting Element Containing Film Containing & Hard Mask Method) of Manufacturing Method of Semiconductor Integrated Circuit Device According to One Embodiment of the Present Application (Mainly FIGS. 23 to 26)
The example described in this section is a modification of the manufacturing method described in Section 3, and is characterized in that a hard mask is used for selective introduction of lanthanum and the like. This is advantageous, for example, for processing a product having a large step, such as SRAM (Static Random Access Memory).

  FIG. 23 is a cross-sectional view taken along the line XX ′ of FIG. 1 for explaining a third modification of the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N channel threshold adjustment element-containing film formation & hard mask method). FIG. 6 is a device cross-sectional view corresponding to (P channel device region covering hard mask film forming step). 24 is a cross-sectional view taken along the line XX ′ of FIG. 1 for explaining a third modification of the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (film formation with N-channel threshold value adjusting element-containing film and hard mask method). FIG. 4 is a device cross-sectional view corresponding to (P channel device region covering hard mask film patterning step). FIG. 25 is a cross-sectional view taken along the line XX ′ of FIG. 1 for explaining a third modification of the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (deposition of an N-channel threshold adjustment element-containing film and hard mask method). FIG. 6 is a device cross-sectional view corresponding to (N channel threshold value adjusting element-containing film forming step). FIG. 26 is a cross-sectional view taken along the line XX ′ of FIG. 1 for explaining a third modification of the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N channel threshold adjustment element-containing film formation & hard mask method). FIG. 6 is a device cross-sectional view corresponding to (N channel threshold value adjusting element-containing film post-heat treatment step). Based on these, a third modification of the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-channel threshold adjustment element-containing film formation & hard mask method) will be described.

  From the state of FIG. 4, as shown in FIG. 23, the cap film or the hard mask film 25 for covering the P channel device region (for example, by reactive sputtering film formation, for example, over almost the entire surface on the device surface 1 a side of the wafer 1. A TiN film having a thickness of about 10 nm is formed. As the P channel device region covering hard mask film 25, TaN can be exemplified as a suitable material in addition to the TiN film.

  Next, as shown in FIG. 24, the P channel device region covering hard mask processing resist film 26 (for example, about 300 nm thick) is patterned by, for example, normal lithography (for example, ArF lithography). Subsequently, by using the patterned P channel device region covering hard mask processing resist film 26 as a mask, the P channel device region covering hard mask film 25 in the N channel device region Rn is removed by, for example, wet etching or the like. Here, as a wet etching liquid, SPM etc. can be illustrated as a suitable thing, for example. Thereafter, the P-channel device region-covering hard mask processing resist film 26 that has become unnecessary is removed by, for example, ashing.

  Next, as shown in FIG. 25, an N-channel threshold adjustment element-containing film 17 (for example, a lanthanum oxide film having a thickness of about 1 nm) is formed on almost the entire surface of the wafer 1 on the device surface 1a side by, for example, sputtering film formation. Film.

  Next, as shown in FIG. 26, by performing a heat treatment (for example, an RTA treatment of about 850 degrees Celsius), an N channel threshold value adjusting element introduction region 3d (N A channel threshold adjustment element outward diffusion prevention region) is formed, and the element isolation region 3 is divided into this region and the original N-channel threshold adjustment element non-introduction region 3u as before.

  Subsequently, in the same manner as described above, the N-channel threshold adjustment element-containing film 17 and the P-channel device region covering hard mask film 25 are removed by wet etching using SPM, for example. Thereafter, the process proceeds to the process of FIG.

  According to such a process, the pattern accuracy can be improved as compared with patterning the N-channel threshold adjustment element-containing film 17 directly with a resist film.

6). Description of Modification of Device Structure (Nitrogen-Doped STI Structure) of Semiconductor Integrated Circuit Device of One Embodiment of the Present Application (Mainly FIGS. 27 to 29)
In this section, a variation of the device structure described in Section 1 will be described. In the example of section 1, the N channel threshold adjustment element introduction region 3d (FIGS. 1 to 3) is used as the N channel threshold adjustment element outward diffusion prevention region, but in this section example, instead, The nitrogen introduction region 3n (FIGS. 27 to 29) is used.

  FIG. 27 is a top view of a device main part (corresponding to FIG. 1) for explaining a modified example (nitrogen-doped STI structure) of the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 28 is a device cross-sectional view corresponding to the X-X ′ cross section of FIG. 27. 29 is a device cross-sectional view corresponding to the Y-Y ′ cross section of FIG. 27. Based on these, a modified example (nitrogen-doped STI structure) of the device structure of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  As shown in FIG. 27, on the device surface 1a of the semiconductor chip 2, the active regions of the N-channel type MISFET (Qn) and the P-channel type MISFET (Qp) constituting the CMIS, that is, the N-channel active region 4n and the P-channel Each of the active regions 4p is surrounded by an STI (Shallow Trench Isolation) region 3 (element isolation region). The surface region of the element isolation region 3 includes a nitrogen introduction region 3n (N channel threshold adjustment element outward diffusion prevention region) around the N channel active region 4n and an N channel threshold adjustment element around the P channel active region 4p. It is divided into the introduction area 3u. An N-channel gate stack 5n and a P-channel gate stack 5p cross or cross each other at the center of the N-channel active region 4n and the P-channel active region 4p.

  Next, as shown in FIG. 28, the semiconductor chip 2 is divided into a substrate portion 1s (P-type single crystal silicon substrate portion) and a well portion thereon, and the well portion corresponds to the N channel device region Rn. It is divided into an N-type well region 6n and a P-type well region 6p corresponding to the P-channel device region Rp. An N-type source / drain region 20n and a P-type source / drain region 20p are provided in the surface regions of the N-channel gate stack 5n and the P-channel gate stack 5p, respectively. The N-channel gate stack 5n includes, from below, an IL (Interfacial Layer), that is, an interfacial oxide insulating film 7, an N-channel High-k gate insulating film 8n (High-k gate insulating film 8), a metal gate electrode film 9m, a poly It is composed of a silicon gate electrode film 9s and the like. On the other hand, the P-channel gate stack 5p includes an IL, that is, an interfacial silicon oxide insulating film 7, a P-channel High-k gate insulating film 8p (High-k gate insulating film 8), a metal gate electrode film 9m, a polysilicon gate from the bottom. The electrode film is composed of 9s and the like.

  Next, as shown in FIG. 29, a nitrogen introduction region 3n is provided on the surface of the STI region 3 (element isolation region) below or around the N-channel gate stack 5n. On the other hand, the nitrogen introduction region 3n is not provided on the surface of the STI region 3 (element isolation region) below or around the P channel gate stack 5p. This is because the threshold voltage control of the P-channel type MISFET (Qp) may be adversely affected.

  As shown in FIG. 27, the nitrogen-introduced region 3n is usually formed over almost the entire surface region of the STI region 3 (element isolation region) corresponding to the N-channel device region Rn for ease of manufacturing. Alternatively, it may be formed only on the surface region of the STI region 3 (element isolation region) below or around the N-channel gate stack 5n.

  As described above, the merit of using the nitrogen introduction region 3n as the N channel threshold adjustment element outward diffusion prevention region is less affected by the etching characteristics of the STI than the N channel threshold adjustment element introduction region 3d. The influence on the device region Rp is small. On the other hand, the N-channel threshold adjustment element introduction region 3d is more effective because it can be easily removed by heat treatment or the like.

7). Description of principal processes in a method of manufacturing a semiconductor integrated circuit device corresponding to a modification of the device structure of the semiconductor integrated circuit device of the one embodiment of the present application (mainly FIGS. 30 and 31)
In this section, an example of a manufacturing method for realizing the device structure described in Section 6 will be described.

  FIG. 30 is a diagram illustrating a main process in a manufacturing method (nitrogen ion implantation method) corresponding to a modified example (nitrogen-doped STI structure) of the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing (nitrogen ion implantation process) corresponding to a XX 'section. FIG. 31 is a diagram illustrating a main process in a manufacturing method (nitrogen ion implantation method) corresponding to a modification (nitrogen-doped STI structure) of the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing (STI formation silicon nitride film etc. removal process) corresponding to a XX 'section. Based on these, the main process in the manufacturing method of the semiconductor integrated circuit device corresponding to the modification of the device structure of the semiconductor integrated circuit device of the one embodiment of the present application will be described.

From the state of FIG. 4, as shown in FIG. 30, the nitrogen-introducing resist film 19 (for example, about 300 nm thick) is patterned by normal lithography (for example, ArF lithography). Using the patterned nitrogen-introducing resist film 19 as an ion implantation mask, nitrogen is ion-implanted into the surface of the STI region 3 corresponding to the N-channel device region Rn, so that the nitrogen-introducing region 3n (N channel threshold adjusting element outward) A diffusion prevention region) is formed. Here, as ion implantation conditions, for example, ion species: nitrogen, implantation energy: about 15 KeV, dose amount: 5 × 10 ¹⁴ / cm ² or the like (for example, implantation energy: about 5 to 30 KeV, dose amount: 5 × 10 ¹³ / Cm ² to 5 × 10 ¹⁵ / cm ² etc.) can be exemplified as a suitable one. As described above, since ion implantation of nitrogen or the like is performed in the state where the silicon nitride film 11 for forming the STI and the pad silicon oxide film 12 are present, it is possible to prevent undesired introduction of nitrogen or the like into the N channel active region 4n. There is a merit that can be.

  Thereafter, the unnecessary nitrogen-introducing resist film 19 is removed by, for example, ashing. Subsequently, the silicon nitride film 11 for forming the STI is removed by, for example, hot phosphoric acid, and the device surface 1a of the wafer 1 is etched back by using, for example, a hydrofluoric acid-based etchant, whereby the pad silicon oxide film 12 is obtained. When these are removed, the result is as shown in FIG.

8). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the gate-first (Gate First) method has been mainly described as an example in the above-described embodiment, but the present invention is not limited thereto, and the gate-last (Gate Last) is described. It goes without saying that it can also be applied to the method.

  The present invention can be widely applied to a threshold voltage control technique in a semiconductor integrated circuit device and a method for manufacturing a semiconductor integrated circuit device (or a semiconductor device).

1 Semiconductor Wafer 1a (Wafer or Chip) Front Side Main Surface (Device Surface)
1b Back side main surface (of wafer or chip) 1s Substrate part (of wafer or chip) (P-type single crystal silicon substrate part)
2 Semiconductor chip 3 STI region (element isolation region)
3d N-channel threshold adjustment element introduction region (N-channel threshold adjustment element outward diffusion prevention region)
3n Nitrogen introduction region (N channel threshold adjustment element outward diffusion prevention region)
3u N-channel threshold adjustment element non-introduced region 4n N-channel active region 4p P-channel active region 5n N-channel gate stack 5p P-channel gate stack 6n N-type well region 6p P-type well region 7 IL (interfacial silicon oxide insulating film)
8 High-k gate insulating film (hafnium oxide High-k gate insulating film)
8n N-channel high-k gate insulating film (lanthanum-doped hafnium oxide-based high-k gate insulating film)
8p P-channel high-k gate insulating film (aluminum-added hafnium oxide-based high-k gate insulating film)
9m Metal gate electrode film (TiN film)
9s Polysilicon gate electrode film 10n N channel threshold adjustment film (lanthanum oxide film)
10p P channel threshold adjustment film (alumina film)
DESCRIPTION OF SYMBOLS 11 Silicon nitride film for STI formation 12 Pad silicon oxide film 14 Resist film for introducing N channel threshold adjustment element 15 Hard mask film (TiN film) for processing P channel threshold adjustment film
16 Hard channel resist film for processing P channel threshold adjustment film 17 N channel threshold adjustment element containing film (lanthanum oxide film)
17s N-channel threshold adjustment element-containing film side wall 18 N-channel threshold adjustment element-containing film processing resist film 19 Nitrogen introduction resist film 20n N-type source / drain region 20p P-type source / drain region 25 P-channel device region covering hard mask film (TiN film)
26 P channel device region covering hard mask resist film Qn N channel MISFET
Qp P channel type MISFET
Rn N channel device region Rp P channel device region

Claims (4)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) By forming an element isolation region on the surface of the first main surface of the semiconductor wafer, an N channel active region and a P channel active region are partitioned on the surface of the first main surface of the semiconductor substrate. Process;
(B) forming an N-channel gate stack that forms an N-channel MISFET across the N-channel active region on the first main surface of the semiconductor substrate;
(C) forming a P-channel gate stack that forms a P-channel MISFET across the P-channel active region on the first main surface of the semiconductor substrate;
(D) Before the steps (b) and (c) and after the step (a), an N channel threshold adjustment element is formed in the surface region of the element isolation region below and around the N channel gate stack. Forming an outward diffusion prevention region,
Here, the formation of the N channel threshold adjustment element outward diffusion prevention region is performed by ion implantation of the N channel threshold adjustment element . 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the N channel threshold adjustment element outward diffusion prevention region is formed under a surface region of the element isolation region under and around the P channel gate stack. The N channel threshold value adjusting element outward diffusion preventing region is not formed . 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the N channel threshold value adjusting element is La, Y, Mg, or Sc . A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) By forming an element isolation region on the surface of the first main surface of the semiconductor wafer, an N channel active region and a P channel active region are partitioned on the surface of the first main surface of the semiconductor substrate. Process;
(B) forming an N-channel gate stack that forms an N-channel MISFET across the N-channel active region on the first main surface of the semiconductor substrate;
(C) forming a P-channel gate stack that forms a P-channel MISFET across the P-channel active region on the first main surface of the semiconductor substrate;
(D) Before the steps (b) and (c) and after the step (a), an N channel threshold adjustment element is formed in the surface region of the element isolation region below and around the N channel gate stack. Forming an outward diffusion prevention region,
Here, the N channel threshold adjustment element outward diffusion prevention region is formed on the surface of the element isolation region of the portion to be the N channel threshold adjustment element outward diffusion prevention region, An oxide film is formed and heat-treated .

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