JP2012256659A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that variations in characteristics of a transistor, which is strongly affected by dependence on an offset spacer length and a sidewall spacer length as discovered by the present inventors, as well as dependence on a gate length as previously considered, increases as a MISFET is more miniaturized and a single-channel effect becomes more obvious.SOLUTION: According to the present invention, there is provided a method of manufacturing a CMIS-type semiconductor integrated circuit device in which a sum of an offset spacer length and a sidewall spacer length is adjusted in an N-channel MISFET and a P-channel MISFET.

Description

  The present invention relates to a technique effective when applied to a threshold voltage control technique in a method for manufacturing a semiconductor integrated circuit device (or a semiconductor device).

  International Publication No. 99/13507 pamphlet (Patent Document 1) discloses the following process as a manufacturing method of a CMIS (Complementary Metal Insulator Semiconductor) type semiconductor integrated circuit device. That is, first, an N-type extension region is introduced by ion implantation using a gate electrode of an N-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) as a mask. Next, a first sidewall and a second sidewall made of a different material are formed on the gate electrode of the N-channel MISFET, and an N-type source / drain region is introduced by ion implantation using these as a mask. Next, the second sidewall is removed from the first sidewall and the second sidewall of the gate electrode of the P-channel MISFET, and a P-type extension region is introduced by ion implantation as a first sidewall mask. Finally, a third sidewall is further formed on the gate electrode of the P-channel MISFET, and a P-type source / drain region is introduced by ion implantation using the first sidewall and the third sidewall as a mask. The channel length of the P channel MISFET is to be individually controlled.

  Japanese Unexamined Patent Publication No. 2006-295071 (Patent Document 2) discloses a method for manufacturing a CMIS type semiconductor integrated circuit device in which the thickness of a dual offset spacer is controlled uniformly for both channels. A technique for controlling the threshold voltage by adjusting the length of the extension is disclosed.

  Japanese Unexamined Patent Publication No. 2009-206318 (Patent Document 3) or US Pat. No. 7,871,871 (Patent Document 4) corresponding thereto discloses an offset spacer (Off-set) in a method for manufacturing a CMIS type semiconductor integrated circuit device. A technique for controlling a threshold voltage by adjusting a halo ion implantation amount based on a result of a spacer process is disclosed.

International Publication No. 99/13507 Pamphlet JP 2006-295071 A JP 2009-206318 A U.S. Pat. No. 7,871,871

  When the MISFET is miniaturized, the single channel effect becomes more prominent, and the characteristic variation of the transistor tends to increase. Here, it has been clarified by the present inventors that the variation in transistor characteristics is more influenced by the offset spacer length and the side wall spacer length in addition to the conventional gate length dependency.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, one invention of the present application is to adjust the sum of the offset spacer length and the sidewall spacer length in the N-channel MISFET and the P-channel MISFET in the manufacturing method of the CMIS type semiconductor integrated circuit device.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in the manufacturing method of the CMIS type semiconductor integrated circuit device, the sum of the offset spacer length and the sidewall spacer length is adjusted in the N-channel MISFET and the P-channel MISFET. It can be controlled to obtain.

It is a device schematic sectional view in a manufacturing process (at the time of completion of gate electrode patterning) for explaining a common CMIS process preceding an adjustment process in a manufacturing method of a semiconductor integrated circuit device of one embodiment of this application. It is a device schematic sectional view in the manufacturing process (at the time of completion of the 1st offset spacer) for explaining the common CMIS process preceding the adjustment process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. During the manufacturing process for explaining the common CMIS process preceding the adjustment process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application (introduction of the N-type extension region and the P-type halo region into the N-type device region is completed) It is a device schematic cross section of (at the time). It is a device schematic sectional view in a manufacturing process (at the time of completion of the 2nd offset spacer) for explaining a common CMIS process preceding an adjustment process in a manufacturing method of a semiconductor integrated circuit device of one embodiment of this application. During the manufacturing process for explaining the common CMIS process preceding the adjustment process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application (introduction of the P-type extension region and the N-type halo region into the P-type device region is completed) It is a device schematic cross section of (at the time). It is a device schematic sectional view in a manufacturing process (at the time of insulating film formation for sidewall formation) for explaining a common CMIS process preceding an adjustment process in a manufacturing method of a semiconductor integrated circuit device of one embodiment of this application. Device schematic during manufacturing process (spacer length advance adjustment step of N type device region) for explaining adjustment process A (N type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is sectional drawing. During the manufacturing process for explaining the adjustment process A (N-type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (secondary adjustment step of the spacer length in the P-type device region and the P-type) It is a device schematic cross section of a source / drain region introducing step). FIG. 6 is a device schematic cross-sectional view during a manufacturing process (N-type source / drain region introduction step) for explaining an adjustment process A (N-type device region advance adjustment) in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application; is there. Device model during manufacturing process (P-type device region spacer length advance adjustment step) for explaining adjustment process B (P-type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is sectional drawing. FIG. 4 is a device schematic cross-sectional view during a manufacturing process (P-type source / drain region introduction step) for explaining an adjustment process B (P-type device region advance adjustment) in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application; is there. During the manufacturing process for explaining the adjustment process B (P-type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the one embodiment of the present application (secondary adjustment step of spacer length in N-type device region and N-type) It is a device schematic cross section of a source / drain region introducing step). It is a device schematic sectional view in the manufacturing process (nickel silicide film formation process) for explaining the common CMIS process following the adjustment process in the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application. It is a device schematic cross section in the manufacturing process (premetal insulating film formation process) for demonstrating the common CMIS process following the adjustment process in the manufacturing method of the semiconductor integrated circuit device of the said one Embodiment of this application. It is a device schematic sectional view in the manufacturing process (tungsten plug formation process) for demonstrating the common CMIS process following the adjustment process in the manufacturing method of the semiconductor integrated circuit device of the said one Embodiment of this application. It is explanatory drawing explaining the proper use of the adjustment processes A and B. It is explanatory drawing explaining each symbol which appears in FIG.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a first gate electrode of an N-channel MISFET and a second gate electrode of a P-channel MISFET on a first main surface of a semiconductor wafer;
(B) forming offset spacers on sidewalls of the first gate electrode and the second gate electrode;
(C) measuring the offset spacer length of the offset spacer;
(D) Introducing an impurity by ion implantation into the semiconductor region of the first main surface around one of the first gate electrode and the second gate electrode in a state where the offset spacer is present. Introducing an extension region by:
(E) forming a spacer including the offset spacer by forming a sidewall spacer on a side wall of one of the first gate electrode and the second gate electrode in a state where the offset spacer is present; ,
Here, the spacer length of the spacer is adjusted by controlling the etch back amount based on the measured offset spacer length of the offset spacer.

  2. In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the spacer length is adjusted independently for the N-channel MISFET and the P-channel MISFET.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” or “semiconductor integrated circuit device” mainly refers to various types of transistors (active elements) alone, and resistors, capacitors, etc. as semiconductor chips (eg, single crystal). The one integrated on the silicon substrate). Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, as a typical integrated circuit configuration, a CMIS (Complementary Metal Insulator Semiconductor) integrated circuit represented by a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit combining an N-channel MISFET and a P-channel MISFET. Can be illustrated.

  A semiconductor process of today's semiconductor integrated circuit device, that is, a LSI (Large Scale Integration) wafer process, is usually performed by carrying a silicon wafer as a raw material to a premetal process (an interlayer insulating film between the lower end of the M1 wiring layer and the gate electrode structure). Etc., contact hole formation, tungsten plug, embedding, etc.) (FEOL (Front End of Line) process) and M1 wiring layer formation, pad opening to the final passivation film on the aluminum-based pad electrode Can be roughly divided into BEOL (Back End of Line) processes up to the formation of the wafer (including the process in the wafer level package process).

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS) and other coating-type silicon oxide, silica-based low-k insulating film (porous insulating) Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Note that SiC has similar properties to SiN, but SiON is often rather classified as a silicon oxide insulating film.

  A silicon nitride film is frequently used as an etch stop film in SAC (Self-Aligned Contact) technology, that is, CESL (Contact Etch-Stop Layer), and also as a stress applying film in SMT (Stress Measurement Technique). .

  Similarly, the term “nickel silicide” usually refers to nickel monosilicide, but includes not only relatively pure ones but also alloys, mixed crystals, and the like whose main components are nickel monosilicide. Further, the silicide is not limited to nickel silicide, but may be cobalt silicide, titanium silicide, tungsten silicide, or the like that has been proven in the past. In addition to the Ni (nickel) film, for example, a Ni-Pt alloy film (Ni and Pt alloy film), a Ni-V alloy film (Ni and V alloy film), A nickel alloy film such as a Ni—Pd alloy film (Ni—Pd alloy film), a Ni—Yb alloy film (Ni—Yb alloy film) or a Ni—Er alloy film (Ni—Er alloy film) is used. be able to. These silicides having nickel as a main metal element are collectively referred to as “nickel-based silicide”.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5). “Wafer” or “semiconductor substrate” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device or an electronic device) is formed, but is an insulating substrate such as an epitaxial wafer or an SOI wafer. Needless to say, a composite wafer such as a semiconductor layer is also included. A “semiconductor chip” or “chip region” is a unit integrated circuit region that forms part of a wafer or the like in the course of a manufacturing process, and is divided into semiconductor chips by dicing or the like after the wafer process is completed.

  6). The impurity layer structure of the short channel MISFET includes a deep and high-concentration “high-concentration source / drain region”, and a shallower and low-concentration same-conductivity type “extension region (LDD region)”. “Halo ion implantation” or “halo region (pocket region)” is a region with a relatively low concentration of the opposite conductivity type, and finally the inner region under the channel region near the tip of the extension region. A region having a higher concentration than the well region is formed. The characteristics of ion implantation in the halo region are that normal ion implantation in a high concentration source / drain region and extension region is performed substantially perpendicular to the device surface of the wafer, whereas a beam tilted around 45 degrees is It is where it is done from the direction. That is, tilt injection or wide angle injection.

  The typical concentration relationship of each impurity region when the device is completed is roughly as follows. That is, substrate <well <halo <extension <high concentration source / drain.

  7). There are two gate peripheral structures of the short channel MISFET: “offset spacer insulating film (may be plural types)” and “sidewall spacer insulating film”. The “offset spacer insulating film” defines the edge of the ion implantation in the extension region and the halo region for the low operating voltage device system, while the “side wall spacer insulating film” is structurally inside. Includes an offset spacer insulating film and defines an edge at the time of ion implantation of the “high concentration source / drain region” with respect to the low operating voltage device system and other systems.

  In the present application, the term “side wall spacer” refers to only the side wall spacer in principle, and the entire structure around the gate electrode, which is an aggregate of the side wall spacer and the offset spacer (in the following example, 1 offset spacer, a second offset spacer, and a side wall spacer) are referred to as “spacer” or “gate peripheral spacer”.

  The term “offset spacer length” refers to the length of the lower end portion of the offset spacer. Further, “spacer length” refers to the length of the lower end of the spacer. In the present application, the unit of length is assumed to be non-negative (positive value or 0) for convenience.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

1. Description of Common CMIS Process Prior to Adjustment Process in Manufacturing Method of Semiconductor Integrated Circuit Device of One Embodiment of the Present Application (Mainly FIGS. 1 to 6)
The current semiconductor integrated circuit wafer process adjusts process and device parameters using various statistical methods based on various process statistical data. Become. Therefore, in the following, a specific description will be given by taking, as an example, a method of actually measuring each wafer. For this reason, it goes without saying that “measured values” in the following examples may be replaced with “estimated values” from other measured values in the statistical method.

  FIG. 1 is a schematic cross-sectional view of a device during a manufacturing process (when gate electrode patterning is completed) for explaining a common CMIS process preceding an adjustment process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 2 is a device schematic cross-sectional view during the manufacturing process (when the first offset spacer is completed) for explaining the common CMIS process preceding the adjustment process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. . FIG. 3 is a diagram illustrating a common CMIS process preceding the adjustment process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (N-type extension region and P-type halo region in the N-type device region). FIG. FIG. 4 is a device schematic cross-sectional view during the manufacturing process (when the second offset spacer is completed) for explaining the common CMIS process preceding the adjustment process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. . FIG. 5 shows a common CMIS process preceding the adjustment process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention (P-type extension region and N-type halo region to the P-type device region). FIG. FIG. 6 is a device schematic cross-sectional view during the manufacturing process (at the time of forming the sidewall forming insulating film) for explaining the common CMIS process preceding the adjustment process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. is there. Based on these, the common CMIS process preceding the adjustment process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  First, the outline of the flow of the wafer process introduction unit will be described with reference to FIG. Device main surface 1a (first main surface, ie, P-type single crystal silicon substrate 1, 1s (here, for example, a 300-phi wafer, but may be a wafer of 450φ or less than 300φ) On the thermal oxide film on the surface opposite to the back surface 1b), silicon nitride by CVD is patterned by ordinary lithography so that silicon nitride on the active region (region where elements are mainly formed) remains. Using this patterned silicon nitride as a mask, an STI element isolation groove is formed on the first main surface 1a of the substrate 1 by dry etching. Subsequently, after a CVD silicon oxide film 2 is formed on the entire surface, reverse pattern etching for subsequent CMP is performed using a black-and-white reversal resist pattern for STI trench etching. Further, the first main surface 1a is planarized by CMP processing, and the field insulating film 4 is left in the trench. Thereafter, silicon nitride that is no longer needed is removed. The field insulating film 4 buried in the STI element isolation trench is an element isolation region 4 that defines a plurality of active regions.

  Next, as shown in FIG. 1, the P-type well region 3 is formed in the N-type device region 21n and the N-type well region 2 is formed in the P-type device region 21p, for example, by ion implantation. Subsequently, a gate insulating film 5 (for example, a nitrided oxide film having a thickness of about 2 nm) is formed on the device main surface 1a (first main surface) of the semiconductor wafer 1 by, for example, thermal oxidation. Further, the gate electrode 6n (for example, N-type polysilicon film) of the N-channel type MISFET is formed on the gate insulating film 5 in the N-type device region 21n by, for example, CVD (Chemical Vapor Deposition) and normal lithography. A gate electrode 6p (for example, a P-type polysilicon film) of a P-channel type MISFET is formed on the gate insulating film 5 in the type device region 21p. Here, the width (gate length) of the gate electrodes 6n and 6p is, for example, about 40 nm (standard target value), and the thickness is, for example, about 80 nm. When it is necessary to feed forward later, the gate width (gate length) of the N-channel MISFET or P-channel MISFET is measured for each wafer 1, for example, 9 points. Then, the average value of each wafer 1 is calculated, and this is used as the individual measured value of the gate length of the wafer. For actual measurement of the gate length, offset spacer length, gate peripheral spacer length, etc., for example, a length measuring SEM (Scanning Electron Microscope) is used. This length measurement is normally performed non-destructively from the device main surface 1a side of the wafer. However, if a correlation with the length measurement SEM of the device cross section is taken in advance, highly accurate measurement becomes possible.

  Next, as shown in FIG. 2, a silicon oxide film such as a TEOS (tetraethylorthosilicate) silicon oxide film is formed on almost the entire device main surface 1a of the wafer 1 as the first offset spacer insulating film 7 by, for example, CVD. (For example, a thickness of about 4 nm) is formed. Subsequently, the device main surface 1a of the wafer 1 is etched back with respect to the first offset spacer insulating film 7, for example, by performing anisotropic dry etching (for example, by a single wafer process). First offset spacers 7 are formed. In this case, the standard target value of the offset spacer length is, for example, about 2 nm.

  Here, for each wafer 1, the first offset spacer length Wno of the N-channel type MISFET is measured for, for example, nine points for each wafer 1, the average value is calculated for each wafer 1, and this is calculated for the first of the wafers. It is assumed that the offset spacer length Wno is 1 and is an actually measured value.

  In this measurement, either the N-channel MISFET or the P-channel MISFET first offset spacer 7 is basically equivalent. This is true for the following offset spacers or gate peripheral spacers as long as the process up to the measurement is substantially the same.

Next, as shown in FIG. 3, by performing ion implantation on the device main surface 1a of the wafer 1 in the N-type device region 21n with the P-type device region 21p covered with the resist film 8, an N-type is obtained. An extension region 9 and a P-type halo region 10 are introduced. Here, the ion type of ion implantation for the N-type extension region 9 is, for example, arsenic, and the implantation method is, for example, vertical implantation. On the other hand, ion species of the ion implantation into the P-type halo region 10 is, for example, BF _2, injection method is, for example, angled implant. Here, when necessary, by adjusting (feed-forward) the dose amount of the P-type halo region 10 based on the previously calculated gate length (individual measured value), variations in transistor characteristics can be reduced. Can be reduced. After the N-type extension region 9 and the P-type halo region 10 are introduced, the resist film 8 that has become unnecessary is removed by ashing or the like.

  Next, as shown in FIG. 4, for example, a silicon nitride film (for example, a thickness of 6.5 nm) is formed on almost the entire device main surface 1a of the wafer 1 as a second offset spacer insulating film 11 by, for example, CVD. Film). Subsequently, the device main surface 1a of the wafer 1 is etched back with respect to the second offset spacer insulating film 11, for example, by performing anisotropic dry etching (for example, by a single wafer process). Then, the second offset spacer 11 is formed. In this case, the target value of the first and second offset spacer lengths Wpo (the sum of the first offset spacer length and the second offset spacer length) of the P-channel MISFET is, for example, about 7 nm.

  Here, for each wafer 1, the first and second offset spacer lengths Wpo of the P-channel type MISFET are measured, for example, at nine points for each wafer 1, and an average value is calculated for each wafer 1, and this is calculated. It is assumed that the first and second offset spacer lengths Wpo of the wafer are individually measured values.

Next, as shown in FIG. 5, by performing ion implantation on the device main surface 1a of the wafer 1 in the P-type device region 21p with the N-type device region 21n covered with the resist film 12, the P-type is obtained. An extension region 13 and an N-type halo region 14 are introduced. Here, the ion type of ion implantation for the P-type extension region 13 is, for example, BF ₂ , and the implantation method is, for example, vertical implantation. On the other hand, the ion species of ion implantation for the N-type halo region 14 is, for example, arsenic or phosphorus, and the implantation method is, for example, inclined implantation. Here, when necessary, variation in transistor characteristics can be reduced by adjusting (feed-forwarding) the dose amount of the N-type halo region 14 based on the previously calculated gate length. . After the introduction of the P-type extension region 13 and the N-type halo region 14, the resist film 12 that is no longer needed is removed by ashing or the like.

  Next, as shown in FIG. 6, for example, a silicon nitride film (for example, a thickness of about 34 nm) is formed as the sidewall insulating film 15 by CVD, for example, on almost the entire device main surface 1 a of the wafer 1. To do.

2. Description of adjustment process A (N-type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (mainly FIGS. 7 to 9, FIGS. 16 and 17)
FIG. 16 is an explanatory diagram for explaining the proper use of the adjustment process A (process branch described in this section) and process B (process branch described in the next section). FIG. 17 is an explanatory diagram for explaining each symbol appearing in FIG. The process described in this section can be applied when the condition of FIG. 16 is other than the condition (# 4). Otherwise, that is, when the condition of FIG. 16 is the condition (# 4), the process of the next section can be applied.

  According to the adjustment process described in this section and the next section, the subsequent gate peripheral spacers are compensated so that the characteristics are compensated for variations in offset spacers that determine the edge of the preceding extension (self-aligned edges). Since the width can be adjusted, the electrical characteristics of the product can be made uniform.

  In addition, by independently adjusting both channels, the electrical characteristics of the N-channel MISFET and the P-channel MISFET can be individually compensated.

  FIG. 7 is a manufacturing process for explaining adjustment process A (N-type device region advance adjustment) in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (spacer length advance adjustment step of N-type device region). FIG. FIG. 8 is a manufacturing process for explaining the adjustment process A (N-type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention (secondary adjustment step of the spacer length of the P-type device region). And FIG. 6 is a device schematic cross-sectional view of a step of introducing a P-type source / drain region. FIG. 9 is a device schematic view during the manufacturing process (N-type source / drain region introduction step) for explaining the adjustment process A (N-type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is sectional drawing. Based on these, the adjustment process A (N-type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application will be described.

Following the process described with reference to FIG. 6, as shown in FIG. 7, the device main surface 1 a of the wafer 1 is etched back with respect to the sidewall insulating film 15 by performing, for example, anisotropic dry etching. The sidewall 15 is formed (for example, by a single wafer process). Here, the target value (individual target value) of the gate peripheral spacer length Wns of the N-channel MISFET after the etch-back for each wafer is determined as follows. That is,
(1) According to FIG. 17, the difference (ΔOSS_n) between the standard target value of the first offset spacer length and the individual actually measured value, the Ids offset spacer sensitivity (ΔIds−oss_n) of the N-channel MISFET whose data has been acquired in advance, and The correction amount (ΔSW_n) from the standard target value of the spacer length of the N channel MISFET is calculated from the Ids gate peripheral spacer sensitivity (ΔIds−sw_n) of the N channel MISFET.
(2) According to whether the correction amount (ΔSW_n) of the spacer length of the N-channel type MISFET from the standard target value is incremented or decreased, the spacer length is changed to the standard target value of the spacer length (for example, 35 nm). In addition, the changed target value is set as an individual target value for the wafer.

  After this etch-back process (side wall primary etch-back process), the gate peripheral spacer length Wns of the N-channel MISFET is measured for each wafer 1, for example, 9 points, and the average value is calculated for each wafer 1. This is used as an individual measured value of the gate peripheral spacer length Wns of the N channel MISFET of the wafer.

Next, as shown in FIG. 8, for example, anisotropic dry etching is performed on the device main surface 1 a of the wafer 1 in a state where the N-type device region 21 n side is covered with the resist film 16. A secondary etchback process is performed on the side wall insulating film 15 of the channel MISFET (for example, by a single wafer process) to form the side wall 15 of the P channel MISFET. Here, the target value (individual target value) of the gate peripheral spacer length Wps of the P-channel MISFET after the etch-back for each wafer is determined as follows. That is,
(1) According to FIG. 17, the difference (ΔOSS_p) between the standard target value of the first and second offset spacer lengths Wpo and the individual actually measured values, the offset spacer sensitivity (ΔIds) of the Ids of the P-channel type MISFET whose data has been acquired in advance. The correction amount (ΔSW_p) from the standard target value of the spacer length of the P-channel type MISFET is calculated from −oss_p) and the Ids gate peripheral spacer sensitivity (ΔIds−sw_p) of the P-channel type MISFET.
(2) According to whether the correction amount (ΔSW_p) from the standard target value of the spacer length of this P-channel type MISFET is an increment or a decrease, the standard target value of the spacer length is changed by the correction amount, The changed target value is set as an individual target value for the wafer. Therefore, the additional etch back amount in the secondary etch back process is equal to the difference between the individual measured value of the gate peripheral spacer length Wns of the N channel MISFET and the individual target value of the spacer length of the P channel MISFET of the wafer.

  Subsequently, for example, boron ions are ion-implanted (perpendicularly implanted) into the device main surface 1a of the wafer 1 in a state where the N-type device region 21n side is covered with the resist film 16, whereby a P-type source / drain region is formed. 17 is introduced. Thereafter, the resist film 16 that is no longer needed is removed by ashing or the like.

  Here, as necessary, the gate peripheral spacer length Wps of the P-channel type MISFET is measured for each wafer 1, for example, nine points, and the average value is calculated for each wafer 1, and this is calculated. It is an individual measured value of the gate peripheral spacer length Wps of the P-channel type MISFET.

  Next, for example, arsenic ions are ion-implanted (vertical implantation) into the device main surface 1a of the wafer 1 with the P-type device region 21p side covered with the resist film 18 as shown in FIG. Thus, the N-type source / drain region 19 is introduced. Thereafter, the resist film 18 that is no longer needed is removed by ashing or the like.

  Thereafter, the process described in section 4 is performed.

3. Description of adjustment process B (P-type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (mainly FIGS. 10 to 12)
The process described in this section can be applied when the condition of FIG. 16 is other than the condition (# 3).

  FIG. 10 is a manufacturing process for explaining adjustment process B (P-type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention (P-type device region spacer length advance adjustment step). FIG. FIG. 11 is a device schematic view during the manufacturing process (P-type source / drain region introduction step) for explaining the adjustment process B (P-type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is sectional drawing. FIG. 12 is a manufacturing process for explaining the adjustment process B (P-type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention (secondary adjustment step of spacer length in the N-type device region). And N-type source / drain region introduction step). Based on these, the adjustment process B (P-type device region advance adjustment) in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application will be described.

Following the process described with reference to FIG. 6, as shown in FIG. 10, the device main surface 1 a of the wafer 1 is etched back with respect to the sidewall insulating film 15 by performing, for example, anisotropic dry etching. The sidewall 15 is formed (for example, by a single wafer process). Here, the target value (individual target value) of the gate peripheral spacer length Wps of the P-channel MISFET after the etch-back for each wafer is determined as follows. That is,
(1) According to FIG. 17, the difference (ΔOSS_p) between the standard target value of the first and second offset spacer lengths Wpo and the individual actually measured values, the offset spacer sensitivity (ΔIds) of the Ids of the P-channel type MISFET whose data has been acquired in advance. The correction amount (ΔSW_p) from the standard target value of the spacer length of the P-channel type MISFET is calculated from −oss_p) and the Ids gate peripheral spacer sensitivity (ΔIds−sw_p) of the P-channel type MISFET.
(2) According to whether the correction amount (ΔSW_p) from the standard target value of the spacer length of this P-channel type MISFET is an increment or a decrease, the spacer length is changed to the standard target value (for example, 35 nm) by the correction amount. In addition, the changed target value is set as an individual target value for the wafer.

  After this etch-back process (side wall primary etch-back process), the gate peripheral spacer length Wps of the P-channel type MISFET is measured for each wafer 1, for example, 9 points, and the average value is calculated for each wafer 1. Then, this is an individual actual measurement value of the gate peripheral spacer length Wps of the P channel MISFET of the wafer.

  Next, as shown in FIG. 11, for example, boron ions are ion-implanted (vertical implantation) into the device main surface 1 a of the wafer 1 with the N-type device region 21 n side covered with the resist film 16. Thus, the P-type source / drain region 17 is introduced. Thereafter, the resist film 16 that is no longer needed is removed by ashing or the like.

Next, as shown in FIG. 12, the device main surface 1a of the wafer 1 is subjected to, for example, anisotropic dry etching while the P-type device region 21p side is covered with the resist film 18, so that N A secondary etchback process is performed on the side wall insulating film 15 of the channel type MISFET (for example, by a single wafer process) to form the side wall 15 of the N channel type MISFET. Here, the target value (individual target value) of the gate peripheral spacer length Wns of the N-channel MISFET after the etch-back for each wafer is determined as follows. That is,
(1) According to FIG. 17, the difference (ΔOSS_n) between the standard target value of the first offset spacer length and the individual actually measured value, the Ids offset spacer sensitivity (ΔIds−oss_n) of the N-channel MISFET whose data has been acquired in advance, and The correction amount (ΔSW_n) from the standard target value of the spacer length of the N channel MISFET is calculated from the Ids gate peripheral spacer sensitivity (ΔIds−sw_n) of the N channel MISFET.
(2) According to whether the correction amount (ΔSW_n) from the standard target value of the spacer length of this N-channel type MISFET is an increment or a decrease, the standard target value of the spacer length is changed by the correction amount, The changed target value is set as an individual target value for the wafer. Therefore, the additional etch back amount in the secondary etch back process is equal to the difference between the individual actual measurement value of the gate peripheral spacer length Wps of the P channel MISFET and the individual target value of the gate peripheral spacer length Wns of the N channel MISFET of the wafer. Become.

  Subsequently, for example, arsenic ions are ion-implanted (perpendicularly implanted) into the device main surface 1a of the wafer 1 in a state where the P-type device region 21p side is covered with the resist film 18 to thereby form an N-type source / drain region. 19 is introduced. Thereafter, the resist film 18 that is no longer needed is removed by ashing or the like.

  Here, if necessary, the gate peripheral spacer length Wns of the N-channel type MISFET is measured, for example, at nine points for each wafer 1, and an average value is calculated for each wafer 1, and this is calculated. It is an individual measured value of the gate peripheral spacer length Wns of the N-channel MISFET.

  Thereafter, the process described in section 4 is performed.

4). Description of common CMIS process subsequent to adjustment process in manufacturing method of semiconductor integrated circuit device of one embodiment of the present application (mainly FIGS. 13 to 15)
FIG. 13 is a device schematic cross-sectional view during the manufacturing process (nickel silicide film forming step) for explaining the common CMIS process subsequent to the adjustment process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 14 is a device schematic sectional view in the manufacturing process (premetal insulating film forming step) for explaining the common CMIS process subsequent to the adjustment process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 15 is a device schematic cross-sectional view in the manufacturing process (tungsten plug formation step) for explaining the common CMIS process subsequent to the adjustment process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. Based on these, the common CMIS process subsequent to the adjustment process in the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application will be described.

  Following the process of FIG. 9 or FIG. 12, as shown in FIG. 13, a silicide film 22 (for example, on the upper surfaces of the source / drain regions 17 and 19 and the upper surfaces of the gate electrodes 6n and 6p by, for example, a salicide process). Nickel silicide film) is formed.

  Next, as shown in FIG. 14, a relatively thin silicon nitride insulating film 23 (which constitutes a part of the premetal insulating film) is formed on almost the entire device surface 1a of the wafer 1 as CESL, for example, by CVD or the like. Is deposited. Subsequently, a silicon oxide premetal insulating film 24 is formed on almost the entire surface of the silicon nitride insulating film 23 by, for example, CVD. Thereafter, the premetal insulating film 24 is planarized by CMP or the like as necessary.

  Next, as shown in FIG. 15, contact holes are formed by performing anisotropic dry etching or the like on the premetal insulating film including the silicon nitride insulating film 23. A tungsten plug 25 is buried in this contact hole by CVD, metal CMP, or the like. Thereafter, copper-based damascene wiring (embedded wiring), aluminum-based non-embedded wiring, or the like is formed as necessary. Thus, the N channel MISFET (Qn) and the P channel MISFET (Qp) are almost completed.

5. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, an example in which a semiconductor integrated circuit device is formed on a P-type single crystal silicon wafer as a raw material has been described. Needless to say, it may be a wafer or an SOI wafer. In the above-described embodiment, the example of measuring the length by a method such as SEM has been mainly described. However, the length is measured by a mechanical method such as AFM (Atomic Force Microscopy) or other optical method. Needless to say.

  In the above embodiment, the gate first method has been mainly described as an example. However, the present invention is not limited to this, and the gate last method and the both methods are used. It goes without saying that it can also be applied to eclectic processes.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1a Wafer or chip | tip surface (device surface, 1st main surface)
1b Wafer or chip backside 1s P-type silicon single crystal semiconductor substrate 2 N-type well region 3 P-type well region 4 STI region (field insulating film)
5 Gate insulating film 6n Gate electrode of N-channel MISFET 6p Gate electrode of P-channel MISFET 7 First offset spacer (first insulating film for offset spacer)
8 N-type extension region introduction resist film 9 N-type extension region 10 P-type halo region 11 Second offset spacer (second offset spacer insulating film)
12 P-type extension region introduction resist film 13 P-type extension region 14 N-type halo region 15 Side wall (insulating film for side wall)
16 P-type source / drain region introduction resist film 17 P-type source / drain region 18 N-type source / drain region introduction resist film 19 N-type source / drain region 21n N-type device region 21p P-type device region 22 Nickel silicide film 23 Silicon nitride system Insulating film 24 Silicon oxide pre-metal insulating film 25 Tungsten plug Qn N-channel MISFET
Qp P channel type MISFET
Wno N-channel MISFET first offset spacer length Wns N-channel MISFET gate peripheral spacer length Wpo P-channel MISFET first and second offset spacer lengths Wps P-channel MISFET gate peripheral spacer length ΔIds-oss_n N-channel Ids offset spacer sensitivity of I-type MISFET ΔIds-oss_p Ids offset spacer sensitivity of P-channel MISFET ΔIds-sw_n Ids gate peripheral spacer sensitivity of N-channel MISFET ΔIds-sw_p Ids gate peripheral spacer sensitivity ΔOSS_n of P-channel MISFET Difference between standard target value of first offset spacer length and individual measured location ΔOSS_p Difference between standard target value of first and second offset spacer length and individual measured location Minute ΔSW_n Correction amount from standard target value of spacer length of N-channel type MISFET ΔSW_p Correction amount from standard target value of spacer length of P-channel type MISFET

Claims (2)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a first gate electrode of an N-channel MISFET and a second gate electrode of a P-channel MISFET on a first main surface of a semiconductor wafer;
(B) forming offset spacers on sidewalls of the first gate electrode and the second gate electrode;
(C) measuring the offset spacer length of the offset spacer;
(D) Introducing an impurity by ion implantation into the semiconductor region of the first main surface around one of the first gate electrode and the second gate electrode in a state where the offset spacer is present. Introducing an extension region by:
(E) forming a spacer including the offset spacer by forming a sidewall spacer on a side wall of one of the first gate electrode and the second gate electrode in a state where the offset spacer is present; ,
Here, the spacer length of the spacer is adjusted by controlling the etch back amount based on the measured offset spacer length of the offset spacer.     In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the spacer length is adjusted independently for the N-channel MISFET and the P-channel MISFET.

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