CN107946172B - Advanced manufacturing process control method - Google Patents
Advanced manufacturing process control method Download PDFInfo
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- CN107946172B CN107946172B CN201610893739.9A CN201610893739A CN107946172B CN 107946172 B CN107946172 B CN 107946172B CN 201610893739 A CN201610893739 A CN 201610893739A CN 107946172 B CN107946172 B CN 107946172B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Abstract
The invention discloses an advanced manufacturing process control method. First, a gate structure is formed on a substrate, then a spacer is formed beside the gate structure, and a first measurement step is performed to measure the critical dimension of the spacer. Then forming an oxide layer on the substrate surface at both sides of the spacer, performing a cleaning step to remove part of the oxide layer and simultaneously adjusting the time of the cleaning step according to the critical dimension of the spacer to control the thickness of the oxide layer, performing a second measuring step to measure the thickness of the oxide layer, and forming a source/drain region in the substrate at both sides of the spacer.
Description
Technical Field
The present invention relates to an advanced manufacturing process control method, and more particularly, to an advanced manufacturing process control method for adjusting the time of a cleaning step according to the critical dimension of a spacer and further controlling the thickness of an oxide layer.
Background
In the fabrication process of semiconductor integrated circuits, a metal-oxide-semiconductor (MOS) transistor is an extremely important electronic component, and as the size of the semiconductor component is smaller, the fabrication process steps of the MOS transistor are improved to fabricate the MOS transistor with small volume and high quality.
In the conventional MOS transistor fabrication process, a gate structure is formed on a semiconductor substrate, and then a Lightly Doped Drain (LDD) structure is formed in the substrate on two opposite sides of the gate structure. Then, a spacer is formed at the side of the gate structure, and an ion implantation step is performed to form a source/drain region in the semiconductor substrate by using the gate structure and the spacer as a mask.
However, the Critical Dimension (CD) of the formed spacer is usually subject to errors under standard fabrication processes and is prone to device variations. To address this drawback, it is common practice to selectively adjust the dopant dose of the source/drain regions or adjust the temperature of the thermal process required to form the source/drain regions to control the spacer critical dimension width based on the spacer critical dimension width. However, any adjustment method has its relative disadvantages, so how to improve the existing manufacturing process and provide a more effective manufacturing process control method is an important issue today.
Disclosure of Invention
The preferred embodiment of the invention discloses an advanced manufacturing process control method. First, a gate structure is formed on a substrate, then a spacer is formed beside the gate structure, and a first measurement step is performed to measure the critical dimension of the spacer. Then forming an oxide layer on the substrate surface at both sides of the spacer, performing a cleaning step to remove part of the oxide layer and simultaneously adjusting the time of the cleaning step according to the critical dimension of the spacer to control the thickness of the oxide layer, performing a second measuring step to measure the thickness of the oxide layer, and forming a source/drain region in the substrate at both sides of the spacer.
Drawings
FIG. 1 is a schematic diagram of a semiconductor device according to a preferred embodiment of the present invention;
FIG. 2 is a flow chart illustrating a first embodiment of the present invention for fabricating the semiconductor device of FIG. 1;
FIG. 3 is a flow chart illustrating a second embodiment of the present invention for fabricating the semiconductor device of FIG. 1;
fig. 4 is a flowchart illustrating a third embodiment of the present invention for fabricating the semiconductor device of fig. 1.
Description of the main elements
12 substrate 14 gate structure
16 gate dielectric layer 18 gate material layer
20 hard mask 22 shallow trench isolation
24 offset spacer 26 lightly doped drain
28 main spacer 30 source/drain region
32 oxide 34 spacer
Width W
Detailed Description
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram illustrating a semiconductor device according to a preferred embodiment of the invention, and fig. 2 is a flowchart illustrating a semiconductor device according to fig. 1 according to a first embodiment of the invention. As shown in fig. 1, a substrate 12 is provided, and at least one gate structure 14 is formed on the substrate 12. In the present embodiment, the gate structure 14 is preferably formed by sequentially forming a gate dielectric layer, a gate material layer and a hard mask on the substrate 12, performing a pattern transfer process using a patterned photoresist (not shown) as a mask, removing a portion of the hard mask, a portion of the gate material layer and a portion of the gate dielectric layer by a single etching step or a sequential etching step, and then stripping the patterned photoresist to form at least one gate structure 14 comprising the patterned gate dielectric layer 16, the patterned gate material layer 18 and the patterned hard mask 20 on the substrate 12. In the present embodiment, the number of the gate structures 14 is, for example, but not limited to, a single gate structure.
In the present embodiment, the substrate 12 is a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto. The gate dielectric layer 16 may comprise silicon dioxide (SiO)2) Silicon nitride (SiN) or high dielectric constant (high-k) materials; the gate material layer 18 may comprise a conductive material such as a metal material, polysilicon, or metal silicide; the hard mask 20 may be selected from the group consisting of silicon oxide, silicon nitride, silicon carbide (SiC), and silicon oxynitride (SiON), but is not limited thereto.
In addition, in one embodiment, a doped well (not shown) or at least one Shallow Trench Isolation (STI) 22 for electrical isolation may be formed in the substrate 12 in advance. Moreover, although the present embodiment is illustrated with a planar transistor, in other variations, the semiconductor fabrication process of the present invention may be applied to a non-planar transistor, such as a Fin-FET (Fin-FET), where the substrate 12 as indicated in fig. 1 is correspondingly represented as a Fin structure formed on a substrate 12.
Then, at least one spacer, such as an offset spacer 24, is formed on the sidewall of the gate structure 14, and a lightly doped ion implantation is selectively performed, and a rapid thermal annealing process is performed at about 930 ℃ to activate the dopants implanted into the substrate 12, so as to form a lightly doped drain 26 in the substrate 12 on both sides of the offset spacer 24. Another spacer, such as a main spacer 28, is then formed on the sidewall of the offset spacer 24, and the offset spacer 24 and the main spacer 28 together form a spacer 34. In the present embodiment, the offset spacers 24 and the main spacers 28 preferably comprise different materials, and both may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride, but are not limited thereto.
Then, in step 101, a measurement step is performed to measure the critical dimension of the spacer, or more specifically, the distance between the offset spacer 24 and the bottom of the main spacer 28 extending from the sidewall edge of the gate structure 14 to the shallow trench isolation 22, and thereby obtaining a width W. A heavily doped ion implantation process is then performed to implant ions into the substrate 12 on both sides of the main spacer 28 to form source/drain regions 30.
Then, in step 102, an oxide layer 32 is formed on the surface of the substrate 12 on both sides of the main spacer 28. More specifically, in the present embodiment, the oxide layer 32 is formed by forming a metal silicide blocking layer (SAB) or a stress layer made of a dielectric material to define a position where the metal silicide is to be formed before forming the metal silicide through a self-aligned silicide (salicide) process, and then forming an oxide layer 32 on the surface of the substrate 12 on both sides of the spacer 34 while removing at least a portion of the metal silicide blocking layer or stress layer by etching. In the present embodiment, the etching solution for removing the silicide barrier layer or the stress layer may include, but is not limited to, a mixed solution of ammonia, hydrogen peroxide, hydrochloric acid, sulfuric acid, nitric acid, and acetic acid, and the thickness of the oxide layer 32 formed at this stage is preferably between 50 a and 60 a.
Then, in step 103, a cleaning step is performed to remove a portion of the oxide layer 32 and adjust the time for performing the cleaning step according to the critical dimension of the spacer 34, such as the critical dimension width W obtained in step 101, thereby controlling the thickness of the oxide layer 32. More specifically, the cleaning step of the present embodiment preferably includes performing a dynamic (dynamic) RCA cleaning step, wherein the longer the RCA cleaning step is performed, the lower the thickness of the remaining oxide layer 32 is, and the shorter the RCA cleaning step is performed, the higher the thickness of the remaining oxide layer 32 is.
Generally, if the measured critical dimension width W of the spacers 34 is larger, the present invention can utilize a longer cleaning time to make the remaining oxide layer 32 have a smaller thickness, thereby bringing the source/drain regions 30 closer to the channel region. Conversely, if the measured critical dimension width W of the spacer 34 is small, the present invention can utilize a shorter cleaning time to make the remaining oxide layer 32 have a larger thickness and to prevent the source/drain regions 30 from being too close to the channel region. In other words, the present invention primarily controls the remaining thickness of the oxide layer 32 on the surface of the substrate 12 by adjusting the time of the cleaning process, and further adjusts the location where the source/drain regions 30 are formed. In this embodiment, the RCA cleaning step mainly comprises using a cleaning solution containing ammonium hydroxide (NH)4OH) and hydrogen peroxide (H)2O2) The RCA cleaning fluid of (1) removes a portion of the oxide layer 32 on the surface of the substrate 12.
Next, in step 104, another measurement step is performed to measure the thickness of the remaining oxide layer 32 after the RCA cleaning step is completed. According to the present embodiment, the thickness of the remaining oxide layer 32 at this stage is between 10 and 40 angstroms.
Then, in step 105, after the thickness of the oxide layer 32 is measured, a thermal annealing process is performed, for example, a high temperature of 1000 to 1050 ℃ is used to activate the dopants previously implanted into the substrate 12 and simultaneously repair the lattice structure on the surface of the substrate 12 damaged in each ion implantation process.
It should be noted that, although the source/drain regions 30 are formed in the substrate 12 by a heavy doping ion implantation process between the steps 101 and 102 in the present embodiment, the time of the heavy doping ion implantation process may be shifted between the steps 104 and 105 according to an embodiment of the present invention, that is, the ion implantation process may be performed to form the source/drain regions 30 after the thickness of the oxide layer 32 is measured, and then the implanted dopants are diffused by a thermal annealing process, which also falls within the scope of the present invention.
A subsequent transistor fabrication process may be performed according to the fabrication process requirements, for example, a Contact Etch Stop Layer (CESL) and an interlayer dielectric layer (ILD) may be sequentially formed on the substrate 12 and cover the gate structure 14, and then, for example, Chemical Mechanical Polishing (CMP) may be used to remove a portion of the ILD, a portion of the contact etch stop layer, and the hard mask 20 and expose the gate material layer 18 made of polysilicon material, so that the upper surface of the gate material layer 18 is flush with the upper surface of the ILD. A metal gate replacement process may then be performed to remove the layer of gate material 18 comprised of polysilicon and convert the gate structure 14 into a metal gate. Thus, the semiconductor device according to the first embodiment of the present invention is completed.
Referring to fig. 1 and fig. 3, fig. 3 is a flowchart illustrating a manufacturing process of the semiconductor device shown in fig. 1 according to a second embodiment of the invention. As shown in fig. 1, a substrate 12 is provided, at least one gate structure 14 is formed on the substrate 12, at least one spacer, such as an offset spacer 24, is formed on a sidewall of the gate structure 14, and a lightly doped drain 26 is selectively formed in the substrate 12 on both sides of the offset spacer 24 by lightly doped ion implantation. Another spacer, such as a main spacer 28, is then formed on the sidewall of the offset spacer 24, wherein the offset spacer 24 and the main spacer 28 together form a spacer 34.
Then, in step 201, a measurement step is performed to measure the critical dimension of the spacer 34, or more specifically, to measure the distance from the sidewall edge of the gate structure 14 to the shallow trench isolation 22 at the bottom of the spacer 34 to obtain a width W. A heavily doped ion implantation process is then performed to implant ions into the substrate 12 on both sides of the spacer 24 to form source/drain regions 30.
Next, in step 202, an oxide layer 32 is formed on the surface of the substrate 12 on both sides of the main spacer 28. The oxide layer 32 is preferably formed by etching and removing the silicide barrier layer or stress layer in accordance with step 101 to form an oxide layer 32 on the surface of the substrate 12 on both sides of the spacer 34.
Then, step 203 is performed to perform a cleaning step, or more specifically, an RCA cleaning step, to remove a portion of the oxide layer 32. In contrast to the step 103, the RCA cleaning step performed at this stage is not a dynamic RCA cleaning step, but only a portion of the oxide layer 32 on the surface of the substrate 12 is removed by using the RCA cleaning solution.
Then, in step 204, a diluted hydrofluoric acid cleaning step is performed to remove a portion of the oxide layer 32 and adjust the time for performing the cleaning step according to the critical dimension of the spacer 34, such as the critical dimension width W obtained in step 201, thereby controlling the thickness of the oxide layer 32. Similar to step 103, the cleaning process at this stage preferably includes performing a dynamic diluted hydrofluoric acid cleaning process to remove a portion of the remaining oxide layer 32, and controlling the thickness of the oxide layer 32 on the surface of the substrate 12 by adjusting the time of the cleaning process. In other words, the longer the diluted hydrofluoric acid cleaning step is performed, the lower the thickness of the remaining oxide layer 32 is, and the shorter the diluted hydrofluoric acid cleaning step is performed, the higher the thickness of the remaining oxide layer 32 is.
Next, in step 205, another measurement step is performed after the diluted hydrofluoric acid cleaning step is completed to measure the thickness of the remaining oxide layer 32. According to the present embodiment, the thickness of the oxide layer 32 remaining at this stage is preferably between 10 and 40 angstroms.
Then, in step 206, a thermal annealing process is performed after the oxide layer thickness is measured, for example, a high temperature of 1000 to 1050 ℃ is used to activate the dopants previously implanted into the substrate 12 and simultaneously repair the lattice structure of the surface of the substrate 12 damaged by the ion implantation processes.
As in the previous embodiments, although the heavily doped ion implantation process is selected to form the source/drain regions 30 in the substrate 12 between the steps 201 and 202, the present embodiment is not limited thereto, and according to an embodiment of the present invention, the time of the heavily doped ion implantation process can be shifted between the steps 205 and 206, i.e., the ion implantation process can be performed to form the source/drain regions 30 after the thickness of the oxide layer 32 is measured, and then the implanted dopants are diffused by the thermal annealing process, which also falls within the scope of the present invention.
Thereafter, a subsequent transistor fabrication process may be performed according to the fabrication process requirements, for example, a contact hole etch stop layer and an interlayer dielectric layer may be sequentially formed on the substrate 12 and cover the gate structure 14, and then, for example, a chemical mechanical polishing process may be used to remove a portion of the interlayer dielectric layer, a portion of the contact hole etch stop layer, and the hard mask 20 and expose the gate material layer 18 formed of polysilicon material, so that the upper surface of the gate material layer 18 is flush with the upper surface of the interlayer dielectric layer. A metal gate replacement process may then be performed to remove the layer of gate material 18 comprised of polysilicon and convert the gate structure 14 into a metal gate. Thus, the semiconductor device according to the second embodiment of the present invention is completed.
Referring to fig. 1 and fig. 4, fig. 4 is a flowchart illustrating a manufacturing process of the semiconductor device shown in fig. 1 according to a third embodiment of the present invention. As shown in fig. 1, a substrate 12 is provided, at least one gate structure 14 is formed on the substrate, at least one spacer, such as an offset spacer 24, is formed on a sidewall of the gate structure 14, and a lightly doped drain 26 is selectively formed in the substrate 12 on both sides of the offset spacer 24 by lightly doped ion implantation. Another spacer, such as a main spacer 28, is then formed on the sidewall of the offset spacer 24, wherein the offset spacer 24 and the main spacer 28 together form a spacer 34.
Then, in step 301, a measurement step is performed to measure the critical dimension of the spacer 34, or more specifically, the distance extending from the sidewall edge of the gate structure 14 to the shallow trench isolation 22 at the bottom of the spacer 34 to obtain a width W. A heavily doped ion implantation process is then performed to implant ions into the substrate 12 on both sides of the spacer 24 to form source/drain regions 30.
Next, step 302 is performed to form an oxide layer 32 on the surface of the substrate 12 on both sides of the main spacer 28. The oxide layer 32 is preferably formed by etching and removing the silicide barrier layer or stress layer in accordance with step 101 to form an oxide layer 32 on the surface of the substrate 12 on both sides of the spacer 34.
Then, step 303 is performed to perform a cleaning step, or more specifically, an RCA cleaning step, to remove a portion of the oxide layer. Like step 203, the RCA cleaning step performed at this stage is not a dynamic RCA cleaning step, but only a RCA cleaning solution is used to remove a portion of the oxide layer 32 on the surface of the substrate 12.
Then, in step 304, another measurement step is performed to measure the thickness of the remaining oxide layer 32.
Then, in step 305, another RCA cleaning step is performed to remove a portion of the oxide layer 32 while adjusting the time for performing the cleaning step according to the critical dimension width W of the spacer 34, thereby controlling the thickness of the oxide layer 32. Like step 103, the RCA cleaning step performed at this stage preferably includes a dynamic RCA cleaning step, in which the thickness of the remaining oxide layer 32 is lower as the RCA cleaning step is performed for a longer time, and the thickness of the remaining oxide layer 32 is higher as the RCA cleaning step is performed for a shorter time. In other words, the remaining thickness of the oxide layer 32 on the surface of the substrate 12 is controlled by adjusting the time of the cleaning process, and the position where the source/drain regions 30 are formed is adjusted.
Next, in step 306, another measurement step is performed after the diluted hydrofluoric acid cleaning step is completed to measure the thickness of the remaining oxide layer 32. According to the present embodiment, the thickness of the oxide layer 32 remaining at this stage is preferably between 10 and 40 angstroms.
Then, in step 307, a thermal annealing process is performed after the oxide layer thickness is measured, for example, a high temperature of 1000 to 1050 ℃ is used to activate the dopants previously implanted into the substrate 12 and simultaneously repair the lattice structure of the surface of the substrate 12 damaged in each ion implantation process.
As in the previous embodiments, although the heavily doped ion implantation process is selected to form the source/drain regions 30 in the substrate 12 between the steps 301 and 302, the present embodiment is not limited thereto, and according to an embodiment of the present invention, the time of the heavily doped ion implantation process can be shifted between the steps 306 and 307, i.e., the ion implantation process can be performed to form the source/drain regions 30 after the thickness of the oxide layer 32 is measured, and then the implanted dopants are diffused by the thermal annealing process, which also falls within the scope of the present invention.
Thereafter, a subsequent transistor fabrication process may be performed according to the fabrication process requirements, for example, a contact hole etch stop layer and an interlayer dielectric layer may be sequentially formed on the substrate 12 and cover the gate structure 14, and then, for example, a chemical mechanical polishing process may be used to remove a portion of the interlayer dielectric layer, a portion of the contact hole etch stop layer, and the hard mask 20 and expose the gate material layer 18 formed of polysilicon material, so that the upper surface of the gate material layer 18 is flush with the upper surface of the interlayer dielectric layer. A metal gate replacement process may then be performed to remove the layer of gate material 18 comprised of polysilicon and convert the gate structure 14 into a metal gate. Thus, the semiconductor device according to the third embodiment of the present invention is completed.
In summary, compared to the conventional method of controlling the critical dimension width of the spacer by adjusting the dopant dose of the source/drain region or adjusting the temperature of the thermal process required for forming the source/drain region, the present invention preferably controls the remaining thickness of the oxide layer on the substrate surface by adjusting the time of the cleaning step without adjusting the dopant dose of any source/drain region (i.e., using a fixed dopant dose) and without adjusting the thermal process temperature (i.e., using a fixed thermal process temperature), and thus controls the location where the source/drain region is formed.
The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.
Claims (8)
1. An advanced manufacturing process control method, comprising:
providing a substrate, wherein a grid structure is arranged on the substrate;
forming a spacer beside the gate structure;
performing a first measurement step to measure the critical dimension of the spacer;
forming an oxide layer on the substrate surface at both sides of the spacer;
performing a cleaning step to remove a portion of the oxide layer and adjusting the time of the cleaning step according to the critical dimension of the spacer to control the thickness of the oxide layer;
performing a second measurement step to measure the thickness of the oxide layer; and
a thermal annealing process is performed.
2. The method of claim 1, wherein the cleaning step comprises performing an RCA cleaning step to remove a portion of the oxide layer.
3. The method of advanced manufacturing process control as claimed in claim 1, wherein said cleaning step comprises:
performing an RCA cleaning step to remove part of the oxide layer; and
a diluted hydrofluoric acid cleaning step is performed to remove a portion of the remaining oxide layer.
4. The method of advanced manufacturing process control as claimed in claim 1, wherein said cleaning step comprises:
performing a first RCA cleaning step to remove part of the oxide layer;
performing a third measurement step to measure the thickness of the oxide layer; and
a second RCA clean step is performed to remove a portion of the remaining oxide layer.
5. The method of claim 1, wherein the thickness of the oxide layer before the cleaning step is between 50 and 60 angstroms.
6. The method of claim 1, wherein a thickness of the oxide layer after the second measuring step is between about 10 and about 40 angstroms.
7. The method of claim 1, further comprising performing an ion implantation process to form a source/drain region after the first measuring step and before the oxide layer is formed.
8. The method of claim 1, further comprising performing an ion implantation process after the second measuring step and before the thermal annealing process to form a source/drain region.
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| CN101740376A (en) * | 2008-11-25 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Method for regulating width of spacer wall and method for etching in construction of spacer wall |
| CN104103503A (en) * | 2013-04-02 | 2014-10-15 | 无锡华润上华科技有限公司 | Formation method of semiconductor device gate oxide layer |
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| US6649426B2 (en) * | 2001-06-28 | 2003-11-18 | Advanced Micro Devices, Inc. | System and method for active control of spacer deposition |
| CN104157564B (en) * | 2013-05-15 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | Improve the method for critical dimension uniformity after etching |
| CN103280408B (en) * | 2013-05-31 | 2016-08-10 | 上海华力微电子有限公司 | The manufacture method of side wall in semiconductor device |
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| CN101740376A (en) * | 2008-11-25 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Method for regulating width of spacer wall and method for etching in construction of spacer wall |
| CN104103503A (en) * | 2013-04-02 | 2014-10-15 | 无锡华润上华科技有限公司 | Formation method of semiconductor device gate oxide layer |
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