JP2005333060A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the complication of a manufacturing step and to reduce thinning of an element isolation oxide film. <P>SOLUTION: While an oxidation prevention film 3 is used as a mask, a semiconductor substrate 1 is selectively oxidized to form an element isolation oxide film 4 in an element isolation area E2. Then, while the oxidation prevention film 3 is used as a mask, ion implantation P1 of n<SP>+</SP>ion is performed into the front surface of the element isolation oxide film 4, thereby forming a nitrogen ion implantation layer 5 on the front surface of the element isolation oxide film 4. The nitrogen ion implantation layer 5 is heated so as to change the nitrogen ion implantation layer 5 into an oxynitride film 6, so that the oxynitride film 6 is formed on the element isolation oxide film 4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable for application to a method for reducing the reduction in element isolation oxide film thickness.

In a conventional semiconductor device, there is a method using a LOCOS structure in order to stably perform element isolation. Further, for example, in Patent Document 1, in a mixed mounting process with a memory cell having a stacked two-layer gate electrode, an insulating film including a silicon nitride film is formed on a field oxide film, thereby performing a subsequent cleaning process or A method for reducing film loss of a field oxide film in an etching process is disclosed.
JP-A-8-88360

However, in the cleaning process and the etching process after the element isolation oxide film is formed, the element isolation oxide film is reduced, and the element isolation oxide film gradually becomes thinner as the semiconductor manufacturing process progresses. For this reason, there has been a problem that the reliability of the semiconductor device deteriorates due to a decrease in field breakdown voltage, field inversion, or an increase in parasitic capacitance.
Further, in the method disclosed in Patent Document 1, in order to form an insulating film including a silicon nitride film on the field oxide film, it is necessary to perform deposition, photolithography, and etching of the insulating film, which increases the number of processes. There was a problem. Further, when the insulating film including the silicon nitride film is etched, there is a problem that the element formation region is also etched and the element formation region is damaged.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce the reduction of the element isolation oxide film while suppressing the complexity of the manufacturing process.

  In order to solve the above-described problem, according to a semiconductor device of one embodiment of the present invention, an element isolation oxide film formed in an element isolation region on a semiconductor and a surface layer of the element isolation oxide film are self-aligned. The formed oxynitride film, the gate electrode formed on the semiconductor element separated by the element isolation oxide film, and the source / drain formed on the semiconductor so as to be disposed on both sides of the gate electrode, respectively. And a layer.

Thus, the oxynitride film can be formed on the surface layer of the element isolation oxide film by performing a heat treatment on the element isolation oxide film implanted with N ⁺ ions. Therefore, it is possible to reduce the thickness of the element isolation oxide film in the cleaning process and the etching process after forming the element isolation oxide film without performing deposition and etching of the insulating film including the silicon nitride film. Become. As a result, it is possible to leave a film thickness necessary as an element isolation oxide film while suppressing an increase in the number of processes, and it is possible to prevent a decrease in field breakdown voltage and a field inversion and to etch an element formation region. Damage can be suppressed.

  In addition, according to the semiconductor device of one embodiment of the present invention, the semiconductor device is formed in a self-aligned manner on the semiconductor layer formed in a partial region on the insulating layer and the surface layer of the insulating layer exposed from the semiconductor layer. And an oxynitride film, a gate electrode formed on the semiconductor layer, and a source / drain layer formed on the semiconductor layer so as to be disposed on both sides of the gate electrode, respectively. .

Thus, an oxynitride film can be formed on the surface of the insulating layer by performing heat treatment on the insulating layer into which N ⁺ ions are implanted. For this reason, even when the mesa element isolation structure is formed on the SOI substrate, it is possible to reduce the decrease in the thickness of the insulating layer of the SOI substrate while suppressing an increase in the number of steps.
In addition, according to the semiconductor device of one embodiment of the present invention, the semiconductor layer formed in a partial region over the insulator and the element formed over the insulator so as to embed the periphery of the semiconductor layer An isolation oxide film, an oxynitride film formed in a self-aligned manner on a surface layer of the element isolation oxide film, a gate electrode formed on the semiconductor layer, and both sides of the gate electrode And a source / drain layer formed on the semiconductor layer.

Thus, the oxynitride film can be formed on the surface layer of the element isolation oxide film by performing a heat treatment on the element isolation oxide film implanted with N ⁺ ions. Therefore, even when the STI structure is formed on the SOI substrate, it is possible to reduce the reduction in the element isolation oxide film while suppressing the increase in the number of processes.
In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming an antioxidant film in the element formation region on the semiconductor and the thermal oxidation of the semiconductor using the antioxidant film as a mask are performed. Forming an element isolation oxide film for element isolation in the element formation region, and implanting N ⁺ ions into a surface layer of the element isolation oxide film using the antioxidant film as a mask, thereby forming the element isolation oxide film Forming a nitrogen ion-implanted layer on the surface layer, removing the antioxidant film on the semiconductor, and heat-treating the nitrogen ion-implanted layer, thereby forming an oxynitride film on the surface of the element isolation oxide film Forming a gate electrode on the semiconductor element separated by the element isolation oxide film, and forming source / drain layers respectively disposed on both sides of the gate electrode in the half. Characterized in that it comprises a step of forming the body.

  As a result, it is possible to form an oxynitride film on the surface of the element isolation oxide film by performing heat treatment on the element isolation oxide film on which the nitrogen ion implanted layer is formed, and to selectively perform thermal oxidation of the semiconductor layer. By using the antioxidant film for performing this process, nitrogen ion implantation can be selectively performed on the element isolation oxide film. For this reason, it is possible to reduce the film loss of the element isolation oxide film in the cleaning process and the etching process after forming the element isolation oxide film without performing the deposition and etching of the insulating film including the silicon nitride film. Thus, it is possible to prevent a decrease in field breakdown voltage and field inversion while suppressing an increase in the number of processes.

In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming a resist pattern that covers part of the semiconductor layer over the insulator, and mesa processing of the semiconductor layer using the resist pattern as a mask A step of isolating the semiconductor layer, and implanting nitrogen ions into the surface of the insulator by implanting N ⁺ ions into the surface of the insulator exposed from the semiconductor layer using the resist pattern as a mask. A step of forming a layer; a step of removing a resist pattern on the semiconductor; and a step of forming an oxynitride film on a surface layer of an insulator exposed from the semiconductor layer by performing a heat treatment of the nitrogen ion implantation layer; Forming a gate electrode on the mesa-processed semiconductor layer, and forming a source / drain layer respectively disposed on both sides of the gate electrode. Characterized in that it comprises a step of forming the semiconductor layer.

As a result, by performing heat treatment of the insulating layer implanted with N ⁺ ions, it becomes possible to form an oxynitride film on the surface layer of the insulating layer and to use a resist pattern for forming a mesa element isolation structure Thus, nitrogen ion implantation can be selectively performed in the insulating layer. For this reason, even when the mesa element isolation structure is formed on the SOI substrate, it is possible to reduce the decrease in the thickness of the insulating layer of the SOI substrate while suppressing an increase in the number of steps.

In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of element isolation of the semiconductor layer by performing mesa processing on the semiconductor layer formed over the insulator; Forming a buried oxide film on the insulator; forming a nitrogen ion implanted layer on the surface of the oxide film by implanting N ⁺ ions into the surface of the oxide film; and A process of forming an oxynitride film on a surface layer of the oxide film by performing a heat treatment of the ion implantation layer, a process of forming a gate electrode on the semiconductor layer separated from the element, and arranged on both sides of the gate electrode, respectively Forming a source / drain layer formed on the semiconductor layer.

  As a result, an oxynitride film can be formed on the surface layer of the element isolation oxide film, and even when the STI structure is formed on the SOI substrate, the increase in the number of processes is suppressed and the decrease in the film thickness of the element isolation oxide film is reduced. It becomes possible to make it.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
1 and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
In FIG. 1A, a sacrificial oxide film 2 is formed on the semiconductor substrate 1 by performing thermal oxidation of the semiconductor substrate 1. In addition, as a material of the semiconductor substrate 1, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe etc. can be used, for example. Then, after the sacrificial oxide film 2 is formed on the semiconductor substrate 1, the antioxidant film 3 is formed on the semiconductor substrate 1 by a method such as CVD. Then, the antioxidant film 3 and the sacrificial oxide film 2 are patterned by using the photolithography technique and the etching technique, thereby removing the antioxidant film 3 and the sacrificial oxide film 2 on the element isolation region E2. For example, a silicon nitride film can be used as the antioxidant film 3.

Next, as shown in FIG. 1B, the element isolation oxide film 4 is formed in the element isolation region E2 by performing selective oxidation of the semiconductor substrate 1 using the antioxidant film 3 as a mask.
Next, as shown in FIG. 1C, by using the antioxidant film 3 as a mask, N ⁺ ion implantation P1 is performed on the surface layer of the element isolation oxide film 4, thereby forming nitrogen on the surface layer of the element isolation oxide film 4. An ion implantation layer 5 is formed. The conditions for the ion implantation P1 can be such that the energy is about 10 to 100 keV and the dose amount is about 1E + 15 to 1E + 17 cm ⁻² .

Next, as shown in FIG. 2A, the antioxidant film 3 and the sacrificial oxide film 2 on the semiconductor substrate 1 are removed. When a silicon nitride film is used as the antioxidant film 3, the antioxidant film 3 can be removed by wet etching using hot phosphoric acid as an etchant.
Next, as shown in FIG. 2B, the nitrogen ion implantation layer 5 is changed to an oxynitride film 6 by performing heat treatment of the nitrogen ion implantation layer 5, and the oxynitride film 6 is formed on the element isolation oxide film 4. Form. As a heat treatment condition for the nitrogen ion implanted layer 5, the temperature can be set to about 1000 ° C. in a nitrogen atmosphere or an oxidizing atmosphere.

  Next, as illustrated in FIG. 2C, the gate insulating film 7 is formed on the surface of the semiconductor substrate 1 in the element formation region E <b> 1 by performing thermal oxidation of the semiconductor substrate 1. Then, a polycrystalline silicon layer is formed on the semiconductor substrate 1 on which the gate insulating film 7 is formed by a method such as CVD. Then, the gate electrode 8 is formed on the semiconductor substrate 1 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique. Then, by using the gate electrode 8 as a mask, impurities such as As, P, and B are ion-implanted into the semiconductor substrate 1 to form the LDD layer 9 composed of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 8. Formed on the semiconductor substrate 1.

  Then, an insulating layer is formed on the semiconductor substrate 1 on which the LDD layer 9 is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE, whereby the side wall of the gate electrode 8 is formed. The sidewalls 10 are formed respectively. Then, impurities such as As, P, and B are ion-implanted into the semiconductor substrate 1 using the gate electrode 8 and the side wall 10 as a mask, so that the high-concentration impurity introduction layers respectively disposed on the sides of the side wall 10 can be used. A source / drain layer 11 is formed on the semiconductor substrate 1.

  Here, by forming the oxynitride film 6 on the element isolation oxide film 4 by the heat treatment of the nitrogen ion implantation layer 5, the element isolation insulating film can be formed without performing the deposition and etching of the insulating film including the silicon nitride film. 4 can be protected. For this reason, in the cleaning process after forming the element isolation insulating film 4 and the etching process for forming the gate electrode 8 and the sidewall 10, it is possible to suppress the thinning of the element isolation insulating film 4, Field inversion can be prevented and etching damage to the element formation region E1 can be suppressed.

Further, by using the antioxidant film 3 for selectively performing thermal oxidation of the semiconductor substrate 1, N ⁺ ion implantation P 1 is performed on the surface layer of the element isolation oxide film 4, thereby forming the nitrogen ion implanted layer 5. The alignment between the region to be formed and the element isolation region E2 can be performed with high accuracy. For this reason, an alignment margin between the region where the nitrogen ion implantation layer 5 is formed and the element isolation region E2 can be eliminated, and deterioration of the degree of integration can be prevented, and the number of steps can be reduced. The increase can be suppressed.

In the above-described embodiment, the method of performing the ion implantation P1 of N ⁺ ions on the surface layer of the element isolation oxide film 4 using the antioxidant film 3 as a mask has been described. However, the resist pattern formed in the element formation region E1 is masked. As an alternative, N ⁺ ion implantation P 1 may be performed on the surface layer of the element isolation oxide film 4.
3 and 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the second embodiment of the present invention.

In FIG. 3A, a BOX layer 22 is formed on the support substrate 21, and a semiconductor layer 23 is formed on the BOX layer 22. The support substrate 21 may be a semiconductor substrate such as Si, Ge, SiGe, GaAs, InP, GaP, GaN, or SiC, or an insulating substrate such as glass, sapphire, or ceramic. Also good. Further, as the material of the semiconductor layer 23, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe or the like can be used, and as the BOX layer 22, for example, SiO ₂ An insulating layer such as SiON or Si ₃ N ₄ or a buried insulating film can be used. In addition, as the semiconductor substrate in which the semiconductor layer 23 is formed on the BOX layer 22, for example, an SOI substrate can be used. As the SOI substrate, a SIMOX (Separation by Implanted Oxgen) substrate, a bonded substrate, or a laser annealed substrate can be used. Etc. can be used. Further, as the semiconductor layer 23, a single crystal semiconductor layer, a polycrystalline semiconductor layer, or an amorphous semiconductor layer may be used.

Then, by using a photolithography technique, a resist pattern R1 that covers the semiconductor layer 23 in the element formation region E11 and exposes the semiconductor layer 23 in the element isolation region E12 is formed.
Next, as shown in FIG. 3B, the semiconductor layer 23 is etched using the resist pattern R1 as a mask, thereby removing the semiconductor layer 23 in the element isolation region E12 and forming a mesa element isolation structure.

Next, as shown in FIG. 3C, N ⁺ ion implantation P2 is performed on the surface layer of the BOX layer 22 using the resist pattern R1 as a mask, thereby forming a nitrogen ion implantation layer 25 on the surface layer of the BOX layer 22. Form.
Next, as shown in FIG. 4A, the resist pattern R1 on the semiconductor layer 23 is removed. Then, as shown in FIG. 4B, the nitrogen ion implanted layer 25 is changed to the oxynitride film 26 by performing a heat treatment of the nitrogen ion implanted layer 25, and the oxynitride film 26 is formed on the BOX layer 22. .

  Next, as shown in FIG. 4C, the semiconductor layer 23 is thermally oxidized to form a gate insulating film 27 on the surface of the semiconductor layer 23 in the element formation region E11. Then, a polycrystalline silicon layer is formed on the semiconductor layer 23 on which the gate insulating film 27 is formed by a method such as CVD. Then, the gate electrode 28 is formed on the semiconductor layer 23 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique. Then, by using the gate electrode 28 as a mask, impurities such as As, P, and B are ion-implanted into the semiconductor layer 23, thereby forming the LDD layer 29 composed of the low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 28. Formed on the semiconductor layer 23.

  Then, an insulating layer is formed on the semiconductor layer 23 on which the LDD layer 29 is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Sidewalls 30 are formed respectively. Then, impurities such as As, P, and B are ion-implanted into the semiconductor layer 23 using the gate electrode 28 and the sidewall 30 as a mask, so that the high-concentration impurity introduction layer disposed on the side of the sidewall 30 is removed. A source / drain layer 31 is formed on the semiconductor layer 23.

Here, by forming the oxynitride film 26 on the BOX layer 22, the BOX layer 22 is thinned in a cleaning process after forming the mesa element isolation structure and an etching process for forming the gate electrode 28 and the sidewall 30. Can be suppressed. Further, by using the resist pattern R1 for forming the mesa element isolation structure, N ⁺ ion implantation P2 is performed on the surface layer of the BOX layer 22, thereby forming a region where the nitrogen ion implantation layer 25 is formed and an element isolation region Positioning with E12 can be performed with high accuracy. For this reason, an alignment margin between the region where the nitrogen ion implantation layer 25 is formed and the element isolation region E12 can be eliminated, and deterioration of the degree of integration can be prevented, and the number of steps can be reduced. The increase can be suppressed.

5 and 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the third embodiment of the present invention.
In FIG. 5A, a BOX layer 42 is formed on the support substrate 41. A semiconductor layer 43 is formed in the element formation region E21 on the BOX layer 42, and the BOX layer 42 in the element isolation region E22 is exposed.

Next, as shown in FIG. 5B, an oxide film 44 is deposited on the entire surface of the BOX layer 42 on which the semiconductor layer 43 is formed by a method such as CVD.
Next, as shown in FIG. 5C, N ⁺ ion implantation P ^< b ^> 3 is performed in the oxide film 44 to form a nitrogen ion implanted layer 45 in the oxide film 44. Here, the depth of N ⁺ ion implantation is set so that the nitrogen ion implanted layer 45 is disposed on the surface layer of the oxide film 44 when the oxide film 44 is planarized to expose the semiconductor layer 43. It is preferable.

Next, as shown in FIG. 6A, the oxide film 44 is planarized to expose the semiconductor layer 43, and the oxide film 44 is embedded around the semiconductor layer 43. Here, as a method of planarizing the oxide film 44, for example, CMP (chemical mechanical polishing) can be used.
Next, as shown in FIG. 6B, the nitrogen ion implanted layer 45 is heat-treated to change the nitrogen ion implanted layer 45 into the oxynitride film 46, and the oxynitride film 46 is formed on the surface layer of the oxide film 44. Form.

  Next, as illustrated in FIG. 6C, the gate insulating film 47 is formed on the surface of the semiconductor layer 43 in the element formation region E <b> 21 by performing thermal oxidation of the semiconductor layer 43. Then, a polycrystalline silicon layer is formed on the semiconductor layer 43 on which the gate insulating film 47 is formed by a method such as CVD. Then, the gate electrode 48 is formed on the semiconductor layer 43 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique. Then, by using the gate electrode 48 as a mask, impurities such as As, P, and B are ion-implanted into the semiconductor layer 43, thereby forming the LDD layer 49 composed of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 48. A semiconductor layer 43 is formed.

  Then, an insulating layer is formed on the semiconductor layer 43 on which the LDD layer 49 is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE, whereby the sidewall of the gate electrode 48 is formed. Side walls 50 are formed respectively. Then, impurities such as As, P, and B are ion-implanted into the semiconductor layer 43 using the gate electrode 48 and the side wall 50 as a mask, so that the high-concentration impurity introduction layers respectively disposed on the sides of the side wall 50 can be used. A source / drain layer 51 is formed on the semiconductor layer 43.

  As a result, the oxide film 44 can be protected by the oxynitride film 46, and even when the STI structure is formed on the SOI substrate, the decrease in the thickness of the oxide film 44 can be reduced while suppressing an increase in the number of processes. It becomes possible.

Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention.

Explanation of symbols

  E1, E11, E21 Device formation region, E2, E12, E22 Device isolation region, 1 Semiconductor substrate, 2 Sacrificial oxide film, 3 Antioxidation film, 4 Device isolation oxide film, 5, 25, 45 Nitrogen ion implantation layer, 6, 26, 46 Oxynitride film, 7, 27, 47 Gate insulating film, 8, 28, 48 Gate electrode, 9, 29, 49 LDD layer, 10, 30, 50 Side wall spacer, 11, 31, 51 Source / drain layer , 21, 41 Support substrate, 22, 42 BOX layer, 23, 43 Single crystal semiconductor layer, 44 Oxide film, R1 resist pattern, P1-P3 ion implantation

Claims (6)

An element isolation oxide film formed in an element isolation region on a semiconductor;
An oxynitride film formed in a self-aligned manner on a surface layer of the element isolation oxide film;
A gate electrode formed on the semiconductor element isolated by the element isolation oxide film;
A semiconductor device comprising: a source / drain layer formed on the semiconductor so as to be disposed on both sides of the gate electrode. A semiconductor layer formed in a partial region on the insulating layer;
An oxynitride film formed in a self-aligned manner on a surface layer of the insulating layer exposed from the semiconductor layer;
A gate electrode formed on the semiconductor layer;
A semiconductor device comprising: a source / drain layer formed on the semiconductor layer so as to be disposed on both sides of the gate electrode. A semiconductor layer formed in a partial region on the insulator;
An element isolation oxide film formed on the insulator so as to embed the periphery of the semiconductor layer;
An oxynitride film formed in a self-aligned manner on a surface layer of the element isolation oxide film;
A gate electrode formed on the semiconductor layer;
A semiconductor device comprising: a source / drain layer formed on the semiconductor layer so as to be disposed on both sides of the gate electrode. Forming an antioxidant film in an element formation region on the semiconductor;
Forming an element isolation oxide film for element isolation of the element formation region by performing thermal oxidation of the semiconductor using the antioxidant film as a mask;
Forming a nitrogen ion-implanted layer on the surface of the element isolation oxide film by implanting N ⁺ ions into the surface layer of the element isolation oxide film using the antioxidant film as a mask;
Removing the antioxidant film on the semiconductor;
Forming a oxynitride film on a surface layer of the element isolation oxide film by performing a heat treatment of the nitrogen ion implanted layer;
Forming a gate electrode on the semiconductor element separated by the element isolation oxide film;
Forming a source / drain layer respectively disposed on both sides of the gate electrode on the semiconductor. Forming a resist pattern covering a part of the semiconductor layer on the insulator;
Performing a mesa process of the semiconductor layer using a resist pattern as a mask, thereby performing element isolation of the semiconductor layer;
Forming a nitrogen ion implanted layer on the surface of the insulator by implanting N ⁺ ions into the surface of the insulator exposed from the semiconductor layer using the resist pattern as a mask;
Removing the resist pattern on the semiconductor;
Forming a oxynitride film on a surface layer of the insulator exposed from the semiconductor layer by performing a heat treatment of the nitrogen ion implanted layer;
Forming a gate electrode on the mesa-processed semiconductor layer;
Forming a source / drain layer respectively disposed on both sides of the gate electrode in the semiconductor layer. A step of performing element isolation of the semiconductor layer by performing mesa processing of the semiconductor layer formed on the insulator;
Forming an oxide film filling the periphery of the semiconductor layer on the insulator;
Forming a nitrogen ion implanted layer on the surface of the oxide film by implanting N ⁺ ions into the surface of the oxide film;
Forming a oxynitride film on a surface layer of the oxide film by performing a heat treatment of the nitrogen ion implanted layer;
Forming a gate electrode on the element-isolated semiconductor layer;
Forming a source / drain layer respectively disposed on both sides of the gate electrode in the semiconductor layer.

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