JP2005311390A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of controlling the deterioration of the threshold voltage Vth of a parasitic MOS transistor, and to provide its manufacturing method. <P>SOLUTION: An oxide layer 14 is formed so that it extends from the top of a channel stopper region 4 to the top of an embedded oxide layer 2. This oxide layer 14 has an upper surface 14a, that inclines toward directly above the channel stopper region 4 and a flat upper surface above the embedded oxide layer 2. A gate electrode 8 extends from the top of an SOI layer 3 to the top of the oxide layer 14. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to an element isolation structure in a semiconductor device.

  Conventionally, a LOCOS (Local Oxidation of Silicon) method is widely known as a method for separating elements. 47 and 48 are cross-sectional views showing a process flow when the above-described LOCOS method is used in a semiconductor device having an SOI (Semiconductor On Insulator) structure.

  First, referring to FIG. 47, using a SIMOX (Separation by Implanted Oxygen) method or the like, a semiconductor layer (hereinafter simply referred to as “SOI layer”) with a buried oxide layer 2 interposed on the main surface of silicon substrate 1. 3) is formed. A nitride layer 11 patterned in a predetermined shape is formed on the SOI layer 3. Boron (B) is ion-implanted into the SOI layer 3 using the nitride layer 11 as a mask. Thereby, an impurity implantation region 4a to be a channel stopper region is formed.

  Next, LOCOS processing is performed on the SOI layer 3 in the state shown in FIG. Thereby, as shown in FIG. 48, the isolation oxide layer 20 is selectively formed in the SOI layer 3. At this time, the formation of the isolation oxide layer 20 almost absorbs impurities (boron) for forming the channel stopper region. Therefore, as shown in FIG. 48, it is necessary to ion-implant boron (B) again in the vicinity of the peripheral portion of the SOI layer 3 after the formation of the isolation oxide layer 20. Thereby, a channel stopper region 4 containing a high concentration impurity (boron) is formed in the vicinity of the peripheral edge of the SOI layer 3. As a result, the threshold voltage Vth of the parasitic MOS transistor near the peripheral edge of the SOI layer 3 can be effectively suppressed from decreasing.

  However, when boron ions are implanted for forming the channel stopper region 4 after the formation of the isolation oxide layer 20, there is a problem as described below.

  As shown in FIG. 48, as one method for forming the channel stopper region 4 after the formation of the isolation oxide layer 20, it is selectively performed only in the vicinity of the peripheral portion of the SOI layer 3 with the nitride layer 11 remaining. A method of implanting boron ions can be mentioned. According to this method, since the channel stopper region 4 can be formed in a self-aligned manner, it is not necessary to newly form a mask layer for the above boron ion implantation. However, as shown in FIG. 48, it is necessary to implant boron ions in the vicinity of the peripheral portion of the SOI layer 3 by an oblique ion implantation method. For this reason, the boron is implanted into the region where the channel of the MOS transistor is formed. As a result, there has been a problem that the effective channel width W is reduced.

  As one method that can solve the above problems, the mesa separation method shown in FIGS. 49 to 51 can be mentioned. FIG. 49 is a cross-sectional view showing a semiconductor device employing a conventional mesa separation method. 50 and 51 are cross-sectional views showing characteristic manufacturing steps of the semiconductor device shown in FIG.

  First, referring to FIG. 49, a channel stopper region 4 is formed in the vicinity of the peripheral portion of the SOI layer 3. A recess 24 is formed immediately below the peripheral edge of the SOI layer 3. A gate insulating layer 7 is formed so as to cover the SOI layer 3, and a gate electrode 8 is formed so as to cover the gate insulating layer 7.

  Next, a method for manufacturing the semiconductor device shown in FIG. 49 will be described with reference to FIGS. First, referring to FIG. 50, boron (B) for forming channel stopper region 4 is ion-implanted into SOI layer 3 by the same method as in the case of LOCOS method described above. Thereafter, a nitride layer (not shown) is further formed so as to cover the nitride layer 11 by using a CVD (Chemical Vapor Deposition) method. Then, the nitride spacer 12 is formed as shown in FIG. 51 by subjecting this nitride layer to anisotropic etching. Next, using the nitride layer 11 and the nitride spacer 12 as a mask, the SOI layer 3 is patterned, and subsequently a thermal oxidation process for removing etching damage is performed. Thereby, sidewall oxide layer 5 is formed on the sidewall of SOI layer 3 as shown in FIG.

  Thereafter, nitride layer 11, nitride spacer 12, and oxide layer 9 are removed by etching. Thereby, as shown in FIG. 49, the recess 24 is formed immediately below the peripheral edge of the SOI layer 3.

  Thereafter, a gate insulating layer 7 is formed on the surface of the SOI layer 3, and a gate electrode 8 is formed so as to cover the gate insulating layer 7. In this case, source / drain regions are formed in the SOI layer 3 so as to sandwich the gate electrode 8.

  The semiconductor device shown in FIG. 49 is formed through the above steps. In the semiconductor device shown in FIG. 49, boron (B) for forming the channel stopper region 4 is not implanted again as in the case where the LOCOS method is employed. Therefore, the problem that the effective channel width W becomes small as in the case where the LOCOS method is adopted can be solved.

  However, the semiconductor device shown in FIG. 49 also has the following problems. As shown in FIG. 51, the sidewall oxide layer 5 is formed after the channel stopper region 4 is formed. At this time, although not as in the case of the LOCOS method, impurities (boron) are sucked out of the channel stopper region 4 due to the formation of the sidewall oxide layer 5. As a result, the impurity (boron) concentration in the channel stopper region 4 is lowered, and the threshold voltage Vth of the parasitic MOS transistor in the peripheral portion of the SOI layer 3 is lowered. In addition, as shown in FIG. 49, a recess 24 is formed immediately below the peripheral edge of the SOI layer 3. By forming such a recess 24, electrolytic concentration tends to occur at the sidewall bottom 26 of the SOI layer 3. As a result, the gate insulating layer 7 is easily broken down, and there is a problem that the yield of the transistor is lowered.

  The present invention has been made to solve the above-described problems. One object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can effectively suppress a decrease in threshold voltage Vth of a parasitic MOS transistor at the peripheral edge of the SOI layer.

  Another object of the present invention is to provide a semiconductor device capable of effectively suppressing dielectric breakdown of a gate insulating layer.

  A semiconductor device according to the present invention is a semiconductor device having an SOI structure, and a semiconductor substrate having a main surface and a source / drain region formed on the main surface of the semiconductor substrate with a buried insulating layer interposed therebetween. A mesa-shaped semiconductor layer, a gate insulating layer formed on the semiconductor layer, an upper surface formed on the peripheral portion of the semiconductor layer and inclined upward from the gate insulating layer on the peripheral portion, and on the buried insulating layer And an isolation insulating layer having a flat upper surface continuous with an upper surface inclined upward, and a gate electrode extending from the semiconductor layer onto the isolation insulating layer.

  The semiconductor device preferably includes a channel stopper region formed in the vicinity of the peripheral portion of the semiconductor layer, and the isolation insulating layer is preferably formed on the channel stopper region and the peripheral portion of the semiconductor layer. The upper surface is inclined upward from the gate insulating layer and the upper surface is continuous with the upper surface inclined upward on the buried insulating layer.

  According to the semiconductor device of the present invention, the gate electrode can be separated from the peripheral edge of the semiconductor layer by the isolation insulating layer. Thereby, it is possible to effectively suppress a decrease in threshold voltage Vth of the parasitic MOS transistor at the peripheral portion of the semiconductor layer. In addition, since the isolation insulating layer has a function of protecting the peripheral portion of the semiconductor layer, it is possible to effectively suppress the dielectric breakdown of the gate insulating layer at the peripheral portion of the semiconductor layer as in the conventional example. It becomes.

Hereinafter, embodiments of the present invention will be described with reference to FIGS.
(Embodiment 1)
First, Embodiment 1 of the present invention will be described with reference to FIGS. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1, and a cross section taken along line II corresponds to the cross sectional view shown in FIG.

  Referring to FIG. 1, SOI layer 3 is formed on the main surface of silicon substrate 1 with buried oxide layer 2 interposed. A channel stopper region 4 is formed in the vicinity of the peripheral edge of the SOI layer 3. A sidewall oxide layer 5 is formed on the sidewall of the SOI layer 3 so as to cover the channel stopper region 4. On the channel stopper region 4, a projecting insulating layer 6a made of silicon nitride or silicon oxide is formed. A sidewall insulating layer 6b made of an insulator such as silicon nitride or silicon oxide is formed so as to cover the sidewall of the sidewall oxide layer 5. A gate insulating layer 7 is formed on the surface of the SOI layer 3. A gate electrode 8 is formed so as to cover the gate insulating layer 7, the projecting insulating layer 6a, and the sidewall insulating layer 6b.

  Next, referring to FIG. 2, sidewall insulating layer 6 b is formed so as to surround channel stopper region 4. A ring-shaped projecting insulating layer 6 a is formed on the channel stopper region 4. For example, when the side wall insulating layer 27 is formed on the side wall of the gate electrode 8, the projecting insulating layer 6 a is planar with a portion located under the side wall insulating layer 27 or the gate electrode 8 and other portions. The width will be different. However, in any case, the side end portion of the projecting insulating layer 6a on the SOI layer 3 is directly above the inner side end portion of the channel stopper region 4 or on the peripheral side of the SOI layer 3 with respect to the inner side end portion. It is preferable to be located at. As a result, the gate electrode 8 can be effectively moved away from the peripheral edge of the SOI layer 3. Thereby, it is possible to effectively suppress a decrease in the threshold voltage Vth of the parasitic MOS transistor in the vicinity of the peripheral edge of the SOI layer 3. Further, as described above, by forming the sidewall oxide layer 5 and the sidewall insulating layer 6b so as to cover the sidewall of the SOI layer 3, it is possible to protect the peripheral portion of the SOI layer 3. In particular, the bottom of the side wall of the SOI layer 3 is covered with the side wall oxide layer 5 and the side wall insulating layer 6b, so that the recess 24 is formed just below the peripheral edge of the SOI layer 3 as in the conventional example. Can be prevented. Thereby, it is possible to effectively suppress the dielectric breakdown of the gate insulating layer in the vicinity of the peripheral edge of the SOI layer 3.

  Next, a method for manufacturing the semiconductor device shown in FIGS. 1 and 2 will be described with reference to FIGS. 3 to 7 are cross-sectional views showing the first to fifth steps of the manufacturing process of the semiconductor device shown in FIG. In each embodiment described below, reference is made to the case where an nMOS transistor is formed, but the idea of the present invention can also be applied to a pMOS transistor.

  First, referring to FIG. 3, SOI layer 3 is formed on the main surface of silicon substrate 1 with buried oxide layer 2 interposed, in the same manner as in the conventional example. An oxide layer 9 having a thickness of about 10 to about 30 nm is formed on the SOI layer 3. A polysilicon layer 10 having a thickness of about 100 to about 250 nm and a nitride layer 11 having a thickness of about 100 to about 250 nm are sequentially deposited on the oxide layer 9. Then, a photoresist pattern (not shown) having a predetermined shape is formed on the nitride layer 11, and the nitride layer 11 and the polysilicon layer 10 are sequentially patterned using this photoresist pattern as a mask. Thereafter, the photoresist pattern is removed. Alternatively, the nitride layer 11 may be patterned using the photoresist pattern as a mask, the photoresist pattern may be removed, and the polysilicon layer 10 may be patterned using the nitride layer 11 as a mask. Next, a nitride layer having a thickness of about 50 to about 100 nm is formed on oxide layer 9 so as to cover nitride layer 11 and polysilicon layer 10. Then, an anisotropic etching process is performed on the nitride layer. Thereby, the nitride spacer 12 is formed.

  Next, referring to FIG. 4, oxide layer 9 and SOI layer 3 are sequentially patterned using nitride layer 11 and nitride spacer 12 as a mask. Thereafter, the sidewall of the SOI layer 3 is thermally oxidized in order to remove etching damage during the patterning. Thereby, the sidewall oxide layer 5 is formed on the peripheral edge of the SOI layer 3.

  Next, the nitride layer 11 and the nitride spacer 12 are removed by etching using hot phosphoric acid or the like. As a result, the oxide layer 9 located on the region near the peripheral edge of the SOI layer 3 is selectively exposed. In this state, as shown in FIG. 5, using the polysilicon layer 10 as a mask, an impurity for forming the channel stopper region 4 is implanted in the vicinity of the peripheral portion of the SOI layer 3. In this case, boron (B) is implanted near the periphery of the SOI layer 3. In the case of forming a complementary metal oxide semiconductor (CMOS), it is necessary to cover the formation region of the pMOS transistor with, for example, a photoresist when boron is implanted into the nMOS transistor.

  As described above, since the impurity (boron) for forming the channel stopper region 4 is implanted into the SOI layer 3 after forming the sidewall oxide layer 5, the channel stopper is formed by forming the sidewall oxide layer 5. It is possible to effectively suppress the impurities introduced into the region 4 from being sucked out. Thereby, it is possible to effectively suppress a decrease in the impurity concentration in the channel stopper region 4. Also, as shown in FIG. 5, since impurities (boron) can be implanted in the vicinity of the peripheral edge of the SOI layer 3 covered with the nitride spacers 12 in a self-aligned manner, the channel stopper region is almost certainly obtained. 4 can be formed. In other words, the channel stopper region 4 containing a high concentration of impurities can be formed almost certainly in the vicinity of the peripheral edge of the SOI layer 3. Thereby, it is possible to effectively suppress a decrease in the threshold voltage Vth of the parasitic MOS transistor in the vicinity of the peripheral edge of the SOI layer 3.

  Next, referring to FIG. 6, on the buried oxide layer 2 so as to cover the polysilicon layer 10 and the SOI layer 3, a CVD (Chemical Vapor Deposition) method or the like is used to form oxide or nitride. An insulating layer (not shown) is formed. Then, an anisotropic etching process is performed on the insulating layer. Thereby, the protruding insulating layer 6a and the sidewall insulating layer 6b are formed simultaneously. At this time, since the polysilicon layer 10 is formed on the SOI layer 3, the surface of the SOI layer 3 is hardly damaged by the anisotropic etching.

  Next, referring to FIG. 7, polysilicon layer 10 and oxide layer 9 are removed by, for example, isotropic etching. At this time, since the peripheral portion of the SOI layer 3 is protected by the side wall oxide layer 5 and the side wall insulating layer 6b, it is possible to effectively prevent the recess portion from being formed immediately below the peripheral portion of the SOI layer 3. Is possible. Thereby, it is possible to effectively prevent the dielectric breakdown of the gate insulating layer in the vicinity of the peripheral edge of the SOI layer 3.

  As described above, after exposing the surface of the SOI layer 3, the gate insulating layer 7 having a thickness of about 6 to 12 nm is formed on the surface of the SOI layer 3 by using, for example, a thermal oxidation method or a CVD method, A gate electrode 8 is formed on the gate insulating layer 7. Through the above steps, the semiconductor device shown in FIG. 1 is formed.

  In the case where the gate insulating layer 7 is formed by the CVD method, it is possible to suppress the extraction of impurities from the channel stopper region 4 when the gate insulating layer 7 is formed. Further, as shown in FIG. 12, after the channel stopper region 4 is formed, channel doping can be performed using the same mask as that used for boron implantation for forming the channel stopper region 4. In this case, it is necessary to implant boron into the SOI layer 3 with energy penetrating the polysilicon layer 10. Thus, by performing channel doping using the same mask as the mask for forming the channel stopper region 4, the manufacturing process can be simplified. The channel doping may be performed before the channel stopper region 4 is formed. In the case of forming a CMOS, the channel doping can be performed while the pMOS formation region is covered with the photoresist. The concept of channel doping can be applied not only to the pMOS transistor as in the case of forming the channel stopper region 4, but also to each embodiment described below.

(Embodiment 2)
Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 8 is a sectional view showing a semiconductor device according to the second embodiment of the present invention.

  Referring to FIG. 8, oxide layer 14 is formed to extend from above channel stopper region 4 to buried oxide layer 2. The oxide layer 14 has an upper surface 14 a inclined immediately above the channel stopper region 4, and has a flat upper surface 14 b above the buried oxide layer 2. The gate electrode 8 extends from the SOI layer 3 to the oxide layer 14. By providing such an oxide layer 14, it is possible to protect the peripheral edge of the SOI layer 3 and to keep the gate electrode 8 away from the peripheral edge of the SOI layer 3. As a result, it is possible to suppress a decrease in the threshold voltage Vth of the parasitic MOS transistor at the peripheral portion of the SOI layer 3 and to effectively prevent dielectric breakdown of the gate insulating layer in the vicinity of the peripheral portion of the SOI layer 3. It becomes possible to suppress.

  Next, a method for manufacturing the semiconductor device shown in FIG. 8 will be described with reference to FIGS. 9 to 11 are cross-sectional views showing the first to third steps of the manufacturing process of the semiconductor device shown in FIG.

  First, referring to FIG. 9, the channel stopper region 4 is formed through the same process as in the first embodiment. Next, an oxide layer 14 having a thickness of about 1 μm is formed by CVD to cover the polysilicon layer 10 and the SOI layer 3.

  Next, a CMP (Chemical Mechanical Polishing) process is performed on the upper surface of the oxide layer 14. Thereby, as shown in FIG. 10, the upper surface of the oxide layer 14 is planarized and the upper surface of the polysilicon layer 10 is exposed. At this time, since the polysilicon layer 10 functions as a stopper for the CMP process, the polishing accuracy by the CMP process is improved. An etch back method can be used instead of the CMP process. The same applies to the following embodiments.

  Next, referring to FIG. 11, polysilicon layer 10 is removed by, for example, isotropic etching, and oxide layer 9 is selectively removed by wet etching. Thereby, the surface of the SOI layer 3 is selectively exposed. Thereafter, the gate insulating layer 7 and the gate electrode 8 are formed by the same method as in the first embodiment. The semiconductor device shown in FIG. 8 is formed through the above steps.

  Next, a modified example of the second embodiment will be described with reference to FIG. FIG. 13 is a cross-sectional view showing a semiconductor device according to a modification of the second embodiment.

  Referring to FIG. 13, in this modification, polysilicon layer 10 used as a mask layer is used as a part of gate electrode 8. Thereby, the step of etching polysilicon layer 10 and oxide layer 9 can be omitted, and the manufacturing process can be simplified as compared with the case of the second embodiment.

(Embodiment 3)
Next, Embodiment 3 of the present invention will be described with reference to FIGS. FIG. 14 is a cross sectional view showing a semiconductor device according to the third embodiment of the present invention.

  In the third embodiment, the idea of the second embodiment is applied to a device formed directly on the main surface of the silicon substrate 1. The idea of the second embodiment can be similarly applied to the fourth embodiment described later.

  Referring to FIG. 14, a pair of trenches 15 are formed on the main surface of silicon substrate 1 at intervals. An oxide layer 16 is formed on the inner surface of the trench 15. The channel stopper region 4 extends along the inner surface of the trench 15 and reaches the side wall upper end corner portion 17 of the trench 15. A gate insulating layer 7 is formed on the main surface of the silicon substrate 1 sandwiched between the channel stopper regions 4, and a gate electrode 8 is formed on the gate insulating layer 7. The gate electrode 8 extends over the oxide layer 14, and the oxide layer 14 has an upper surface 14 a inclined above the channel stopper region 4 and a flat upper surface 14 b above the trench 15.

  Next, a method for manufacturing a semiconductor device having the above structure will be described with reference to FIGS. 15 to 19 are cross-sectional views showing the first to fifth steps of the manufacturing process of the semiconductor device shown in FIG.

  First, referring to FIG. 15, oxide layer 9, polysilicon layer 10, nitride layer 11, and nitride spacer 12 are formed on the main surface of silicon substrate 1 by the same method as in the first embodiment. Form.

  Next, referring to FIG. 16, trench 15 is formed by etching the main surface of silicon substrate 1 using nitride layer 11 and nitride spacer 12 as a mask. The depth of the trench 15 may be about 250 nm to about 300 nm, for example. Next, the oxide layer 16 is formed by thermally oxidizing the inner surface of the trench 15. Thereby, etching damage due to the formation of the trench 15 can be removed.

  Next, referring to FIG. 17, nitride layer 11 and nitride spacer 12 are removed by the same method as in the first embodiment. Thereafter, using the polysilicon layer 10 as a mask, p-type impurities such as boron are implanted into the inner surface of the trench 15 and in the vicinity of the side wall upper end corner portion 17 of the trench 15. Thereby, the channel stopper region 4 is formed. At this time, since the oxide layer 16 is formed before the channel stopper region 4 is formed, the p-type impurity introduced into the channel stopper region 4 is effectively absorbed by the oxide layer 16. It becomes possible to stop. Thereby, a channel stopper region 4 containing a high concentration of impurities can be formed.

  Next, as shown in FIG. 18, an oxide layer 14 is formed so as to cover trench 15 and polysilicon layer 10 by the same method as in the second embodiment. Then, a CMP process is performed on the oxide layer 14. Thereby, the upper surface of the polysilicon layer 10 is exposed as shown in FIG. Thereafter, the semiconductor device shown in FIG. 14 is formed through the same steps as in the second embodiment.

(Embodiment 4)
Next, Embodiment 4 of this invention and its modification are demonstrated using FIGS. 20-26. 20 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention.

  Referring to FIG. 20, in the fourth embodiment, gate electrode 8 is formed of a laminated structure of first polysilicon layer 10a and third polysilicon layer 10c. The oxide layer 14 is formed so as to extend from the channel stopper region 4 to the buried oxide layer 2, and the inclined upper surface 14 a positioned above the channel stopper region 4 and the buried oxide layer 2. And a flat upper surface 14b located above the upper surface. The inclined upper surface 14 a is inclined so as to be separated from the upper surface of the SOI layer 3 toward the peripheral edge of the SOI layer 3. A flat upper surface 14b is formed so as to be continuous with the inclined upper surface 14a. The third polysilicon layer 10c in the gate electrode 8 extends on the inclined upper surface 14a and the flat upper surface 14b. The height of the flat upper surface 14 b from the upper surface of the SOI layer 3 is set to be higher than the height of the upper surface of the first polysilicon layer 10 a from the upper surface of the SOI layer 3. As a result, the gate electrode 8 can be effectively moved away from the peripheral edge of the SOI layer 3. Thereby, it is possible to effectively suppress a decrease in the threshold voltage Vth of the parasitic MOS transistor at the peripheral edge of the SOI layer 3.

  Next, a method for manufacturing the semiconductor device shown in FIG. 20 will be described with reference to FIGS. 21 to 24 are cross-sectional views showing the first to fourth steps of the manufacturing process of the semiconductor device shown in FIG.

  Referring to FIG. 21, oxide layer 9a, first polysilicon layer 10a, oxide layer 9b, and second polysilicon layer are formed on the surface of SOI layer 3 formed by the same method as in the first embodiment. 10b and the nitride layer 11 are formed sequentially. Then, a photoresist (not shown) patterned in the shape of the element formation region is formed on the nitride layer 11, and the nitride layer 11 and the second polysilicon layer 10b are used using this photoresist as a mask. The oxide layer 9b and the first polysilicon layer 10a are sequentially patterned. After removing the photoresist, a nitride layer (not shown) is formed on the entire surface, and this nitride layer is subjected to anisotropic etching. Thereby, the nitride spacer 12a is formed.

  Next, referring to FIG. 22, heat treatment is performed on the sidewall of SOI layer 3 in an oxidizing atmosphere using nitride layer 11 and nitride spacer 12a as a mask. Thereby, the sidewall oxide layer 5 is formed on the peripheral edge of the SOI layer 3. Thereafter, nitride layer 11 and nitride spacer 12a are removed using hot phosphoric acid or the like.

  Thereby, as shown in FIG. 23, the surface of the oxide layer 9a located in the vicinity of the peripheral edge of the SOI layer 3 is selectively exposed. Then, boron is ion-implanted in the vicinity of the peripheral portion of the SOI layer 3 using the second polysilicon layer 10b as a mask. Thereby, a channel stopper region 4 is formed in the vicinity of the peripheral portion of the SOI layer 3. As described above, also in this embodiment, the channel stopper region 4 containing a high concentration of impurities can be formed in a self-aligned manner, as in the case of the above-described embodiments.

  Next, an oxide layer 14 having a thickness of about 1 μm is formed on the entire surface by CVD or the like. Then, a CMP process is performed on the upper surface of the oxide layer 14. Thereby, the upper surface of the second polysilicon layer 10b is exposed.

  Next, the second polysilicon layer 10b and the oxide layer 9b are removed by etching. Thereby, as shown in FIG. 20, an inclined upper surface 14 a is formed in the oxide layer 14 located on the channel stopper region 4.

  Thereafter, the third polysilicon layer 10c is formed to extend from the first polysilicon layer 10a to the oxide layer 14 by using a CVD method or the like. Then, by patterning the third polysilicon layer 10c and the first polysilicon layer 10a at the same time, the gate electrode 8 is formed as shown in FIG. Through the above steps, the semiconductor device shown in FIG. 20 is formed.

  Next, a modification of the fourth embodiment will be described with reference to FIGS. 25 and 26. FIG. FIG. 25 is a cross-sectional view showing a semiconductor device according to a modification of the fourth embodiment.

  Referring to FIG. 25, in the present modification, the first sidewall oxide layer 18 is formed on the peripheral portion of the first polysilicon layer 10a, and the thickness of the sidewall oxide layer 5 is shown in FIG. It is larger than the case of 4. Other structures are substantially the same as those of the semiconductor device shown in FIG.

  Next, a characteristic manufacturing process of the semiconductor device shown in FIG. 25 will be described with reference to FIG. FIG. 26 is a cross-sectional view showing a characteristic manufacturing process of the semiconductor device in the above modification.

  Referring to FIG. 26, nitride layer 11 is formed through the same process as in the above-described fourth embodiment, and first and second polysilicon layers 10a and 10b are formed using this nitride layer 11 as a mask. The peripheral part is thermally oxidized. At the same time, the surface of the SOI layer 3 is also selectively oxidized. By the above thermal oxidation treatment, etching damage during patterning of the first and second polysilicon layers 10a and 10b can be removed. Thereafter, the semiconductor device shown in FIG. 25 is formed through the same steps as in the fourth embodiment.

(Embodiment 5)
Next, Embodiment 5 of the present invention will be described with reference to FIGS. FIG. 27 is a cross sectional view showing a semiconductor device according to the fifth embodiment of the present invention.

  Referring to FIG. 27, oxide layer 20 is selectively formed on SOI layer 3. The oxide layer 20 is formed by the LOCOS method and extends on the channel stopper region 4 formed in the vicinity of the peripheral edge of the SOI layer 3. Gate electrode 8 is formed to extend from the SOI layer 3 to the oxide layer 20.

  Next, a method for manufacturing the semiconductor device shown in FIG. 27 will be described with reference to FIGS. 28 to 31 are cross-sectional views showing the first to fourth steps of the manufacturing process of the semiconductor device shown in FIG.

  First, referring to FIG. 28, nitride spacer 12 is formed through the same process as in the first embodiment. At this time, the thickness of the oxide layer 9 is about 10 to about 30 nm, the thickness of the polysilicon layer 10 is about 100 to about 300 nm, and the thickness of the nitride layer 11 is about 100 to about 300 nm. It is preferable.

  Next, heat treatment is performed on the SOI layer 3 in an oxidizing atmosphere using the nitride layer 11 and the nitride spacer 12 as a mask. Thereby, so-called LOCOS oxidation is performed, and an oxide layer 20 reaching the buried oxide layer 2 is selectively formed in the SOI layer 3 as shown in FIG.

  Next, the nitride layer 11 and the nitride spacer 20 are removed using hot phosphoric acid or the like. Thereby, as shown in FIG. 30, the polysilicon layer 10 remains on the SOI layer 3 excluding the region in the vicinity of the peripheral edge. Then, using this polysilicon layer 10 as a mask, boron ions are implanted into a region near the peripheral edge of the SOI layer 3. As a result, the channel stopper region 4 is formed in a region near the peripheral edge of the SOI layer 3 in a self-aligning manner. Since the channel stopper region 4 is formed after the oxide layer 20 is formed, the oxide layer 20 hardly absorbs impurities contained in the channel stopper region 4. As a result, it is possible to effectively prevent a decrease in the impurity concentration in the channel stopper region 4.

  Next, the polysilicon layer 10 and the oxide layer 9 are removed by etching. Thereby, as shown in FIG. 31, the surface of the SOI layer 3 is selectively exposed. Thereafter, a gate insulating layer 7 is formed on the surface of the SOI layer 3, and a gate electrode 8 is formed on the gate insulating layer 7. Through the above steps, the semiconductor device shown in FIG. 27 is formed.

(Embodiment 6)
Next, Embodiment 6 of this invention and its modification are demonstrated using FIGS. 32-40. FIG. 32 is a cross sectional view showing a semiconductor device according to the sixth embodiment of the present invention.

  Referring to FIG. 32, in the sixth embodiment, the inclination of side wall 3a of SOI layer 3 is steeper than that in the fifth embodiment. Accordingly, the shape of the oxide layer 20a is slightly different from the shape of the oxide layer 20. Other structures are almost the same as those shown in FIG. In the sixth embodiment, as shown in FIG. 32, the thinning of the vicinity of the peripheral portion of the SOI layer 3 can be suppressed as compared with the case of the fifth embodiment. Thereby, the formation of a parasitic MOS transistor having a low threshold voltage Vth can be effectively suppressed as compared with the case of the fifth embodiment.

  Next, a method for manufacturing a semiconductor device according to the sixth embodiment having the above structure will be described with reference to FIGS. 33 to 38 are cross-sectional views showing the first to sixth steps in the manufacturing process of the semiconductor device shown in FIG.

  First, referring to FIG. 33, up to nitride spacer 12 is formed through the same process as in the first embodiment. Then, the SOI layer 3 is selectively oxidized using the nitride layer 11 and the nitride spacer 12 as a mask. Thereby, the oxide layer 20a ′ is selectively formed. At this time, for example, the oxidation amount is adjusted so that the thickness of the SOI layer 3 remaining under the oxide layer 20 a ′ is about half of the initial thickness of the SOI layer 3. Specifically, when the initial thickness of the SOI layer 3 is about 100 nm, the oxidation amount is set so that the thickness of the oxide layer 20a ′ is about 110 nm. As a result, the SOI layer 3 having a thickness of about 50 nm remains immediately below the oxide layer 20a ′.

  Next, after the oxide layer 20a 'is removed by wet etching or the like, the surface of the SOI layer 3 is selected using the nitride layer 11 and the nitride spacer 12 again as a mask as shown in FIG. Oxidizes. As a result, a thin oxide layer 21 of about 10 to about 30 nm is formed so as to extend under the nitride spacer 12. Next, a nitride layer 22 having a thickness of about 10 to about 20 nm is formed on the entire surface by CVD or the like. The thin oxide layer 21 can be omitted.

  Next, the nitride layer 22 is subjected to anisotropic etching. Thereby, as shown in FIG. 35, it is possible to leave the nitride spacer 22 a only under the nitride spacer 12. This is because the nitride layer 22 is formed after removing the oxide layer 20 a ′ formed so as to extend under the nitride spacer 12, so that the nitride layer 22 extends directly under the nitride spacer 12. This is because it can be formed so as to enter.

  Next, heat treatment is again performed on the SOI layer 3 in an oxidizing atmosphere using the nitride layer 11, the nitride spacer 12, and the nitride spacer 22a as a mask. Thereby, an oxide layer 20 a reaching the buried oxide layer 2 is selectively formed in the SOI layer 3. In this way, the oxide layer 20a formed through the two-step process can reduce bird's beaks more than the oxide layer 20 shown in FIG. Thereby, it is possible to make the inclination of the both side walls 3a of the SOI layer 3 steep.

  Next, the nitride layer 11, the nitride spacer 12, and the nitride spacer 22a are removed using hot phosphoric acid or the like. Then, using the polysilicon layer 10 as a mask, boron is ion-implanted into the region near the peripheral edge of the SOI layer 3 from a substantially vertical direction. Thereby, the channel stopper region 4 containing a high concentration p-type impurity is formed in a self-aligned manner.

  Thereafter, the polysilicon layer 10 and the oxide layer 9 are removed. Thereby, as shown in FIG. 38, the surface of the SOI layer 3 is selectively exposed. Then, a gate insulating layer 7 is formed on the exposed surface of the SOI layer 3, and a gate electrode 8 is formed on the gate insulating layer 7. The semiconductor device shown in FIG. 32 is formed through the above steps.

  As shown in FIG. 39, also in this embodiment, channel doping can be performed with the polysilicon layer 10 used for forming the channel stopper region 4 formed. This idea can also be applied to the above-described fifth embodiment.

  Next, a modification of the sixth embodiment will be described with reference to FIG. FIG. 40 is a cross-sectional view showing a semiconductor device in a modification of the sixth embodiment.

  Referring to FIG. 40, in this modification, the polysilicon layer 10 shown in FIG. 37 is left without being removed, and a polysilicon layer 23 is further formed on the polysilicon layer 10. Then, the gate electrode 8 is formed by simultaneously patterning the polysilicon layer 23 and the polysilicon layer 10. Thereby, the process of removing polysilicon layer 10 and oxide layer 9 can be omitted, so that the manufacturing process can be simplified as compared with the case of the sixth embodiment.

(Embodiment 7)
Next, Embodiment 7 of this invention and its modification are demonstrated using FIGS. 41-46. FIG. 41 is a cross sectional view showing a semiconductor device according to the seventh embodiment of the present invention.

  Referring to FIG. 41, in the seventh embodiment, nitride spacers 12 are formed on both side walls of SOI layer 3. The gate electrode 8 extends from the SOI layer 3 to the nitride spacer 12. By providing such a nitride spacer 12, the gate electrode 8 can be moved away from the side bottom of the SOI layer 3. Further, since the nitride spacer 12 is formed, the recessed portion 24 stays under the nitride spacer 12 and does not almost extend directly under the SOI layer 3. As described above, it is possible to effectively suppress the dielectric breakdown of the gate insulating layer in the vicinity of the peripheral portion of the SOI layer 3, which has been a problem in the conventional example.

  Next, a method for manufacturing the semiconductor device shown in FIG. 41 will be described with reference to FIGS. 42 to 45 are cross-sectional views showing the first to fourth steps of the manufacturing process of the semiconductor device in the seventh embodiment shown in FIG.

  Referring to FIG. 42, nitride layer 11 is formed by the same method as in the first embodiment. In the seventh embodiment, the oxide layer 9 has a thickness of about 10 to about 30 nm, the polysilicon layer 10 has a thickness of about 50 to about 100 nm, and the nitride layer 11 has a thickness of about 200. It is preferably about ˜250 nm. Next, a photoresist (not shown) patterned in the shape of the element formation region is formed on the nitride layer 11, and the nitride layer 11 is patterned using this as a mask. Boron ions are implanted into the SOI layer 3 using the nitride layer 11 as a mask. Thereby, an impurity implantation region 4 a is selectively formed in the SOI layer 3.

  Next, after depositing a nitride layer on the entire surface, the nitride layer is subjected to anisotropic etching. Thereby, nitride spacers 12 b are formed on the sidewalls of the nitride layer 11. Using this nitride spacer 12b and nitride layer 11 as a mask, polysilicon layer 10, oxide layer 9 and SOI layer 3 are successively patterned. Thereby, a channel stopper region 4 is formed in the vicinity of the peripheral portion of the SOI layer 3. This state is shown in FIG. The nitride layer for forming the nitride spacer 12b may be formed to a thickness of about 30 to about 100 nm.

  Next, the nitride layer 11 and the nitride spacer 12b are removed using hot phosphoric acid or the like. Thereafter, an insulating layer (not shown) such as an oxide or a nitride is deposited on the entire surface by using a CVD method or the like, and an anisotropic etching process is performed on the insulating layer. Thereby, as shown in FIG. 44, for example, nitride spacers 12 are formed on the sidewalls of SOI layer 3. At this time, since the polysilicon layer 10 is formed on the SOI layer 3, etching damage hardly occurs on the surface of the SOI layer 3 due to anisotropic etching for forming the nitride spacer 12.

  Next, the polysilicon layer 10 is removed by, for example, isotropic etching, and then the oxide layer 9 is removed by wet etching. Thereby, the surface of the SOI layer 3 is exposed. At this time, the surface of the buried oxide layer 2 is also slightly etched to form a recess portion 24 having a depth D. However, since the recess 24 remains below the nitride spacer 12, the side bottom of the SOI layer 3 is not exposed. Thereby, it is possible to suppress the dielectric breakdown of the gate insulating layer at the peripheral edge of the SOI layer 3.

  Thereafter, a gate insulating layer 7 is formed on the surface of the SOI layer 3, and a gate electrode 8 is formed on the gate insulating layer 7. The semiconductor device shown in FIG. 41 is formed through the above steps.

  Incidentally, since the recess 24 is formed as shown in FIG. 45, there is a concern that a substance for forming the gate electrode 8 remains in the recess 24 when the gate electrode 8 is patterned. Therefore, it can be said that it is preferable to add an isotropic etching process when the gate electrode 8 is formed.

  Next, a modified example of the seventh embodiment will be described with reference to FIG. FIG. 46 is a partial cross-sectional view showing a characteristic manufacturing process in the present modification.

  In the seventh embodiment, the nitride spacer 12 is formed on the side wall of the SOI layer 3. On the other hand, in this modification, a CVD oxide spacer 25 is formed on the sidewall of the SOI layer 3. More preferably, the CVD oxide spacer 25 is preferably made of CVD oxide using TEOS. It is known that CVD oxide generally has a higher etching rate than thermal oxide. Since the buried oxide film layer 2 has a property close to that of a thermal oxide, when the polysilicon layer 10 or the oxide layer 9 is etched, the buried oxide layer 2 has a recess 24a having a depth D. Even if this is formed, it is possible to effectively prevent the recess 24a from being formed under the CVD oxide spacer 25. Thus, patterning of the gate electrode 8 can be performed more easily than in the case of the seventh embodiment.

  Note that the oxide layer 9 may also be composed of CVD oxide. Thereby, the depth D of the recess portions 24 and 24a can be reduced.

  Moreover, silicon nitride can be given as a typical example of the nitride layer in each of the above embodiments, and silicon oxide can be given as a typical example of the oxide layer. In the case where a polysilicon layer is used as the gate electrode 8, it is preferable that the polysilicon layer is appropriately doped with p-type or n-type impurities. In the case of forming a dual gate, the n-type dopant and the p-type dopant may be doped into the gate electrode made of polysilicon by using a photoresist for the nMOS transistor and the pMOS transistor.

  As described above, various embodiments have been described. However, it should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is sectional drawing which shows the semiconductor device in Embodiment 1 of this invention. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 10 is a cross sectional view showing a first step of a manufacturing process of the semiconductor device in the first embodiment. FIG. 6 is a cross sectional view showing a second step of the manufacturing process of the semiconductor device in the first embodiment. FIG. 10 is a cross sectional view showing a third step of the manufacturing process of the semiconductor device in the first embodiment. FIG. 10 is a cross sectional view showing a fourth step of the manufacturing process of the semiconductor device in the first embodiment. FIG. 10 is a cross sectional view showing a fifth step of the manufacturing process of the semiconductor device in the first embodiment. It is sectional drawing which shows the semiconductor device in Embodiment 2 of this invention. FIG. 11 is a cross sectional view showing a first step of a semiconductor device manufacturing process in the second embodiment. FIG. 10 is a cross sectional view showing a second step of the manufacturing process of the semiconductor device in the second embodiment. FIG. 10 is a cross sectional view showing a third step of the manufacturing process of the semiconductor device in the second embodiment. It is sectional drawing which shows a mode that channel doping is performed in Embodiment 1 and Embodiment 2. FIG. FIG. 10 is a cross-sectional view showing a semiconductor device in a modification of the second embodiment. It is sectional drawing which shows the semiconductor device in Embodiment 3 of this invention. FIG. 11 is a cross sectional view showing a first step of a manufacturing process of a semiconductor device in Embodiment 3. FIG. 10 is a cross sectional view showing a second step of the manufacturing process of the semiconductor device in the third embodiment. 12 is a cross-sectional view showing a third step of the manufacturing process of the semiconductor device in the third embodiment. FIG. FIG. 11 is a cross sectional view showing a fourth step of the manufacturing process of the semiconductor device in the third embodiment. FIG. 24 is a cross sectional view showing a fifth step of the manufacturing process of the semiconductor device in the third embodiment. It is sectional drawing which shows the semiconductor device in Embodiment 4 of this invention. FIG. 23 is a cross sectional view showing a first step of a semiconductor device manufacturing process in the fourth embodiment. FIG. 24 is a cross sectional view showing a second step of the manufacturing process of the semiconductor device in the fourth embodiment. FIG. 24 is a cross sectional view showing a third step of the manufacturing process of the semiconductor device in the fourth embodiment. FIG. 24 is a cross sectional view showing a fourth step of the manufacturing process of the semiconductor device in the fourth embodiment. FIG. 10 is a cross-sectional view showing a semiconductor device in a modification of the fourth embodiment. FIG. 26 is a cross-sectional view showing a characteristic manufacturing step of the semiconductor device shown in FIG. 25. It is sectional drawing which shows the semiconductor device in Embodiment 5 of this invention. FIG. 23 is a cross sectional view showing a first step of a semiconductor device manufacturing process in the fifth embodiment. FIG. 25 is a cross sectional view showing a second step of the manufacturing process of the semiconductor device in the fifth embodiment. FIG. 24 is a cross sectional view showing a third step of the manufacturing process of the semiconductor device in the fifth embodiment. FIG. 24 is a cross sectional view showing a fourth step of the manufacturing process of the semiconductor device in the fifth embodiment. It is sectional drawing which shows the semiconductor device in Embodiment 6 of this invention. FIG. 29 is a cross sectional view showing a first step of a manufacturing process of the semiconductor device in the sixth embodiment. FIG. 24 is a cross sectional view showing a second step of the manufacturing process of the semiconductor device in the sixth embodiment. FIG. 29 is a cross sectional view showing a third step of the manufacturing process of the semiconductor device in the sixth embodiment. FIG. 25 is a cross sectional view showing a fourth step of the manufacturing process of the semiconductor device in the sixth embodiment. FIG. 24 is a cross sectional view showing a fifth step of the manufacturing process of the semiconductor device in the sixth embodiment. FIG. 24 is a cross-sectional view showing a sixth step of the manufacturing process of the semiconductor device in the sixth embodiment. It is sectional drawing which shows a mode that channel dope is performed in Embodiment 6. FIG. FIG. 25 is a cross-sectional view showing a semiconductor device in a modification of the sixth embodiment. FIG. 10 is a cross-sectional view showing a semiconductor device in a seventh embodiment. FIG. 23 is a cross sectional view showing a first step of a manufacturing process of the semiconductor device in the seventh embodiment. FIG. 25 is a cross sectional view showing a second step of the manufacturing process of the semiconductor device in the seventh embodiment. FIG. 24 is a cross sectional view showing a third step of the manufacturing process of the semiconductor device in the seventh embodiment. FIG. 24 is a cross sectional view showing a fourth step of the manufacturing process of the semiconductor device in the seventh embodiment. It is sectional drawing which shows the modification of the manufacturing process shown by FIG. It is sectional drawing which shows the 1st process of the manufacturing process of the conventional semiconductor device using LOCOS method. It is sectional drawing which shows the 2nd process of the manufacturing process of the conventional semiconductor device using LOCOS method. It is sectional drawing which shows the semiconductor device using the conventional mesa separation method. FIG. 50 is a cross-sectional view showing a first step of a manufacturing process of the semiconductor device shown in FIG. 49. FIG. 50 is a cross-sectional view showing a second step of the manufacturing process of the semiconductor device shown in FIG. 49.

Explanation of symbols

  1 silicon substrate, 2 buried oxide layer, 3 SOI layer (semiconductor layer), 3a sidewall, 4 channel stopper region, 4a impurity implantation region, 5 sidewall oxide layer, 6a projecting insulating layer, 6b, 27 sidewall insulating layer 7 gate insulating layer, 8 gate electrode, 9, 9a, 9b, 14, 16, 20, 20a, 20a ', 21 oxide layer, 10, 23 polysilicon layer, 10a first polysilicon layer, 10b second poly Silicon layer, 10c third polysilicon layer, 11, 22 nitride layer, 12, 12a, 12b, 22a nitride spacer, 13a, 13b insulating layer, 14a inclined top surface, 14b flat top surface, 15 trench, 17 trench sidewall Top corner, 18 first sidewall oxide layer, 19 second sidewall oxide layer, 24, 24a recess, 25 CVD oxide spacer.

Claims (3)

A semiconductor device having an SOI (Semiconductor On Insulator) structure,
A semiconductor substrate having a main surface;
A mesa-like semiconductor layer formed on the main surface of the semiconductor substrate with a buried insulating layer interposed between the source and drain regions;
A gate insulating layer formed on the semiconductor layer;
An isolation formed on a peripheral portion of the semiconductor layer and having an upper surface inclined upward from the gate insulating layer on the peripheral portion and a flat upper surface continuous with the upper surface inclined upward on the buried insulating layer An insulating layer;
A gate electrode extending from above the semiconductor layer onto the isolation insulating layer;
A semiconductor device comprising: A channel stopper region formed in the vicinity of the peripheral edge of the semiconductor layer;
The isolation insulating layer is formed on the channel stopper region and a peripheral edge of the semiconductor layer, and has an upper surface inclined upward from the gate insulating layer on the channel stopper region, and on the buried insulating layer. The semiconductor device according to claim 1, further comprising a flat upper surface continuous with an upper surface inclined upward. The isolation insulating layer extends from the channel stopper region onto the buried insulating layer adjacent to the semiconductor layer, and has a flat upper surface continuous with the inclined upper surface above the buried insulating layer. And
A first conductive layer is formed on the semiconductor layer with a gate insulating layer interposed therebetween,
A second conductive layer is formed on the first conductive layer so as to extend on the isolation insulating layer,
The gate electrode is formed by the first and second conductive layers;
The semiconductor device according to claim 2, wherein the flat upper surface is positioned higher than the upper surface of the semiconductor layer than the upper surface of the first conductive layer.

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