JP2005353892A - Semiconductor substrate, semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate with a trench-embedded element isolation region, capable of suppressing a leakage current due to crystal defects in the device of a low-drive voltage and securing the field inversion withstand voltage of the device of a high-drive voltage. <P>SOLUTION: An oxide film 13 is embedded in the trench 12 of a prescribed depth on a silicon substrate 11, and element isolation regions 141 and 142 are formed. The element isolation region 141 is formed in a device region A1 to which a first drive voltage is supplied. The element isolation region 142 is formed in a device region A2 to which a second drive voltage lower than the first drive voltage is supplied. In the element isolation region 142, the height of the embedded oxide film 13 is lower than the one in the element isolation region 141. Thus, by comparison, in the same volume part of the trench 12, the volume of the embedded oxide film 13 is smaller in the element isolation region 142 than that in the element isolation region 141. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to the manufacture of a semiconductor device in which devices having different drive voltages are mixed, and more particularly to a semiconductor substrate, a semiconductor device, and a method of manufacturing the same, which include a step of manufacturing STI (Shallow Trench Isolation).

  Some semiconductor devices are configured by using a plurality of devices having different drive voltages in order to achieve high integration, high performance, or multiple functions. Particularly in a semiconductor memory device or the like, high breakdown voltage MOS transistors and low breakdown voltage MOS transistors are mixed in a semiconductor chip. Along with the high integration and miniaturization of devices, STI (Shallow Trench Isolation), a structure in which an insulator (oxide film) is buried in a trench (groove), has been used.

  With respect to the STI structure, the planarized oxide film embedded in the trench is unified at a substantially uniform height from the bottom of the trench to the active region on the semiconductor substrate throughout the semiconductor substrate. That is, the buried depth (height) of the oxide film with respect to the active region is substantially constant regardless of the drive voltage of the device.

  Due to the structure of STI, the stress in the substrate increases due to the thermal history during the manufacturing process due to the difference in thermal expansion coefficient between silicon of the semiconductor substrate and the oxide film embedded in the trench (STI stress). As a result, it is known that dislocations are generated near the upper edge and the bottom edge of the trench, and crystal defects are generated. Crystal defects easily capture metal impurities and the like, and increase junction leakage.

Conventionally, the quality of the buried oxide film is devised as a technique for reducing crystal defects in the substrate in buried element isolation, such as STI. For example, an oxide film is embedded in a trench having an aspect ratio in a predetermined range by an organic silicon CVD method. A heat treatment at 1100 ° C. to 1350 ° C. is performed before or after planarization. Thereby, the ring structure is separated, and a film structure including a ring structure having a 5-membered ring or more and a ring structure having a 4-membered ring or less in a predetermined ratio (for example, see Patent Document 1).
JP-A-9-205140 (7th, 8th page, FIG. 1)

  In the STI structure, the depth of the trench and the height of the oxide film buried and planarized in the trench with respect to the active region are mainly determined by the field inversion breakdown voltage of the device having a high drive voltage. Therefore, it becomes a structure with higher STI stress than necessary for a device with a low driving voltage. Even if the film quality of the buried oxide film is devised as in the prior art, the oxide film buried state in the trench is mainly formed in accordance with the field inversion breakdown voltage of the device having a high drive voltage. In devices with a low drive voltage, even minor defects can affect performance. Therefore, it is not useful to configure element isolation in an oxide film buried state more than necessary in a device having a low driving voltage. There is room for improvement.

  The present invention has been made in consideration of the above-described circumstances, and is a trench capable of suppressing a leakage current due to crystal defects in a device having a low driving voltage and ensuring a field inversion breakdown voltage of a device having a high driving voltage. An object of the present invention is to provide a semiconductor substrate having a buried element isolation region, a semiconductor device, and a manufacturing method thereof.

  The semiconductor substrate according to the present invention includes an element isolation region in which an insulator is embedded on the substrate, the first element isolation region provided in a device region to which a first drive voltage is applied, and the first drive And a second element isolation region provided in a device region to which a second drive voltage lower than the voltage is applied and having a lower height of the insulator embedded than the first element isolation region.

  According to the semiconductor substrate of the present invention, the second element isolation region is formed in which the height of the insulator embedded in the substrate is lower than that of the first element isolation region. Thereby, in the device region to which the second drive voltage lower than the first drive voltage is applied, the stress on the substrate of the embedded insulator is relaxed.

  The semiconductor substrate according to the present invention includes an element isolation region in which an insulator is embedded in a trench having a predetermined depth formed in the substrate, and is provided in a device region to which a first drive voltage is applied. The volume of the insulator embedded in the first element isolation region compared with the trench of the same volume provided in the region and the device region to which the second drive voltage lower than the first drive voltage is applied And a second element isolation region having a small size.

  According to the semiconductor substrate of the present invention, the second element isolation region in which the volume of the insulator embedded is smaller than that of the first element isolation region is formed as compared with the trench having the same volume formed in the substrate. . Thereby, in the device region to which the second drive voltage lower than the first drive voltage is applied, the stress on the substrate of the embedded insulator is relaxed.

  In each of the semiconductor substrates according to the present invention, one element region on the substrate surrounded by the second element isolation region is more than one element region on the substrate surrounded by the first element isolation region. It is characterized by a small area. That is, it is important to prevent a crystal defect related to the element isolation region for a small-sized element.

  Further, the insulator embedded in the trench is not limited to the first and second driving voltages, but is embedded in a device region to which the first driving voltage or other predetermined driving voltage lower than the first driving voltage is applied. It is also possible to adjust the height.

  A semiconductor device according to the present invention includes an element isolation region in which an insulator is embedded on a semiconductor substrate, the first element isolation region provided in a device region to which a first drive voltage is applied, and the first element isolation region A second element isolation region provided in a device region to which a second drive voltage lower than the drive voltage is applied, and having a lower height of the insulator embedded than the first element isolation region; A first MOS type element provided with a first gate length and a width on a semiconductor substrate surrounded by the element isolation region, and the first MOS type element provided on the semiconductor substrate surrounded by the second element isolation region. And a second MOS type element provided with a second gate length and width smaller than one MOS type element.

  According to the semiconductor device of the present invention, the second element isolation region in which the height of the insulator embedded in the substrate is lower than that of the first element isolation region is formed. In the device region to which the second driving voltage lower than the first driving voltage is applied, the stress on the substrate of the embedded insulator is relaxed. A second MOS type element having a second gate length and width smaller than the first MOS type element is provided on the semiconductor substrate surrounded by the second element isolation region. That is, the reliability of the second MOS type element having a small size that is more susceptible to crystal defects is improved.

The second MOS type element has a diffusion layer concentration peak in the semiconductor substrate at a level equivalent to or lower than the upper surface of the insulator buried in the element isolation region. That is, this is a configuration for obtaining the reliability of the second MOS type element.
The second MOS type element has a diffusion layer concentration peak in the semiconductor substrate at a level equivalent to or lower than the upper surface of the insulator buried in the element isolation region. In both the second MOS type elements, the gate electrode and the diffusion layer are silicided. This is a configuration for obtaining the reliability of the silicide structure in the second MOS type element.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a trench for element isolation on a semiconductor substrate and a step of embedding an insulator in the trench, and the depth of the trench is a first driving voltage. The insulator embedded in the trench is necessary for the device region to which the first driving voltage or another predetermined driving voltage lower than the first driving voltage is applied. Adjust to the embedding height.

  According to the semiconductor device manufacturing method of the present invention, the amount of the insulating film embedded in the trench of the device region to which a predetermined drive voltage lower than the first drive voltage is applied is optimized, and the field inversion breakdown voltage is secured. The stress embedded in the substrate is reduced by the insulator embedded in the substrate.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a trench for element isolation on a semiconductor substrate, a step of embedding an insulating film in the trench, and a first among the insulating films embedded in the trench. The portion provided in the device region to which the driving voltage is applied is protected by an etching-resistant member, and the portion provided in the device region to which the second driving voltage lower than the first driving voltage is provided has a predetermined thickness on the upper portion of the insulating film. An etching process to remove, and a process of forming MOS type elements having different sizes on the semiconductor substrate in the device region to which the first drive voltage is applied and the semiconductor substrate in the device region to which the second drive voltage is applied And including.

  According to the semiconductor device manufacturing method of the present invention, selective etching is performed on the insulating film embedded in the trench in the device region to which the second drive voltage lower than the first drive voltage is applied. Thus, stress relaxation of the insulator embedded in the substrate to the substrate is achieved. Depending on the size of the MOS type element, the reliability of the MOS type element that is more susceptible to crystal defects is improved.

In the method of manufacturing a semiconductor device according to the present invention, the step of forming the element isolation trench includes a step of forming a mask pattern of a stack of an oxide film and a nitride film on the semiconductor substrate, and the mask pattern. Performing the anisotropic etching to form the trench, the step of etching and removing the oxide film at the upper edge of the trench by a predetermined amount, and oxidizing the inner wall of the trench with heat treatment to form the upper portion of the trench Rounding the edge and bottom edge. Appropriate rounding is applied to relieve stress at the top and bottom edges of the trench that are likely to cause crystal defects.
In addition, after the etching process for removing the upper portion of the insulating film to a predetermined thickness, a process for oxidizing the exposed semiconductor substrate portion above the trench may be further included.

BEST MODE FOR CARRYING OUT THE INVENTION

  FIG. 1 is a cross-sectional view showing the main configuration of a semiconductor substrate according to an embodiment of the present invention. A trench 12 having a predetermined depth is formed on the silicon substrate 11. An oxide film 13 which is an insulator is buried in the trench 12 to form element isolation regions 141 and 142. Here, the element isolation region 141 is formed in the device region A <b> 1 to which the first drive voltage is applied in the substrate 11. The element isolation region 142 is formed in the device region A2 in the substrate 11 where a second drive voltage lower than the first drive voltage is applied. In the element isolation region 142, the height of the buried oxide film 13 is lower than that of the element isolation region 141. As a result, when compared with the same volume portion of the trench 12, the volume of the oxide film 13 in which the element isolation region 142 is embedded is smaller than that of the element isolation region 141. Further, when the areas of the one element regions B1 and B2 are compared between the device regions A1 and A2, the area of the one element region B2 in the device region A2 is smaller.

  The depth of the trench 12 is set in accordance with the field inversion breakdown voltage of the device region A1 to which the higher first driving voltage is applied. When this trench 12 is filled up to the top with the oxide film 13, considerable stress (stress on the substrate 11) is applied. This is because the stress is applied differently depending on the thermal process in the process of manufacturing the semiconductor device. In the device region A1, a high drive voltage is applied, and the leak due to a very few crystal defects is not so much affected. However, if the device region A2 is provided with a low drive voltage that easily affects leakage due to very few crystal defects and is composed of an element with a small size, it is desirable that the device region A2 does not require much STI stress. In addition, the device region A2 may be smaller than the device region A1 in terms of field inversion withstand voltage. Therefore, the element isolation region 142 in the device region A2 has a configuration in which the oxide film 13 is not filled up to the top of the trench 12. In the element isolation region 142, the height of the buried oxide film 13 is lower than that of the element isolation region 141, the volume is reduced, and the stress on the substrate 11 is also reduced. Thus, the element isolation region 142 has a structure in which crystal defects are less likely to occur than the element isolation region 141.

2 to 4 are cross-sectional views showing the manufacturing method of the configuration shown in FIG. 1 in the order of steps.
As shown in FIG. 2, an oxide film 21 and a nitride film 22 are formed on the silicon substrate 11 with a predetermined thickness by using a CVD method or the like. The oxide film 21 has a thickness of about 10 nm, and the nitride film 22 has a thickness of about 20 nm. Next, a resist pattern (not shown) is formed on the oxide film 21 and the nitride film 22 by using a photolithography technique, and anisotropic etching is performed according to the pattern. Thereby, a mask pattern is formed by the oxide film 21 and the nitride film 22 where the trench formation planned portion of the substrate 11 is exposed. Anisotropic etching is performed according to this mask pattern to form a trench 12 having a predetermined depth selected from, for example, 300 to 700 nm. The anisotropic etching is dry etching with plasma and uses a fluorine-based etching gas. Next, the undercut 23 is formed by removing the oxide film 21 in the depth direction by, for example, about 30 nm by wet etching using hydrofluoric acid.

Next, as shown in FIG. 3, an oxide film 24 having a thickness of 20 nm to 30 nm is formed on the inner wall of the trench in a dry oxidation atmosphere at 1000 to 1100 ° C. using the nitride film 22 as a mask. Thereby, the upper edge TE and the bottom edge BE of the trench 12 are rounded. Next, a dense plasma oxide film is deposited using a CVD technique involving high-density plasma. As the film forming conditions, the film is deposited in a thickness of about 700 to 800 nm in about 1 minute in a SiH ₄ gas plasma atmosphere having a pressure of about 1 Pa. As a result, the trench 12 is filled with the oxide film 13 to a level above the substrate 11.

  Next, as shown in FIG. 4, the oxide film 13 is removed and planarized by a CMP (chemical mechanical polishing) technique using the nitride film 22 as a mask. Thereby, the element isolation region 141 is formed. Thereafter, a resist pattern 25 is formed to cover the device region A1 to which the higher first drive voltage is applied. Next, an etch back process is performed. For example, dry etching using fluorine-based gas plasma. The element isolation region 142 of the device region A2 is formed by etching about several hundred nm, for example, about 200 nm under a condition with a low etching rate.

  Next, the nitride film 22 is removed by wet etching using hot phosphoric acid. Further, the oxide film 21 is removed by wet etching using hydrofluoric acid to expose the substrate 11. As a result, the structure as shown in FIG. 1 is obtained, having element isolation regions 141 and 142 having different heights of the oxide film 13 embedded in the substrate 11.

  According to the embodiment and the method, the element isolation region 141 that secures the field inversion breakdown voltage of the device having a high driving voltage is formed. Further, an element isolation region 142 in which the height of the oxide film 13 embedded in the substrate 11 is lower than that of the element isolation region 141 is formed. The element isolation region 142 is used in the device region A2 to which a second drive voltage lower than the first drive voltage applied to the device region A1 is applied. That is, the prevention of crystal defects caused by the element isolation region due to the thermal process in the process of manufacturing the semiconductor device is utilized in a more important place, and the effect is exhibited. The element isolation region 142 can suppress a leakage current due to crystal defects in a device with a low drive voltage, and the element isolation region 141 can secure a field inversion breakdown voltage of a device with a high drive voltage.

  FIG. 5 is a cross-sectional view showing the main configuration of a semiconductor device according to the second embodiment of the present invention. In the semiconductor substrate of FIG. 1 shown in the first embodiment, a MOS transistor is formed in each element region. The MOS transistors 51 and 52 are configured to have a substrate (or well) 11 and a diffusion layer (source / drain) having a reverse conductivity type. The MOS transistor 52 formed in the device region A2 to which the second drive voltage lower than the first drive voltage is applied has a size compared to the MOS transistor 51 formed in the device region A1 to which the first drive voltage is applied. small. That is, the gate length and gate width of the MOS transistor 52 are smaller than those of the MOS transistor 51. Accordingly, the thickness of the gate oxide film may be varied. Regarding the MOS transistor 52, the concentration peak of the source / drain diffusion layer 662 is desirably present in the substrate 11 at a level equivalent to or lower than the upper surface of the oxide film 13 embedded in the element isolation region 142. Thereby, the reliability to silicidation is obtained.

6 to 8 are cross-sectional views showing the main part of the semiconductor device and the manufacturing method thereof according to the third embodiment of the present invention in the order of steps. The same reference numerals are given to the same portions as those in the configuration of FIGS.
As shown in FIG. 6, in the semiconductor substrate 11 of FIG. 1, a wet oxidation process is performed in a steam atmosphere in a range of about 700.degree. C. to 850.degree. C. to form a thin pre-oxide film of about 10 nm. As a result, the shape of the upper edge TE of the trench 12 is further rounded. Next, a pre-oxide film is formed again in a dry oxidation atmosphere in the range of 1000 ° C. to 1100 ° C. Thereby, a comprehensive sacrificial oxide film 61 of about 30 nm is formed. High temperature dry oxidation increases the roundness of the upper edge TE of the trench 12 and contributes to stress relaxation on the bottom edge BE of the trench 12 and the walls of the substrate 11 forming the trench 12.

  A well and a channel region (not shown) are formed through the oxide film 61 through a plurality of photolithography processes and ion implantation processes. The sacrificial oxide film 61 has an oxide film quality that can withstand resist peeling caused by a plurality of photolithography processes / ion implantations through the above processes. Further, the flatness of the substrate on the element region is improved. In particular, this contributes to prevention of oxide film omission and rounding in the element region near the element isolation region 142.

  Next, as shown in FIG. 7, the sacrificial oxide film 61 is peeled off, and gate oxide films 621 and 622 are formed. When the thicknesses of the gate oxide films 621 and 622 are different, one gate oxide film is formed over the entire area, and then only a region where the other gate oxide film is necessary is peeled off using the mask member, and the other is newly added. Rebuild the gate oxide film. Next, gate electrodes 631 and 632 having a predetermined pattern are formed. After forming source / drain extension regions 641 and 642 to form an LDD (Lightly Doped Drain) structure, sidewalls (spacers) 651 and 652 are formed, and source / drain diffusion layers 661 and 662 are formed. Thereby, the configuration as shown in FIG. 5 is obtained.

  Next, as shown in FIG. 8, silicide layers 67 are formed on the gate electrodes 631 and 632 and on the source / drain diffusion layers 661 and 662 by using a salicide process. Thus, the resistance is reduced.

  According to the embodiment and the method described above, the element isolation region 141 that secures the field inversion withstand voltage of the MOS transistor 51 having a high drive voltage and the element isolation region 142 that secures the field inversion withstand voltage of the MOS transistor 52 having a lower drive voltage are provided. It is formed. In addition, the MOS transistor 52 having a lower driving voltage than the MOS transistor 51 has a lower field inversion breakdown voltage, and is more affected by a leakage current due to crystal defects than the MOS transistor 51. Therefore, in the region where the MOS transistor 52 is formed, the height of the oxide film 13 embedded in the substrate 11 is lower and the volume of the device isolation region 142 is smaller than that of the device isolation region 141 even though the depth of the trench 12 is the same. Is formed. As a result, the effect of preventing the derivation of crystal defects and transition defects is increased in the process of manufacturing a semiconductor device involving a thermal process, and the reliability is improved in the MOS transistor 52 where prevention of crystal defects caused by the element isolation region is more important.

  The oxide film 13 embedded in the trench 12 is not limited to the first and second driving voltages, but is embedded in each device region to which the first driving voltage or other predetermined driving voltage lower than the first driving voltage is applied. It is also possible to adjust the height. That is, a semiconductor substrate or a semiconductor device in which the buried height of the oxide film 13 is 3 or more can be considered.

  As described above, according to the present invention, the trench and insulator embedding form related to the element isolation region having the higher drive voltage and the element isolation region having the lower drive voltage are not matched in the same manner. Even if the depth of the trench is the same, an insulator is not filled up to the top of the trench. Thereby, the embedded volume of the insulator for element isolation is reduced, and the stress on the substrate is also reduced. Such an element isolation region is used for element isolation that constitutes a small-sized element that is more susceptible to crystal defects. As a result, a semiconductor substrate having a trench embedded element isolation region that can suppress a leakage current due to crystal defects in a device with a low driving voltage and can secure a field inversion withstand voltage of a device with a high driving voltage, and a semiconductor device and its manufacture A method can be provided.

Sectional drawing which shows the principal part structure of the semiconductor substrate which concerns on one Embodiment. The 1st sectional view showing the manufacturing method of the composition of Drawing 1 in order of a process. The 2nd sectional view following Drawing 2. FIG. 4 is a third sectional view following FIG. 3. Sectional drawing which shows the principal part structure of the semiconductor device which concerns on 2nd Embodiment. The 1st sectional view showing the semiconductor device and manufacturing method principal part of a 3rd embodiment in order of a process. The 2nd sectional view following Drawing 6. FIG. 8 is a third sectional view following FIG. 7.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Silicon substrate, 12 ... Trench, 13, 21, 24, 61 ... Oxide film, 141, 142 ... Element isolation region, 22 ... Nitride film, 23 ... Undercut, 25 ... Resist pattern, 51, 52 ... MOS transistor, 621, 622 ... gate oxide film, 631, 632 ... gate electrode, 641, 642 ... extension region, 651, 652 ... sidewall (spacer), 661, 662 ... source / drain diffusion layer, 67 ... silicide layer, TE ... trench Top edge, TB ... Trench bottom edge. A1, A2 ... Device region, B1, B2 ... One element region.

Claims (10)

Comprising an element isolation region in which an insulator is embedded on the substrate;
A first element isolation region provided in a device region to which a first drive voltage is applied;
A second element isolation region provided in a device region to which a second drive voltage lower than the first drive voltage is applied, and having a lower height of the insulator embedded than the first element isolation region;
Including a semiconductor substrate. An element isolation region in which an insulator is embedded in a trench having a predetermined depth formed in the substrate,
A first element isolation region provided in a device region to which a first drive voltage is applied;
Compared with a trench having the same volume provided in a device region to which a second drive voltage lower than the first drive voltage is applied, the volume of the insulator embedded in the device isolation region is smaller than that in the first element isolation region. Two element isolation regions;
Including a semiconductor substrate. 3. The semiconductor according to claim 1, wherein the one element region on the substrate surrounded by the second element isolation region has a smaller area than the one element region on the substrate surrounded by the first element isolation region. substrate. Comprising an element isolation region in which an insulator is embedded on a semiconductor substrate;
A first element isolation region provided in a device region to which a first drive voltage is applied;
A second element isolation region provided in a device region to which a second drive voltage lower than the first drive voltage is applied, and having a lower height of the insulator embedded than the first element isolation region;
A first MOS type element provided with a first gate length and width on a semiconductor substrate surrounded by the first element isolation region;
A second MOS type element provided on the semiconductor substrate surrounded by the second element isolation region and having a second gate length and width smaller than the first MOS type element;
A semiconductor device including: 5. The semiconductor device according to claim 4, wherein the second MOS type element has a diffusion layer concentration peak in the semiconductor substrate at a level equivalent to or lower than the upper surface of the insulator buried in the element isolation region. The second MOS type element has a concentration peak of a diffusion layer in the semiconductor substrate at a level equivalent to or lower than the upper surface of the insulator buried in the element isolation region. 5. The semiconductor device according to claim 4, wherein the gate electrode and the diffusion layer are silicided in both of the MOS type elements. Forming a trench for element isolation on a semiconductor substrate;
Embedding an insulator in the trench,
The depth of the trench is set in accordance with a device region to which a first driving voltage is applied, and the insulator embedded in the trench is the first driving voltage or another predetermined voltage lower than the first driving voltage. A method for manufacturing a semiconductor device, wherein a device region to which a drive voltage is applied is adjusted to a required embedded height. Forming a trench for element isolation on a semiconductor substrate;
Embedding an insulating film in the trench;
Of the insulating film embedded in the trench, a portion provided in a device region to which a first driving voltage is applied is protected by an etching resistant member, and a device to which a second driving voltage lower than the first driving voltage is applied The portion provided in the region is an etching process for removing a predetermined thickness of the upper part of the insulating film;
Forming MOS-type elements having different sizes on the semiconductor substrate in the device region to which the first drive voltage is applied and the semiconductor substrate in the device region to which the second drive voltage is applied;
A method of manufacturing a semiconductor device including: The step of forming the element isolation trench includes the steps of: forming a mask pattern of a stack of an oxide film and a nitride film on the semiconductor substrate; and forming the trench by anisotropic etching according to the mask pattern; A step of etching and removing a predetermined amount of the oxide film on the upper edge of the trench in a depth direction, and a step of oxidizing the inner wall of the trench with heat treatment and rounding the upper edge and the bottom edge of the trench. A method for manufacturing a semiconductor device according to claim 5. 7. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of oxidizing the exposed semiconductor substrate portion above the trench after the etching step of removing the upper portion of the insulating film by a predetermined thickness.

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