JPH113974A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a standby current in a semiconductor integrated circuit device, by a method wherein an interelement isolation region is formed by burying an insulating film in a groove formed in a semiconductor substrate, and the height of the surface of the insulating film on the regions of thin gate insulating films is formed almost flush with that of the surface of the substrate. SOLUTION: Thin gate insulating films 11 are formed on an internal circuit provided with a CMOSFET having a short gate length by a second thermal oxidation treatment, and a thick gate insulating film 12 is provided on an I/O circuit provided with a CMOSFET having a long gate length by first and second thermal oxidation treatments. An interelement isolation region for insulating electrically the adjacent MOSFETs from each other is formed by burying an insulating film 4 in a groove 3 formed in a semiconductor substrate 1. Moreover, in the internal circuit, the height of the surface of the film 4 buried in the groove 3 is formed in roughly the same height as that of the surface of the substrate 1, and the surface of the substrate 1 in the internal circuit is made lower than that of the substrate 1 in the I/O circuit. As a result, an electric field concentration in a semiconductor integrated circuit device due to a malformation of the film 4 is inhibited and a standby current in the device can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a CMOSFET.
(Complementary Metal Oxide Semiconductor Field Ef
Logic Transistor (Large Sc)
The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device having an ale integrated circuit.

[0002]

2. Description of the Related Art CMOS logic LSI and SRAM
(Static Random Access Memory) or DRAM (Dy
In a CMOS logic LSI equipped with a dynamic random access memory (NRAM), the power supply voltages of the internal circuit and the input / output circuit may be different. For example, CMOS for high speed
In a logic LSI, since the length (gate length) of the gate electrode of the MOSFET in the internal circuit is shorter than the gate length of the MOSFET in the input / output circuit, the withstand voltage of the semiconductor region forming the source and drain regions of the MOSFET in the internal circuit is reduced. To ensure this, the power supply voltage of the internal circuit is set lower than the power supply voltage of the input / output circuit.

Further, an MO of an input / output circuit having a high power supply voltage is used.
The reliability of the gate insulating film is ensured by making the thickness of the gate insulating film of the SFET larger than the thickness of the gate insulating film of the MOSFET of the internal circuit having a low power supply voltage.
For example, a CM provided with a gate electrode having a length of 0.2 μm
In a CMOS logic LSI having an OSFET in an internal circuit, the power supply voltage of the internal circuit is 1.8 V, the power supply voltage of the input / output circuit is 3.3 V, the thickness of the gate insulating film of the MOSFET in the internal circuit is about 4 nm, and the input voltage is about 4 nm. The thickness of the gate insulating film of the MOSFET in the output circuit is about 8 nm.

As a method of forming two types of gate insulating films having different thicknesses on a semiconductor substrate composed of silicon single crystal, first, a LOCOS (Local) is formed in an element isolation region on a main surface of the semiconductor substrate. Oxidation of Silicon)
After forming the oxide film, a first thermal oxidation treatment is performed on the semiconductor substrate to form a first silicon oxide film on the surface of the semiconductor substrate, and then a first oxidation of a region where a thin gate insulating film is formed is performed. A method is employed in which the silicon film is removed by wet etching, and then the semiconductor substrate is again subjected to a second thermal oxidation treatment to form a second silicon oxide film on the surface of the semiconductor substrate.

That is, the thin gate insulating film is formed by the second silicon oxide film formed by the second thermal oxidation process, and the thick gate insulating film is formed by the first thermal oxidation process and the second thermal oxidation process. And a second silicon oxide film to be formed.

An MO having a thin gate insulating film is provided.
MOSFET with SFET and thick gate insulating film
As an example of a semiconductor integrated circuit device having a DRAM, there is a DRAM embedded logic described in “Nikkei Micro Device” issued by Nikkei McGraw-Hill Company, March 1996, pages P54 to P59.

[0007]

However, in the above method of forming gate insulating films having different thicknesses on a semiconductor substrate, the first silicon oxide film in a region where a thin gate insulating film is formed is removed by wet etching. When doing
The LOCOS oxide film formed in the element isolation region is shaved, and the upper surface of the LOCOS oxide film is lower than the surface of the semiconductor substrate at the end of the LOCOS oxide film.

[0008] Therefore, the concentration of electric field on the end portion of the LOCOS oxide film MOSFET drain current (I _ds) - Kink (Kink) occurs in the gate voltage (V _g) characteristics, MOSF
Even when the ET is off, there is a problem that the standby current flows and the power consumption increases.

It is an object of the present invention to provide a MOSFET provided with a thin gate insulating film and a MOSFET provided with a thick gate insulating film.
It is an object of the present invention to provide a technology capable of suppressing an increase in power consumption by reducing a standby current in a semiconductor integrated circuit device having an OSFET.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. (1) The semiconductor integrated circuit device of the present invention includes a MOSFET provided with a thin gate insulating film and a MOSFET provided with a thick gate insulating film, and electrically insulates adjacent semiconductor elements. The element isolation region is formed by an insulating film embedded in a groove formed in the semiconductor substrate, and the surface of the insulating film in the region where the thin gate insulating film is formed is almost the same as the surface of the semiconductor substrate. Height.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, first, a first silicon nitride film is deposited on a semiconductor substrate, and then the first silicon nitride film and the semiconductor substrate are sequentially processed. A groove is formed in the element isolation region of the substrate. Next, after depositing an insulating film on the semiconductor substrate, a second silicon nitride film is formed over the groove in the region where the thin gate insulating film is formed, and then the second silicon nitride film and the insulating film are formed. The surface is polished, and an insulating film is embedded in the groove.
Next, after removing the first and second silicon nitride films, a first thermal oxidation treatment is performed on the semiconductor substrate to form a first silicon oxide film on the surface of the semiconductor substrate, and then a thin gate insulating film is formed. Removing the first silicon oxide film in the region where is formed, and then subjecting the semiconductor substrate to a second thermal oxidation process,
Forming a second silicon oxide film on a surface of a semiconductor substrate to form a thin gate insulating film formed by a second thermal oxidation process, and a thin gate insulating film formed by a first thermal oxidation process and a second thermal oxidation process A thick gate insulating film is provided.

According to the above means, when the surfaces of the second silicon nitride film and the insulating film are polished and the insulating film is buried in the grooves provided in the semiconductor substrate, the surface of the semiconductor substrate where the grooves are not formed is formed. The first silicon nitride film remains. Here, since the second silicon nitride film serves as a stopper during the polishing, the thickness of the first silicon nitride film is large in a region where a thin gate insulating film is formed, and a thick gate insulating film is formed. Area becomes thinner.

Therefore, after that, when the first silicon nitride film is removed, in a region where a thin gate insulating film is formed,
The surface of the insulating film buried in the groove is higher than the surface of the semiconductor substrate, and in the region where the thick gate insulating film is formed, the surface of the insulating film buried in the groove is almost the same as the surface of the semiconductor substrate. And height.

Further, after that, a first thermal oxidation treatment is performed on the semiconductor substrate to form a first silicon oxide film on the surface of the semiconductor substrate, and then a first silicon oxide film in a region where a thin gate insulating film is formed is formed. Even if the silicon oxide film is removed, the insulating film buried in the groove does not become locally thin, and the surface of the insulating film buried in the groove in the region where the thin gate insulating film is formed and the surface of the semiconductor substrate are removed. They are almost the same height.

Accordingly, the electric field concentration due to the defective shape of the insulating film constituting the element isolation region is suppressed, and the MOSFE
Since it is possible to prevent the occurrence of kink in the I _ds -V _g characteristics of the T, MOSFET is the standby current in the off state it is possible to suppress an increase in reduced power consumption.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a CM according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating an internal circuit and an input / output circuit of an OS logic LSI. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

As shown in FIG. 1, a CMO having a short gate length is used.
In an internal circuit having an SFET, a thin gate insulating film 11 having a thickness of, for example, about 4 nm, which is formed by a second thermal oxidation process, is provided.
In an input / output circuit having ET, for example, about 8 nm formed by the first thermal oxidation process and the second thermal oxidation process.
A gate insulating film 12 having a large thickness is provided. An element isolation region provided for electrically insulating adjacent MOSFETs from each other is constituted by an insulating film 4 buried in a groove 3 formed in the semiconductor substrate 1. Further, in the internal circuit, the surface of the insulating film 4 buried in the groove 3 and the surface of the semiconductor substrate 1 are substantially at the same height, and the surface of the semiconductor substrate 1 of the internal circuit is And the height difference (h) is 30 nm or less.

A method of manufacturing the internal circuit and the input / output circuit of the CMOS logic LSI according to the present embodiment will be described with reference to the cross-sectional views of the main parts of the semiconductor substrate shown in FIGS.

First, as shown in FIG. 2, a first silicon nitride film 2 is deposited on a semiconductor substrate 1 made of an n-type silicon single crystal, and then, using a patterned photoresist as a mask, The first silicon nitride film 2 is etched to leave the first silicon nitride film 2 only in the active region where the semiconductor element is formed. Next, a trench 3 is formed in the semiconductor substrate 1 from which the first silicon nitride film has been removed. The thickness of the silicon nitride film 2 is, for example, 70 nm, and the depth of the groove 3 is, for example, 0.35 μm.

Next, a thickness of 350 to 50
After depositing an insulating film 4 having a thickness of 0 nm, for example, a silicon oxide film, a second silicon nitride film 5 having a thickness of, for example, 170 nm is formed only on the groove 3 provided in the semiconductor substrate 1 of the internal circuit.
To form The second silicon nitride film 5 is provided to improve flatness when polishing the surface of the insulating film 4 later.

Next, as shown in FIG. 3, the surfaces of the second silicon nitride film 5 and the insulating film 4 are polished by a chemical mechanical polishing method until the first silicon nitride film 2 is exposed. By doing, groove 3
Is embedded in the insulating film 4, and the insulating film 4 embedded in the trench 3 forms an element isolation region. Since the second silicon nitride film 5 provided in the internal circuit serves as a stopper during the above polishing, the first silicon nitride film 2 in the internal circuit is thick and the first silicon nitride film in the input / output circuit. 2 becomes thinner.

Next, as shown in FIG. 4, the silicon nitride film 2 is removed by hot phosphoric acid. Here, in the internal circuit, the surface of the insulating film 4 buried in the groove 3 is higher than the surface of the semiconductor substrate 1, and in the input / output circuit, the surface of the insulating film 4 buried in the groove 3 is in contact with the surface of the semiconductor substrate 1. They are almost the same height. Thereafter, the p-type well 6 and the n-type well 7 are
To form

Next, although not shown, the p-type wells 6 and n
After a p-type impurity (for example, boron (B)) is introduced into each channel region of the mold well 7 to form a threshold voltage control layer, a first thermal oxidation process is performed on the semiconductor substrate 1 to form a p-type impurity. A first silicon oxide film 8 having a thickness of about 5 nm is formed on the surfaces of the well 6 and the n-type well 7.

Next, as shown in FIG. 5, a photoresist 9 is formed on the input / output circuit, and using the photoresist 9 as a mask, the first circuit of the internal circuit is treated with an aqueous solution containing hydrofluoric acid (HF).
Of silicon oxide film 8 and insulating film 4 are etched.

Next, as shown in FIG. 6, after the photoresist 9 is removed, a second thermal oxidation treatment is performed on the semiconductor substrate 1 so that the surface of the p-type well 6 and the n-type well 7 of the internal circuit is A second silicon oxide film 10a having a thickness of 4 nm is formed, and a second silicon oxide film 10b having a thickness of about 8 nm is formed on the surface of the p-type well 6 of the input / output circuit.

That is, the thin gate insulating film 1 of the internal circuit
Reference numeral 1 denotes a second silicon oxide film 10a formed by a second thermal oxidation process, and a thick gate insulating film 12 of an input / output circuit is formed by a first thermal oxidation process and a second thermal oxidation process. Second silicon oxide film 10 to be formed
b.

Next, as shown in FIG. 7, a polycrystalline silicon film into which phosphorus (P) is introduced is deposited on the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method.
Using the patterned photoresist as a mask, the polycrystalline silicon film is etched to form a gate electrode 13 composed of the polycrystalline silicon film.

Next, using the gate electrode 13 as a mask, an n-type impurity (for example, P) is introduced into the p-type well 6 to form a low-concentration n which forms part of a source region and a drain region of the n-channel MISFET. Forming the type semiconductor region 14;
Similarly, a p-type impurity (for example, boron fluoride (BF ₂ )) is introduced into the n-type well 7 using the gate electrode 13 as a mask, and a low-level impurity that forms part of the source region and the drain region of the p-channel MISFET is formed. A p-type semiconductor region 15 having a concentration is formed.

Next, the silicon oxide film deposited on the semiconductor substrate 1 by the CVD method is etched by the RIE (Reactive Ion Etching) method to form a sidewall spacer 16 on the side wall of the gate electrode 13.

Next, using the gate electrode 13 and the sidewall spacer 16 as a mask, an n-type impurity (for example, arsenic (As)) is introduced into the p-type well 6 to form a source region and a drain region of the n-channel MISFET. A high-concentration n ⁺ -type semiconductor region 17 constituting another part is formed. Similarly, the gate electrode 13 and the sidewall spacer 1
6 is used as a mask, a p-type impurity (for example, BF ₂ ) is introduced into the n-type well 7, and a high-concentration p ⁺ -type semiconductor region constituting another part of the source region and the drain region of the p-channel MISFET 18 are formed.

Next, a titanium film (not shown) having a thickness of 30 to 50 nm is deposited on the semiconductor substrate 1 by a sputtering method or a CVD method. Then, in a nitrogen atmosphere, 60
Heat treatment (first annealing) is performed at a temperature of 0 to 700 ° C. This first annealing, a high-resistance titanium silicide layer _{(TiSi x (0 <x <} 2)) n -channel type M
It is formed on the surface of the gate electrode 13 of the ISFET and the surface of the n ⁺ -type semiconductor region 17 and on the surface of the gate electrode 13 and the surface of the p ⁺ -type semiconductor region 18 of the p-channel MISFET.

Next, the unreacted titanium film is replaced with H ₂ O ₂ : NH
After removal with ₄ OH: H ₂ O solution, 800
Heat treatment (second annealing) at a temperature of ~ 900 ° C;
The high-resistance titanium silicide film is changed to a low-resistance titanium silicide film (TiSi ₂ ) 19.

After that, a silicon nitride film 20 and an interlayer insulating film 21 are sequentially deposited on the semiconductor substrate 1, and then the interlayer insulating film 21 and the silicon nitride film 20 are sequentially etched to form a contact hole 22. By etching a metal film (not shown) deposited on the film 21 to form the wiring layer 23, the CMOS shown in FIG.
The internal circuit and the input / output circuit of the logic LSI are completed.

In this embodiment, the p-type well 6 and the n-type well 7 are formed by implanting impurity ions into the semiconductor substrate 1 after removing the first silicon nitride film 2.
In order to prevent defects occurring in the semiconductor substrate 1 when implanting impurity ions, after removing the first silicon nitride film 2, a through silicon oxide film of about 10 nm is formed on the surface of the semiconductor substrate 1. Impurity ions may be implanted into the semiconductor substrate 1 through the film.

The second silicon oxide films 10a, 10a
After the formation of b, the semiconductor substrate 1 is subjected to a heat treatment in a nitrogen oxide (N ₂ O or NO) atmosphere, nitrogen is introduced into the interface between the semiconductor substrate 1 and the second silicon oxide films 10a and 10b, and hot The electron resistance may be improved.

After the gate electrode 13 is formed, an n-type impurity such as P is introduced into the polycrystalline silicon film constituting the gate electrode 13 of the n-channel MOSFET to form an n-gate. A p-type impurity, for example, boron (B) may be introduced into the polycrystalline silicon film forming the gate electrode 13 of the type MOSFET to form a p-gate, thereby forming a surface channel.

As described above, according to the present embodiment, when the first silicon oxide film 8 formed in the internal circuit is etched, the surface of the insulating film 4 embedded in the groove 3 is also etched. The insulating film 4 buried in the groove 3 is not locally thinned, and the surface of the insulating film 4 and the surface of the semiconductor substrate 1 have substantially the same height. Thus, defective shape of the insulating film 4 constituting the device isolation region is suppressed electric field concentration caused, it is possible to prevent the occurrence of kink in the I _ds -V _g characteristics of the MOSFET, MOSFET is in the OFF state Standby current is reduced, and an increase in power consumption can be suppressed.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0041]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, a MOSFET provided with a thin gate insulating film and a MOSFET provided with a thick gate insulating film are provided.
In the semiconductor integrated circuit device having a OSFET, is possible to prevent the shape defect of the insulating film of the device isolation region is suppressed electric field concentration caused kink occurs in I _ds -V _g characteristics of the MOSFET Therefore, the standby current can be reduced and the increase in power consumption can be suppressed.

[Brief description of the drawings]

FIG. 1 shows a CMOS logic LS according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a main part of a semiconductor substrate showing an internal circuit and an input / output circuit of I.

FIG. 2 is a diagram illustrating a CMOS logic LS according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing an internal circuit and an input / output circuit of I.

FIG. 3 is a diagram illustrating a CMOS logic LS according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing an internal circuit and an input / output circuit of I.

FIG. 4 is a diagram illustrating a CMOS logic LS according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing an internal circuit and an input / output circuit of I.

FIG. 5 is a diagram illustrating a CMOS logic LS according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing an internal circuit and an input / output circuit of I.

FIG. 6 is a diagram illustrating a CMOS logic LS according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing an internal circuit and an input / output circuit of I.

FIG. 7 shows a CMOS logic LS according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing an internal circuit and an input / output circuit of I.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 first silicon nitride film 3 groove 4 insulating film 5 second silicon nitride film 6 p-type well 7 n-type well 8 first silicon oxide film 9 photoresist 10a second silicon oxide film 10b second Silicon oxide film 11 thin gate insulating film 12 thick gate insulating film 13 gate electrode 14 n − type semiconductor region 15 p − type semiconductor region 16 sidewall spacer 17 n ⁺ type semiconductor region 18 p ⁺ type semiconductor region 19 titanium silicide film 20 Silicon nitride film 21 Interlayer insulating film 22 Contact hole 23 Wiring layer h Altitude difference between the surface of the semiconductor substrate of the internal circuit and the surface of the semiconductor substrate of the input / output circuit

Claims (7)

[Claims] 1. A MOSF provided with a thin gate insulating film
A semiconductor integrated circuit device having an ET and a MOSFET provided with a thick gate insulating film, wherein an element isolation region electrically insulating adjacent semiconductor elements is embedded in a groove formed in a semiconductor substrate. A semiconductor integrated circuit device comprising an insulating film, wherein a surface of the insulating film and a surface of the semiconductor substrate in a region where the thin gate insulating film is formed have substantially the same height. 2. The semiconductor integrated circuit device according to claim 1, wherein a surface of said semiconductor substrate in a region where said thin gate insulating film is formed and a surface of said semiconductor substrate in a region where said thick gate insulating film is formed. A semiconductor integrated circuit device having an altitude difference of 30 nm or less. 3. The semiconductor integrated circuit device according to claim 1, wherein nitrogen is introduced into an interface between said thin gate insulating film and said semiconductor substrate and an interface between said thick gate insulating film and said semiconductor substrate. A semiconductor integrated circuit device characterized by the above-mentioned. 4. The MOSFET according to claim 1, wherein said thin gate insulating film is provided.
And MOSFET provided with the thick gate insulating film
Are surface channel type MOSFETs or buried channel type MOSFETs, respectively. 5. A MOSF provided with a thin gate insulating film
A method for manufacturing a semiconductor integrated circuit device having an ET and a MOSFET provided with a thick gate insulating film, comprising: (a) forming a groove in an element isolation region of a semiconductor substrate and then embedding an insulating film in the groove; (B) performing a first thermal oxidation treatment on the semiconductor substrate to form a first silicon oxide film on a surface of the semiconductor substrate; and (c) a region where the thin gate insulating film is formed. Removing the first silicon oxide film, and (d) forming a second silicon oxide film on the surface of the semiconductor substrate by performing a second thermal oxidation treatment on the semiconductor substrate. A method for manufacturing a semiconductor integrated circuit device. 6. A MOSF provided with a thin gate insulating film
A method for manufacturing a semiconductor integrated circuit device having an ET and a MOSFET provided with a thick gate insulating film, comprising: (a) depositing a first silicon nitride film on a semiconductor substrate, And forming a groove in an element isolation region of the semiconductor substrate by sequentially processing the semiconductor substrate, and (b) a region where the thin gate insulating film is formed after depositing an insulating film on the semiconductor substrate. Forming a second silicon nitride film on the groove, and (c) polishing the surfaces of the second silicon nitride film and the insulating film to bury the insulating film in the groove; (d) performing a first thermal oxidation treatment on the semiconductor substrate to form a first silicon oxide film on the surface of the semiconductor substrate; and (e) forming a first silicon oxide film on a region where the thin gate insulating film is formed. Removing the first silicon oxide film; (F) said performing a second thermal oxidation treatment on the semiconductor substrate, the manufacturing method of a semiconductor integrated circuit device characterized by a step of forming a second silicon oxide film on the semiconductor substrate surface. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein said insulating film is a silicon oxide film.