JP2001085531A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor integrated circuit device which has multiple kinds of MISFETs (metal insulator semiconductor field-effect transistor) which differ in gate insulating film thickness. SOLUTION: By this manufacturing method, a silicon nitride film 7 of about 4 nm or smaller in thickness is formed on a silicon oxide film 6 formed on the top surface of a semiconductor substrate 1 and then the silicon nitride film 7 and silicon oxide film 6 in an region B where a thin gate insulating film is formed are removed in the order, by using a resist pattern 8 as a mask. Then the resist pattern 8 is removed, followed by the entire silicon nitride film 7 and the silicon oxide film 6 of about 0.2 nm or smaller in thickness are removed, and the semiconductor substrate 1 is treated by thermal oxidation to form gate insulating films which are different in thickness.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to, for example, two types of MISFETs (Metal Insulator Semiconductors) having different applied voltages.
The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device having a built-in uctor field effect transistor).

[0002]

2. Description of the Related Art CMOS (Complementary Metal Oxide)
Semiconductor) Logic LSI (LargeScale Integrated)
Circuit), SRAM (Static Random Access Memory)
) Or DRAM (Dynamic Random Access Memory)
CMO with memory LSI and memory circuit such as
In the S logic LSI, the power supply voltages of the internal circuit and the input / output circuit may be different.

For example, in a CMOS logic LSI, the speed is increased by setting the length (gate length) of the gate electrode of the MISFET of the internal circuit shorter than the gate length of the MISFET of the input / output circuit. MISF
The power supply voltage of the internal circuit is set lower than the power supply voltage of the input / output circuit in order to ensure the withstand voltage of the semiconductor region forming the source and drain of the ET. At this time, in order to secure the reliability of the gate insulating film of the MISFET of the input / output circuit having a high power supply voltage, the thickness of the gate insulating film is larger than the thickness of the gate insulating film of the MISFET of the internal circuit having a low power supply voltage. It is formed.

As a method of forming two types of gate insulating films having different thicknesses on a semiconductor substrate made of silicon, first, an element isolation region is formed on a main surface of the semiconductor substrate, and then, one layer is formed on the semiconductor substrate. A second thermal oxidation treatment is performed to form a silicon oxide film on the surface of the semiconductor substrate. Next, the region where the thick gate insulating film is formed is covered with a resist film, the silicon oxide film in the region where the thin gate insulating film is formed is removed by wet etching, and then the resist film is removed. Is subjected to a second thermal oxidation treatment. That is, the thin gate insulating film is formed by the second thermal oxidation process, and the thick gate insulating film is formed by the first and second thermal oxidation processes.

A technique for forming a thin gate insulating film and a thick gate insulating film on a semiconductor substrate is described in, for example, Japanese Patent Application Laid-Open No. 2-15374.

[0006]

However, according to the study by the present inventor, according to the method of forming two types of gate insulating films having different thicknesses, the silicon oxide in the region where the thin gate insulating film is formed is formed. When the film is removed by wet etching, the region where the thick gate insulating film is formed is covered with a resist film, so that contamination by the resist film,
It has been considered that the thin gate insulating film, the thick gate insulating film, or both of these gate insulating films are deteriorated in breakdown voltage due to some damage in the resist removing step and the subsequent cleaning step.

An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor integrated circuit device having a plurality of types of MISFETs having different thicknesses of gate insulating films.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) a method of manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of: providing a MISFET having a gate insulating film having a relatively large effective film thickness in a first active region of a semiconductor substrate; Forming a first insulating film on the semiconductor substrate when forming a MISFET including a gate insulating film having a relatively small effective film thickness; and forming a second insulating film on the first insulating film. Forming, covering the first active region with a resist pattern, and sequentially removing the second insulating film and the first insulating film in the second active region using the resist pattern as a mask. Removing the resist pattern, removing all of the second insulating film and part of the first insulating film, and forming a third insulating film on the semiconductor substrate. .

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention, comprising: a MISFET having a gate insulating film having a relatively large effective film thickness in a first active region of a semiconductor substrate;
Forming a first insulating film on the semiconductor substrate when forming a MISFET having a gate insulating film having a relatively small effective thickness in a second active region; and forming an upper layer on the first insulating film. Forming a second insulating film on the substrate, covering the first active region with a resist pattern, and using the resist pattern as a mask, forming the second insulating film and the first insulating film in the second active region. Sequentially removing,
After the resist pattern is removed, the method includes a step of performing a cleaning process on the semiconductor substrate and a step of forming a third insulating film on the semiconductor substrate.

(3) A method of manufacturing a semiconductor integrated circuit device according to the present invention, comprising: a MISFET having a gate insulating film having a relatively large effective film thickness in a first active region of a semiconductor substrate;
Forming a first insulating film on the semiconductor substrate when forming a MISFET having a gate insulating film having a relatively small effective thickness in a second active region; and forming an upper layer on the first insulating film. Forming a second insulating film on the substrate, covering the second active region with a resist pattern, and using the resist pattern as a mask, forming the second insulating film and the first insulating film in the first active region. Sequentially removing,
After the resist pattern is removed, the method includes a step of performing a cleaning process on the semiconductor substrate, and a step of selectively forming a third insulating film on the semiconductor substrate in the first active region.

(4) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a MISFET according to the above (1) or (2), wherein the first insulating film and the third insulating film are a silicon oxide film, A titanium oxide film or a tantalum oxide film, and the second insulating film is a silicon nitride film formed by a chemical vapor deposition method, a jet plasma vapor deposition method, a remote plasma nitrization method, or a thermal nitriding treatment. Things.

(5) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a MISFET according to the item (3), wherein the first insulating film is a silicon oxide film, a titanium oxide film, or a tantalum oxide film. Chemical vapor deposition, jet plasma vapor deposition, remote
The silicon nitride film is formed by a plasma nitrization method or a thermal nitridation process.

(6) The method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing a MISFET according to (1), wherein the first insulating film and the third insulating film are silicon oxide films, The insulating film is a silicon nitride film having a thickness of about 4 nm or less.

(7) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the method for manufacturing a MISFET according to the item (2), the first insulating film and the third insulating film may be silicon oxide films, and The insulating film is a silicon nitride film having a thickness of about 4 to 6 nm.

(8) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the method for manufacturing a MISFET according to the item (3), the first insulating film may be a silicon oxide film having a thickness of about 1 to 2 nm. The second insulating film is a silicon nitride film.

(9) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a MISFET according to the item (3), a fourth insulating film is further formed on the second insulating film. All or the upper part of the insulating film is removed by the cleaning process.

(10) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a MISFET according to the item (9), the fourth insulating film is a TEOS oxide film.

(11) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the same as the method for manufacturing a MISFET according to the above (3), except that the insulating film having a different electric conduction mechanism and a relatively large effective film thickness is used. An insulating film having a small effective film thickness is formed.

According to the above means (1) and (2), a resist pattern is not formed directly on the first insulating film provided in the region where the gate insulating film having a relatively large effective film thickness is formed. Since the resist pattern is formed with the second insulating film interposed, contamination from the resist film adheres to the second insulating film. Thereafter, by removing all of the second insulating film or cleaning the surface thereof, it is possible to avoid the contamination of the first insulating film by the resist film and the influence of any damage or the like in the resist removing step and the subsequent cleaning step. can do. Further, even if all of the second insulating film is removed in the pre-cleaning process in the step of forming the third insulating film, a weak spot generated in the first insulating film can be reduced by suppressing the shaving amount of the first insulating film. Can be suppressed.

Further, according to the means (3), the resist is formed on the first insulating film provided in the region where the gate insulating film having a relatively small effective film thickness is formed, with the second insulating film interposed therebetween. Since the pattern is formed, contamination from the resist film adheres to the second insulating film. After this, the second
By performing cleaning treatment on the semiconductor substrate under conditions where the insulating film is difficult to remove, contamination from the resist film can be removed without affecting the first insulating film such as damage. A second insulating film and a first insulating film are formed in a region where a gate insulating film having a relatively small effective film thickness is formed.
By using an insulating film having a higher relative dielectric constant than the third insulating film as the second insulating film, the effective film thickness can be reduced, and a plurality of types of gate insulating films having different electric conduction mechanisms can be formed. .

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) A method of manufacturing a CMOS device according to an embodiment of the present invention will be described with reference to FIGS. In the figure, Qn is an n-channel MISFET, Q
p indicates a p-channel MISFET, region A indicates a region where a thick gate insulating film is formed, and region B indicates a region where a thin gate insulating film is formed.

First, as shown in FIG.
A semiconductor substrate 1 made of a silicon single crystal of about cm is prepared, and a shallow groove 2 is formed on the main surface of the semiconductor substrate 1.
Thereafter, a thermal oxidation process is performed on the semiconductor substrate 1 to form a silicon oxide film (not shown). After further depositing the silicon oxide film 3, this is subjected to chemical mechanical polishing (ChemicalMechanical polishing).
An element isolation region is formed by polishing by a mechanical polishing (CMP) method and leaving the silicon oxide film 3 only in the shallow groove 2.

When polishing by the CMP method, various measures have been taken to prevent the active region from being polished or to prevent the surface of the silicon oxide film 3 from being lower than the surface of the active region. Although it is necessary, the description is omitted here.

Next, a p-type impurity, for example, B (boron) is ion-implanted into a region for forming the n-channel MISFET to form a p-type well 4, and the p-channel MISFET is formed.
Is formed by ion-implanting an n-type impurity, for example, P (phosphorus) into a region for forming an n-type well 5. Subsequent to this ion implantation, impurities for adjusting the threshold voltages of the n-channel MISFET and the p-channel MISFET, for example, BF ₂ (boron fluoride) are added to the channel region of the p-type well 4 and P is added to the n-type MISFET. Ion is implanted into the channel region of the well 5 to form a threshold voltage control layer (not shown).

Next, after cleaning the surface of the semiconductor substrate 1 using an aqueous solution of HF (hydrofluoric acid), the semiconductor substrate 1 is subjected to a thermal oxidation treatment as shown in FIG. A silicon oxide film 6 having a thickness of about 6 to 7 nm is formed. Next, as shown in FIG. 3, chemical vapor deposition (Chemical Vapor Deposition:
A silicon nitride film 7 having a thickness of about 4 nm or less, for example, about 1 to 2 nm is deposited by a CVD method.

Next, as shown in FIG. 4, after a resist film is applied on the semiconductor substrate 1, the resist film is patterned by exposing and developing to form a thick gate insulating film having a resist pattern 8 thereon. Area A on the semiconductor substrate 1. Next, as shown in FIG. 5, the silicon nitride film 7 and the silicon oxide film 6 are sequentially removed by dry etching using the resist pattern 8 as a mask and BHF (Buffered HF) treatment, thereby forming a thin gate insulating film. The surface of the semiconductor substrate 1 in the region B is exposed.

Next, as shown in FIG. 6, after removing the resist pattern 8, the semiconductor substrate 1 is subjected to a pre-cleaning process.

In general, as shown in FIG. 7, to remove contamination on the surface of the silicon oxide film, it is necessary to increase the shaving amount of the silicon oxide film. However, excessive cleaning creates a weak spot on the silicon oxide film. It will be crowded. However, in the first embodiment, since the surface of the silicon oxide film 6 is protected by the silicon nitride film 7, contamination by the resist film is removed by removing the silicon nitride film 7. The effect of any damage or the like can be avoided. Further, as shown in FIG. 8, when the shaved amount of the silicon oxide film is about 0.2 nm or less, the generation of weak spots is suppressed and the defect density of the silicon oxide film is reduced to about 0.01 / cm ^2. Can be suppressed.

Therefore, in the pre-cleaning process, control is performed so that all of the silicon nitride film 7 provided on the silicon oxide film 6 and the silicon oxide film 6 having a thickness of about 0.2 nm or less are removed. You. Thereby, the silicon nitride film 7
Thus, the contamination of the resist film and the influence of some damage can be avoided, and the silicon oxide film 6 with a small number of weak spots can be obtained by reducing the shaving amount of the silicon oxide film 6 to about 0.2 nm or less.

Next, as shown in FIG. 9, the semiconductor substrate 1 is subjected to a thermal oxidation treatment to form a thick gate insulating film in a region A where the silicon oxide film 6 is formed.
A silicon oxide film 9a having a thickness of about 2 to 4 nm forming a thin gate insulating film is formed in a region B where the surface of the semiconductor substrate 1 is exposed.

Next, as shown in FIG.
After depositing a polycrystalline silicon film to which an n-type impurity such as P is added by a CVD method, the polycrystalline silicon film is etched using a resist pattern as a mask to form a gate electrode composed of the polycrystalline silicon film. Form 10.

Next, the n-type well 5 is covered with a resist film,
Using the gate electrode 10 as a mask, an n-type impurity (eg, P) is introduced into the p-type well 4 to form an n-channel MISFET Q
A low-concentration n ⁻ -type semiconductor region 11a forming a part of n source and drain is formed. Similarly, the p-type well 4 is covered with a resist film, and a p-type impurity (for example, BF ₂ ) is introduced into the n-type well 5 using the gate electrode 10 as a mask.
Forming a type semiconductor region 12a ^- channel MISFETQp source, a low concentration of p constituting a part of the drain.

Next, as shown in FIG. 11, a silicon oxide film deposited on the semiconductor substrate 1 by CVD is subjected to RIE (Re
The side wall spacer 13 is formed on the side wall of the gate electrode 10 by etching by an active ion etching (active ion etching) method.

Next, the n-type well 5 is covered with a resist film,
Using the gate electrode 10 and the sidewall spacer 13 as a mask, an n-type impurity (for example, As
(Arsenic)) is introduced to form a high-concentration n ^{+ -type} semiconductor region 11b constituting another part of the source and drain of the n-channel MISFET Qn. Similarly, the p-type well 4 is covered with a resist film, and a p-type impurity (for example, BF ₂ ) is introduced into the n-type well 5 using the gate electrode 10 and the side wall spacer 13 as a mask.
A high-concentration p ^{+ -type} semiconductor region 12b constituting another part of the source and drain of Qp is formed.

Next, a low-resistance titanium silicide film 14 is formed on the surface of the gate electrode 10 of the n-channel MISFET Qn and the surface of the n ^{+ type} semiconductor region 11b, and the surface of the gate electrode 10 of the p-channel MISFET Qp and the p ⁺ It is formed on the surface of the semiconductor region 12b.

Thereafter, as shown in FIG. 12, an interlayer insulating film 15 is formed on the semiconductor substrate 1 and then the interlayer insulating film 15 is formed.
To form a contact hole 16 by etching
By etching the metal film deposited on the interlayer insulating film 15 to form the wiring layer 17, a CMOS device is completed.

In the first embodiment, the silicon nitride film 7 is formed by the CVD method. However, a jet plasma vapor deposition (JVD) method or a remote plasma nitrification (Remote
The film may be formed by a formation method capable of controlling the thickness at an atomic level, such as a plasma nitrification method, or a thermal nitridation treatment.

In the first embodiment, the thick gate insulating film and the thin gate insulating film are formed by the silicon oxide films 6, 9a, 9b formed by the thermal oxidation method, but are formed by different manufacturing methods. Other insulating films, for example, a titanium oxide film or a tantalum oxide film may be used, and the same effect is obtained.

In the first embodiment, the thickness of the silicon nitride film 7 is set to about 4 nm or less, and the silicon nitride film 7 is entirely removed in a process before forming the gate insulating film. By setting the height to about 4 to 6 nm,
By leaving a part of the silicon nitride film 7 in the region A where the thick gate insulating film is formed, a gate insulating film having a stacked structure including the silicon nitride film 7 may be formed.

As described above, according to the first embodiment, when forming two types of gate insulating films having different thicknesses, the resist pattern 8 is not directly formed on the silicon oxide film 6,
Since the silicon nitride film 7 is formed, the contamination from the resist film adheres to the silicon nitride film 7. Thereafter, by removing the silicon nitride film 7, the influence of the resist film on the silicon oxide film 6, such as contamination and any damage, can be avoided. Further, in the pre-cleaning process when forming the gate insulating film, although the entire silicon nitride film 7 is removed, the shaved amount of the silicon oxide film 6 is suppressed to about 0.2 nm or less.
Since the silicon oxide film 6 with few weak spots is obtained, the silicon oxide film 9a having a low defect density can be formed.

(Embodiment 2) A method of manufacturing a gate insulating film of a CMOS device according to another embodiment of the present invention will be described with reference to FIGS.

First, in the first embodiment, FIG.
As in the manufacturing method described with reference to FIG.
Form well 4 and n-well 5 are formed.

Next, after cleaning the surface of the semiconductor substrate 1 using an HF-based aqueous solution, as shown in FIG.
A silicon oxide film 18 having a thickness of about nm is formed. Next, as shown in FIG. 14, a silicon nitride film 19 of about 4 to 6 nm is formed on the silicon oxide film 18 by CVD.
Is deposited.

Next, as shown in FIG.
After a resist film is applied thereon, the resist film is patterned by performing exposure and development treatments to form a resist pattern 8 on the semiconductor substrate 1 in a region B where a thin gate insulating film is formed. Then, as shown in FIG.
The silicon nitride film 19 and the silicon oxide film 18 are sequentially removed by dry etching and BHF processing using the resist pattern 8 as a mask to expose the surface of the semiconductor substrate 1 in the region A where the thick gate insulating film is formed.

Next, as shown in FIG. 17, after the resist pattern 8 is removed, the semiconductor substrate 1 is subjected to a cleaning process under conditions where the silicon nitride film 19 is difficult to remove, thereby removing contamination by the resist film. At this time, the silicon nitride film 19 serves as a protective film, the silicon oxide film 18 is not removed, and the influence of the resist film on the silicon oxide film 18 such as contamination and any damage can be avoided.

Next, as shown in FIG. 18, the semiconductor substrate 1 is subjected to a thermal oxidation treatment to form a thick gate insulating film in a region A where the surface of the semiconductor substrate 1 is exposed.
A silicon oxide film 20 of about 8 nm is formed. further,
Since the surface of the silicon nitride film 19 in the region B is hardly oxidized, it has a laminated structure mainly composed of the silicon nitride film 19 and the silicon oxide film 18 and has a thickness of 2 to 4 nm in terms of the thickness of the silicon oxide film in consideration of the relative dielectric constant. A thin gate insulating film having an effective film thickness of the order is obtained.

In the second embodiment, the silicon nitride film 19 for protecting the silicon oxide film 18 is provided in the region B where the thin gate insulating film is formed. An insulating film having a high wet etching rate, for example, TEOS (Tetra Ethyl Ortho Silicon)
e; TEO formed by a plasma CVD method using Si (OC ₂ H ₅ ) ₄ ) gas and ozone (O ₃ ) gas as sources.
An S oxide film may be provided. This causes contamination on the silicon nitride film 19 constituting a part of the thin gate insulating film,
The effect of some kind of damage can be reduced.

In the second embodiment, the silicon oxide film 18 is formed by a thermal oxidation method. However, another insulating film, such as a titanium oxide film or a tantalum oxide film, formed by a different manufacturing method may be used. Well, similar effects can be obtained.

As described above, according to the second embodiment, the first to second layers provided in the region B where the thin gate insulating film is formed are formed.
Since the resist pattern 8 is formed on the silicon oxide film 18 having a thickness of about nm with the silicon nitride film 19 interposed therebetween, contamination from the resist film is prevented.
Will adhere to. Thereafter, by performing a pre-cleaning process on the semiconductor substrate under conditions where the silicon nitride film 19 is difficult to remove, contamination from the resist film can be removed without causing any damage to the silicon oxide film 18.

Further, in the region A where the thick gate insulating film is formed, the silicon oxide film 2 having a thickness of about 6 to 8 nm
0 is formed, but in a region B where a thin gate insulating film is formed, a silicon nitride film 19 having a thickness of about 4 to 6 nm and a silicon oxide film 20 having a thickness of about 1 to 2 nm are formed. And a gate insulating film having an effective film thickness of about 2 to 4 nm is formed.
Two types of gate insulating films having different electric conduction mechanisms can be formed.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the case where the present invention is applied to the method of manufacturing a CMOS device has been described.
The present invention can be applied to a method for manufacturing any semiconductor device having a plurality of types of insulating films having different thicknesses.

[0056]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, when forming a plurality of types of gate insulating films having different thicknesses, it is possible to avoid the effects of contamination by the resist film, and any damages in the resist removing step and the subsequent cleaning step. Can be prevented from deteriorating the withstand voltage and the like of the gate insulating film.
The reliability of a semiconductor integrated circuit device having a plurality of ET types can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the embodiment of the present invention;

FIG. 7 is a conceptual diagram showing the relationship between the amount of contamination, the amount of weak spot formation, and the amount of silicon oxide film shaved.

FIG. 8 is a graph showing the relationship between the defect density of the silicon oxide film and the shaving amount.

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a gate insulating film of a CMOS device according to another embodiment of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a gate insulating film of a CMOS device according to another embodiment of the present invention.

FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a gate insulating film of a CMOS device according to another embodiment of the present invention.

FIG. 16 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a gate insulating film of a CMOS device according to another embodiment of the present invention.

FIG. 17 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a gate insulating film of a CMOS device according to another embodiment of the present invention.

FIG. 18 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a gate insulating film of a CMOS device according to another embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate 2 shallow trench 3 silicon oxide film 4 p type well 5 n-type well 6 silicon oxide film 7 silicon nitride film 8 resist pattern 9a silicon oxide film 9b silicon oxide film 10 gate electrode 11a n ^- type semiconductor region 11b n ⁺ form Semiconductor region 12a p ^{− -type} semiconductor region 12b p ^{+ -type} semiconductor region 13 sidewall spacer 14 titanium silicide film 15 interlayer insulating film 16 contact hole 17 wiring layer 18 silicon oxide film 19 silicon nitride film 20 silicon oxide film A thick gate insulating film Region to be formed B Region to form thin gate insulating film Qn n-channel MISFET Qp p-channel MISFET

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Norio Suzuki 3-16-1, Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Satoshi Sakai 6--16, Shinmachi, Ome-shi, Tokyo 3 F-term in Hitachi, Ltd. Device Development Center (reference) 5F048 AA07 AC01 AC03 BA01 BB05 BB08 BB11 BB13 BB16 BD04 BE03 BF06 BG14 DA25

Claims (10)

[Claims] 1. A semiconductor wherein an insulating film having a relatively large effective film thickness is formed in a first active region of a semiconductor substrate and an insulating film having a relatively small effective film thickness is formed in a second active region. A method for manufacturing an integrated circuit device, comprising: (a) forming a first insulating film on the semiconductor substrate; and (b) forming a second insulating film on the first insulating film. (C). The first
(D) using the resist pattern as a mask, sequentially removing the second insulating film and the first insulating film in the second active region, and (e). After removing the resist pattern, removing all of the second insulating film and part of the first insulating film; and (f) forming a third insulating film on the semiconductor substrate. A method for manufacturing a semiconductor integrated circuit device, comprising: 2. A semiconductor wherein an insulating film having a relatively large effective film thickness is formed in a first active region of a semiconductor substrate and an insulating film having a relatively small effective film thickness is formed in a second active region. A method for manufacturing an integrated circuit device, comprising: (a) forming a first insulating film on the semiconductor substrate; and (b) forming a second insulating film on the first insulating film. (C). The first
(D) using the resist pattern as a mask, sequentially removing the second insulating film and the first insulating film in the second active region, and (e). After removing the resist pattern, performing a cleaning process on the semiconductor substrate; and (f) forming a third insulating film on the semiconductor substrate. Production method. 3. A semiconductor in which an insulating film having a relatively large effective film thickness is formed in a first active region of a semiconductor substrate and an insulating film having a relatively small effective film thickness is formed in a second active region. A method for manufacturing an integrated circuit device, comprising: (a) forming a first insulating film on the semiconductor substrate; and (b) forming a second insulating film on the first insulating film. (C). The second
Covering the active region with a resist pattern, and (d) sequentially removing the second insulating film and the first insulating film in the first active region using the resist pattern as a mask, and (e). After removing the resist pattern, performing a cleaning process on the semiconductor substrate; and (f) selectively forming a third insulating film on the semiconductor substrate in the first active region. A method for manufacturing a semiconductor integrated circuit device. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first insulating film and said third insulating film are a silicon oxide film, a titanium oxide film or a tantalum oxide film, and The insulating film is made by chemical vapor deposition,
Jet plasma vapor deposition, remote plasma
A method for manufacturing a semiconductor integrated circuit device, wherein the method is a silicon nitride film formed by a nitrization method or a thermal nitridation process. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein said first insulating film is a silicon oxide film, a titanium oxide film or a tantalum oxide film, and said second insulating film is a chemical vapor deposition. A method for manufacturing a semiconductor integrated circuit device, comprising: a silicon nitride film formed by a sputtering method, a jet plasma vapor deposition method, a remote plasma nitrization method, or a thermal nitriding treatment. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first insulating film and said third insulating film are silicon oxide films, and said second insulating film has a thickness of about 4 nm or less. A method for manufacturing a semiconductor integrated circuit device, wherein the method is a silicon nitride film. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein said first insulating film and said third insulating film are silicon oxide films, and said second insulating film is 6 to 7 nm.
A method for manufacturing a semiconductor integrated circuit device, comprising a silicon nitride film having a thickness of about one. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein said first insulating film is a silicon oxide film having a thickness of about 1 to 2 nm, and said second insulating film is a silicon nitride film. A method for manufacturing a semiconductor integrated circuit device. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein after forming the second insulating film in the step (b), a fourth insulating film is further formed on the second insulating film. A method of manufacturing a semiconductor integrated circuit device, wherein all or an upper portion of the fourth insulating film is removed by the cleaning process in the step (e). 10. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said insulating film has a relatively large effective film thickness and said relatively thin effective film thickness has an effective film thickness. The method for manufacturing a semiconductor integrated circuit device, wherein the insulating film is a gate insulating film of a MIS transistor.