JP2003068874A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique to improve reliability of a semiconductor integrated circuit device including two or more kinds of gate insulation films of different thicknesses. SOLUTION: A thin film 10 is formed as an upper layer of a silicon oxide film 9 formed on the surface of a semiconductor substrate 1. Thereafter, after the thin film 10 and the silicon oxide film 9 are sequentially removed from the region where a thin gate insulation film is formed using, as the mask, a photoresist pattern 11 covering the region A where a thick gate insulation film is formed, the photoresist pattern 11 is removed. Subsequently, after the cleaning process is performed to the entire part including the main surface of the semiconductor substrate 1 using the buffered fluoric acid solution to which interfacial active agent is added, the thermal oxidation process is executed to form the gate insulated films of difference thicknesses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor integrated circuit device, and more particularly, to a technique for applying a different voltage.
MISFET (Metal Insulator Semiconductor)
The present invention relates to a technology effectively applied to a semiconductor integrated circuit device having a built-in field effect transistor.

[0002]

2. Description of the Related Art CMOS (Complementary Metal Oxide)
Semiconductor) Logic LSI (Large Scale Integrated)
Circuit), SRAM (Static Random Access Memory)
In a memory LSI such as a DRAM (Dynamic Random Access Memory) and a CMOS logic LSI having a memory circuit, the power supply voltage between the internal circuit and the input / output circuit may be different. For example, CMOS logic LSI
In order to increase the speed, the length (gate length) of the gate electrode of the MISFET of the internal circuit is set shorter than the gate length of the MISFET of the input / output circuit, but the source and drain of the MISFET of the internal circuit are configured. In order to ensure the withstand voltage of the semiconductor region, the power supply voltage of the internal circuit is set lower than the power supply voltage of the input / output circuit. On this occasion,
In order to secure the reliability of the gate insulating film of the MISFET of the input / output circuit having a high power supply voltage, the thickness of the gate insulating film is set to be thicker than the thickness of the gate insulating film of the MISFET of the internal circuit having a low power supply voltage. .

As a method of forming two types of gate insulating films having different thicknesses on a semiconductor substrate made of silicon, first, an element isolation region is formed on the main surface of the semiconductor substrate, and then 1 is formed on the semiconductor substrate. A thermal oxide treatment is performed a second time to form a silicon oxide film on the surface of the semiconductor substrate. Next, the active region where the thick gate insulating film is formed is covered with a photoresist film, the silicon oxide film in the active region where the thin gate insulating film is formed is removed by wet etching, and then the photoresist film is removed. Then, a method of applying a second thermal oxidation treatment to the semiconductor substrate is adopted. That is, the thin gate insulating film is formed by the second thermal oxidation treatment, and the thick gate oxide film is formed by the first and second thermal oxidation treatments.

Here, regarding the technique for forming the above-described two types of gate insulating films having different thicknesses on a semiconductor substrate,
For example, JP-A-2-96378 and JP-A-2-96378.
It is disclosed in Japanese Patent No. 153574.

[0005]

However, the present inventors have found that the above-described method of forming two types of gate insulating films having different thicknesses has the following problems.

That is, when the silicon oxide film in the active region where the thin gate insulating film is formed is removed by wet etching, the active region where the thick gate insulating film is formed is covered with the photoresist film, so that the contamination by the photoresist film is caused. There is a problem that the thin gate insulating film, the thick gate insulating film, or the gate insulating films of both of them may be deteriorated in withstand voltage due to some damage in the resist removing step and the subsequent cleaning step.

An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor integrated circuit device having a plurality of MISFETs having different gate insulating film thicknesses.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, according to the present invention, a step of thermally oxidizing a semiconductor substrate to form a first insulating film on the surface of the semiconductor substrate and a first thin film containing silicon as a main component are formed on the first insulating film. A step of covering the first region of the semiconductor substrate with a masking pattern, and the first region of the second region of the semiconductor substrate using the masking pattern as a mask.
A step of removing the thin film and the first insulating film; a step of removing the masking pattern, a step of cleaning the semiconductor substrate with a cleaning solution containing hydrofluoric acid; and a step of thermally oxidizing the semiconductor substrate, Forming an insulating film having a first film thickness in one region and forming an insulating film having a second film thickness that is relatively thin as compared to the first film thickness in the second region,
When forming the insulating film having the first thickness, the first thin film in the first region is oxidized and becomes a part of the insulating film having the first thickness.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

The semiconductor integrated circuit device of this embodiment is, for example, a CMOS device. A method of manufacturing this CMOS device will be described with reference to FIGS. A in the figure
A region indicates a region where a thick gate insulating film is formed (first region), and a region B indicates a region where a thin gate insulating film is formed (second region).

First, as shown in FIG. 1, the specific resistance is 10Ω.
Semiconductor substrate 1 formed of single crystal silicon of about cm
And the shallow groove 2 is formed on the main surface of the semiconductor substrate 1. The depth of the shallow groove 2 is, eg, about 0.35 μm.
Then, the semiconductor substrate 1 is subjected to thermal oxidation treatment to form a silicon oxide film (not shown). After further depositing the silicon oxide film 3, this is subjected to chemical mechanical polishing (Chemical Mec
hanical Polishing (CMP) method to polish the shallow groove 2
An element isolation region (trench isolation) is formed by leaving the silicon oxide film 3 only inside. Note that C
When polishing by the MP method, various measures are required to prevent the active region from being polished and to prevent the surface of the silicon oxide film 3 from becoming lower than the surface of the active region. The description is omitted here.

Then, an impurity (for example, B (boron)) having a conductivity type of p-type is ion-implanted into a region where the n-channel type MISFET is formed to form a p-type well 4, and p
An impurity of n-type conductivity (for example, P (phosphorus)) is ion-implanted into the region where the channel-type MISFET is formed to form the n-type well 5.

Next, as shown in FIG. 2, the semiconductor substrate 1 is subjected to a thermal oxidation process or the like to form a sacrificial oxide film 6 made of, for example, a silicon oxide film on the main surface of the semiconductor substrate 1.
After forming the n-channel MISFE
Adjust the threshold voltage of the T and p channel MISFETs.

First, as shown in FIG. 3, a photoresist pattern 7A is formed on the main surface of the semiconductor substrate 1 so that the formation region of the n-channel type MISFET is exposed and the other regions are covered, and then this is formed. As a mask, for example, B
F ₂ (boron fluoride) is implanted in the channel region of the p-type well 4. Then, after removing the photoresist pattern 7A, as shown in FIG. 4, on the main surface of the semiconductor substrate 1,
A photoresist pattern 7B is formed in which the formation region of the p-channel type MISFET is exposed and the rest is covered. Then, using the photoresist pattern 7B as a mask, P, for example, is implanted into the channel region of the n-type well 5. Then, the photoresist pattern 7B is removed, and the semiconductor substrate 1 is heat-treated. This allows
As shown in FIG. 5, threshold voltage control layers 8A and 8B can be formed on the semiconductor substrate 1. The threshold voltage control layer has a thickness of, for example, about 20 nm.

Next, as shown in FIG. 6, after cleaning the surface of the semiconductor substrate 1 with an HF (hydrofluoric acid) -based aqueous solution,
The semiconductor substrate 1 is subjected to thermal oxidation treatment to form a silicon oxide film (first insulating film) 9 on the surface of the semiconductor substrate 1. Then, as shown in FIG. 7, for example, CVD (Chemical Vap
or Deposition) method on the upper layer of the silicon oxide film 9,
A thin film (first thin film) 10 made of polycrystalline silicon or amorphous silicon is deposited.

Next, as shown in FIG. 8, the region A where the thick gate insulating film is formed is covered and the region B where the thin gate insulating film is formed is exposed while being in contact with the thin film 10. Photoresist pattern (masking pattern)
11 is formed. Then, using the photoresist pattern 11 as a mask, the thin film 10 and the silicon oxide film 9 in the region B where the thin gate insulating film is formed are sequentially removed by a dry etching method or a wet etching method. The photoresist pattern 11 is formed by a normal photolithography technique. That is, the photoresist pattern 11 is patterned by applying a photoresist film and then exposing and developing the photoresist film.

Next, as shown in FIG. 9, the photoresist pattern 11 is removed by an ashing method or the like. At this time, in the lower part of the photoresist pattern 11,
Since the thin film 10 is formed on the silicon oxide film 9,
Damage to the silicon oxide film 9 can be reduced.

Then, the semiconductor substrate 1 is subjected to a cleaning treatment using, for example, NH ₃ / H ₂ O ₂ . By this cleaning process, the foreign matter mainly attached to the semiconductor substrate 1 can be removed. Then, the semiconductor substrate 1 is subjected to a cleaning process using, for example, HCl / H ₂ O ₂ . This cleaning process
The purpose is mainly to remove the metal adhering to the semiconductor substrate 1.

Then, the entire surface including the main surface of the semiconductor substrate 1 is washed with a buffered hydrofluoric acid solution to which a surfactant such as hydrocarbon is added. This can reduce or eliminate damage at the time of removing the natural oxide film and the photoresist pattern 11 formed on the main surface of the semiconductor substrate 1 in the region B where the thin gate insulating film is formed. In addition, since a surfactant is added to the buffered hydrofluoric acid solution,
Since the surface tension can be lowered, it is effective in preventing the removal residue of the pattern end.

In the present embodiment, since the silicon oxide film 9 does not come into direct contact with the photoresist pattern 11 due to the presence of the thin film 10 in the region A where the thick gate insulating film is formed, the photoresist pattern 1
The contamination of the silicon oxide film 9 by 1 can be reduced or prevented. Therefore, it is not necessary to consider the photoresist film contamination of the silicon oxide film 9 in the cleaning process. As a result, it is possible to suppress damage to the silicon oxide film 9 serving as a thick gate insulating film, and thus it is possible to secure the breakdown voltage of the thick gate insulating film that requires a high breakdown voltage.

When the cleaning process using the buffered hydrofluoric acid solution is performed, the thin film 10 made of polycrystalline silicon or amorphous silicon has a slower etching rate than the silicon oxide film. In, it becomes possible to leave the thin film 10 by a predetermined thickness. The remaining thin film 10 can be made a part of a thick gate insulating film by performing a thermal oxidation process in a later step. Therefore, the film thickness of the silicon oxide film 9 formed in the above step is compared with that in the later step. It is possible to form the gate insulating film thinner than the thick gate insulating film formed in the above step. This makes it possible to shorten the time required for the thermal oxidation process when forming the silicon oxide film 9. Further, the time required to remove the silicon oxide film 9 in the region B where the thin gate insulating film is formed can be shortened. That is, the time required for manufacturing the semiconductor integrated circuit device of this embodiment can be shortened.

If only the suppression of damage to the silicon oxide film 9 which is a part of the thick gate insulating film is considered, a silicon oxide film or a silicon nitride film formed by the CVD method may be used as the thin film 10. In this case, the thin film 10 may be removed by the cleaning process using the buffered hydrofluoric acid solution, and the upper portion of the silicon oxide film 9 may be scraped. In this case, the scraped amount is the latent amount of the silicon oxide film 9. It can be made extremely small so that the weak spots are not exposed. That is, even when a silicon oxide film or a silicon nitride film formed by the CVD method is used as the thin film 10,
It is possible to secure the withstand voltage of a thick gate insulating film that requires a high withstand voltage.

Next, as shown in FIG. 10, the semiconductor substrate 1
A silicon oxide film (second insulating film) is formed on the surface of the silicon oxide film by subjecting it to thermal oxidation treatment. As a result, the silicon oxide film 12A having a film thickness of about 8 nm (first film thickness) becomes a thick gate insulating film in the region where the silicon oxide film 9 was formed.
Then, a silicon oxide film 12B having a film thickness of about 3 to 4 nm (second film thickness) to be a thin gate insulating film can be formed in the region B where the surface of the semiconductor substrate 1 was exposed.
At this time, the thin film 10 remaining on the silicon oxide film 9 is also oxidized and can be a part of the silicon oxide film 12A. Further, after this thermal oxidation treatment, NO or N ₂
Oxidation treatment is performed in an O atmosphere to form a silicon oxide film 12
Nitrogen may be introduced into the films of A and 12B. Thereby, resistance to the hot carrier effect can be improved.

Next, as shown in FIG. 11, for example, a polycrystalline silicon film doped with an impurity (for example, P) having an n-type conductivity type is deposited by the CVD method, and then this photoresist pattern is used as a mask. The gate electrode 14 is formed by etching the crystalline silicon film.

Then, using the gate electrode 14 as a mask,
An impurity (for example, P) having an n-type conductivity is introduced into the p-type well 4 to form a low concentration n ⁻ -type semiconductor region 15 which constitutes a part of the source and drain of the n-channel type MISFET.
To form. Similarly, using the gate electrode 10 as a mask,
An impurity having a p-type conductivity type (for example, BF ₂ ) is introduced into the n-type well 5 to form a low-concentration p ⁻ -type semiconductor region 16 forming part of the source and drain of the p-channel type MISFET.

Next, as shown in FIG. 12, the semiconductor substrate 1
The silicon oxide film deposited by the CVD method on the RIE (Reac
The sidewall spacers 17 are formed on the sidewalls of the gate electrode 14 by anisotropically etching by the tive ion etching method.

Subsequently, using the gate electrode 14 and the sidewall spacers 17 as a mask, impurities (for example, As (arsenic)) having n-type conductivity are introduced into the p-type well 4, and the source and drain of the n-channel type MISFET are introduced. A high-concentration n ⁺ type semiconductor region 18 forming another part of the is formed. Similarly, using the gate electrode 14 and the sidewall spacers 13 as masks, impurities (for example, BF ₂ ) having p-type conductivity type are introduced into the n-type well 5, and other parts of the source and drain of the p-channel type MISFET are introduced. Forming a high-concentration p ⁺ type semiconductor region 19 constituting the. Through the steps up to here, the p-channel type M in the region A is formed.
An ISFET (first MISFET) Qp1 is formed, and a p-channel type MISFET (second MISFE) having characteristics different from those of the p-channel type MISFET Qp1 in the region B is formed.
T) Qp2 and n-channel type MISFET (second MI
SFET) Qn can be formed.

Next, the low-resistance titanium silicide film 14 is formed by the self-alignment method on the surface of the gate electrode 14 of the n-channel type MISFET Qn and the surface of the n ⁺ type semiconductor region 18, and the surface of the gate electrode 14 of the p-channel type MISFET Qp and p. ^It is formed on the surface of the ⁺ type semiconductor region 19. That is, with the upper surfaces of the n ⁺ type semiconductor region 18, the p ⁺ type semiconductor region 19 and the gate electrode 14 exposed, a metal film such as titanium is sputtered or deposited on the main surface of the semiconductor substrate 1. After the deposition by the method or the like, the semiconductor substrate 1 is heat-treated to form a titanium silicide film 20 at the contact portion between the metal film and the n ⁺ type semiconductor region 18, the p ⁺ type semiconductor region 19 and the gate electrode 14. Can be formed. However, the silicide film formed here is not limited to the titanium silicide film, and can be variously changed, and may be, for example, a cobalt silicide film.

After that, as shown in FIG. 13, after forming an interlayer insulating film 21 on the semiconductor substrate 1, the interlayer insulating film 2 is formed.
1 is etched to form a contact hole 22.
Then, the metal film (not shown) deposited on the interlayer insulating film 21 is etched to form the wiring layer 23, and the semiconductor integrated circuit device of the present embodiment is manufactured.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications are possible without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-mentioned embodiment, damage is caused when removing the natural oxide film or the photoresist pattern formed on the main surface of the semiconductor substrate by using the buffered hydrofluoric acid solution containing the surfactant. Although the case of reducing or eliminating is shown, a dilute hydrofluoric acid solution may be used instead of the buffered hydrofluoric acid solution containing the surfactant.

Further, the method for manufacturing a semiconductor integrated circuit device of the present invention is not limited to the CMOS device of the above-mentioned embodiment, and has various kinds of gate insulating films having different thicknesses, for example, various LSIs including DRAM. It can also be applied to.

[0035]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) When forming a plurality of types of gate insulating films having different thicknesses, it is possible to avoid contamination by the photoresist film (masking pattern) and damages in the photoresist film removing step and the subsequent cleaning step. It is possible to prevent the breakdown voltage of the gate insulating film from being deteriorated. (2) Since a plurality of types of gate insulating films having different thicknesses can be formed with good controllability, the manufacturing yield of MISFETs can be improved.

[Brief description of drawings]

FIG. 1 is a main-portion cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 3 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 2;

FIG. 4 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 3;

5 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 6 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 5;

FIG. 7 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 6;

8 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

9 is a main-portion cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 8;

FIG. 10 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 9;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 10;

12 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 12;

[Explanation of symbols]

1 semiconductor substrate 2 shallow groove 3 silicon oxide film 4 p-type well 5 n-type well 6 sacrificial oxide film 7A photoresist pattern 7B photoresist pattern 8A threshold voltage control layer 8B threshold voltage control layer 9 silicon oxide film (first 1 insulating film) 10 thin film (first thin film) 11 photoresist pattern (masking pattern) 12A silicon oxide film 12B silicon oxide film 14 gate electrode 15 n ⁻ type semiconductor region 16 p ⁻ type semiconductor region 17 side wall spacer 18 n ⁺ type Semiconductor region 19 p ⁺ type semiconductor region 20 titanium silicide film 21 interlayer insulating film 22 contact hole 23 wiring layer Qn n channel type MISFET (second MISFET) Qp1 p channel type MISFET (first MISFE
T) Qp2 p-channel type MISFET (second MISFE
T)

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Taishi Kubota             2-2-1 Yaesu, Chuo-ku, Tokyo Elp             Inside Memory Memory Co., Ltd. (72) Inventor Takuo Ohashi             2-2-1 Yaesu, Chuo-ku, Tokyo Elp             Inside Memory Memory Co., Ltd. F-term (reference) 5F048 AA07 AB01 AC01 AC03 BA01                       BB06 BB08 BB11 BB12 BB16                       BD04 BE03 BF06 BG14 DA25

Claims (4)

[Claims] 1. A step of: (a) thermally oxidizing a semiconductor substrate to form a first insulating film on a surface of the semiconductor substrate; and (b) forming a first thin film containing silicon as a main component on the first insulating film. Forming, (c) covering the first region of the semiconductor substrate with a masking pattern, (d) using the masking pattern as a mask, the first region of the second region of the semiconductor substrate
Removing the thin film and the first insulating film, (e) removing the masking pattern, and then cleaning the semiconductor substrate with a cleaning solution containing hydrofluoric acid, (f) thermally oxidizing the semiconductor substrate The first area in the first area
Forming an insulating film having a film thickness and forming an insulating film having a second film thickness, which is relatively thinner than the first film thickness, in the second region,
In the step (f), the first thin film in the first region is oxidized and becomes a part of the insulating film having the first film thickness. 2. A step of: (a) thermally oxidizing a semiconductor substrate to form a first insulating film on a surface of the semiconductor substrate; and (b) forming a first thin film containing silicon as a main component on the first insulating film. Forming, (c) covering the first region of the semiconductor substrate with a masking pattern, (d) using the masking pattern as a mask, the first region of the second region of the semiconductor substrate
Removing the thin film and the first insulating film, (e) removing the masking pattern, and then cleaning the semiconductor substrate with a cleaning solution containing hydrofluoric acid, (f) thermally oxidizing the semiconductor substrate The first area in the first area
Forming an insulating film having a film thickness and forming an insulating film having a second film thickness, which is relatively thinner than the first film thickness, in the second region,
And the cleaning solution is a buffered hydrofluoric acid solution to which a predetermined surfactant is added, and the first thin film in the first region is oxidized in the step (f), and the insulating film having the first thickness is formed. And a method for manufacturing a semiconductor integrated circuit device. 3. A step of (a) thermally oxidizing a semiconductor substrate to form a first insulating film on the surface of the semiconductor substrate, and (b) a first thin film containing silicon as a main component on the first insulating film. Forming, (c) covering the first region of the semiconductor substrate with a masking pattern, (d) using the masking pattern as a mask, the first region of the second region of the semiconductor substrate
Removing the thin film and the first insulating film, (e) removing the masking pattern, and then cleaning the semiconductor substrate with a cleaning solution containing hydrofluoric acid, (f) thermally oxidizing the semiconductor substrate The first area in the first area
Forming an insulating film having a film thickness and forming an insulating film having a second film thickness, which is relatively thinner than the first film thickness, in the second region,
And the cleaning solution is a buffered hydrofluoric acid solution to which a predetermined surfactant is added, and the first thin film in the first region is oxidized in the step (f), and the insulating film having the first thickness is formed. And the insulating film having the first thickness is the first MI.
It serves as a gate insulating film of the SFET, and the insulating film having the second film thickness has a second MISF having characteristics different from those of the first MISFET.
A method for manufacturing a semiconductor integrated circuit device, which is a gate insulating film of ET. 4. A step of (a) thermally oxidizing a semiconductor substrate to form a first insulating film on the surface of the semiconductor substrate, and (b) a first thin film containing silicon as a main component on the first insulating film. Forming, (c) covering the first region of the semiconductor substrate with a masking pattern, (d) using the masking pattern as a mask, the first region of the second region of the semiconductor substrate
Removing the thin film and the first insulating film, (e) removing the masking pattern, and then cleaning the semiconductor substrate with a cleaning solution containing hydrofluoric acid, (f) thermally oxidizing the semiconductor substrate The first area in the first area
Forming an insulating film having a film thickness and forming an insulating film having a second film thickness, which is relatively thinner than the first film thickness, in the second region,
The silicon is polycrystalline silicon or amorphous silicon, the cleaning solution is a buffered hydrofluoric acid solution to which a predetermined surfactant is added, and in the step (f), the first region of the first region is used. 1 The thin film is oxidized and the first
The insulating film having the first film thickness serves as a part of the insulating film having the film thickness, the insulating film having the first film thickness serves as a gate insulating film of the first MISFET, and the insulating film having the second film thickness has a second characteristic different from that of the first MISFET.
A method for manufacturing a semiconductor integrated circuit device, which is a gate insulating film of an ISFET.