JP2002231938A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a leakage current of a MISFET and reduce the fringe capacitance between the gate electrode and the source and drain region. SOLUTION: On a side wall of a side wall film 16s which is a silicon oxide film formed on a side wall of a gate electrode G of a MISFET, a side wall film 20s consisting of a silicon nitride film which is hard to etch by a washing liquid for washing before a silicide reaction. Thereafter, washing is conducted before silicide reaction to deposite CoSi2 21a. Consequently, the reduction of a film thickness of the side wall film 20s is made small and the distance between the source and drain region (17) and the CoSi2 21a can be secured, reducing the leakage current. Since the most part of the side wall films (16s, 20s) can be constituted of a silicon oxide film having a low relative permittivity, the fringe capacitance can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly, to a fine MISFE.
T (Metal Insulator Semiconductor Field Effect Tra
The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device having an nsistor.

[0002]

2. Description of the Related Art On the source and drain regions of the MISFET, the resistance of the source and drain regions is reduced.
A silicide layer is formed to reduce contact resistance with a plug formed on the source and drain regions.

For example, the 1999 Symposium on VLSI Technol
ogy Digest of Technical Papers 5A-1 p.49-50
A technique for forming a silicide layer using a sidewall film made of a silicon oxide film for forming source and drain regions having an LDD structure as a mask is described.

[0004]

However, before forming a silicide layer, a natural oxide film or the like on the source and drain regions is removed using hydrofluoric acid or the like. The thickness decreases. As a result, as will be described later in detail, there is a problem that the silicide layer approaches the junction between the source and drain regions, penetrates through the junction, and increases junction leakage.

On the other hand, in order to suppress the reduction in the thickness of the sidewall film, a method of forming the sidewall film using a silicon nitride film has been studied. For the sidewall film made of silicon nitride film, see 2000 Symposium on VLSI T
This is described in echnology Digest of Technical Papers T15-1.

However, since the relative permittivity of the silicon nitride film is about twice that of the silicon oxide film, when the silicon nitride film is used for the sidewall film, the fringe capacitance between the gate electrode and the source and drain regions increases. As a result, the element performance deteriorates. In particular, since the phase between the gate electrode and the drain is electrically opposite to each other, if the capacitance between the gate electrode and the drain increases, the signal transmission speed decreases and the switching characteristics deteriorate.

An object of the present invention is to secure the operation speed of a semiconductor integrated circuit device and reduce product defects.

Another object of the present invention is to reduce current consumption of a semiconductor integrated circuit device.

The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises: (a) forming a gate insulating film on a silicon substrate; and (b) forming a conductive film on the gate insulating film. Forming a gate electrode by patterning, (c) depositing a silicon oxide film on a silicon substrate including the gate electrode, and (d) anisotropically etching the silicon oxide film. (E) depositing a silicon nitride film on the silicon substrate, the first sidewall film, and the gate electrode; and (f) forming a first sidewall film on the sidewall of the gate electrode. Forming a second sidewall film on the side wall of the second sidewall film by anisotropically etching the silicon nitride film; (g)
Forming source and drain regions by injecting impurities into the silicon substrate using the second sidewall film as a mask; and (h) cleaning the surfaces of the source and drain regions using a hydrofluoric acid-based cleaning solution. The process of
(I) depositing a metal film on the source / drain region; and (j) causing a silicidation reaction using the second sidewall film as a mask, thereby forming the source / drain region and the metal film. Forming a metal silicide layer at a contact portion with the metal film, and (k) removing the unreacted metal film.

According to such a means, the thickness of the second sidewall film can be prevented from being reduced by a hydrofluoric acid-based cleaning solution, the distance between the source / drain region and the metal silicide layer can be secured, and the leakage current can be reduced. Can be kept low. Further, since a part of the first and second sidewall films can be occupied by the silicon oxide film having a low dielectric constant, the fringe capacitance between the gate electrode and the source / drain regions can be reduced.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, after forming a first sidewall film made of a silicon oxide film, source and drain regions are formed using the first sidewall film as a mask. Then, a second sidewall film made of a silicon nitride film is formed on a side wall of the first sidewall film, and a silicide layer is formed using the second sidewall film as a mask.

According to such a means, the thickness of the second sidewall film can be prevented from being reduced by the hydrofluoric acid-based cleaning solution, and the distance, source and drain corresponding to the thickness of the second sidewall film can be prevented. The region and the metal silicide layer can be separated from each other, and the leakage current can be suppressed low. Further, since a part of the first and second sidewall films can be occupied by the silicon oxide film having a low dielectric constant, the fringe capacitance between the gate electrode and the source / drain regions can be reduced.

(3) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, after forming a first sidewall film made of a first silicon oxide film, a source and a drain are formed using the first sidewall film as a mask. Forming a region and forming a second silicon oxide film on the side wall of the first side wall film;
Is formed, and a silicide layer is formed using the second sidewall film as a mask.

According to such means, the distance corresponding to the thickness of the second sidewall film, the source and drain regions and the metal silicide layer can be separated, and the leak current can be suppressed low. Further, since the entire first and second sidewall films can be occupied by the silicon oxide film having a low dielectric constant, the fringe capacitance between the gate electrode and the source / drain regions can be reduced.

(4) The semiconductor integrated circuit device of the present invention
(A) a gate electrode formed on a silicon substrate via a gate insulating film, (b) source and drain regions formed in the silicon substrate on both sides of the gate electrode, and (c) side walls of the gate electrode. A first sidewall film formed of the first insulating film formed; and (d) a second sidewall film formed on the side wall of the first sidewall film and formed of the second insulating film.
(E) a metal silicide layer formed on the source and drain regions using the second sidewall film as a mask, and (f) the first insulating film comprises The dielectric constant is lower than that of the second insulating film.

(5) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a gate electrode formed on a silicon substrate via a gate insulating film; and (b) a gate electrode formed on a side wall of the gate electrode. A first sidewall film made of one silicon oxide film; (c) a source / drain region formed using the first sidewall film as a mask; and (d) a side wall of the first sidewall film. (E) a second sidewall film formed and made of a second silicon oxide film;
A metal silicide layer formed on the source and drain regions using the second sidewall film as a mask.

According to such a means, since the source and drain regions and the metal silicide layer are separated from each other, the leak current can be suppressed low, and a part of the first and second sidewall films can be suppressed. Alternatively, since the whole can be occupied by the silicon oxide film having a low dielectric constant, the fringe capacitance between the gate electrode and the source and drain regions can be reduced.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) A method of manufacturing a semiconductor integrated circuit device according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG.
An element isolation 2 is formed therein. This element isolation 2 is formed as follows. For example, an element isolation groove having a depth of about 250 nm is formed by etching a silicon substrate 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm.

Thereafter, the silicon substrate 1 is thermally oxidized at about 1000 ° C. to form a thin silicon oxide film (not shown) having a thickness of about 10 nm on the inner wall of the groove. The silicon oxide film is formed to recover the damage of the dry etching generated on the inner wall of the groove and to reduce the interface state between the silicon oxide film 5 and the silicon substrate 1 embedded in the groove in the next step. I do.

Next, a film thickness of 450 is formed on the silicon substrate 1 including the inside of the groove by CVD (Chemical Vapor deposition).
A silicon oxide film 5 of about 500 nm is deposited, and the silicon oxide film 5 above the groove is polished by a chemical mechanical polishing (CMP) method to flatten the surface.

Next, a p-type impurity (boron) and an n-type impurity (for example, phosphorus) are ion-implanted into the silicon substrate 1, and then the impurities are diffused by a heat treatment at about 1000 ° C., so that the p-type impurity is added to the silicon substrate 1. A well 3 and an n-type well (not shown) are formed.

Next, an n-channel MISFET is formed on the main surface of the p-type well 3 of the silicon substrate 1.

First, as shown in FIG. 2, after the surface of the silicon substrate 1 (p-type well 3) is wet-cleaned using a hydrofluoric acid-based cleaning solution, the p-type well 3 is thermally oxidized at about 800.degree.
A clean gate oxide film 6 (gate insulating film) is formed on the surface of the substrate.

Next, a film thickness of 250 nm is formed on the gate oxide film.
A polycrystalline silicon film 9 is deposited by the CVD method. Next, the gate electrode G is formed by dry-etching the polycrystalline silicon film 9 using a photoresist film (not shown) as a mask.

Next, as shown in FIG. 3, a thin oxide film (hereinafter, referred to as a light oxide film) 11 of about 2 nm is formed on the side wall of the gate electrode G (polycrystalline silicon film 9) and the silicon substrate 1 by light oxidation. Form. This light oxide film 1
1 denotes a gate oxide film 6 when the gate electrode G is etched.
It is formed to repair a defect generated at the end of the.

Next, an n-type impurity (arsenic) is applied to both sides of the gate electrode G on the p-type well 3 with an energy of 10 KeV.
After injecting about 1.0 × 10 ¹⁵ / cm ² , at 950 ° C.,
Heat treatment is performed for one second to form an n ⁻ type semiconductor region 13.

Next, as shown in FIG. 4, LP-CVD (Low Pressure-Chemical Vapor D)
silicon oxide film 1 with a thickness of about 100 nm by the eposition method
6 is deposited and anisotropically etched to form a sidewall film 16s (first sidewall film) on the side wall of the gate electrode G. This sidewall film 1
The film thickness of 6 s is about 60 nm. Here, the thickness of the sidewall film refers to a thickness in a gate length direction below the sidewall film.

Subsequently, as shown in FIG. 5, on the silicon substrate 1, the side wall film 16s and the gate electrode G,
A silicon nitride film 20 having a thickness of about 15 nm is deposited by the LP-CVD method, and is etched anisotropically to form a sidewall film 20s on the sidewall of the gate electrode G (sidewall film 16s). The thickness of the sidewall film 20s is about 7 nm.

Then, using the side wall film 20s as a mask, an n-type impurity (arsenic) is implanted into the p-type well 3 at an energy of 50 KeV at about 4.0 × 10 ¹⁵ / cm ² .
By performing a heat treatment at 950 ° C. for one minute, an n ⁺ type semiconductor region 17 (source and drain regions) is formed.
At this time, the polycrystalline silicon forming the gate electrode 9G becomes n ⁺ -type.

Next, the surface of the silicon substrate 1 (n ⁺ type semiconductor region 17) and the natural oxide film on the surface of the gate electrode G are removed by cleaning the surface of the silicon substrate 1 using a hydrofluoric acid-based cleaning solution ( Cleaning before silicidation).

Next, as shown in FIG. 6, a Co film 21 having a thickness of about 15 nm is deposited by a sputtering method, and is subjected to a heat treatment at 500 ° C. for 1 minute in a nitrogen atmosphere to thereby form the silicon substrate 1 (n ⁺ type semiconductor region). 17) A silicidation reaction (generation of CoSi) is caused at the contact portion between the Co film 21 and the contact portion between the gate electrode G and the Co film 21.

Next, the unreacted Co film is etched with a mixed solution of NH ₄ OH and H ₂ O ₂ . In this state, the layer remaining on the silicon substrate 1 (the n ⁺ type semiconductor region 17) and the gate electrode G is a CoSi layer.
Subsequently, the CoSi layer is converted into a low-resistance CoSi ₂ layer 21a by performing a heat treatment at 800 ° C. for 30 seconds in a nitrogen atmosphere (FIG. 7).

As described above, in this embodiment, since the sidewall film 20s made of the silicon nitride film is formed on the side wall of the sidewall film 16s, the pre-cleaning is performed, and the silicidation reaction is performed. Between the drain region (n ⁺ type semiconductor region 17) and the CoSi ₂ layer 21a.

That is, when only the side wall film 16s is used, as shown in FIG. 8, the thickness of the side wall film is reduced by the cleaning before silicidation. This is because the sidewall film 16s is made of a silicon oxide film and is etched by a hydrofluoric acid-based cleaning solution for removing the natural oxide film on the silicon substrate 1.
As a result, the CoSi ₂ layer 21a comes close to the junction surface between the source and drain regions (n ⁺ type semiconductor region 17) (arrow portion in the figure), and a leak current occurs at such a location.

FIG. 9 is a diagram showing the relationship between the junction leakage current and its frequency. When the sidewall film is composed of a silicon oxide film, as shown in the graph (a ₁ : ○),
The variation in junction leak at the end of the gate electrode is large. On the other hand. When the sidewall film is composed of the silicon nitride film and the silicon oxide film, as shown in the graph (b ₁ : ●), it is possible to reduce the variation of the junction leak at the end of the gate electrode, and to obtain the junction leak current value [A / Length] could also be reduced. Also, graphs (a ₂ : △), (b ₂ :
▲) indicates the junction leak [A / area] at the gate flat portion. Also in this case, when the sidewall film was formed of the silicon nitride film and the silicon oxide film, as shown in the graph (b ₂ ), the variation in the junction leak could be reduced.

Further, as shown in FIG. 10, when the side wall film is formed of a silicon nitride film (116s), the silicon nitride film is hard to be etched by a hydrofluoric acid-based cleaning solution. Source and drain regions (n ⁺ type semiconductor region 1
7) and the CoSi ₂ layer 21a can be secured.

However, while the relative permittivity of the silicon oxide film is about 3.9, the relative permittivity of the silicon nitride film is about 7.5, which is almost double. Therefore, when a silicon nitride film is used for the sidewall film, the fringe capacitance (C) between the gate electrode and the source / drain region is reduced.
f) increases and the signal delay time increases.

The delay time will be described below based on simulation data.

FIG. 11 shows the fringe capacitance (C
It is a figure which shows the relationship between f) and delay time. When the side wall film is made of a silicon nitride film, as shown at point (a), Cf is about 0.15 [fF / μm] and the delay time is about 11.8 [ps / stage]. On the other hand, when the side wall film is composed of the silicon nitride film and the silicon oxide film, the Cf is about 0.
11 [fF / μm], delay time is about 10.8 [ps / s]
stage], and both Cf and delay time could be reduced. When the sidewall film is formed of a silicon oxide film, Cf is about 0.09 [fF / μ
m], and the delay time was about 10.5 [ps / stage] (point (c)).

FIG. 12 shows the MISF constituting the inverter.
FIG. 7 is a diagram illustrating a relationship between a reciprocal of a saturation current of ET and a delay time. Note that the reciprocal of the saturation current of the MISFET constituting the inverter is the sum of the reciprocal of the saturation current (Idsatn) of the n-channel MISFET and the reciprocal of the saturation current (Idsattp) of the p-channel MISFET (Idsatn ⁻¹ + Idsatp ^{−). 1} ), hereafter abbreviated as 1 / Idsat. When the sidewall film is composed of a silicon nitride film, 1 / Idsat is about 4.0 to 4.3 [× 10 ⁻³ μm, as shown in the graph (a).
m / μA] and the delay time is about 15 [ps / stag].
e] In contrast, when the sidewall film is composed of the silicon nitride film and the silicon oxide film, 1 / Idsat is about 3.5 to 3.6 as shown in the graph (b).
[× 10 ^-3 μm / μA], delay time is about 11 [ps]
/ Stage], and both 1 / Idsat and delay time could be reduced. The delay time is 1 / Id
Since it is proportional to sat, the relationship between the delay time for the sidewall film and 1 / Idsat is shown by the solid line in FIG. Therefore, the same 1 / Idsa for these solid lines
The difference in delay time with respect to t will indicate the effect of fringe capacitance.

As described above, according to the present embodiment, the fringe capacitance between the gate electrode and the source and drain regions can be reduced, and the delay time can be reduced. As a result, the speed of operation of a circuit using such a MISFET can be increased.

(Embodiment 2) A method of manufacturing a semiconductor integrated circuit device according to the present embodiment will be described with reference to FIGS. The steps up to the step of forming the sidewall film 16s described with reference to FIGS. 1 to 4 are the same as those in the first embodiment, and a description thereof will be omitted.

First, the silicon substrate 1 in which the sidewall film 16s is formed on the side wall of the gate electrode G shown in FIG. 4 described in the first embodiment is prepared. Next, as shown in FIG. 13, an n-type impurity (arsenic) is implanted into the p-type well 3 at a dose of about 4.0 × 10 ¹⁵ / cm ² at an energy of 50 KeV using the sidewall film 16s as a mask.
Then, an n ⁺ type semiconductor region 17 (source and drain regions) is formed by performing a heat treatment for one minute.

Next, as shown in FIG. 14, the silicon substrate 1 (n ⁺ type semiconductor region 17), the side wall film 16
A silicon nitride film 20 having a thickness of about 15 nm is deposited on the gate electrode G (sidewall film 16s) by LP-CVD on the gate electrode G (sidewall film 16s). 20 s are formed. The thickness of the sidewall film 20s is 7 nm.
It is about.

Next, the surface of the silicon substrate 1 (the n ⁺ type semiconductor region 17) and the natural oxide film on the surface of the gate electrode G are removed by cleaning the surface of the silicon substrate 1 using a hydrofluoric acid-based cleaning solution (FIG. 4B). Cleaning before silicidation).

Next, a Co film 21 having a thickness of about 15 nm is deposited by a sputtering method, and is subjected to a heat treatment at 500 ° C. for 1 minute in a nitrogen atmosphere, so that the silicon substrate 1 (the n ⁺ type semiconductor region 17) and the Co film 21 are formed. And a contact portion between the gate electrode G and the Co film 21 causes a silicidation reaction (generation of CoSi).

Next, the unreacted Co film is etched with a mixed solution of NH ₄ OH and H ₂ O ₂ . In this state, the layer remaining on the silicon substrate 1 (the n ⁺ type semiconductor region 17) and the gate electrode G is a CoSi layer.
Subsequently, the CoSi layer is converted into a low-resistance CoSi ₂ layer 21a by performing a heat treatment at 800 ° C. for 30 seconds in a nitrogen atmosphere (FIG. 15).

As described above, in the present embodiment, after the source and drain regions (the n ⁺ -type semiconductor regions 17) are formed using the side wall film 16s as a mask, the side wall film 20s on the side wall of the side wall film 16s is removed. Since the silicidation reaction is performed on the mask, it is possible to secure a space between the source / drain region (n ⁺ type semiconductor region 17) and the CoSi ₂ layer 21a. Also, the side wall film 2
Since the formation of the 0s of a silicon nitride film can reduce the film reduction of the side wall film 20s by silicidation before washing, as described in the first embodiment, the source, the drain region (n ⁺ -type semiconductor region 17) CoSi _The gap between the first and _second layers 21a can be secured, and the leak current can be reduced.

Further, the side wall film (16s, 20
s), most of it is constituted by the sidewall film 16s made of a silicon oxide film, so that the fringe capacitance between the gate electrode and the source / drain region can be reduced as described in the first embodiment. ,Also,
Delay time can be reduced. As a result, the speed of operation of a circuit using such a MISFET can be increased.

(Embodiment 3) A method of manufacturing a semiconductor integrated circuit device according to the present embodiment will be described with reference to FIGS. The steps up to the step of forming the sidewall film 16s described with reference to FIGS. 1 to 4 are the same as those in the first embodiment, and a description thereof will be omitted.

First, the silicon substrate 1 having the side wall film 16s formed on the side wall of the gate electrode G shown in FIG. 4 described in the first embodiment is prepared. Next, as shown in FIG. 16, n-type impurities (arsenic) are implanted into the p-type well 3 at an energy of 50 KeV at a dose of about 4.0 × 10 ¹⁵ / cm ^{2 using the} sidewall film 16 s as a mask.
Then, an n ⁺ type semiconductor region 17 (source and drain regions) is formed by performing a heat treatment for one minute.

Next, as shown in FIG. 17, the silicon substrate 1 (n ⁺ type semiconductor region 17), the side wall film 16
A silicon oxide film 220 having a thickness of about 50 nm is deposited on the gate electrode G (sidewall film 16s) by an LP-CVD method and is etched anisotropically. 220s
To form The thickness of the sidewall film 220s is
It is about 30 nm.

Next, the surface of the silicon substrate 1 (the n ⁺ -type semiconductor region 17) and the natural oxide film on the surface of the gate electrode G are removed by cleaning the surface of the silicon substrate 1 using a hydrofluoric acid-based cleaning solution (see FIG. 4). Cleaning before silicidation). During this cleaning, as shown in FIG.
0s is etched, and the side wall film 220 is etched.
The thickness of s is about 15 nm.

Then, a Co film 21 having a thickness of about 15 nm is deposited by a sputtering method, and is subjected to a heat treatment at 500 ° C. for 1 minute in a nitrogen atmosphere, so that the silicon substrate 1 (n ⁺ type semiconductor region 17) and the Co film 21 are formed. And a contact portion between the gate electrode G and the Co film 21 causes a silicidation reaction (generation of CoSi).

Next, the unreacted Co film is etched with a mixed solution of NH ₄ OH and H ₂ O ₂ . In this state, the layer remaining on the silicon substrate 1 (the n ⁺ type semiconductor region 17) and the gate electrode G is a CoSi layer.
Subsequently, as shown in FIG.
By applying a heat treatment for 30 seconds at
It is converted to a low-resistance CoSi ₂ layer 21a.

As described above, in the present embodiment, after the source and drain regions (the n ⁺ type semiconductor regions 17) are formed using the side wall film 16s as a mask, the side wall film 220s on the side wall of the side wall film 16s is formed. Since the silicidation reaction is performed on the mask, it is possible to secure a space between the source / drain region (n ⁺ type semiconductor region 17) and the CoSi ₂ layer 21a. Also, in consideration of the film reduction due to the cleaning before silicidation of the sidewall film 220s made of the silicon oxide film, the desired thickness is obtained after the cleaning.
Since the sidewall film 220s is formed thick in advance, a space between the source / drain region (the n ⁺ type semiconductor region 17) and the CoSi ₂ layer 21a can be ensured, and a leak current can be reduced.

The side wall film (16s, 220
s) Since the whole is made of a silicon oxide film having a low relative dielectric constant, the fringe capacitance between the gate electrode and the source / drain region can be reduced, and the delay time can be reduced (see FIG. 11, point). (C)). As a result, the speed of operation of a circuit using such a MISFET can be increased.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,
In particular, in the above embodiment, the n-channel MIS
FET has been described as an example, but p-channel type MISFET
It is also possible to apply the present invention to the above. Further, in the above embodiment, the CoSi ₂ layer 21 is formed by using a Co film.
Although a is formed, a metal silicide layer (TiSi layer or the like) may be formed using another metal film (Ti film or the like).

[0063]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

The distance between the source and drain regions of the MISFET and the metal silicide layer formed thereon can be ensured, and the leakage current can be kept low. Also, MI
Fringe capacitance between the gate electrode of the SFET and the source and drain regions can be reduced.

As a result, the current consumption of the semiconductor integrated circuit device can be reduced, the operating speed can be secured, and the product yield can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a silicon substrate showing a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the silicon substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of the silicon substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the silicon substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the silicon substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of the silicon substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the silicon substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 8 is a diagram for explaining an effect of the present invention.

FIG. 9 is a diagram for explaining the effect of the present invention.

FIG. 10 is a diagram for explaining the effect of the present invention.

FIG. 11 is a diagram for explaining an effect of the present invention.

FIG. 12 is a diagram for explaining an effect of the present invention.

FIG. 13 is a fragmentary cross-sectional view of the silicon substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the silicon substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the silicon substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the silicon substrate showing the method for manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the silicon substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the silicon substrate showing the method for manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the silicon substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 silicon substrate 2 element isolation 3 p-type well 5 silicon oxide film 6 gate oxide film 9 polycrystalline silicon film G gate electrode 11 light oxide film 13 n ^- type semiconductor region 16 silicon oxide film 16s sidewall film 17 n ⁺ type semiconductor region Reference Signs List 20 silicon nitride film 20 s sidewall film 116 s sidewall film 220 silicon oxide film 220 s sidewall film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tomohiro Saito 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Yohei Yanagita 6--16 Shinmachi, Ome-shi, Tokyo 3 F-term in Hitachi, Ltd. Device Development Center (Reference) 4M104 AA01 BB01 BB20 BB25 CC01 CC05 DD04 DD23 DD37 DD43 DD55 DD64 DD65 DD78 DD84 DD89 EE09 EE12 EE14 EE17 FF14 GG08 HH16 HH18 5F040 DA01 DA02 DA11 EC03 EC02 EC04 EC02 EK05 FA05 FA07 FA10 FB02 FB04 FC10 FC19 FC21 5F048 AC03 BA01 BB05 BB08 BB12 BC06 BE03 BF06 BG01 BG13 DA25

Claims (5)

[Claims] (A) forming a gate insulating film on a silicon substrate; and (b) forming a conductive film on the gate insulating film and patterning to form a gate electrode. (C) depositing a silicon oxide film on a silicon substrate including on the gate electrode; and (d) anisotropically etching the silicon oxide film to form first sidewalls on sidewalls of the gate electrode. Forming a film; (e) depositing a silicon nitride film on the silicon substrate, the first sidewall film and the gate electrode; and (f) anisotropically etching the silicon nitride film. Forming a second sidewall film on the side wall of the first sidewall film, and (g) forming a second sidewall film on the side wall of the silicon substrate by using the second sidewall film as a mask. A step of forming source and drain regions by injecting a pure substance; (h) a step of cleaning the surface of the source and drain regions using a hydrofluoric acid-based cleaning solution; and (i) a step of cleaning the source and drain regions. Depositing a metal film; and (j) forming a metal silicide layer at a contact portion between the source and drain regions and the metal film by causing a silicidation reaction using the second sidewall film as a mask. And (k) a step of removing the unreacted metal film. (A) forming a gate insulating film on a silicon substrate; and (b) forming a conductive film on the gate insulating film and patterning to form a gate electrode. (C) depositing a silicon oxide film on a silicon substrate including on the gate electrode; and (d) anisotropically etching the silicon oxide film to form first sidewalls on sidewalls of the gate electrode. Forming a film; (e) forming source and drain regions by implanting impurities into the silicon substrate using the first sidewall film as a mask; (f) forming the source and drain regions; Depositing a silicon nitride film on the first sidewall film and the gate electrode; and (g) etching the silicon nitride film anisotropically. Forming a second sidewall film on the side wall of the first sidewall film; (h) cleaning the surface of the source and drain regions using a hydrofluoric acid-based cleaning solution; Depositing a metal film on the drain region; and A method for manufacturing a semiconductor integrated circuit device, comprising: a step of forming a silicide layer; and (k) a step of removing the unreacted metal film. (A) forming a gate insulating film on a silicon substrate; and (b) forming a conductive film on the gate insulating film and patterning to form a gate electrode. (C) depositing a first silicon oxide film on a silicon substrate including on the gate electrode; and (d) anisotropically etching the first silicon oxide film to form sidewalls of the gate electrode. (E) implanting impurities into the silicon substrate using the first sidewall film as a mask to form source and drain regions; and (f) forming a first sidewall film. Depositing a second silicon oxide film on the source and drain regions, the first sidewall film, and the gate electrode; and (g) etching the second silicon oxide film anisotropically. (H) cleaning the surface of the source and drain regions using a hydrofluoric acid-based cleaning solution; (i) depositing a metal film on the source and drain regions; and (j) causing a silicidation reaction using the second sidewall film as a mask, thereby forming Forming a metal silicide layer at the contact portion of (a); and (k) removing the unreacted metal film. (A) a gate electrode formed on a silicon substrate via a gate insulating film; (b) source and drain regions formed in the silicon substrate on both sides of the gate electrode; A first sidewall film formed of a first insulating film formed on a sidewall of the gate electrode; and (d) formed on a sidewall of the first sidewall film;
(E) a metal silicide layer formed on the source and drain regions using the second sidewall film as a mask;
(F) a semiconductor integrated circuit device, wherein the first insulating film has a lower dielectric constant than the second insulating film. 5. A (a) gate electrode formed on a silicon substrate via a gate insulating film; and (b) a first sidewall film made of a first silicon oxide film formed on a side wall of the gate electrode. (C) source and drain regions formed using the first sidewall film as a mask; and (d) formed on sidewalls of the first sidewall film.
A second sidewall film made of a second silicon oxide film; and (e) a metal silicide layer formed on the source and drain regions using the second sidewall film as a mask;
A semiconductor integrated circuit device comprising: