JPH11330473A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique which is capable of materializing the high- speed operation of a MISFET made on an SOI board, and prevent the operational failures of the MISFET. SOLUTION: The depletion layer of an n<+> -type semiconductor region 6 and the depletion layer of a p<+> -type semiconductor region 14 are in zero bias contact with an embedded insulating film 2 at all times, by providing this device with a film silicon layer 3 where impurities in low concentration of about 10<16> cm<-3> are implanted between an n<+> -type semiconductor region 6 and an embedded insulating film 2 and between a p<+> -type semiconductor region 14 and the embedded insulating film 2, so that the operation speed of a MISFET can be raised by suppressing the parasitic capacitance low. At the same time, it becomes possible to made the film silicon layer 3 thickness large, and the film silicon layer 3 is provided under an insulating film 4 for element isolation, so that the potential of the film silicon layer 3 can be fixed, and the operation failure of the MISFET caused by potential ripples can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to an SOI (Silicon) device.
On Insulator) Complementary MOSFET formed on substrate
(Complementary Metal Oxide Semiconductor Field Eff
ect Transistor (CMOSFET)).

[0002]

2. Description of the Related Art A MISFET (Metal Insulato) formed on a thin silicon layer of about 0.1 to 0.3 .mu.m on an SOI substrate.
Since the bottom surface of the semiconductor region constituting the source and the drain can be insulated by the buried insulating film, the parasitic capacitance of the r Semiconductor FET can be smaller than that of the MISFET formed on the bulk substrate.

Furthermore, by forming a thick isolation insulating film for electrically isolating adjacent MISFETs on the surface of a thin silicon layer, it is possible to suppress a latch-up phenomenon or a leak phenomenon between adjacent MISFETs. it can. That is, by completely surrounding the active region of the MISFET with the insulating film, it is possible to reduce the parasitic capacitance and suppress the parasitic transistor effect.

However, when the MISFET formed in the active region completely surrounded by the insulating film is operated, the MISFE
There is a problem that minority carriers generated in the T channel region accumulate without being diffused and the potential of the thin film silicon layer fluctuates.

Therefore, in order to diffuse the generated minority carriers and further fix the potential of the thin film silicon layer,
A MISFET structure in which an element isolation insulating film constituting an element isolation region does not contact a buried insulating film has been studied.

MIS having the above structure formed on an SOI substrate
For FETs, for example, IEE
IEEE Symposium on VLSI Technology, Digest
of Technical Papers. PP.92 to PP.93, 1996).

[0007]

However, the present inventor has found the following problems in developing a MISFET formed on a thin silicon layer constituting an SOI substrate.

That is, as the speed and integration of the semiconductor integrated circuit device increase, the MIS formed on the SOI substrate
The FET is miniaturized, and the semiconductor region forming the source and drain of the MISFET is also formed shallowly. However, when the semiconductor regions constituting the source and the drain are made shallow, M
In order to keep the parasitic capacitance of the ISFET small, it is necessary to reduce the thickness of the thin silicon layer.

On the other hand, in order to fix the potential of the thin film silicon layer, it is necessary to provide the thin film silicon layer below the element isolation region. Therefore, when the thickness of the thin film silicon layer is reduced, the insulating film for element isolation is required. Must be made thinner. However, the semiconductor regions constituting the source and drain are usually formed by introducing impurity ions into the thin silicon layer by ion implantation. Leaks into the thin silicon layer below the element isolation insulating film.

An object of the present invention is to provide a technique capable of realizing a high-speed operation of a MISFET formed on an SOI substrate and preventing a malfunction.

Another object of the present invention is to provide a technique capable of realizing miniaturization of a MISFET formed on an SOI substrate.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In the semiconductor integrated circuit device of the present invention, the MISFE is formed on the thin-film silicon layer of the SOI substrate having the thin-film silicon layer formed on the supporting substrate via the buried insulating film.
T is formed, and a semiconductor region forming a source and a drain of the MISFET is not in contact with the buried insulating film, and a distance between the semiconductor region forming the source and the drain and the buried insulating film is about 0.1 μm or more. And a concentration of an impurity introduced into the thin film silicon layer between the semiconductor region forming the source and the drain and the buried insulating film and having a conductivity type opposite to a channel conductivity type is about 10 ¹⁷ c
The concentration of the impurity introduced into the thin film silicon layer below the gate electrode is set to about 10 ¹⁸ cm ⁻³ or less and m ⁻³ or less.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein
First, after a gate insulating film and a gate electrode are sequentially formed on a thin silicon layer of an SOI substrate, a sidewall spacer formed of an insulating film is formed on a side wall of the gate electrode. Next, a first impurity ion having a conductivity type opposite to the conductivity type of the channel is introduced into the thin film silicon layer below the gate electrode so that the impurity concentration becomes maximum,
Under the semiconductor region constituting the drain, the impurity is implanted into the SOI substrate so that the impurity concentration becomes maximum in the buried insulating film, and then second impurity ions of the same conductivity type as the channel conductivity type are injected into the SOI substrate. By implanting, a semiconductor region constituting the source and the drain is formed on the surface of the thin-film silicon layer.

According to the above-described means, even if a thin film silicon layer is provided between the semiconductor region constituting the source and drain and the buried insulating film, the concentration of the impurity introduced into this thin film silicon layer is about 10 ¹⁷ cm. Since it is as low as ⁻³ or less, the depletion layer of the semiconductor region constituting the source and the drain is always in contact with the buried insulating film at zero bias, the parasitic capacitance is suppressed to a low level, and the MISFET can operate at high speed. Therefore, it is possible to increase the thickness of the thin silicon layer, which is the active layer of the SOI substrate, and the potential of the thin silicon layer can be fixed since the thin silicon layer is provided between the isolation insulating film and the buried insulating film. MI due to potential fluctuation
The operation failure of the SFET can be prevented.

Further, since a high concentration impurity of about 10 ¹⁸ cm ^-3 or more is introduced into the thin film silicon layer below the gate electrode, the short channel effect is suppressed, and the short channel M
An ISFET can be formed.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an SO according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a main part of an SOI substrate, showing a CMOSFET formed on the I substrate. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

Q ₁ is an n-channel MISFET, and Q ₂ is a p-channel MISFET. The SOI substrate includes a support substrate 1 and a buried insulating film 2 provided on the support substrate 1.
And a thin silicon layer 3 provided on the buried insulating film 2
And an n-channel type MISFET
Q ₁ and p-channel type MISFET Q ₂ are formed in active regions provided in the thin silicon layer 3 surrounded by the isolation insulating film 4, respectively.

The n-channel type MISFET Q ₁ is formed on a p-type well 5 having an impurity concentration of about 10 ¹⁶ cm ⁻³ formed in the thin-film silicon layer 3. ^{The +} type semiconductor region 6 constitutes a source and a drain. The depth of the n ⁺ type semiconductor region 6 is
The distance between the n ⁺ type semiconductor region 6 and the buried insulating film 2 is, for example, about 120 nm.

A gate insulating film 7 of a silicon oxide film is formed on the p-type well 5 between the pair of n ⁺ -type semiconductor regions 6, and an n ⁺ -type gate electrode of an n-type polycrystalline silicon film is formed thereon. 8a is configured.

[0023] Under the the n-channel type MISFET Q ₁ isolation insulating film 4 provided around the active region forming a have thin silicon layer 3, the impurity concentration in the thin film silicon layer 3 is 10 ¹⁸ cm ^{- A} first p ⁺ -type impurity region 9 having a high concentration of about ³ is formed.

In the p-type well 5 located below the n ⁺ -type gate electrode 8a, a second p ⁺ -type impurity region 10 having a high impurity concentration of about 10 ¹⁸ cm ^-3 is formed. Also, a p ⁺ -type semiconductor region 11 for fixing the potential of the p-type well 5 is surrounded by the element isolation insulating film 4.
And the impurity concentration of the p ⁺ type semiconductor region 11 is about 10 ¹⁸ cm ⁻³ .

The surface of the n ⁺ type gate electrode 8a, the surface of the n ⁺ type semiconductor region 6 constituting the source and drain, and p ⁺
A low resistance titanium silicide film 12 is formed on the surface of the type semiconductor region 11.

Similarly, a p-channel type MISFET Q
₂ indicates that the impurity concentration formed in the thin silicon layer 3 is 10
Formed on the ¹⁶ cm ^-3 of about n-type well 13, on the surface of the n-type well 13, the source, the drain is constituted by a pair of p ⁺ -type semiconductor region 14. The depth of the p ⁺ type semiconductor region 14 is, for example, about 120 nm, and p ⁺
The distance between the mold semiconductor region 14 and the buried insulating film 2 is, for example, about 100 nm.

N between the pair of p ⁺ -type semiconductor regions 14
A gate insulating film 7 is formed of a silicon oxide film on the mold well 13, and ap ⁺ type gate electrode 8b is formed thereon of a p-type polycrystalline silicon film.

Below the element isolation insulating film 4 provided around the active region for forming the p-channel type MISFET Q ₂ , there is a thin film silicon layer 3 having an impurity concentration of 10 ¹⁸ cm ^{− A} first n ⁺ -type impurity region 15 having a high concentration of about ³ is formed.

In the n-type well 13 located below the p ⁺ -type gate electrode 8b, a second n ⁺ -type impurity region 16 having a high impurity concentration of about 10 ¹⁸ cm ^-3 is formed. Further, the n ⁺ -type semiconductor region 17 for fixing the potential of the n-type well 13 is formed on the surface of the n-type well 13 surrounded by the element isolation insulating film 4, the impurity of the n ⁺ -type semiconductor region 17 The concentration is about 10 ¹⁸ cm ^-3 .

The surface of p ⁺ type gate electrode 8b, the surface of p ⁺ type semiconductor region 14 constituting the source and drain, and n
^On the surface of the ⁺ type semiconductor region 17, a low resistance titanium silicide film 12 is formed.

Next, the CMOSFET of the present embodiment
Will be described with reference to FIGS.

As shown in FIG. 2, the SOI substrate is composed of a support substrate 1, a buried insulating film 2, and a thin silicon layer 3, and the thin silicon layer 3 is an n-channel type MI.
This is an active layer in which the SFET Q ₁ and the p-channel MISFET Q ₂ are formed. The thickness of the buried insulating film 2 is, for example, about 200 nm, and the thickness of the thin silicon layer 3 is,
For example, it is about 225 nm.

First, as shown in FIG. 3, a p-type well 5 and an n-type well 13 having an impurity concentration of, for example, about 10 ¹⁶ cm ^-3 are formed in the thin film silicon layer 3. Next, a silicon oxide film 18 having a thickness of about 10 nm is formed on the surface of the thin silicon layer 3.
After the formation of the chemical vapor deposition (Chemical Vapor Depos)
A silicon nitride film 19 having a thickness of about 100 nm is deposited on the silicon oxide film 18 by a method (ition; CVD). Next, using the resist pattern as a mask, the silicon nitride film 19 and the silicon oxide film 18 are sequentially etched to form the silicon nitride film 19 in the element isolation regions 20a and 20b.
Then, the silicon oxide film 18 is removed.

Next, the thin film silicon layer 3 is etched using the silicon nitride film 19 as a mask to form a groove 21 having a depth of about 170 nm in the thin film silicon layer 3. Therefore, groove 2
A thin silicon layer 3 having a thickness of about 50 nm is left under 1.

Next, an n-type well 1 is formed using a resist pattern.
After covering the upper surface 3, the p-type impurity ions 22, for example, boron (B) ions are implanted into the thin film silicon layer 3 of the element isolation region 20a by ion implantation using the silicon nitride film 19 as a mask. B ions are implanted at an acceleration energy of, for example, 7 keV and about 5 × 10 ¹² cm ⁻² . As a result, the n-channel MISFET Q _{1 has} the n-channel MISFET Q ₁ in the thin-film silicon layer 3 in the element isolation region 20 a.
Conductivity type p-type impurity of opposite SFETQ ₁ channel is introduced about 10 ¹⁸ cm ^-3.

Similarly, a p-type well 5 is formed using a resist pattern.
After the top is covered, n-type impurity ions 23, for example, phosphorus (P) ions are implanted into the thin film silicon layer 3 in the element isolation region 20b by ion implantation using the silicon nitride film 19 as a mask. P ions are implanted at an acceleration energy of, for example, 20 keV and about 5 × 10 ¹² cm ⁻² . Thus, the p-channel type MISFET Q ₂ of the isolation region 20b thin silicon layer 3, the p-channel type MIS
Conductivity type n-type impurity of opposite channel FETs Q ₂ is introduced about 10 ¹⁸ cm ^-3.

Next, as shown in FIG. 4, a silicon oxide film (not shown) having a thickness of about 250 nm is deposited on the SOI substrate by the CVD method. The surface of the silicon film is, for example, chemically mechanically polished (Chemical Mechanical Polishing; CMP).
By flattening by a method, a silicon oxide film is buried in the trench 21 to form an element isolation insulating film 4 composed of the silicon oxide film. Thereafter, the silicon nitride film 19 is removed, and subsequently, the silicon oxide film 18 is removed.

Next, as shown in FIG. 5, a gate insulating film 7 made of a silicon oxide film is formed on the surface of the thin film silicon layer 3 to a thickness of about 3.5 nm. Next, SOI
A polycrystalline silicon film (not shown) is deposited on the substrate. The thickness of this polycrystalline silicon film is, for example, 200 nm.

Next, an n-type well 13 is formed using a resist pattern.
After the top is covered, n-type impurity ions, for example, P ions are introduced into the polycrystalline silicon film on the p-type well region 5 by ion implantation. P ions are, for example, 30 keV
In the acceleration energy driven into 2 × 10 ¹⁵ cm ^-2 order of polycrystalline silicon film.

Similarly, a p-type well 5 is formed using a resist pattern.
After the top is covered, p-type impurity ions, for example, B ions are introduced into the polycrystalline silicon film on the n-type well region 13 by ion implantation. B ions are, for example, 10 ke
About 2 × 10 ¹⁵ cm ⁻² is implanted into the polycrystalline silicon film at an acceleration energy of V.

Next, the polycrystalline silicon film is etched using the resist pattern as a mask to form an n-channel M
Forming a high-concentration n ⁺ -type gate electrode 8a and the high-concentration p ⁺ -type gate electrode 8b of the p-channel type MISFET Q ₂ of ISFETQ _1.

Next, on the SOI substrate by the CVD method,
After depositing a silicon oxide film (not shown) having a thickness of about 100 nm, this silicon oxide film is removed by RIE (Reactive Ion).
Etching) to form an n ⁺ type gate electrode 8a
Then, a sidewall spacer 24 is formed on each side wall of the p ⁺ type gate electrode 8b.

Next, as shown in FIG. 6, after covering the n-type well 13 with a resist pattern, p-type impurity ions 25 are implanted into the p-type well region 5 by ion implantation. At this time, the range of the p-type impurity ions 25 is about 3
The conditions for the implantation of the p-type impurity ions 25, for example, the acceleration energy and the dose are set so as to be 50 nm.

Thus, in the region below the n ⁺ type gate electrode 8a, the p-type impurity ions 25 are implanted into the thin film silicon layer 3, while in the region other than below the n ⁺ type gate electrode 8a, Most of the impurity ions 25 are implanted into the buried insulating film 2.

For example, when implanting B ions, the acceleration energy and the dose amount are each 125 keV.
And 5 × 10 ¹² cm ⁻² . by this,
B ions are introduced into the thin film silicon layer 3 under the n ⁺ type gate electrode 8a at about 10 ¹⁸ cm ⁻³ . On the other hand, impurity ions in the buried insulating film 2 hardly diffuse and hardly diffuse into the thin silicon layer 3, so that B ions are introduced into the thin silicon layer 3 in a region other than under the n ⁺ type gate electrode 8a. Not done.

Similarly, a p-type well 5 is formed using a resist pattern.
After the top is covered, n-type impurity ions 26 are implanted into the n-type well region 13 by ion implantation. On this occasion,
The implantation conditions of the n-type impurity ions 26 are set so that the range of the n-type impurity ions 26 is about 350 nm,
For example, the acceleration energy and the dose are set.

As a result, in the region below the p ⁺ type gate electrode 8b, the n-type impurity ions 26 are implanted into the thin film silicon layer 3, while in the region other than below the p ⁺ -type gate electrode 8b, the n-type impurity ions 26 Most of the impurity ions 26 are implanted into the buried insulating film 2.

For example, when implanting P ions, the acceleration energy and the dose amount are each 285 keV.
And 5 × 10 ¹² cm ⁻² . by this,
P ions are introduced into the thin film silicon layer 3 under the p ⁺ type gate electrode 8b at about 10 ¹⁸ cm ⁻³ . On the other hand, since the impurity ions in the buried insulating film 2 hardly diffuse and hardly diffuse into the thin silicon layer 3, P ions are introduced into the thin silicon layer 3 in a region other than under the p ⁺ type gate electrode 8b. Not done.

Next, using the n ⁺ type gate electrode 8a and the side wall spacer 24 as a mask, an n channel type MI
N-type impurity ions 27, for example, arsenic (As) ions implanted by ion implantation into the active region of the p-type well 5 SFETQ ₁ is formed. At this time, the n-type impurity ions 27 to the active region 28 provided for fixing the potential of the n-type well 13 of the p-channel type MISFET Q ₂ is injected.

Similarly, the p ⁺ -type gate electrode 8b and the sidewall spacer 24 are used as a mask to form a p-channel type
P-type impurity ions 29 are ion-implanted into the active region of the n-type well 13 where the ISFET Q ₂ is to be formed;
For example, boron fluoride (BF ₂ ) ions are implanted. At this time, the active region 30 provided for fixing the potential of the p-type well 5 of the n-channel type MISFET Q _{1 also has} the p-type conductivity.
Type impurity ions 28 are implanted.

Thereafter, as shown in FIG. 7, the SOI substrate is subjected to a heat treatment at a temperature of, for example, 950.degree. C. for about 10 seconds, so that p-type impurity ions 22, 25, 29 and n-type impurity ion 2
Activate 3,26,27.

Thus, the n-channel type MISFET
Q ₁ at about 120nm source depth, the high-concentration n ⁺ -type semiconductor region 6 and p ⁺ -type semiconductor region 11 constituting the drain is formed, p-channel type MISFET Q ₂ at about 120nm source depth, drain High concentration p ⁺ -type semiconductor region 14 and n ⁺ -type semiconductor region 17
Is formed. Further, the n-channel type MISFET Q ₁
Is formed in the thin silicon layer 3 under the element isolation insulating film 4 provided around the active region in which the high concentration first p ⁺
-Type impurity region 9 is formed, and a p-channel MISFET
A high-concentration first n ⁺ -type impurity region 15 is formed in the thin-film silicon layer 3 under the element isolation insulating film 4 provided around the active region in which Q ₂ is formed. Further, n-channel type MISFET Q second p ⁺ -type impurity regions 10 of high concentration in the thin film silicon layer 3 under the gate electrode 8a of _1, and p-channel type thin film silicon layer 3 under the gate electrode 8b of the MISFET Q ₂ A high concentration second n ⁺ -type impurity region 16 is formed.

Next, the surface of the SOI substrate is treated with hydrofluoric acid (HF).
After cleaning with an aqueous solution, a titanium film (not shown) having a thickness of about 25 nm is deposited on the SOI substrate by a sputtering method. Thereafter, the SOI substrate is subjected to a heat treatment by a RTA (Rapid Thermal Annealing) method at a temperature of 650 ° C. for about 1 minute in a nitrogen atmosphere. By this heat treatment, a high-resistance titanium silicide film (TiSi _x (0 <x <
2)) (surface of the not shown) to the n-channel type MISFET Q ₁ n ⁺ -type gate electrode 8a, the source, the surface of the surface and the p ⁺ -type semiconductor region 11 of the n ⁺ -type semiconductor region 6 constituting the drain, and p the surface of the channel type MISFET Q ₂ p ⁺ -type gate electrode 8b, is formed on the surface of the surface and the n ⁺ -type semiconductor region 17 of the p ⁺ -type semiconductor region 14 constituting the source and drain.

Next, the unreacted titanium film is made of H ₂ O ₂ and NH
After removing with an etching solution containing ₄ OH, the SOI substrate is subjected to a heat treatment at a temperature of 850 ° C. for about 1 minute by an RTA method. By this heat treatment, the high-resistance titanium silicide film is changed to a low-resistance titanium silicide film (TiSi ₂ ) 1.
Change to 2.

Thereafter, an interlayer insulating film 31 is deposited on the SOI substrate, and the interlayer insulating film 31 is etched to form a contact hole 32, and then a metal film (not shown) deposited on the interlayer insulating film 31 Is etched to form a wiring layer 33, whereby the C of the present embodiment shown in FIG.
The MOSFET is completed.

As described above, according to the present embodiment, between the n ⁺ type semiconductor region 6 and the buried insulating film 2 constituting the source and drain of the n channel type MISFET Q ₁ , and the source of the p channel type MISFET Q ₂ There is a gap of about 0.1 μm between the p ⁺ type semiconductor region 14 constituting the drain and the buried insulating film 2, but the impurity concentration of the thin silicon layer 3 in this region is as low as about 10 ¹⁶ cm ^−3. So
The extension of the depletion layer of the n ⁺ -type semiconductor region 6 or the p ⁺ -type semiconductor region 14 at zero bias becomes 0.1 μm or more, and these depletion layers always reach the buried insulating film 2. Can be realized. Therefore, the thickness of the thin silicon layer 3 can be increased, and the thin silicon layer 3 is provided between the element isolation insulating film 4 and the buried insulating film 2, so that the p-type well 5 and the n-type well 13 are formed. Can be fixed, and n
Channel type MISFET Q ₁ and p channel type MIS
It is possible to prevent malfunction of the FETs Q _2.

[0057] Further, the n-channel type MISFET Q ₁ of n ⁺ -type underneath the gate electrode 8a thin silicon layer 3, 1
The second p having a high impurity concentration of about 0 ¹⁸ cm ^-3
+ -Type impurity regions 10 are formed, the short channel effect is suppressed, the n-channel type MISFET Q ₁ to the effective channel length is approximately 0.15μm can be operated normally. Similarly, a p-channel type MISFET
A _second n ⁺ -type impurity region 16 having a high impurity concentration of about 10 ¹⁸ cm ^-3 is formed in the thin film silicon layer 3 under the p ⁺ -type gate electrode 8b of Q2, The effect is suppressed and the effective channel length is about 0.15
The p-channel type MISFET Q ₂ up to about μm can be operated normally.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0059]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, even if a gap of about 0.1 μm is provided between the semiconductor region forming the source and drain and the buried insulating film, the depletion layer of the semiconductor region forming the source and drain at zero bias is provided. Are always in contact with the buried insulating film and the parasitic capacitance is kept low, so that a high-speed operation of the MISFET can be realized. Further, the thickness of the thin silicon layer can be increased, and the thin silicon layer is provided between the isolation insulating film and the buried insulating film, so that the potential of the thin silicon layer can be fixed, and the operation of the MISFET due to the potential change can be performed. Failure can be prevented.

Further, according to the present invention, the short channel effect is suppressed by the high concentration impurity region provided in the thin film silicon layer below the gate electrode, so that a short channel MISFET can be formed. Fine M
An ISFET can be formed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a principal part of a semiconductor substrate showing a CMOSFET according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a CMOSFET according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOSFET according to the embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOSFET according to the embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOSFET according to the embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOSFET according to the embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOSFET according to the embodiment of the present invention;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 support substrate 2 buried insulating film 3 thin-film silicon layer 4 isolation insulating film 5 p-type well 6 n ⁺ type semiconductor region 7 gate insulating film 8 an n ⁺ type gate electrode 8 bp ⁺ type gate electrode 9 first p ⁺ type Impurity region 10 second p ⁺ -type impurity region 11 p ⁺ -type semiconductor region 12 titanium silicide film 13 n-type well 14 p ⁺ -type semiconductor region 15 first n ⁺ -type impurity region 16 second n ⁺ -type impurity region 17 n ⁺ type semiconductor region 18 silicon oxide film 19 silicon nitride film 20a device isolation region 20b device isolation region 21 groove 22 p-type impurity ion 23 n-type impurity ion 24 side wall spacer 25 p-type impurity ion 26 n-type impurity Ion 27 n-type impurity ion 28 active region 29 p-type impurity ion 30 active region 31 interlayer insulating film 32 contact Hole 33 wiring layer

Claims (8)

[Claims] 1. A semiconductor integrated circuit device in which a field-effect transistor is formed on a thin-film silicon layer of an SOI substrate having a thin-film silicon layer formed on a supporting substrate via a buried insulating film, wherein the field-effect transistor is The semiconductor region forming the drain is not in contact with the buried insulating film, is introduced into the thin film silicon layer between the semiconductor region and the buried insulating film, and has a conductivity type opposite to that of the channel. A semiconductor integrated circuit device having a concentration lower than a concentration of an impurity introduced into the thin film silicon layer below a gate electrode of the field effect transistor. 2. The semiconductor integrated circuit device according to claim 1, wherein said thin film is provided between an element isolation insulating film provided around an active region in which said field effect transistor is formed and said buried insulating film. A semiconductor integrated circuit device having a silicon layer interposed. 3. The semiconductor integrated circuit device according to claim 1, wherein the concentration of the impurity introduced into the thin film silicon layer below the gate electrode is about 10 ¹⁸ cm ⁻³ or more. Semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein a distance between the semiconductor region forming the drain and the buried insulating film is about 0.1 μm or more;
The semiconductor integrated circuit device according to claim 1, wherein a concentration of the impurity introduced into the thin film silicon layer between the semiconductor region forming the drain and the buried insulating film is about 10 ¹⁷ cm ^-3 or less. 5. The semiconductor integrated circuit device according to claim 1, wherein a depletion layer of a semiconductor region forming said drain reaches said buried insulating film at zero bias. . 6. The semiconductor integrated circuit device according to claim 2, wherein a concentration of the impurity introduced into the thin silicon layer between the element isolation insulating film and the buried insulating film is:
A semiconductor integrated circuit device having a size of about 10 ¹⁸ cm ⁻³ or more. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein (a) a step of sequentially forming a gate insulating film and a gate electrode on the thin silicon layer; and (b) the gate electrode. Forming a side wall spacer formed of an insulating film on the side wall of the thin film silicon layer under the gate electrode by applying a first impurity ion of a conductivity type opposite to the conductivity type of the channel; Implanting the SOI substrate under the condition that the impurity concentration becomes the maximum and the impurity concentration becomes the maximum in the buried insulating film under the semiconductor region constituting the drain; and (d) the same conductivity type as the channel conductivity type. Forming a semiconductor region constituting the drain on the surface of the thin-film silicon layer by implanting the second impurity ions into an SOI substrate. Production method. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein: (a) a step of sequentially forming a gate insulating film and a gate electrode on a thin silicon layer; and (b) the gate electrode. Forming side wall spacers made of an insulating film on the side walls of (c). First impurity ions of a conductivity type opposite to the conductivity type of the channel and the thin film silicon under the gate electrode. Implanting the SOI substrate under the condition that the impurity concentration becomes maximum in the layer and the impurity concentration becomes maximum in the buried insulating film below the first semiconductor region constituting the drain; and (d) channel implantation. Forming a first semiconductor region constituting the drain on the surface of the thin-film silicon layer by implanting a second impurity ion of the same conductivity type as the conductivity type into the SOI substrate; Third impurity ions of a conductivity type opposite to the conductivity type of the semiconductor layer are implanted into the SOI substrate, and a second semiconductor region for fixing the potential of the thin-film silicon layer is formed by a first semiconductor region forming the drain. Forming the thin film silicon layer on the other surface where the semiconductor region is not formed.