JPH0794721A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form an opening to put the channel region of a MOS transistor of SOI structure in contact with a substrate body in self-alignment manner with a gate electrode. CONSTITUTION:Oxygen 33 is implanted into a Si substrate 11 using a polycrystalline Si film 22, a gate electrode, as a mask, and a buried SiO2 layer 35 is thereby formed. Arsenic 36 is implanted into the Si substrate 11 using the polycrystalline Si film 22 as a mask, and a source and a drain 23 are thereby formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an SOI (Silicon On Insulator
Semiconductor On Insulator) MOS formed on the substrate
The present invention relates to improvements in transistors and the like.

[0002]

2. Description of the Related Art Conventionally, SOI substrates have been used as substrates for high speed devices because of their characteristics of low parasitic capacitance and latch-up free. However, the SOI substrate also has an inherent defect in its structure. First, since the substrate portion is in a floating state, it has the effect of increasing the operation speed, but on the other hand, there is the problem that the electrical characteristics fluctuate during operation and become unstable. Secondly, when a MOS device is formed on an SOI substrate and the bottom surface of the impurity diffusion layer is brought into contact with the insulator layer, the junction capacitance at the bottom surface of the diffusion layer is lost, which makes it vulnerable to electrostatic breakdown. Is.

In order to overcome these problems, some techniques for fixing the substrate potential have been proposed in the past, one of which is shown in FIGS.

This prior art will be described according to its manufacturing method. First, as shown in FIG.
On the surface of the SiO 2 by thermal oxidation method with a film thickness of about 500 nm
_{2 The} film 12 is formed.

Next, as shown in FIG.
A photoresist 13 having a pattern in which a region for forming an S transistor is opened is formed by a photolithography technique into Si.
It is formed on the O ₂ film 12, and the SiO ₂ film 12 is selectively removed by etching using the photoresist 13 as a mask.

Next, as shown in FIG. 5C, after the photoresist 13 is removed, the exposed portion of the Si substrate 11 is thermally oxidized to form a SiO ₂ film 14 having a thickness of about 50 nm.
To form.

Next, as shown in FIG. 6 (a), SiO ₂
A photoresist 15 having a pattern having an opening at a portion of the film 14 is formed on the SiO ₂ films 12 and 14 by a photolithography technique, and the SiO ₂ film 14 reaches the Si substrate 11 by etching using the photoresist 15 as a mask. The opening 16 is formed.

Next, as shown in FIG.
Selective epitaxial growth is performed at a temperature of up to 1200 ° C. in an atmosphere containing SiH ₄ . Then, the Si substrate 11 exposed in the opening 16 functions as a seed (nucleus) for growth, and the epitaxial layer 17 grows according to its crystal orientation.

Next, as shown in FIG. 6 (c), SiO ₂
The portion of the epitaxial layer 17 protruding above the film 12 is removed by a surface polishing method to form an SOI substrate.

Thereafter, as shown in FIG. 6D, a SiO ₂ film 21 as a gate insulating film and a polycrystalline Si film 22 as a gate electrode are formed respectively, and this polycrystalline Si film 22 is formed.
Impurity diffusion layers 23 as source / drain are formed in the epitaxial layers 17 on both sides of. After that, as shown in FIG. 4, an interlayer insulating film 24, a contact hole 25, and an Al electrode 26 are formed, respectively, to form a MOS transistor.

In the MOS transistor having this structure, the epitaxial layer 17 and the Si substrate 11, which are the substrate portion, are in contact with each other through the opening 16, and the potential of the epitaxial layer 17 is fixed. This MOS
Transistors are actually DRs that require substrate bias
Used as a transfer gate for AM.

[0012]

However, in the above-mentioned conventional manufacturing method, since the polycrystalline Si film 22 which is the gate electrode and the opening 16 of the SiO ₂ film 12 are formed in the steps independent of each other, these There was a problem that the positional consistency between them was not guaranteed. In particular, when the gate electrode width is narrowed due to miniaturization, the opening 16 is formed in the impurity diffusion layer 2
3 directly below, the epitaxial layer 17 and the Si substrate 11
It is possible that the contact between and does not come into contact sufficiently, and in that case, since the epitaxial layer 17 that is the substrate portion of the MOS transistor is in a floating state, the above-mentioned problems of the SOI substrate cannot be solved. in short,
The conventional manufacturing method described above has a problem that it is difficult to cope with future miniaturization.

Therefore, an object of the present invention is to provide a semiconductor device corresponding to miniaturization by forming a contact portion for fixing the potential of a substrate portion of a MOS transistor, for example, in a self-aligned manner with a gate electrode, and a manufacturing method thereof. It is to be.

[0014]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate insulating film as a first insulating film on a semiconductor substrate of a first conductivity type. A step of sequentially depositing a gate electrode material and a second insulating film on the gate insulating film, a step of processing the gate electrode material and the second insulating film into a gate electrode pattern, and a step of forming the gate electrode pattern. Introducing oxygen into the semiconductor substrate as a mask to form a buried oxide layer at a predetermined depth position in the semiconductor substrate, and then using the gate electrode pattern as a mask to form a second oxide in the semiconductor substrate. Introducing a conductivity type impurity to form a second conductivity type impurity diffusion layer in the vicinity of the surface of the semiconductor substrate.

A method of manufacturing a semiconductor device according to an aspect of the present invention includes a step of forming a gate insulating film as a first insulating film on a semiconductor substrate of the first conductivity type, and a polycrystalline silicon film on the gate insulating film. And a step of sequentially depositing a second insulating film, a step of processing the polycrystalline silicon film and the second insulating film into a gate electrode pattern, and oxygen in the semiconductor substrate using the gate electrode pattern as a mask. Introduced,
Forming a buried oxide layer at a predetermined depth of the semiconductor substrate; then removing the second insulating film; and thereafter adding impurities of the second conductivity type to the polycrystalline silicon film. Introducing the second conductivity type impurity into the semiconductor substrate using the polycrystalline silicon film as a mask, and forming a second conductivity type impurity diffusion layer in the vicinity of the surface of the semiconductor substrate. Have.

A method of manufacturing a semiconductor device according to another aspect of the present invention includes a step of forming a gate insulating film as a first insulating film on a semiconductor substrate of the first conductivity type, and a gate electrode on the gate insulating film. A step of sequentially depositing a material and a second insulating film, a step of processing the gate electrode material and the second insulating film into a gate electrode pattern, and a region on one side of the gate electrode pattern with a third insulating film. A step of covering with a film, and using the third insulating film and the gate electrode pattern as a mask, oxygen is introduced into the semiconductor substrate in the region on the other side of the gate electrode pattern, Forming a buried oxide layer at a predetermined depth of the semiconductor substrate, then removing the third insulating film, and then using the gate electrode pattern as a mask And a step of a second conductivity type impurity is introduced to form a second conductivity type impurity diffusion layer near the surface portion of said semiconductor substrate.

A semiconductor device of the present invention comprises a gate electrode formed on a first conductivity type semiconductor substrate via a gate insulating film, and a pair of impurity diffusion layers formed in the vicinity of the surface of the semiconductor substrate. And a buried insulator layer formed just below one of the pair of impurity diffusion layers.

[0018]

In the method of manufacturing a semiconductor device of the present invention, for example, M
Since the insulator layer immediately below the impurity diffusion layer serving as the source / drain of the OS transistor is formed by oxygen ion implantation using the gate electrode pattern of the MOS transistor as a mask, the buried oxide layer is used as a gate. It can be formed with good positional alignment with respect to the electrodes.

Since the buried oxide layer can be formed only in the semiconductor substrate on one side of the gate electrode, the buried oxide layer is brought into contact with the buried oxide layer in order to improve the resistance to soft error due to α-rays, for example. By not forming the buried oxide layer directly below the impurity diffusion layer on the side that is not the necessary impurity diffusion layer, it is possible to improve the resistance to electrostatic breakdown.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments with reference to FIGS. In addition, in the following examples, FIG.
Components corresponding to those of the conventional example shown in FIG. 6 are designated by the same reference numerals.

1A and 2 show a first embodiment of the present invention. In the first embodiment, first, as shown in FIG. 2A, the SiO ₂ film 3 is formed on the surface of the element isolation region of the P-type Si substrate 11 by a normal selective oxidation (LOCOS) method.
1 is formed, and the region surrounded by the SiO ₂ film 31 is used as an element formation region.

Next, as shown in FIG.
The Si substrate 11 is thermally oxidized in a water vapor atmosphere at 900 ° C. to form a SiO ₂ film 21 as a gate insulating film. After that, the polycrystalline Si film 22 having a film thickness of about 300 nm and containing an N-type impurity, and the SiO ₂ film 3 having a film thickness of about 1 μm.
2 and 2 are sequentially deposited on the entire surface by the CVD method, and then SiO ₂
The film 32 and the polycrystalline Si film 22 are processed into a gate electrode pattern by photolithography and anisotropic dry etching.

Next, as shown in FIG. 2C, SiO ₂
Using the films 31 and 32 and the polycrystalline Si film 22 as a mask, S
Oxygen 33 is ion-implanted at an acceleration energy of 150 to 200 keV and a dose amount of 1 × 10 ¹⁶ / cm ⁻² so that the i-substrate 11 has a concentration profile peak at a depth of about 0.5 μm. And 1000 to 1200
℃ heat treated go of, to form a buried SiO ₂ layer 35 having a gap 34 only just below the polycrystalline Si film 22.

Next, as shown in FIG. 2D, SiO ₂
After removing the film 32, the SiO ₂ film 31 and the polycrystalline Si are again formed.
Using the film 22 as a mask, N-type impurities such as arsenic 3
6 is ion-implanted into the Si substrate 11, and an impurity diffusion layer sandwiched between the SiO ₂ film 21 and the embedded SiO ₂ layer 35, that is, a portion near the surface of the Si substrate 11 is filled with the embedded Si.
The impurity diffusion layer 23 that contacts the O ₂ layer 35 is formed. If it is not necessary to adjust the impurity concentration in the polycrystalline Si film 22, arsenic ion implantation may be performed before removing the SiO ₂ film 32.

Thereafter, similarly to the conventional example shown in FIG. 4, the interlayer insulating film 24, the contact hole 25 and the Al electrode 26 are formed respectively to form the MOS transistor shown in FIG.

A second embodiment of the present invention is shown in FIGS. 1 (b) and 3. In this second embodiment, as shown in FIG. 3A, the same steps as those in the above-mentioned first embodiment are executed and S
After the iO ₂ film 32 and the polycrystalline Si film 22 are processed into the pattern of the gate electrode, the SiN film 41 is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 3B, a photoresist 42 is patterned so as to cover a region on one side of the polycrystalline Si film 22 which is a gate electrode, and then the photoresist 42 is used as a mask. The anisotropic dry etching is performed to remove the SiN film 41 in the region on the other side of the polycrystalline Si film 22.

Next, as shown in FIG. 3C, SiO ₂
Using the films 31 and 32, the polycrystalline Si film 22, and the SiN film 41 as a mask, oxygen 33 is ion-implanted into the Si substrate 11 under the same conditions as in the above-described first embodiment, and heat treatment is performed under the same conditions. The embedded SiO ₂ layer 35 is formed only in the Si substrate 11 in the region on the other side of the polycrystalline Si film 22.

Next, as shown in FIG. 3D, the remaining SiN film 41 is removed, and the SiO ₂ films 31 and 32 and the polycrystalline Si film 22 are used as a mask to remove N-type impurities, for example, By implanting arsenic 36 into the Si substrate 11 by ion implantation,
One of which is embedded in the vicinity of the surface of No. 1 SiO ₂ layer 35
Impurity diffusion layer 23 in contact with is formed.

Then, after removing the SiO ₂ film 32, the interlayer insulating film 24, the contact hole 25 and the Al electrode 26 are respectively formed as in the conventional example shown in FIG. 4, and the MOS shown in FIG. Form a transistor.

In the structure of the second embodiment, the buried S is provided immediately below one impurity diffusion layer 23 of the MOS transistor.
The iO ₂ layer 35 is not formed. Therefore, for example, in a 1-transistor 1-capacitor type MOS / DRAM,
The impurity diffusion layer 2 on the source side, which is not the impurity diffusion layer 23 on the drain side that needs to be in contact with the embedded SiO ₂ layer 35 in order to improve the resistance to the soft error due to α rays
By not forming the embedded SiO ₂ layer directly under 3, it is possible to obtain a large junction capacitance at the bottom surface of the source, and to obtain an electrostatic breakdown strength almost the same as in the case of a bulk MOS having no embedded SiO ₂ layer 35. be able to.

FIG. 1 (c) shows a third embodiment of the present invention. In the third embodiment, the SiO ₂ film 4 in the element isolation region is used.
3 is substantially the same as the first embodiment shown in FIGS. 1A and 2 except that the forming method is different.

FIG. 1 (d) shows a fourth embodiment of the present invention. This fourth embodiment is the third embodiment shown in FIG. 1 (c) except that it has an LDD structure. Substantially the same as the example.

[0034]

According to the method of manufacturing a semiconductor device of the present invention, both the buried oxide layer and the impurity diffusion layer are formed in a self-aligned manner with respect to the gate electrode. The contact between the formed channel region and the semiconductor substrate body is guaranteed, and the substrate potential of the device can be fixed. Therefore, a semiconductor device having stable electric characteristics during operation can be provided.

By forming the buried oxide layer only under one of the impurity diffusion layers, it is possible to obtain a semiconductor device resistant to electrostatic breakdown.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a configuration of a semiconductor device of each of first to fourth embodiments of the present invention.

FIG. 2 is a vertical cross-sectional view showing the method of manufacturing a semiconductor device of the first embodiment of the present invention in the order of steps.

FIG. 3 is a vertical cross-sectional view showing a method of manufacturing a semiconductor device of a second embodiment of the present invention in process order.

FIG. 4 is a vertical cross-sectional view of a conventional semiconductor device.

FIG. 5 is a vertical cross-sectional view showing a method of manufacturing a conventional semiconductor device in the order of steps.

FIG. 6 is a vertical cross-sectional view showing a method of manufacturing a conventional semiconductor device in the order of steps.

[Explanation of symbols]

11 Si substrate 21 SiO ₂ film 22 Polycrystalline Si film 23 Impurity diffusion layer 33 Oxygen 35 Embedded SiO ₂ layer 36 Arsenic

Claims (4)

[Claims] 1. A step of forming a gate insulating film as a first insulating film on a semiconductor substrate of a first conductivity type, and a step of sequentially depositing a gate electrode material and a second insulating film on the gate insulating film. Processing the gate electrode material and the second insulating film into a gate electrode pattern, introducing oxygen into the semiconductor substrate using the gate electrode pattern as a mask, and burying the oxygen at a predetermined depth position in the semiconductor substrate. Forming an oxide layer, and then introducing a second conductivity type impurity into the semiconductor substrate using the gate electrode pattern as a mask, and diffusing the second conductivity type impurity into a portion near the surface of the semiconductor substrate. And a step of forming a layer. 2. A step of forming a gate insulating film as a first insulating film on a semiconductor substrate of the first conductivity type, and a step of sequentially depositing a polycrystalline silicon film and a second insulating film on the gate insulating film. And a step of processing the polycrystalline silicon film and the second insulating film into a gate electrode pattern, introducing oxygen into the semiconductor substrate using the gate electrode pattern as a mask, and setting a predetermined depth position of the semiconductor substrate. And a step of removing the second insulating film, and then introducing a second conductivity type impurity into the polycrystalline silicon film and removing the polycrystalline silicon film. Introducing a second conductivity type impurity into the semiconductor substrate using the film as a mask,
And a step of forming an impurity diffusion layer of the second conductivity type in the vicinity of the surface of the semiconductor substrate. 3. A step of forming a gate insulating film as a first insulating film on a semiconductor substrate of the first conductivity type, and a step of sequentially depositing a gate electrode material and a second insulating film on the gate insulating film. Processing the gate electrode material and the second insulating film into a gate electrode pattern, covering a region on one side of the gate electrode pattern with a third insulating film, the third insulating film, Using the gate electrode pattern as a mask, oxygen is introduced into the semiconductor substrate in the region on the other side of the gate electrode pattern, and a buried oxide layer is formed at a predetermined depth position of the semiconductor substrate in the region on the other side. And a step of removing the third insulating film, followed by introducing a second conductivity type impurity into the semiconductor substrate using the gate electrode pattern as a mask to form the semiconductor substrate. And a step of forming an impurity diffusion layer of the second conductivity type in the vicinity of the surface of the plate. 4. A gate electrode formed on a semiconductor substrate of the first conductivity type via a gate insulating film, a pair of impurity diffusion layers formed in the vicinity of the surface of the semiconductor substrate, and a pair of impurity diffusions. A semiconductor device having a buried insulator layer formed only directly below one of the layers.