JP2734434B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a gate electrode and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a MOS type semiconductor device, L is used to prevent deterioration of a gate insulating film due to hot carriers.
It is widely practiced to adopt a DD (Lightly Doped Drain) structure. FIG. 5A shows a cross-sectional structure of a general LDD type MOS transistor, and FIG.
FIG. 5C is a cross-sectional view taken along line CC ′ of FIG. 5B.

A gate oxide film 30 is formed on a silicon substrate 301.
2 is formed, and a gate electrode 303 is formed using polysilicon deposition, photolithography technology and etching technology.
To form Thereafter, ion implantation for forming the LDD region 304 is performed, and a sidewall 306 serving as a spacer is formed by depositing a silicon oxide film and etching back the silicon oxide film. Then, impurities are introduced using the gate electrode and the sidewalls as a mask to form the source / drain regions 305.
Is formed to manufacture a conventional LDD type MOS transistor [FIG. 5 (a)].

[0005] As shown in FIG. 5 (b), a source / drain region 305 is a LOCOS which is an element isolation oxide film.
It is formed in a region surrounded by the oxide film 307. The gate electrode 303 has a portion necessary for forming a channel formed as thin as possible, and a gate pad 303a and a simple gate wiring 303b which require a relatively large area to serve as a pedestal of a hole for conducting the gate electrode and an upper wiring are formed. The gate electrode is drawn out to a position above the LOCOS oxide film 307 and is formed only on the LOCOS oxide film (FIG. 5B). In this case, the LOC is set between the substrate and the gate pad 303a or the gate wiring 303b.
Only the OS oxide film 307 is formed (FIG. 5C).

As an improved type of the above-mentioned LDD type MOS transistor, a transistor having a structure shown in FIG. 6 has been proposed in Japanese Patent Application Laid-Open No. 4-112544 in order to increase the speed. An LDD region 406 and a source / drain region 407 are formed below the LOCOS oxide film 404 on the silicon substrate 401, and a gate insulating film 405 is formed on the substrate.
A gate electrode including a first gate electrode 402a and a second gate electrode 402b is formed via a LOCOS oxide film 404, and the surface of the gate electrode is covered with a silicon oxide film 403. In this transistor, the channel current is increased by overlapping the gate electrodes (402a, 402b) and the source / drain regions (406, 407), and the LOCOS oxide film 404
The bird's beak is the gate electrode (402a, 402a).
By forming it so as to protrude between b) and the source / drain, the capacitance between the gate electrode and the source / drain is reduced, and the leak current between the gate electrode and the substrate is reduced.

Although it does not relate to a MOS transistor having an LDD structure, a structure shown in FIG. 7 has been proposed by JP-A-57-197866 to reduce the capacitance between a gate electrode and a source / drain region. In this transistor, a relatively thick first oxide film 503 and a relatively thick second oxide film 504 are provided on a silicon substrate 501 in addition to the gate oxide film 502, and under the first oxide film 503. A channel stopper 505 is formed, and source / drain regions 506 are formed below the second oxide film 504. An electrode extraction region 507 is formed on the surface of the silicon substrate that is not covered with the oxide film, and a metal wiring 508 is formed thereon. Also, the gate oxide film 50
A metal gate 509 is formed from 2 to the second oxide film 504. In this conventional example, the gate electrode can be formed of a metal material, and the gate electrode and the source electrode can be formed.
Since the drain wiring and the same material can be formed, the design margin can be reduced. Further, since the gate electrode and the source / drain are separated by a relatively thick oxide film, the capacitance therebetween is reduced.

[0007]

SUMMARY OF THE INVENTION Conventional LDD type MOS
In transistors, the gate pad and gate wiring are LOS
It is formed only on the OS oxide film. In particular, the gate pad needs an area which is equal to the size of the contact hole plus a margin for misalignment in two photolithography steps when forming the gate pad and the contact hole, and is necessary for forming a channel of the gate electrode. Since the area is considerably larger than that of the part, it has been an obstacle to high-density integration. Also, in the conventional LDD transistor, the gate length cannot be reduced to a size smaller than the limit of the photolithography technology, and the gate length is further reduced to realize high integration and high-speed operation of the transistor. However, it was impossible with the conventional structure.

The method proposed in each of the above publications for realizing high-speed operation of a transistor by reducing the capacitance between a gate electrode and a substrate or between a gate electrode and a source / drain is disclosed in US Pat. In an attempt to increase the distance between the gate electrode and the source / drain by bird's beak by thermal oxidation, it is generally extremely difficult to accurately control the amount of protrusion of the bird's beak below the gate electrode. Therefore, in this conventional technique, as the gate becomes finer, a problem arises in the controllability of the channel length which affects the operation speed of the transistor.

Therefore, an object of the present invention is to improve the degree of freedom in the layout of the gate pad and the gate wiring, and
An object of the present invention is to provide a structure of an LDD type MOS transistor and a method of manufacturing the same, which enable high integration of an SI and miniaturize a gate with good controllability.

[0010]

In order to achieve the above object, a semiconductor device according to the present invention has an interlayer insulating film having a gate opening formed on a silicon substrate, and has a gate insulating film formed on a side surface of the gate opening in the interlayer insulating film. A sidewall is formed, a gate electrode is formed on the silicon substrate in a region sandwiched between the sidewalls via a gate insulating film, and a low impurity concentration source is formed in a surface region of the silicon substrate below the sidewall. A drain region is formed, and a source / drain region having a high impurity concentration is formed outside the drain region.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a first conductive type high impurity concentration source / drain region on a silicon substrate having a gate opening on a silicon substrate; Forming a film; and introducing a impurity through the gate opening to form a first conductivity type low impurity concentration source / drain region in a surface region of the silicon substrate where the gate opening is formed. Forming a sidewall on a side surface of a gate opening of the interlayer insulating film by depositing an insulating film and etching back the insulating film; and forming a second sidewall on the low impurity concentration source / drain region in a region sandwiched between the sidewalls. Forming a channel region by introducing a conductivity type impurity, and forming a gate electrode on the channel region via a gate insulating film. It is intended.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a plan view for explaining an embodiment of the present invention, and FIG.
It is sectional drawing of the A 'line. As shown in FIG. 1, a LOCOS oxide film 2 is formed on the surface of a silicon substrate 1 to separate elements from each other and to partition an active region.
In the region surrounded by the S oxide film 2, a high impurity concentration source
A drain region 3 is formed. An interlayer insulating film 4 having a gate opening 4a is formed on the substrate so as to cover the source / drain region 3.

A sidewall 5 made of an insulator is formed on the side surface of the gate opening 4a of the interlayer insulating film 4, and an LDD which is a low impurity concentration source / drain region is formed on the surface of the silicon substrate immediately below the sidewall. Region 6 is formed. A gate oxide film 7 is formed on the silicon substrate in a region sandwiched between the sidewalls 5, and a gate electrode 8 partially extending on the interlayer insulating film 4 is formed thereon. . Part of the region of the gate electrode 8 is
It is formed wide as a gate pad 8a for connection with an upper layer.

The semiconductor device shown in FIG. 1 is manufactured as follows. A LOCOS oxide film 2, which is an element isolation insulating film, is formed on a silicon substrate 1, and a first or a first LOCOS oxide film is formed entirely or selectively in a region surrounded by the LOCOS oxide film 2.
The source / drain region 3 is formed by introducing a conductive impurity at a high concentration. An interlayer insulating film 4 is deposited, and a gate opening 4a is formed.
To form LDD region 6 is formed by introducing impurities of the first conductivity type or the second conductivity type through gate opening 4a. At this time, the region that will be the channel region in the future is also the LDD region.

By the formation of the insulating film and its etch back,
A sidewall 5 is formed on the side surface of the gate opening 4a of the interlayer insulating film 4. By introducing a second conductivity type impurity through this gate opening, a channel region 1a is formed on the surface of the silicon substrate sandwiched between the side walls 5, and a gate oxide film 5 is formed. Then, a gate electrode 8 is formed by patterning this film.

In the MOS transistor thus formed, since the gate electrode is buried in the interlayer insulating film, the region where the gate pad and the gate wiring are formed is LOCO.
It is not limited to only on the S oxide film, and it is possible to form these on the active region (channel region and source / drain region), so that the degree of freedom of design is increased and the chip area can be effectively used. Therefore, high-density integration can be realized. In addition, since the gate length is determined by the distance between the sidewalls, it is possible to form a gate electrode having a size equal to or smaller than the resolution limit of the photolithography technology, and to achieve miniaturization and high performance of a transistor. .

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIGS. 2A to 2F show a first embodiment of the present invention.
6A to 6C are process order cross-sectional views for describing a manufacturing process of the example of FIG. First, a LOCOS oxide film 102 is formed on a p-type silicon substrate 101, and a first sacrificial oxide film 103 for ion implantation is formed on an active region not covered with the LOCOS oxide film 102 [FIG. a)]. Next, 5.0E
Arsenic is ion-implanted at a dose of 14 / cm ² ,
A drain region 104 is formed (FIG. 2B).

Next, after the sacrificial oxide film 103 is removed by wet etching, a silicon oxide film 105 is formed to a thickness of 1500 °, and then an interlayer insulating film 106 is formed to a thickness of 5000 ° [FIG. )]. Subsequently, the interlayer insulating film 1 is formed using photolithography technology and dry etching technology.
In 06, a portion directly above a portion to be a channel region and an LDD region is etched to form a gate opening 106a having a width of 0.5 μm. Next, after forming a second sacrificial oxide film 107 for ion implantation, an interlayer insulating film 106 is formed.
Is used as a mask, boron ions are implanted at a dose of 4.7E14 / cm ² to form an LDD region 108 [FIG.
(D)].

Subsequently, after a silicon oxide film is grown at 1500.degree., It is etched back by a dry etching technique to form sidewalls 109 serving as spacers on the side surfaces of the gate opening 106a of the interlayer insulating film. Next, a third sacrificial oxide film 110 for ion implantation is formed, and the interlayer insulating film 106 and the sidewalls 109 are used as masks.
LDD region 108 at a dose of 3.5E13 / cm ^2.
Is ion-implanted at an accelerating voltage at which ions are implanted to a depth equal to or greater than the depth of the channel region 111 to form a channel region 111 (FIG. 2E).

Subsequently, the third sacrificial oxide film 110 is removed, and a gate oxide film 112 having a thickness of 90 ° is formed by thermal oxidation. Next, polysilicon is grown (here, 8000 °) to a thickness sufficient to bury the region sandwiched between the sidewalls 109, and is patterned by photolithography and dry etching to form a gate electrode 113 [FIG. 2 (f)]. Through the above steps, a gate electrode having a gate length of 0.3 μm could be formed.

[Modification of First Embodiment] FIG. 3A is a plan view showing a modification of the first embodiment, and FIG. 3B is a cross-sectional view taken along the line BB '. is there. In the above-described first embodiment, one MOS transistor is formed in one active region surrounded by the LOCOS oxide film, but in this modified example, two transistors are formed. In this example, the gate pad 113a and the gate wiring 113b are formed so as to partially cover the active region.

[Second Embodiment] FIGS. 4 (a) to 4 (f)
It is sectional drawing of a process order for demonstrating the manufacturing process of the 2nd Example of this invention. After forming a pad oxide film 203 and a silicon nitride film 204 having a thickness of 6000 ° on a p-type silicon substrate 201, removing the silicon nitride film and the pad oxide film in a region where an element isolation region is to be formed, and removing the remaining silicon nitride film. As a mask, LOCOS oxide film 202 is formed by performing steam thermal oxidation. Next, the silicon nitride film 204
Is patterned by photolithography technology and dry etching technology so as to remain on the region that becomes the LDD region and the channel region of the transistor (here, a width of 0.1 mm).
5 μm). Next, arsenic is ion-implanted at a dose of 5E15 / cm ² as a mask of the silicon nitride film 204 to form source / drain regions 205 (FIG. 4A).

Subsequently, an insulating film 206 'for forming an interlayer insulating film is formed to a thickness of 12000.degree. [FIG.
(B)] This is polished using a wafer polishing technique (CMP) until the surface of the silicon nitride film 204 is exposed to form an interlayer insulating film 206 (FIG. 4C). Insulating film 20
As the flattening method 6 ', an etch-back method can be used instead of the CMP method. When the etch-back method is used, the etch-back can be performed after forming a film such as a photoresist on the insulating film 206 '. The exposed silicon nitride film 204 is removed by a wet method to form a gate opening 206a.
As a mask, arsenic is ion-implanted at a dose of 3E13 / cm ² to form an LDD region 207 [FIG.
(D)].

Subsequently, a silicon oxide film is formed to a thickness of 1500 ° and is etched back by using a dry etching technique to form a sidewall 208 on the side surface of the gate opening of the interlayer insulating film 206. After forming a sacrificial oxide film 209 for ion implantation, boron is deposited at 3.5E13 / cm.
^At a dose of ² , ions are implanted at an acceleration voltage at which ions are implanted to a depth equal to or greater than the depth of the LDD region 207 to form a channel region 210 (FIG. 4E).

Subsequently, the sacrificial oxide film 209 is removed, and thermal oxidation is performed to form a gate oxide film 211 having a thickness of 90 °. Next, polysilicon is deposited to a thickness (here, 8000 °) that can sufficiently fill the region sandwiched between the sidewalls 208, and a gate electrode 212 is formed by using a photolithography technique and a dry etching technique [FIG. 4 (f)].

In the above embodiment, an n-channel MOS transistor has been described. However, the present invention can be similarly applied to a p-channel MOS transistor in which the conductivity types of impurities are all reversed. Further, the film thickness, ion implantation dose, and ion type shown in the embodiment may be appropriately changed according to required performance. The formation and removal of the sacrificial oxide film at the time of ion implantation may be performed as needed.

[0027]

As described above, the LD according to the present invention can be used.
In a D-type MOS transistor, an electrode portion necessary for channel formation in a gate electrode is buried in an opening formed in an interlayer insulating film, and other electrode portions such as a gate pad and a gate wiring are formed on the interlayer insulating film. Since it has a structure to be formed, the gate pad and the gate wiring are
It can be formed not only on the OS oxide film but also on the active region. Therefore, according to the present invention, the degree of freedom in design is improved, the chip area can be effectively used, and the integration of LSI can be increased. For example, taking a gate array with a gate length of 0.35 μm as an example,
When the gate width is 10 μm, the area of the LOCOS oxide film can be reduced by about 20% by drastically reducing the area.

Further, according to the present invention, since the gate length can be formed to a size smaller than the resolution limit of the photolithography technique, the transistor can be miniaturized and the performance can be improved. In addition, since all of the source / drain region, the channel region, the gate electrode, and the like are formed so as to be self-aligned with the gate opening, high-precision manufacturing can be performed similarly to a conventional self-aligned transistor. Also,
Gate pads and gate wiring formed outside the active area
Since the substrate is opposed to the substrate via the LOCOS oxide film and the interlayer insulating film, the capacitance of the substrate can be reduced as compared with the conventional example in which the substrate is opposed only via the LOCOS oxide film, and the operation of the transistor can be reduced. It can contribute to speeding up.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view illustrating an embodiment of the present invention.

FIG. 2 is a cross-sectional view in a process order for explaining a manufacturing method according to a first embodiment of the present invention.

FIG. 3 is a plan view and a cross-sectional view for explaining a modification of the first embodiment of the present invention.

FIG. 4 is a process order sectional view for explaining a manufacturing method according to a second embodiment of the present invention.

FIG. 5 is a sectional view and a plan view of a first conventional example.

FIG. 6 is a sectional view of a second conventional example.

FIG. 7 is a sectional view of a third conventional example.

[Explanation of symbols]

1, 301, 401, 501 Silicon substrate 101, 201 P-type silicon substrate 1a, 111, 210 Channel region 2, 102, 202, 307, 404 LOCOS oxide film 3, 104, 205, 305, 407, 506 Source / drain region 4, 106, 206 Interlayer insulating film 4a, 106a, 206a Gate opening 206 'Insulating film 5, 109, 208, 306 Sidewall 6, 108, 207, 304, 406 LDD region 7, 112, 211, 302, 405, 502 Gate oxide film 8, 113, 212, 303 Gate electrode 8a, 113a, 303a Gate pad 113b, 303b Gate wiring 103 First sacrificial oxide film 105, 403 Silicon oxide film 107 Second sacrificial oxide film 110 Third sacrificial oxide Film 203 pad oxide film 2 4 Silicon nitride film 209 Sacrificial oxide film 402a First gate electrode 402b Second gate electrode 503 Relatively thick first oxide film 504 Relatively thick second oxide film 505 Channel stopper 507 Electrode extraction region 508 Metal wiring 509 Metal Gate

Claims (6)

(57) [Claims] An interlayer insulating film having a gate opening is formed on a silicon substrate, a sidewall is formed on a side surface of the gate opening of the interlayer insulating film, and a sidewall is formed on the silicon substrate in a region sandwiched between the sidewalls. A gate electrode is formed via a gate insulating film, a low impurity concentration source / drain region is formed in a surface region of the silicon substrate below the sidewall, and a high impurity concentration source / drain region is formed outside the gate electrode. A semiconductor device comprising: 2. A gate pad which extends over the interlayer insulating film, and serves as a base of a contact hole for connecting the gate electrode to a wiring in an upper layer. 2. The semiconductor device according to claim 1, wherein at least a part of a gate wiring formed integrally with the gate electrode extends over the source / drain region and the channel region. 3. A step of: (1) forming an interlayer insulating film having a gate opening on a silicon substrate on which a source / drain region of a first conductivity type having a high impurity concentration is formed; and (2) via the gate opening. Forming a source / drain region of the first conductivity type with a low impurity concentration in the surface region of the silicon substrate in which the gate opening is formed by introducing an impurity, and (3) depositing an insulating film and etching back the insulating film. Forming a sidewall on the side surface of the gate opening of the interlayer insulating film, and (4) introducing a second conductivity type impurity into the low impurity concentration source / drain region in a region sandwiched between the sidewalls. And (5) forming a gate electrode on the channel region with a gate insulating film interposed therebetween. 4. A step of (1) forming an element isolation insulating film on a silicon substrate; and (2) introducing a first conductivity type impurity into a surface region of the silicon substrate surrounded by the element isolation insulating film. (3) forming an interlayer insulating film on the element isolation insulating film and the silicon substrate; and (4) forming the high impurity concentration on the interlayer insulating film. Forming a gate opening extending longitudinally through the source / drain region with high concentration; (5) forming a source / drain region with low impurity concentration by introducing a second conductivity type impurity through the gate opening; 6) depositing an insulating film and forming a sidewall on the side surface of the gate opening of the interlayer insulating film by etching back; (7) the low impurity concentration silicon in a region sandwiched between the sidewalls; Forming a channel region by introducing an impurity of the second conductivity type into the source / drain region; and (8) forming a gate electrode on the channel region via a gate insulating film. A method for manufacturing a semiconductor device. 5. A step of (1) selectively forming a silicon nitride film on a silicon substrate and selectively thermally oxidizing the silicon substrate using the silicon nitride film as a mask to form an element isolation insulating film; Forming a mask film extending over the active region surrounded by the isolation insulating film; and (3) a first conductivity type in a surface region of the silicon substrate using the element isolation insulating film and the mask film as a mask. Forming a source / drain region having a high impurity concentration by introducing impurities; (4) depositing an interlayer insulating film on the element isolation insulating film, the mask film, and the silicon substrate; (5) A step of exposing a surface of the mask film by polishing or etching back the interlayer insulating film and removing the surface by etching to form a gate opening in the interlayer insulating film; Forming a source / drain region with a low impurity concentration by introducing an impurity of the first conductivity type through the opening, and (7) depositing an insulating film and etching back the insulating film to form side surfaces of the gate opening of the interlayer insulating film. (8) a step of forming a channel region by introducing a second conductivity type impurity into the low impurity concentration source / drain region in a region sandwiched between the side walls; 9) a step of forming a gate electrode on the channel region via a gate insulating film. 6. The method according to claim 5, wherein the formation of the mask film in the step (2) is performed by patterning the silicon nitride film used in the step (1). A method for manufacturing a semiconductor device.