JP2000323716A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, which has a semiconductor layer in SOI structure improving element characteristics while preventing a drop in threshold voltage, a kink phenomenon, etc., and its manufacture. SOLUTION: This semiconductor device has a gate electrode 30 formed on a channel formation region of the semiconductor layer 10a in the SOI structure, source and drain regions (11 and 12) formed in the semiconductor layer at both side of the gate electrode, and a back-gate electrode 31 formed across a back-gate insulating film 26 buried in an insulating film below the channel formation region and the insulating film 23 is thicker below the channel formation region than below the source and drain regions and the semiconductor layer 10a is thinner in the channel formation region than in the source and drain regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an SOI (Silicon On Insulator or
The present invention relates to a semiconductor device having a semiconductor layer having a semiconductor on insulator (miconductor on insulator) structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art MOS (Metal Oxide Semiconductor)
Field Effect Transistor (MOSFET; MOS Field Effe
2. Description of the Related Art Along with the high integration and high performance of an LSI mounted with a ct transistor, a semiconductor device having a semiconductor layer having an SOI structure has attracted attention. In the SOI structure, complete element isolation is performed by an insulating film such as silicon oxide, so that soft errors and latch-up are suppressed, and L
High reliability is also obtained in SI. In addition, since the junction capacitance of the diffusion layer can be reduced, charging / discharging related to switching is reduced, which is advantageous for higher speed and lower power consumption.

In the MOSFET having the SOI structure, the thickness of the silicon active layer immediately below the gate electrode is small as a parameter affecting device characteristics such as a threshold voltage. It is desirable to increase the thickness as a parameter affecting their parasitic resistance.

As described above, a MOS having an SOI structure
In a FET, there is a structure called a trench gate (Recessed Channel) as a structure in which the thickness of a silicon active layer (hereinafter also referred to as an SOI layer) having an SOI structure is locally changed, and a so-called LOCOS (LOCal Ox) is used as a forming method thereof.
The following process using the idation of Silicon) method is known. In the above method, first, a mask layer in which a gate electrode formation region is locally opened is formed on a semiconductor substrate having an SOI structure (hereinafter, also referred to as an SOI substrate), and the SOI layer is heated using the mask layer as a mask. Oxidation selectively forms a silicon oxide film in the gate electrode formation region. Next, the silicon oxide film is removed. Thereby, the SOI in the gate electrode formation region
The surface portion of the layer is removed, and the surface of the SOI layer is processed into a groove shape. Hereinafter, a gate electrode is formed at the bottom of the groove formed as described above via a gate insulating film, and a desired MOSF is formed.
ET.

FIG. 11A is a plan view of a semiconductor device having a MOSFET formed as described above. A gate electrode G (30) is formed on a semiconductor layer SOI (10a) having an SOI structure separated by an element isolation insulating film I (20), and the source / drain regions in the semiconductor layer SOI on both sides thereof. Thus, a MOSFET is configured.

FIG. 11B is a view showing XX 'in FIG. 11A.
11 (c) is a cross-sectional view taken along line YY 'in FIG. 11 (a). An interlayer insulating film 23 made of, for example, silicon oxide is formed on the upper surface of the bonding surface S of the support substrate 100, and is surrounded by an element isolation insulating film 20 to form a silicon active layer (SOI structure) having an SOI structure.
I layer) 10a is formed. S by LOCOS method
A groove R is formed in the surface of the SOI layer 10a in the gate electrode region by removing an oxide film formed by selectively oxidizing the gate electrode region of the OI layer 10a.
A gate electrode 30 made of, for example, polysilicon is formed at the bottom of the groove R via a gate insulating film 24 made of, for example, silicon oxide. On both sides of the gate electrode 30, for example, a sidewall insulating film 25 of silicon oxide is formed. In the SOI layer 10a below the sidewall insulating film 25 on both sides of the gate electrode 30,
A low concentration diffusion layer 11 containing a conductive impurity at a low concentration is formed, and a high concentration diffusion layer 12 containing a conductive impurity at a high concentration is formed on both sides of the low concentration diffusion layer 11 by being connected to the low concentration diffusion layer 11. LDD (Lightly Doped Drain) structure source
A drain region is formed. In addition, the high concentration diffusion layer 1
A metal silicide layer 13 such as titanium silicide or cobalt silicide is formed on the upper layer 2.

In the above semiconductor device, a groove R is formed on the surface of the SOI layer 10a by removing an oxide film formed on the surface of the SOI layer 10a in the gate electrode formation region by the LOCOS method. The thickness of the SOI layer 10a in the region directly below the electrode 30 is small, and the thickness of the SOI layer 10a in the source / sole region is relatively formed. Therefore, the threshold voltage and the parasitic resistance of the MOSFET formed in the SOI layer are reduced. Element characteristics can be improved.

[0008]

However, in the MOSFET formed on the SOI layer, the LOC
When the oxide film formed by the OS method is removed by etching, the surfaces of the SOI layer 10a and the element isolation insulating film 20 are also etched by overetching. In particular, at the end Za of the SOI layer 10a in the direction in which the gate electrode 30 extends, oxidation easily proceeds when an oxide film is formed by the LOCOS method, and the SOI layer 10a is also etched from the side surface of the element isolation insulating film during overetching. Therefore, as shown in FIG. 11C, the thickness of the end Za of the SOI layer 10a in the extending direction of the gate electrode 30 becomes particularly small.

As described above, the thickness of the end of the SOI layer 10a in the extending direction of the gate electrode 30 is particularly small,
When the OSFET is operated, an excessive electric field concentrates on the region Zb near the end of the SOI layer 10a from the direction of the arrow in the drawing, which adversely affects the device characteristics such as a decrease in threshold voltage and a kink phenomenon in this portion. Is easy to cause.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to prevent a threshold voltage drop, a kink phenomenon, and the like from occurring in a semiconductor element such as a MOSFET formed in a semiconductor layer having an SOI structure. It is another object of the present invention to provide a semiconductor device having a semiconductor layer having an SOI structure capable of improving element characteristics and a method for manufacturing the same.

[0011]

In order to achieve the above object, a semiconductor device of the present invention comprises a substrate, an insulating film formed on the substrate, and a channel forming region formed on the insulating film. A semiconductor layer, a gate insulating film formed above the channel forming region, a gate electrode formed above the gate insulating film, and the semiconductor layer on both sides of the gate in the semiconductor layer. A source / drain region formed by connection, a back gate electrode buried in the insulating film below the channel forming region, and a back gate insulating film formed at an interface between the back gate electrode and the semiconductor layer The insulating film partially protrudes toward the semiconductor layer side, and the thickness of the insulating film below the channel formation region is equal to the source / drain Thicker than the thickness of the insulating film below the range, the film thickness of the semiconductor layer in the channel formation region is formed to be thinner than the thickness of the semiconductor layer in said source and drain regions.

The semiconductor device of the present invention is preferably
A plurality of the semiconductor layers separated from each other by an element isolation insulating film are formed on the substrate, and among the plurality, the insulating film below at least one of the semiconductor layers is closer to the semiconductor layer. A portion of the semiconductor layer in the channel formation region is formed to be thinner than a portion of the semiconductor layer in the source / drain region.

The semiconductor device according to the present invention is preferably
A full depletion type transistor and a partial depletion type transistor are formed in the semiconductor layer. Alternatively, preferably, of the plurality of semiconductor layers, a full depletion type transistor is formed on the semiconductor layer on which the insulating film protrudes, and a partial depletion type transistor is formed on the semiconductor layer on which the insulating film does not protrude. A transistor is formed.

Preferably, the above-described semiconductor device of the present invention
The semiconductor layer is a silicon active layer. Also preferably,
An upper portion of the source / drain region is formed as a metal silicide layer.

According to the above semiconductor device, the MOSFE having the back gate formed in the semiconductor layer having the SOI structure
At T, the insulating film below the semiconductor layer of the SOI structure partially protrudes toward the semiconductor layer, and the thickness of the insulating film below the channel formation region of the MOSFET is reduced below the source / drain region. The thickness of the semiconductor layer having the SOI structure in the channel formation region is smaller than the thickness of the semiconductor layer in the source / drain region. The element characteristics can be improved while preventing an excessive electric field from concentrating in the region and preventing a decrease in threshold voltage and a kink phenomenon.

The above structure has a plurality of SOI structure semiconductor layers separated from each other on the same substrate, and has a SOI structure CMO having both a full depletion type transistor and a partial depletion type transistor.
It can be applied to an S semiconductor device. Further, even in a semiconductor layer having one SOI structure, a structure in which a full depletion type and a partial depletion type are partially shared can be employed, and the design is made so as to reinforce the disadvantages of both types of transistors. By doing so, the characteristics can be further improved. Here, a full depletion type transistor means that the depletion layer is SOI during operation.
It is a transistor that reaches the insulating film below the semiconductor layer having the structure, and is resistant to threshold fluctuation due to a short channel effect. In addition, a partial depletion type transistor is a transistor in which a depletion layer does not reach an insulating film below a semiconductor layer having an SOI structure during operation.
The transistor has a small dependency on the variation in the thickness of the silicon active layer.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a mask layer for partially opening the active region on a first substrate made of a semiconductor having an active region; Forming an oxide film on a surface layer portion of the first substrate in an opening region of the mask layer by using the mask layer as a mask;
Forming a groove in the surface of the substrate, removing the mask layer, and forming the first
Forming an insulating film on the upper layer of the substrate, bonding a second substrate from above the insulating film, and leaving the semiconductor layer of a predetermined thickness in the active region portion of the first substrate. Polishing the substrate.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, before the step of forming the mask layer, the method further includes a step of forming an element isolation insulating film in an element isolation region of the first substrate, and the step of polishing the first substrate includes the step of: Polishing is performed using the isolation insulating film as a stopper. More preferably, the step of forming the element isolation insulating film includes:
Forming a device isolation groove in the device isolation region of the first substrate; and filling the device isolation groove with an insulator.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, after the step of polishing the first substrate, a step of forming a gate insulating film in an upper layer of the semiconductor layer, and a step of forming a gate electrode in an extending direction of the groove in the upper layer of the gate insulating film; Forming a source / drain region in the semiconductor layer on both sides of the gate electrode. More preferably, after the step of removing the mask layer and before the step of forming an insulating film in the groove and on the first substrate overlying the groove, a back gate insulating film is formed on the bottom of the groove. Further comprising forming a back gate electrode in the direction in which the groove extends in the upper layer of the back gate insulating film, and forming an insulating film in the upper layer of the first substrate in the groove and continuous with the groove. Is formed by covering the back gate electrode.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, the method further includes a step of flattening the insulating film after the step of forming the insulating film and before the step of bonding the second substrate. More preferably, the step of flattening the insulating film is a chemical mechanical polishing step.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, before the step of bonding the second substrate, the method further includes a step of forming a bonding layer on an upper layer of the second substrate. More preferably, a silicon oxide layer is formed as the bonding layer.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, after the step of forming the insulating film, before the step of bonding the second substrate, the method further includes a step of forming a bonding layer on the insulating film. More preferably, a polysilicon layer is formed as the bonding layer. More preferably, after the step of forming the bonding layer and before the step of bonding the second substrate,
The method further includes a step of flattening the bonding layer, and more preferably, the step of flattening the bonding layer is a chemical mechanical polishing process.

In the above-described method of manufacturing a semiconductor device, an element isolation groove is formed in an element isolation region of a first substrate made of a semiconductor having an active region, and the element isolation groove is filled with an insulator. After forming the insulating film, a mask layer that opens a part of the active region of the first substrate is formed, and an oxide film is formed on a surface layer of the first substrate in the opening region of the mask layer using the mask layer as a mask. The film is removed to form a groove on the surface of the first substrate. Next, the mask layer is removed, an insulating film is formed in the groove and on the first substrate continuous with the groove, and the surface of the insulating film is planarized by a chemical mechanical polishing treatment or the like, or Then, a bonding layer of polysilicon or the like is formed, and the surface of the bonding layer is flattened by a chemical mechanical polishing process or the like, and then the second substrate is bonded from above. Alternatively, before bonding the second substrate, a bonding layer such as silicon oxide is formed on the second substrate in advance, and then the second substrate is bonded. Next, the semiconductor layer having a predetermined thickness in the active region portion of the first substrate is left by using the element isolation insulating film as a stopper or the like.
Polish the substrate. Forming a gate electrode on the semiconductor layer via a gate insulating film in a direction in which the trench of the semiconductor layer having the SOI structure extends, and further forming source / drain regions in the semiconductor layer on both sides of the gate electrode; A MOSFET is formed on the semiconductor layer having the structure. Further, before forming an insulating film in the groove and on the first substrate continuous with the groove, a back gate electrode is formed in advance in the direction in which the groove extends through the back gate insulating film at the bottom of the groove, SOI
MO having back gate formed in semiconductor layer having structure
Form an SFET.

According to the method of manufacturing a semiconductor device described above, S
In a method of forming a semiconductor element such as a MOSFET on a semiconductor layer having an OI structure, an insulating film below a semiconductor layer having an SOI structure partially projects to the semiconductor layer side to form a MOSFE.
The thickness of the insulating film below the channel formation region of T is
The thickness of the insulating film below the source / drain region is larger than that of the source / drain region.
The semiconductor layer having the structure can be formed to be thinner than the semiconductor layer in the source / drain regions. Therefore, an excessively large electric field does not concentrate in a region near the end of the semiconductor layer having an SOI structure, and a semiconductor having an SOI structure capable of improving device characteristics while preventing a decrease in threshold voltage and a kink phenomenon. A semiconductor device having a layer can be manufactured.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1A is a plan view of a semiconductor device according to this embodiment. SOI separated by element isolation insulating film I (20)
The gate electrode G (3) is formed on the semiconductor layer SOI (10a) having the structure.
0) is formed, and the semiconductor layer SOI on both sides thereof is a source / drain region to constitute a MOSFET.

FIG. 1B is a sectional view taken along line XX 'in FIG. 1A, and FIG. 1C is a sectional view taken along line YY' in FIG.
FIG. An interlayer insulating film 2 made of, for example, silicon oxide is formed on the upper surface of the bonding surface S of the support substrate 100.
3 is formed, and a silicon active layer (SOI layer) 1 having an SOI structure is surrounded by an element isolation insulating film 20 thereon.
0a is formed. Over the SOI layer 10a, a gate electrode 30 made of, for example, polysilicon is formed via a gate insulating film 24 made of, for example, silicon oxide. On both sides of the gate electrode 30, for example, a sidewall insulating film 25 of silicon oxide is formed. A low-concentration diffusion layer 11 containing a conductive impurity at a low concentration is formed in the SOI layer 10a below the sidewall insulating film 25 on both sides of the gate electrode 30, and a low-concentration diffusion layer 11 is formed on both sides thereof. To form a high-concentration diffusion layer 12 containing conductive impurities at a high concentration.
A source / drain region having a Doped Drain structure is formed. A metal silicide layer 13 such as titanium silicide or cobalt silicide is formed on the high concentration diffusion layer 12.

Here, the SOI layer 10a has an island shape with a flat surface. The interlayer insulating film 23 below the channel formation region, which is the lower region of the gate electrode 30, has an overhanging portion 23a on the SOI layer 10a side. Correspondingly, a groove R is formed in the SOI layer 10a in the direction in which the gate electrode extends. Are formed. Accordingly, the SOI layer 10a is formed to have a smaller thickness in the channel formation region than in the source / drain regions. For this reason, the thickness of the silicon active layer immediately below the gate electrode is made sufficiently thin,
Transistor characteristics such as a threshold voltage can be improved. In addition, the thickness of the silicon active layer in the source region and the drain region is made sufficiently thick to reduce the resistance at the interface between the source / drain region and the silicon active layer, thereby improving transistor characteristics such as current driving capability. be able to.

Further, in the semiconductor device having the above structure, the thickness of the end of the SOI layer in the direction in which the gate electrode extends does not become particularly thin unlike the conventional example.
To prevent the excessive electric field from concentrating in the region near the edge of the SOI layer when T is operated, and to improve the device characteristics while preventing the threshold voltage from dropping and the kink phenomenon in this region. Can be.

The method of manufacturing the above-described semiconductor device will be described with reference to a drawing corresponding to a cross-sectional view taken along line XX ′ in FIG. First, as shown in FIG. 2A, an element isolation groove is formed in an element isolation region of the first silicon semiconductor substrate 10 and, for example, CVD (Chemical Vapor Depositio).
The element isolation trench is filled with silicon oxide by the method n) to form an element isolation insulating film 20. Alternatively, it can be formed, for example, by the LOCOS method.

Next, as shown in FIG.
Is deposited on the entire surface of silicon nitride by a VD process, a resist film is formed (not shown) of the pattern P _R for opening the gate electrode forming region by a photolithography process, RIE
Forming a mask layer 21 of the pattern P _R for opening the trench formation region is subjected to etching such as reactive ion etching ().

Next, as shown in FIG. 2C, thermal oxidation is performed using, for example, the mask layer 21 as a mask to form the mask layer 21.
An oxide film 22 is formed on the surface layer of the first silicon semiconductor substrate 10 in the opening region of FIG.

Next, as shown in FIG.
The oxide film 22 is removed by etching such as IE, and the mask layer 21 is further removed by etching with changed conditions. As a result, a groove R is formed on the surface of the first silicon semiconductor substrate 10 in the gate electrode formation region.

Next, as shown in FIG.
Silicon oxide such as BPSG (silicon oxide containing boron and phosphorus) is deposited on the entire surface of the trench R and over the interlayer insulating film 23 continuous with the trench R by the VD method. Form. At this time, the groove R
An overhang portion 23a of the interlayer insulating film 23 is formed therein. Next, for example, CMP (Chemical Mechanical Polish)
The surface of the interlayer insulating film 23 is planarized by the ing) method.

Next, as shown in FIG. 3 (f), a second silicon semiconductor substrate (support) in which a bonding surface (not shown) of silicon oxide is previously formed on the upper surface of the interlayer insulating film 23 by oxidizing the bonding surface. The substrate 100 is bonded on the bonding surface S. Alternatively, a bonding layer (not shown) made of polysilicon or the like may be laminated on the interlayer insulating film 23 by, for example, a CVD method.
The surface of the bonding layer may be flattened by a method and bonded to the second silicon semiconductor substrate (supporting substrate) 100 whose bonding surface has been polished in advance. After the bonding process, the bonding surface S is fixed by, for example, a heat treatment at a temperature of 850 to 1100 ° C.

Next, as shown in FIG.
The MP is polished from the first silicon semiconductor substrate 10 side using the element isolation insulating film 20 as a stopper, and the SO separated into islands by the element isolation insulating film 20 and the interlayer insulating film 23.
A semiconductor layer (SOI layer) 10a having an I structure is formed. Here, the drawing is drawn upside down from FIG. 3 (f).

Next, as shown in FIG. 4H, a gate insulating film 24 is formed on the surface of the SOI layer 10a by, for example, a thermal oxidation method, and polysilicon is deposited on the entire surface by, for example, a CVD method. Then, conductive impurities are introduced into the polysilicon layer by ion implantation or the like, and then a resist film _RG having a gate electrode pattern is formed by a photolithography process. At this time, the resist film _RG is patterned along the position of the groove R formed in the SOI layer 10a. Next, using the resist film _RG as a mask, R
The gate electrode 30 is patterned by performing etching such as IE.

Next, as shown in FIG. 4I, a conductive impurity D1 such as phosphorus or boron is ion-implanted using the gate electrode 30 as a mask, and a conductive impurity D1 is formed in the SOI layer 10a on both sides of the gate electrode 30. A low concentration diffusion layer containing an impurity at a low concentration is formed in a self-aligned manner with respect to a gate electrode.

Next, as shown in FIG.
Silicon oxide is deposited on the entire surface by the VD method, and then RI
The silicon oxide is removed by etching back by etching such as E, leaving portions on both sides of the gate electrode 30, and the sidewall insulating film 25 of silicon oxide is removed.
To form

Next, as shown in FIG. 5 (k), conductive impurities D2 such as phosphorus and boron are ion-implanted using the sidewall insulating film 25 as a mask, and the SOI layers 10a on both sides of the gate electrode 30 are implanted. The high-concentration diffusion layer 12 containing conductive impurities at a high concentration is formed so as to be connected to the low-concentration diffusion layer 11 in a self-aligned manner with respect to the gate electrode 30. As described above, the source / drain region having the LDD structure including the low concentration diffusion layer 11 and the high concentration diffusion layer 12 is formed.

Next, a metal silicide layer such as titanium silicide or cobalt silicide is formed on the high concentration diffusion layer 12 to arrive at the semiconductor device shown in FIG.

According to the method of manufacturing a semiconductor device of the present embodiment described above, in a method of forming a semiconductor element such as a MOSFET on a semiconductor layer having an SOI structure, an insulating film below a semiconductor layer having an SOI structure is formed on the semiconductor layer side. Partially overhanging, the thickness of the insulating film below the channel forming region of the MOSFET is larger than the thickness of the insulating film below the source / drain region, and thereby the thickness of the SOI structure semiconductor layer in the channel forming region is reduced. The thickness can be smaller than the thickness of the semiconductor layer in the source / drain regions. Therefore, an excessively large electric field does not concentrate in a region near the end of the semiconductor layer having an SOI structure, and a semiconductor having an SOI structure capable of improving device characteristics while preventing a decrease in threshold voltage and a kink phenomenon. A semiconductor device having a layer can be manufactured.

The semiconductor device according to the present embodiment is based on a full-depletion type transistor excellent in the threshold control function by the SOI type MOSFET having the above-described structure as a basic element, and a DTMOS (Dynami
By using c Threshold MOSFET), high speed and low power consumption can be achieved. Here, the DTMOS is a transistor having a structure in which a body and a gate electrode of a partial depletion type transistor are connected.
Further, regions having different thicknesses of the SOI layer are provided in the gate width direction of the semiconductor layer (SOI layer) having the same SOI structure to form a full depletion type transistor and a partial depletion type transistor in the same element. It is also possible to insert.

Second Embodiment FIG. 6A is a plan view of a semiconductor device according to the second embodiment . 6B is a cross-sectional view taken along line XX ′ in FIG. 6A, and FIG. 6C is a cross-sectional view taken along line YY ′ in FIG. 6A. The semiconductor device according to the present embodiment includes:
Although substantially the same as the semiconductor device according to the first embodiment, the SOI layer 10a which is the lower layer of the gate electrode 30 has a SO
The difference is that the back gate electrode 31 is formed from the I layer 10a via the back gate insulating film 26.

The semiconductor device of this embodiment has a MOSFE having a back gate formed on a semiconductor layer having an SOI structure.
At T, as in the first embodiment, the interlayer insulating film 23 below the channel formation region, which is the region below the gate electrode 30.
Have an overhang 23a on the SOI layer 10a side,
Correspondingly, a groove R is formed in the SOI layer 10a in the direction in which the gate electrode extends, and a back gate electrode 31 is formed along the groove R. The above SOI layer 10
In a, the film thickness in the channel formation region is formed smaller than the film thickness in the source / drain regions. For this reason, the thickness of the silicon active layer immediately below the gate electrode can be made sufficiently thin, and the transistor characteristics such as the threshold voltage can be improved. In addition, the thickness of the silicon active layer in the source region and the drain region is made sufficiently thick to reduce the resistance at the interface between the source / drain region and the silicon active layer, thereby improving transistor characteristics such as current driving capability. be able to.

Further, in the semiconductor device having the above-described structure, unlike the conventional example, the electrode does not go around the portion where the thickness of the end of the SOI layer in the direction of extension of the gate electrode is thin, so that the M
To prevent an excessive electric field from concentrating in a region near an end of an SOI layer when an OSFET is operated, and to improve device characteristics while preventing a decrease in threshold voltage and a kink phenomenon in this portion. Can be.

A method of manufacturing the above-described semiconductor device will be described with reference to a drawing corresponding to a cross-sectional view taken along line XX ′ of FIG. First, as shown in FIG. 7A, an element isolation groove is formed in an element isolation region of the first silicon semiconductor substrate 10 and, for example, CVD (Chemical Vapor Depositio).
The element isolation trench is filled with silicon oxide by the method n) to form an element isolation insulating film 20. Alternatively, it can be formed, for example, by the LOCOS method.

Next, as shown in FIG.
Is deposited on the entire surface of silicon nitride by a VD process, a resist film is formed (not shown) of the pattern P _R for opening the gate electrode forming region by a photolithography process, RIE
Forming a mask layer 21 of the pattern P _R for opening the trench formation region is subjected to etching such as reactive ion etching ().

Next, as shown in FIG. 7C, thermal oxidation is performed by using, for example, the mask layer 21 as a mask.
An oxide film 22 is formed on the surface layer of the first silicon semiconductor substrate 10 in the opening region of FIG.

Next, as shown in FIG.
The oxide film 22 is removed by etching such as IE, and the mask layer 21 is further removed by etching with changed conditions. As a result, a groove R is formed on the surface of the first silicon semiconductor substrate 10 in the gate electrode formation region.

Next, as shown in FIG. 8E, a back gate insulating film 26 is formed on the surface of the SOI layer 10a by, for example, a thermal oxidation method, and polysilicon is deposited on the entire surface by, for example, a CVD method. Accordingly, conductive impurities are introduced into the polysilicon layer by ion implantation or the like, and then a resist film _RBG having a pattern of a back gate electrode is formed by a photolithography process. At this time, the resist film _RBG is patterned along the position of the groove R formed in the SOI layer 10a. Next, etching such as RIE is performed using the resist film _RBG as a mask to pattern the back gate electrode 31.

Next, as shown in FIG.
The back gate electrode 31 is coated with silicon oxide such as BPSG (silicon oxide containing boron and phosphorus) by the VD method, and is entirely coated on the interlayer insulating film 23 in the above-described trench R and over the trench R. Then, an interlayer insulating film 23 is formed. At this time, the interlayer insulating film 23 is formed in the groove R.
Overhang 23a is formed. Next, for example, CMP
The surface of the interlayer insulating film 23 is flattened by a (Chemical Mechanical Polishing) method.

Next, as shown in FIG. 9 (g), a second silicon semiconductor substrate (support) in which a bonding surface (not shown) of silicon oxide is formed on the upper surface of the interlayer insulating film 23 by previously oxidizing the bonding surface. The substrate 100 is bonded on the bonding surface S. Alternatively, a bonding layer (not shown) made of polysilicon or the like may be laminated on the interlayer insulating film 23 by, for example, a CVD method.
The surface of the bonding layer may be flattened by a method and bonded to the second silicon semiconductor substrate (supporting substrate) 100 whose bonding surface has been polished in advance. After the bonding process, the bonding surface S is fixed by, for example, a heat treatment at a temperature of 850 to 1100 ° C.

Next, as shown in FIG.
The MP is polished from the first silicon semiconductor substrate 10 side using the element isolation insulating film 20 as a stopper, and the SO separated into islands by the element isolation insulating film 20 and the interlayer insulating film 23.
A semiconductor layer (SOI layer) 10a having an I structure is formed. Here, the drawing is drawn upside down from FIG. 9 (g).

Next, as shown in FIG. 9I, a gate insulating film 24 is formed on the surface of the SOI layer 10a by, for example, a thermal oxidation method, and polysilicon is deposited on the entire surface by, for example, a CVD method. Then, conductive impurities are introduced into the polysilicon layer by ion implantation or the like, and then a resist film _RG having a gate electrode pattern is formed by a photolithography process. At this time, the resist film _RG is patterned along the position of the groove R formed in the SOI layer 10a. Next, using the resist film _RG as a mask, R
The gate electrode 30 is patterned by performing etching such as IE.

Next, as shown in FIG. 10 (j), a conductive impurity D1 such as phosphorus or boron is ion-implanted using the gate electrode 30 as a mask, and a conductive impurity is implanted in the SOI layer 10a on both sides of the gate electrode 30. A low concentration diffusion layer containing an impurity at a low concentration is formed in a self-aligned manner with respect to a gate electrode.

Next, as shown in FIG. 10 (k), silicon oxide is deposited on the entire surface by, for example, a CVD method.
The silicon oxide is removed by etching back by etching such as IE, leaving portions on both sides of the gate electrode 30, and the sidewall insulating film 2 of silicon oxide is removed.
5 is formed.

Next, as shown in FIG. 10 (l), a conductive impurity D2 such as phosphorus or boron is ion-implanted using the side wall insulating film 25 as a mask, and is implanted into the SOI layer 10a on both sides of the gate electrode 30. The high-concentration diffusion layer 12 containing conductive impurities at a high concentration is formed so as to be connected to the low-concentration diffusion layer 11 in a self-aligned manner with respect to the gate electrode 30. As described above, the low concentration diffusion layer 11 and the high concentration diffusion layer 12
The source / drain region having the LDD structure composed of

Next, a metal silicide layer such as titanium silicide or cobalt silicide is formed on the high concentration diffusion layer 12 to arrive at the semiconductor device shown in FIG.

According to the method of manufacturing a semiconductor device of the present embodiment described above, in the method of forming a semiconductor element such as a MOSFET having a back gate in a semiconductor layer of an SOI structure, the insulating film under the semiconductor layer of the SOI structure is The thickness of the insulating film extending partly over the semiconductor layer and below the channel forming region of the MOSFET is larger than the thickness of the insulating film below the source / drain regions, thereby increasing the SOI structure in the channel forming region. Can be formed thinner than the thickness of the semiconductor layer in the source / drain regions. Therefore, an excessively large electric field does not concentrate in a region near the end of the semiconductor layer having an SOI structure, and a semiconductor having an SOI structure capable of improving device characteristics while preventing a decrease in threshold voltage and a kink phenomenon. A semiconductor device having a layer can be manufactured.

MOSFET having the above back gate
, The back gate electrode is made of SOI as in the conventional example.
The SOI layer is formed along a groove formed in the SOI layer, and is formed in a portion where the thickness of the SOI layer becomes thin. Because it is often used as
The effect of the electric field concentration on the portion where the thickness of the SOI layer is small is small, and there is no problem.

The semiconductor device of the present invention can be applied to any semiconductor device having a MOSFET in the SOI type semiconductor layer, and can have various semiconductor elements in addition to the MOSFET.

The present invention is not limited to the above embodiment. For example, each of the gate electrode and the back gate electrode may have a single-layer structure or a multilayer structure. The metal silicide layer formed in the source / drain region can be formed also on the gate electrode. The interlayer insulating film may have a single-layer structure or a multilayer structure. In addition, various changes can be made without departing from the spirit of the present invention.

[0064]

As described above, according to the semiconductor device of the present invention, in a MOSFET having a back gate formed on a semiconductor layer having an SOI structure, an insulating film below a semiconductor layer having an SOI structure has a lower insulating film. The thickness of the insulating film below the channel formation region of the MOSFET is thicker than the thickness of the insulating film below the source / drain regions, thereby forming the semiconductor layer having the SOI structure in the channel formation region. Is formed thinner than the thickness of the semiconductor layer in the source / drain regions, so that an excessive electric field does not concentrate in the region near the end of the semiconductor layer having the SOI structure, and the threshold voltage of the The device characteristics can be improved while preventing a decrease and a kink phenomenon.

According to the method of manufacturing a semiconductor device of the present invention, in the method of forming a semiconductor element such as a MOSFET on a semiconductor layer having an SOI structure, an insulating film below a semiconductor layer having an SOI structure is partially formed on the semiconductor layer side. Overhang, M
The thickness of the insulating film below the channel forming region of the OSFET is larger than the thickness of the insulating film below the source / drain regions, whereby the thickness of the semiconductor layer having the SOI structure in the channel forming region is reduced. It can be formed thinner than the thickness of the semiconductor layer in the drain region. Therefore, an excessively large electric field does not concentrate in a region near the end of the semiconductor layer having an SOI structure, and a semiconductor having an SOI structure capable of improving device characteristics while preventing a decrease in threshold voltage and a kink phenomenon. A semiconductor device having a layer can be manufactured.

[Brief description of the drawings]

FIG. 1A is a plan view of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a plan view of X in FIG. 1A.
FIG. 1C is a cross-sectional view taken along a line X-X ′, and FIG.
It is sectional drawing in -Y '.

FIGS. 2A and 2B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 2A illustrates a process up to forming an element isolation insulating film, and FIG. (C) shows the steps up to the step of forming the oxide film.

FIG. 3 shows a step subsequent to that of FIG. 2; (d) shows up to a step of removing an oxide film and a mask layer; (e) shows up to a step of forming an interlayer insulating film; The process is shown.

FIG. 4 shows a step subsequent to that of FIG. 3; (g) shows a step of forming a semiconductor layer having an SOI structure by polishing; (h) shows a step of forming a gate electrode; and (i) shows a low concentration diffusion. The steps up to the step of forming a layer are shown.

FIG. 5 shows a step subsequent to that of FIG. 4; (j) shows up to a step of forming a sidewall insulating film; and (k) shows a step up to a step of forming a high-concentration diffusion layer.

FIG. 6A is a plan view of a semiconductor device according to a second embodiment of the present invention, and FIG. 6B is a plan view of X in FIG. 6A.
FIG. 6C is a cross-sectional view at −X ′, and FIG.
It is sectional drawing in -Y '.

FIGS. 7A and 7B are cross-sectional views illustrating a manufacturing process of a method of manufacturing a semiconductor device according to a second embodiment, in which FIG. 7A illustrates up to a step of forming an element isolation insulating film, and FIG. (C) shows the steps up to the step of forming the oxide film.

8 shows a step subsequent to that of FIG. 7; (d) shows up to a step of removing an oxide film and a mask layer; (e) shows up to a step of forming a back gate electrode; and (f) shows a step of forming an interlayer insulating film. The steps up to the formation step are shown.

9 shows a step subsequent to that of FIG. 8, (g) shows a step until the supporting substrate is bonded, and (h) shows an SOI by polishing.
(I) shows the steps up to the step of forming the semiconductor layer having the structure and the steps up to the step of forming the gate electrode.

10 shows a step subsequent to that of FIG. 9; (j) shows a step of forming a low-concentration diffusion layer, (k) shows a step of forming a sidewall insulating film, and (l) shows a step of forming a high-concentration diffusion layer. Up to the formation step.

11 (a) is a plan view of a semiconductor device according to a conventional example, and FIG. 11 (b) is XX ′ in FIG. 11 (a).
11 (c) is a sectional view taken along line Y- in FIG. 11 (a).
It is sectional drawing in Y '.

[Explanation of symbols]

Reference Signs List 10: first silicon semiconductor substrate, 10a (SOI): semiconductor layer (SOI layer), 11: low concentration diffusion layer, 12: high concentration diffusion layer, 13: metal silicide layer, 20 (I): element isolation insulating film, 21: mask layer, 22: oxide film, 23: interlayer insulating film, 23a: overhanging portion, 24: gate insulating film,
25 ... sidewall insulating film, 26 ... back gate insulating film, 30 (G) ... gate electrode, 31 ... back gate electrode, 100 ... second silicon semiconductor substrate (support substrate), R
… Groove, S… Laminated surface, R _G , R _BG … Resist film, D
1, D2 ... conductive impurities, a pattern for exposing the P _R ... groove forming region.

Continued on the front page F term (reference) 5F110 AA01 AA08 AA09 AA15 AA18 BB20 CC02 DD05 DD12 DD13 DD17 DD21 DD24 EE09 EE22 EE30 EE32 EE45 FF02 GG02 GG12 GG22 HJ01 HJ13 HK05 HL05 HM02 HM15 Q19 Q19 Q19 Q19 Q19 Q19

Claims (19)

[Claims] A substrate, an insulating film formed on the substrate, a semiconductor layer having a channel forming region formed on the insulating film, and a gate insulating film formed on the channel forming region. A gate electrode formed in an upper layer of the gate insulating film; source / drain regions formed in the semiconductor layer on both sides of the gate so as to be connected to the channel formation region; A back gate electrode embedded in the insulating film; and a back gate insulating film formed at an interface between the back gate electrode and the semiconductor layer, wherein the insulating film partially extends to the semiconductor layer side. A thickness of the insulating film below the channel formation region is larger than a thickness of the insulating film below the source / drain regions; Thickness of the semiconductor layer in the formation region,
A semiconductor device formed to be thinner than the thickness of the semiconductor layer in the source / drain regions. 2. The semiconductor device according to claim 2, wherein a plurality of the semiconductor layers separated from each other by an element isolation insulating film are formed on the substrate; 2. The semiconductor device according to claim 1, wherein the semiconductor layer partially extends to the semiconductor layer side, and a thickness of the semiconductor layer in the channel formation region is formed smaller than a thickness of the semiconductor layer in the source / drain regions. . 3. The semiconductor device according to claim 1, wherein a full depletion type transistor and a partial depletion type transistor are formed in said semiconductor layer. 4. A full depletion type transistor is formed on the semiconductor layer of the plurality of semiconductor layers on which the insulating film protrudes, and a partial depletion type transistor is formed on the semiconductor layer on which the insulating film does not protrude. 3. The semiconductor device according to claim 2, wherein a transistor is formed. 5. The semiconductor device according to claim 1, wherein said semiconductor layer is a silicon active layer. 6. The semiconductor device according to claim 1, wherein an upper portion of said source / drain region is formed as a metal silicide layer. 7. A step of forming a mask layer for opening a part of the active region on a first substrate made of a semiconductor having an active region, and using the mask layer as a mask in the opening region of the mask layer. Forming an oxide film on the surface of the first substrate; removing the oxide film to form a groove on the surface of the first substrate; removing the mask layer; Forming an insulating film on an upper layer of the first substrate, bonding a second substrate from above the insulating film, and leaving a semiconductor layer having a predetermined thickness in the active region portion of the first substrate. Polishing the first substrate by using the above method. 8. The method according to claim 8, further comprising: before forming the mask layer, forming an element isolation insulating film in an element isolation region of the first substrate. 8. The method according to claim 7, wherein the polishing is performed using the element isolation insulating film as a stopper. 9. The step of forming an element isolation insulating film includes a step of forming an element isolation groove in an element isolation region of the first substrate, and a step of filling the element isolation groove with an insulator. A method for manufacturing a semiconductor device according to claim 8. 10. A step of forming a gate insulating film on the semiconductor layer after the step of polishing the first substrate, and a step of forming a gate electrode in the extending direction of the groove in the upper layer of the gate insulating film. 8. The method according to claim 7, further comprising: forming source / drain regions in the semiconductor layer on both sides of the gate electrode. 11. A back gate insulating film is formed on the bottom of the groove after the step of removing the mask layer and before the step of forming an insulating film in the groove and on an upper layer of the first substrate continuous with the groove. And a step of forming a back gate electrode in a direction in which the groove extends in an upper layer of the back gate insulating film, wherein an insulating film is formed in an upper layer of the first substrate in the groove and continuous with the groove. The method of manufacturing a semiconductor device according to claim 10, wherein in the step of forming, the back gate electrode is formed to cover the back gate electrode. 12. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of flattening the insulating film after the step of forming the insulating film and before the step of bonding the second substrate. 13. The method according to claim 12, wherein the step of flattening the insulating film is a chemical mechanical polishing step. 14. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming a bonding layer on the second substrate before the step of bonding the second substrate. 15. The method according to claim 14, wherein a silicon oxide layer is formed as the bonding layer. 16. The semiconductor device according to claim 7, further comprising a step of forming a bonding layer on the insulating film after the step of forming the insulating film and before the step of bonding the second substrate. Production method. 17. The method according to claim 16, wherein a polysilicon layer is formed as the bonding layer. 18. After the step of forming the bonding layer,
18. The method of manufacturing a semiconductor device according to claim 17, further comprising a step of flattening the bonding layer before the step of bonding the second substrate. 19. The method according to claim 18, wherein the step of flattening the bonding layer is a chemical mechanical polishing step.